Add template and build environment.

116 files changed, 33977 insertions, 0 deletions

diff --git a/ext/.bld/bldrc b/ext/.bld/bldrc
new file mode 100644
index 0000000..03101b8
--- /dev/null
+++ b/ext/.bld/bldrc
@@ -0,0 +1 @@
+http://mbed.org/users/mbed_official/code/mbed/builds/99a22ba036c9
\ No newline at end of file
diff --git a/ext/Adafruit_GFX.cpp b/ext/Adafruit_GFX.cpp
new file mode 100644
index 0000000..ed4ae9f
--- /dev/null
+++ b/ext/Adafruit_GFX.cpp
@@ -0,0 +1,454 @@
+/***********************************
+This is a our graphics core library, for all our displays. 
+We'll be adapting all the
+existing libaries to use this core to make updating, support 
+and upgrading easier!
+
+Adafruit invests time and resources providing this open source code, 
+please support Adafruit and open-source hardware by purchasing 
+products from Adafruit!
+
+Written by Limor Fried/Ladyada  for Adafruit Industries.  
+BSD license, check license.txt for more information
+All text above must be included in any redistribution
+****************************************/
+
+/*
+ *  Modified by Neal Horman 7/14/2012 for use in mbed
+ */
+
+#include "mbed.h"
+
+#include "Adafruit_GFX.h"
+#include "glcdfont.h"
+
+#if defined(GFX_WANT_ABSTRACTS)
+// draw a circle outline
+void Adafruit_GFX::drawCircle(int16_t x0, int16_t y0, int16_t r, uint16_t color)
+{
+    int16_t f = 1 - r;
+    int16_t ddF_x = 1;
+    int16_t ddF_y = -2 * r;
+    int16_t x = 0;
+    int16_t y = r;
+    
+    drawPixel(x0, y0+r, color);
+    drawPixel(x0, y0-r, color);
+    drawPixel(x0+r, y0, color);
+    drawPixel(x0-r, y0, color);
+    
+    while (x<y)
+    {
+        if (f >= 0)
+        {
+            y--;
+            ddF_y += 2;
+            f += ddF_y;
+        }
+        x++;
+        ddF_x += 2;
+        f += ddF_x;
+        
+        drawPixel(x0 + x, y0 + y, color);
+        drawPixel(x0 - x, y0 + y, color);
+        drawPixel(x0 + x, y0 - y, color);
+        drawPixel(x0 - x, y0 - y, color);
+        drawPixel(x0 + y, y0 + x, color);
+        drawPixel(x0 - y, y0 + x, color);
+        drawPixel(x0 + y, y0 - x, color);
+        drawPixel(x0 - y, y0 - x, color);
+    }
+}
+
+void Adafruit_GFX::drawCircleHelper( int16_t x0, int16_t y0, int16_t r, uint8_t cornername, uint16_t color)
+{
+    int16_t f     = 1 - r;
+    int16_t ddF_x = 1;
+    int16_t ddF_y = -2 * r;
+    int16_t x     = 0;
+    int16_t y     = r;
+    
+    while (x<y)
+    {
+        if (f >= 0)
+        {
+            y--;
+            ddF_y += 2;
+            f += ddF_y;
+        }
+        x++;
+        ddF_x += 2;
+        f += ddF_x;
+        
+        if (cornername & 0x4)
+        {
+            drawPixel(x0 + x, y0 + y, color);
+            drawPixel(x0 + y, y0 + x, color);
+        } 
+
+        if (cornername & 0x2)
+        {
+            drawPixel(x0 + x, y0 - y, color);
+            drawPixel(x0 + y, y0 - x, color);
+        }
+
+        if (cornername & 0x8)
+        {
+            drawPixel(x0 - y, y0 + x, color);
+            drawPixel(x0 - x, y0 + y, color);
+        }
+        
+        if (cornername & 0x1)
+        {
+            drawPixel(x0 - y, y0 - x, color);
+            drawPixel(x0 - x, y0 - y, color);
+        }
+    }
+}
+
+void Adafruit_GFX::fillCircle(int16_t x0, int16_t y0, int16_t r, uint16_t color)
+{
+    drawFastVLine(x0, y0-r, 2*r+1, color);
+    fillCircleHelper(x0, y0, r, 3, 0, color);
+}
+
+// used to do circles and roundrects!
+void Adafruit_GFX::fillCircleHelper(int16_t x0, int16_t y0, int16_t r, uint8_t cornername, int16_t delta, uint16_t color)
+{
+    int16_t f     = 1 - r;
+    int16_t ddF_x = 1;
+    int16_t ddF_y = -2 * r;
+    int16_t x     = 0;
+    int16_t y     = r;
+    
+    while (x<y)
+    {
+        if (f >= 0)
+        {
+            y--;
+            ddF_y += 2;
+            f += ddF_y;
+        }
+        x++;
+        ddF_x += 2;
+        f += ddF_x;
+        
+        if (cornername & 0x1)
+        {
+            drawFastVLine(x0+x, y0-y, 2*y+1+delta, color);
+            drawFastVLine(x0+y, y0-x, 2*x+1+delta, color);
+        }
+
+        if (cornername & 0x2)
+        {
+            drawFastVLine(x0-x, y0-y, 2*y+1+delta, color);
+            drawFastVLine(x0-y, y0-x, 2*x+1+delta, color);
+        }
+    }
+}
+#endif
+
+#if defined(GFX_WANT_ABSTRACTS) || defined(GFX_SIZEABLE_TEXT)
+// bresenham's algorithm - thx wikpedia
+void Adafruit_GFX::drawLine(int16_t x0, int16_t y0,  int16_t x1, int16_t y1, uint16_t color)
+{
+    int16_t steep = abs(y1 - y0) > abs(x1 - x0);
+    
+    if (steep)
+    {
+        swap(x0, y0);
+        swap(x1, y1);
+    }
+    
+    if (x0 > x1)
+    {
+        swap(x0, x1);
+        swap(y0, y1);
+    }
+    
+    int16_t dx, dy;
+    dx = x1 - x0;
+    dy = abs(y1 - y0);
+    
+    int16_t err = dx / 2;
+    int16_t ystep;
+    
+    if (y0 < y1)
+        ystep = 1;
+    else
+        ystep = -1;
+    
+    for (; x0<=x1; x0++)
+    {
+        if (steep)
+            drawPixel(y0, x0, color);
+        else
+            drawPixel(x0, y0, color);
+
+        err -= dy;
+        if (err < 0)
+        {
+            y0 += ystep;
+            err += dx;
+        }
+    }
+}
+
+void Adafruit_GFX::drawFastVLine(int16_t x, int16_t y, int16_t h, uint16_t color)
+{
+    // stupidest version - update in subclasses if desired!
+    drawLine(x, y, x, y+h-1, color);
+}
+
+void Adafruit_GFX::fillRect(int16_t x, int16_t y, int16_t w, int16_t h, uint16_t color)
+{
+    // stupidest version - update in subclasses if desired!
+    for (int16_t i=x; i<x+w; i++)
+        drawFastVLine(i, y, h, color); 
+}
+#endif
+
+#if defined(GFX_WANT_ABSTRACTS)
+// draw a rectangle
+void Adafruit_GFX::drawRect(int16_t x, int16_t y, int16_t w, int16_t h, uint16_t color)
+{
+    drawFastHLine(x, y, w, color);
+    drawFastHLine(x, y+h-1, w, color);
+    drawFastVLine(x, y, h, color);
+    drawFastVLine(x+w-1, y, h, color);
+}
+
+void Adafruit_GFX::drawFastHLine(int16_t x, int16_t y, int16_t w, uint16_t color)
+{
+    // stupidest version - update in subclasses if desired!
+    drawLine(x, y, x+w-1, y, color);
+}
+
+void Adafruit_GFX::fillScreen(uint16_t color)
+{
+    fillRect(0, 0, _width, _height, color);
+}
+
+// draw a rounded rectangle!
+void Adafruit_GFX::drawRoundRect(int16_t x, int16_t y, int16_t w, int16_t h, int16_t r, uint16_t color)
+{
+    // smarter version
+    drawFastHLine(x+r  , y    , w-2*r, color); // Top
+    drawFastHLine(x+r  , y+h-1, w-2*r, color); // Bottom
+    drawFastVLine(  x    , y+r  , h-2*r, color); // Left
+    drawFastVLine(  x+w-1, y+r  , h-2*r, color); // Right
+    // draw four corners
+    drawCircleHelper(x+r    , y+r    , r, 1, color);
+    drawCircleHelper(x+w-r-1, y+r    , r, 2, color);
+    drawCircleHelper(x+w-r-1, y+h-r-1, r, 4, color);
+    drawCircleHelper(x+r    , y+h-r-1, r, 8, color);
+}
+
+// fill a rounded rectangle!
+void Adafruit_GFX::fillRoundRect(int16_t x, int16_t y, int16_t w, int16_t h, int16_t r, uint16_t color)
+{
+    // smarter version
+    fillRect(x+r, y, w-2*r, h, color);
+    
+    // draw four corners
+    fillCircleHelper(x+w-r-1, y+r, r, 1, h-2*r-1, color);
+    fillCircleHelper(x+r    , y+r, r, 2, h-2*r-1, color);
+}
+
+// draw a triangle!
+void Adafruit_GFX::drawTriangle(int16_t x0, int16_t y0, int16_t x1, int16_t y1, int16_t x2, int16_t y2, uint16_t color)
+{
+    drawLine(x0, y0, x1, y1, color);
+    drawLine(x1, y1, x2, y2, color);
+    drawLine(x2, y2, x0, y0, color);
+}
+
+// fill a triangle!
+void Adafruit_GFX::fillTriangle ( int16_t x0, int16_t y0, int16_t x1, int16_t y1, int16_t x2, int16_t y2, uint16_t color)
+{
+    int16_t a, b, y, last;
+    
+    // Sort coordinates by Y order (y2 >= y1 >= y0)
+    if (y0 > y1)
+        swap(y0, y1); swap(x0, x1);
+
+    if (y1 > y2)
+        swap(y2, y1); swap(x2, x1);
+
+    if (y0 > y1)
+        swap(y0, y1); swap(x0, x1);
+
+    
+    if(y0 == y2)
+    { // Handle awkward all-on-same-line case as its own thing
+        a = b = x0;
+        if(x1 < a)
+            a = x1;
+        else if(x1 > b)
+            b = x1;
+            
+        if(x2 < a)
+            a = x2;
+        else if(x2 > b) b = x2;
+            drawFastHLine(a, y0, b-a+1, color);
+        return;
+    }
+
+    int16_t
+        dx01 = x1 - x0,
+        dy01 = y1 - y0,
+        dx02 = x2 - x0,
+        dy02 = y2 - y0,
+        dx12 = x2 - x1,
+        dy12 = y2 - y1,
+        sa   = 0,
+        sb   = 0;
+
+    // For upper part of triangle, find scanline crossings for segments
+    // 0-1 and 0-2.  If y1=y2 (flat-bottomed triangle), the scanline y1
+    // is included here (and second loop will be skipped, avoiding a /0
+    // error there), otherwise scanline y1 is skipped here and handled
+    // in the second loop...which also avoids a /0 error here if y0=y1
+    // (flat-topped triangle).
+    if(y1 == y2)
+        last = y1;   // Include y1 scanline
+    else
+        last = y1-1; // Skip it
+
+    for(y=y0; y<=last; y++)
+    {
+        a   = x0 + sa / dy01;
+        b   = x0 + sb / dy02;
+        sa += dx01;
+        sb += dx02;
+        /* longhand:
+        a = x0 + (x1 - x0) * (y - y0) / (y1 - y0);
+        b = x0 + (x2 - x0) * (y - y0) / (y2 - y0);
+        */
+        if(a > b)
+            swap(a,b);
+        drawFastHLine(a, y, b-a+1, color);
+    }
+
+    // For lower part of triangle, find scanline crossings for segments
+    // 0-2 and 1-2.  This loop is skipped if y1=y2.
+    sa = dx12 * (y - y1);
+    sb = dx02 * (y - y0);
+    for(; y<=y2; y++)
+    {
+        a   = x1 + sa / dy12;
+        b   = x0 + sb / dy02;
+        sa += dx12;
+        sb += dx02;
+        /* longhand:
+        a = x1 + (x2 - x1) * (y - y1) / (y2 - y1);
+        b = x0 + (x2 - x0) * (y - y0) / (y2 - y0);
+        */
+        if(a > b)
+            swap(a,b);
+        drawFastHLine(a, y, b-a+1, color);
+    }
+}
+
+void Adafruit_GFX::drawBitmap(int16_t x, int16_t y, const uint8_t *bitmap, int16_t w, int16_t h, uint16_t color)
+{
+    for (int16_t j=0; j<h; j++)
+    {
+        for (int16_t i=0; i<w; i++ )
+        {
+            if (bitmap[i + (j/8)*w] & _BV(j%8))
+                drawPixel(x+i, y+j, color);
+        }
+    }
+}
+#endif
+
+size_t Adafruit_GFX::writeChar(uint8_t c)
+{
+    if (c == '\n')
+    {
+        cursor_y += textsize*8;
+        cursor_x = 0;
+    }
+    else if (c == '\r')
+        cursor_x = 0;
+    else
+    {
+        drawChar(cursor_x, cursor_y, c, textcolor, textbgcolor, textsize);
+        cursor_x += textsize*6;
+        if (wrap && (cursor_x > (_width - textsize*6)))
+        {
+            cursor_y += textsize*8;
+            cursor_x = 0;
+        }
+    }
+    return 1;
+}
+
+// draw a character
+void Adafruit_GFX::drawChar(int16_t x, int16_t y, unsigned char c, uint16_t color, uint16_t bg, uint8_t size)
+{
+    if(
+        (x >= _width) || // Clip right
+        (y >= _height) || // Clip bottom
+        ((x + 5 * size - 1) < 0) || // Clip left
+        ((y + 8 * size - 1) < 0) // Clip top
+        )
+    return;
+    
+    for (int8_t i=0; i<6; i++ )
+    {
+        uint8_t line = 0;
+
+        if (i == 5) 
+            line = 0x0;
+        else 
+            line = font[(c*5)+i];
+            
+        for (int8_t j = 0; j<8; j++)
+        {
+            if (line & 0x1)
+            {
+#if defined(GFX_WANT_ABSTRACTS) || defined(GFX_SIZEABLE_TEXT)
+                if (size == 1) // default size
+                    drawPixel(x+i, y+j, color);
+                else // big size
+                    fillRect(x+(i*size), y+(j*size), size, size, color);
+#else
+                drawPixel(x+i, y+j, color);
+#endif
+            }
+            else if (bg != color)
+            {
+#if defined(GFX_WANT_ABSTRACTS) || defined(GFX_SIZEABLE_TEXT)
+                if (size == 1) // default size
+                    drawPixel(x+i, y+j, bg);
+                else // big size
+                    fillRect(x+i*size, y+j*size, size, size, bg);
+#else
+                drawPixel(x+i, y+j, bg);
+#endif
+            }
+            line >>= 1;
+        }
+    }
+}
+
+void Adafruit_GFX::setRotation(uint8_t x)
+{
+    x %= 4;  // cant be higher than 3
+    rotation = x;
+    switch (x)
+    {
+        case 0:
+        case 2:
+            _width = _rawWidth;
+            _height = _rawHeight;
+            break;
+        case 1:
+        case 3:
+            _width = _rawHeight;
+            _height = _rawWidth;
+            break;
+    }
+}
diff --git a/ext/Adafruit_GFX.h b/ext/Adafruit_GFX.h
new file mode 100644
index 0000000..d3c2240
--- /dev/null
+++ b/ext/Adafruit_GFX.h
@@ -0,0 +1,183 @@
+/***********************************
+This is a our graphics core library, for all our displays. 
+We'll be adapting all the
+existing libaries to use this core to make updating, support 
+and upgrading easier!
+
+Adafruit invests time and resources providing this open source code, 
+please support Adafruit and open-source hardware by purchasing 
+products from Adafruit!
+
+Written by Limor Fried/Ladyada  for Adafruit Industries.  
+BSD license, check license.txt for more information
+All text above must be included in any redistribution
+****************************************/
+
+/*
+ *  Modified by Neal Horman 7/14/2012 for use in mbed
+ */
+
+#ifndef _ADAFRUIT_GFX_H_
+#define _ADAFRUIT_GFX_H_
+
+#include "Adafruit_GFX_Config.h"
+
+static inline void swap(int16_t &a, int16_t &b)
+{
+    int16_t t = a;
+    
+    a = b;
+    b = t;
+}
+
+#ifndef _BV
+#define _BV(bit) (1<<(bit))
+#endif
+
+#define BLACK 0
+#define WHITE 1
+
+/**
+ * This is a Text and Graphics element drawing class.
+ * These functions draw to the display buffer.
+ *
+ * Display drivers should be derived from here.
+ * The Display drivers push the display buffer to the
+ * hardware based on application control.
+ *
+ */
+class Adafruit_GFX : public Stream
+{
+ public:
+    Adafruit_GFX(int16_t w, int16_t h)
+        : _rawWidth(w)
+        , _rawHeight(h)
+        , _width(w)
+        , _height(h)
+        , cursor_x(0)
+        , cursor_y(0)
+        , textcolor(WHITE)
+        , textbgcolor(BLACK)
+        , textsize(1)
+        , rotation(0)
+        , wrap(true)
+        {};
+
+    /// Paint one BLACK or WHITE pixel in the display buffer
+    // this must be defined by the subclass
+    virtual void drawPixel(int16_t x, int16_t y, uint16_t color) = 0;
+    // this is optional
+    virtual void invertDisplay(bool i) {};
+    
+    // Stream implementation - provides printf() interface
+    // You would otherwise be forced to use writeChar()
+    virtual int _putc(int value) { return writeChar(value); };
+    virtual int _getc() { return -1; };
+
+#ifdef GFX_WANT_ABSTRACTS
+    // these are 'generic' drawing functions, so we can share them!
+    
+    /** Draw a Horizontal Line
+     * @note GFX_WANT_ABSTRACTS must be defined in Adafruit_GFX_config.h
+     */
+    virtual void drawFastHLine(int16_t x, int16_t y, int16_t w, uint16_t color);
+    /** Draw a rectangle
+     * @note GFX_WANT_ABSTRACTS must be defined in Adafruit_GFX_config.h
+     */
+    virtual void drawRect(int16_t x, int16_t y, int16_t w, int16_t h, uint16_t color);
+    /** Fill the entire display
+     * @note GFX_WANT_ABSTRACTS must be defined in Adafruit_GFX_config.h
+     */
+    virtual void fillScreen(uint16_t color);
+
+    /** Draw a circle
+     * @note GFX_WANT_ABSTRACTS must be defined in Adafruit_GFX_config.h
+     */
+    void drawCircle(int16_t x0, int16_t y0, int16_t r, uint16_t color);
+    void drawCircleHelper(int16_t x0, int16_t y0, int16_t r, uint8_t cornername, uint16_t color);
+    
+    /** Draw and fill a circle
+     * @note GFX_WANT_ABSTRACTS must be defined in Adafruit_GFX_config.h
+     */
+    void fillCircle(int16_t x0, int16_t y0, int16_t r, uint16_t color);
+    void fillCircleHelper(int16_t x0, int16_t y0, int16_t r, uint8_t cornername, int16_t delta, uint16_t color);
+
+    /** Draw a triangle
+     * @note GFX_WANT_ABSTRACTS must be defined in Adafruit_GFX_config.h
+     */
+    void drawTriangle(int16_t x0, int16_t y0, int16_t x1, int16_t y1, int16_t x2, int16_t y2, uint16_t color);
+    /** Draw and fill a triangle
+     * @note GFX_WANT_ABSTRACTS must be defined in Adafruit_GFX_config.h
+     */
+    void fillTriangle(int16_t x0, int16_t y0, int16_t x1, int16_t y1, int16_t x2, int16_t y2, uint16_t color);
+    
+    /** Draw a rounded rectangle
+     * @note GFX_WANT_ABSTRACTS must be defined in Adafruit_GFX_config.h
+     */
+    void drawRoundRect(int16_t x0, int16_t y0, int16_t w, int16_t h, int16_t radius, uint16_t color);
+    /** Draw and fill a rounded rectangle
+     * @note GFX_WANT_ABSTRACTS must be defined in Adafruit_GFX_config.h
+     */
+    void fillRoundRect(int16_t x0, int16_t y0, int16_t w, int16_t h, int16_t radius, uint16_t color);
+    /** Draw a bitmap
+     * @note GFX_WANT_ABSTRACTS must be defined in Adafruit_GFX_config.h
+     */
+    void drawBitmap(int16_t x, int16_t y, const uint8_t *bitmap, int16_t w, int16_t h, uint16_t color);
+#endif
+
+#if defined(GFX_WANT_ABSTRACTS) || defined(GFX_SIZEABLE_TEXT)
+    /** Draw a line
+     * @note GFX_WANT_ABSTRACTS or GFX_SIZEABLE_TEXT must be defined in Adafruit_GFX_config.h
+     */
+    virtual void drawLine(int16_t x0, int16_t y0, int16_t x1, int16_t y1, uint16_t color);
+    /** Draw a vertical line
+     * @note GFX_WANT_ABSTRACTS or GFX_SIZEABLE_TEXT must be defined in Adafruit_GFX_config.h
+     */
+    virtual void drawFastVLine(int16_t x, int16_t y, int16_t h, uint16_t color);
+    /** Draw and fill a rectangle
+     * @note GFX_WANT_ABSTRACTS or GFX_SIZEABLE_TEXT must be defined in Adafruit_GFX_config.h
+     */
+    virtual void fillRect(int16_t x, int16_t y, int16_t w, int16_t h, uint16_t color);
+#endif
+
+    /// Draw a text character at a specified pixel location
+    void drawChar(int16_t x, int16_t y, unsigned char c, uint16_t color, uint16_t bg, uint8_t size);
+    /// Draw a text character at the text cursor location
+    size_t writeChar(uint8_t);
+
+    /// Get the width of the display in pixels
+    inline int16_t width(void) { return _width; };
+    /// Get the height of the display in pixels
+    inline int16_t height(void) { return _height; };
+
+    /// Set the text cursor location, based on the size of the text
+    inline void setTextCursor(int16_t x, int16_t y) { cursor_x = x; cursor_y = y; };
+#if defined(GFX_WANT_ABSTRACTS) || defined(GFX_SIZEABLE_TEXT)
+    /** Set the size of the text to be drawn
+     * @note Make sure to enable either GFX_SIZEABLE_TEXT or GFX_WANT_ABSTRACTS
+     */
+    inline void setTextSize(uint8_t s) { textsize = (s > 0) ? s : 1; };
+#endif
+    /// Set the text foreground and background colors to be the same
+    inline void setTextColor(uint16_t c) { textcolor = c; textbgcolor = c; }
+    /// Set the text foreground and background colors independantly
+    inline void setTextColor(uint16_t c, uint16_t b) { textcolor = c; textbgcolor = b; };
+    /// Set text wraping mode true or false
+    inline void setTextWrap(bool w) { wrap = w; };
+
+    /// Set the display rotation, 1, 2, 3, or 4
+    void setRotation(uint8_t r);
+    /// Get the current rotation
+    inline uint8_t getRotation(void) { rotation %= 4; return rotation; };
+
+protected:
+    int16_t  _rawWidth, _rawHeight;   // this is the 'raw' display w/h - never changes
+    int16_t  _width, _height; // dependent on rotation
+    int16_t  cursor_x, cursor_y;
+    uint16_t textcolor, textbgcolor;
+    uint8_t  textsize;
+    uint8_t  rotation;
+    bool  wrap; // If set, 'wrap' text at right edge of display
+};
+
+#endif
diff --git a/ext/Adafruit_GFX_Config.h b/ext/Adafruit_GFX_Config.h
new file mode 100644
index 0000000..f3aaed6
--- /dev/null
+++ b/ext/Adafruit_GFX_Config.h
@@ -0,0 +1,14 @@
+#ifndef _ADAFRUIT_GFX_CONFIG_H_

+#define _ADAFRUIT_GFX_CONFIG_H_

+

+// Uncomment this to turn off the builtin splash

+//#define NO_SPLASH_ADAFRUIT

+

+// Uncomment this to enable all functionality

+//#define GFX_WANT_ABSTRACTS

+

+// Uncomment this to enable only runtime font scaling, without all the rest of the Abstracts

+//#define GFX_SIZEABLE_TEXT

+

+

+#endif
\ No newline at end of file
diff --git a/ext/Adafruit_SSD1306.cpp b/ext/Adafruit_SSD1306.cpp
new file mode 100644
index 0000000..fe3e6bf
--- /dev/null
+++ b/ext/Adafruit_SSD1306.cpp
@@ -0,0 +1,230 @@
+/*********************************************************************
+This is a library for our Monochrome OLEDs based on SSD1306 drivers
+
+  Pick one up today in the adafruit shop!
+  ------> http://www.adafruit.com/category/63_98
+
+These displays use SPI to communicate, 4 or 5 pins are required to  
+interface
+
+Adafruit invests time and resources providing this open source code, 
+please support Adafruit and open-source hardware by purchasing 
+products from Adafruit!
+
+Written by Limor Fried/Ladyada  for Adafruit Industries.  
+BSD license, check license.txt for more information
+All text above, and the splash screen below must be included in any redistribution
+*********************************************************************/
+
+/*
+ *  Modified by Neal Horman 7/14/2012 for use in mbed
+ */
+
+#include "mbed.h"
+#include "Adafruit_SSD1306.h"
+
+#define SSD1306_SETCONTRAST 0x81
+#define SSD1306_DISPLAYALLON_RESUME 0xA4
+#define SSD1306_DISPLAYALLON 0xA5
+#define SSD1306_NORMALDISPLAY 0xA6
+#define SSD1306_INVERTDISPLAY 0xA7
+#define SSD1306_DISPLAYOFF 0xAE
+#define SSD1306_DISPLAYON 0xAF
+#define SSD1306_SETDISPLAYOFFSET 0xD3
+#define SSD1306_SETCOMPINS 0xDA
+#define SSD1306_SETVCOMDETECT 0xDB
+#define SSD1306_SETDISPLAYCLOCKDIV 0xD5
+#define SSD1306_SETPRECHARGE 0xD9
+#define SSD1306_SETMULTIPLEX 0xA8
+#define SSD1306_SETLOWCOLUMN 0x00
+#define SSD1306_SETHIGHCOLUMN 0x10
+#define SSD1306_SETSTARTLINE 0x40
+#define SSD1306_MEMORYMODE 0x20
+#define SSD1306_COMSCANINC 0xC0
+#define SSD1306_COMSCANDEC 0xC8
+#define SSD1306_SEGREMAP 0xA0
+#define SSD1306_CHARGEPUMP 0x8D
+
+void Adafruit_SSD1306::begin(uint8_t vccstate)
+{
+    rst = 1;
+    // VDD (3.3V) goes high at start, lets just chill for a ms
+    wait_ms(1);
+    // bring reset low
+    rst = 0;
+    // wait 10ms
+    wait_ms(10);
+    // bring out of reset
+    rst = 1;
+    // turn on VCC (9V?)
+
+    command(SSD1306_DISPLAYOFF);
+    command(SSD1306_SETDISPLAYCLOCKDIV);
+    command(0x80);                                  // the suggested ratio 0x80
+
+    command(SSD1306_SETMULTIPLEX);
+    command(_rawHeight-1);
+
+    command(SSD1306_SETDISPLAYOFFSET);
+    command(0x0);                                   // no offset
+
+    command(SSD1306_SETSTARTLINE | 0x0);            // line #0
+
+    command(SSD1306_CHARGEPUMP);
+    command((vccstate == SSD1306_EXTERNALVCC) ? 0x10 : 0x14);
+
+    command(SSD1306_MEMORYMODE);
+    command(0x00);                                  // 0x0 act like ks0108
+
+    command(SSD1306_SEGREMAP | 0x1);
+
+    command(SSD1306_COMSCANDEC);
+
+    command(SSD1306_SETCOMPINS);
+    command(_rawHeight == 32 ? 0x02 : 0x12);        // TODO - calculate based on _rawHieght ?
+
+    command(SSD1306_SETCONTRAST);
+    command(_rawHeight == 32 ? 0x8F : ((vccstate == SSD1306_EXTERNALVCC) ? 0x9F : 0xCF) );
+
+    command(SSD1306_SETPRECHARGE);
+    command((vccstate == SSD1306_EXTERNALVCC) ? 0x22 : 0xF1);
+
+    command(SSD1306_SETVCOMDETECT);
+    command(0x40);
+
+    command(SSD1306_DISPLAYALLON_RESUME);
+
+    command(SSD1306_NORMALDISPLAY);
+    
+    command(SSD1306_DISPLAYON);
+}
+
+// Set a single pixel
+void Adafruit_SSD1306::drawPixel(int16_t x, int16_t y, uint16_t color)
+{
+    if ((x < 0) || (x >= width()) || (y < 0) || (y >= height()))
+        return;
+    
+    // check rotation, move pixel around if necessary
+    switch (getRotation())
+    {
+        case 1:
+            swap(x, y);
+            x = _rawWidth - x - 1;
+            break;
+        case 2:
+            x = _rawWidth - x - 1;
+            y = _rawHeight - y - 1;
+            break;
+        case 3:
+            swap(x, y);
+            y = _rawHeight - y - 1;
+            break;
+    }  
+    
+    // x is which column
+    if (color == WHITE) 
+        buffer[x+ (y/8)*_rawWidth] |= _BV((y%8));  
+    else // else black
+        buffer[x+ (y/8)*_rawWidth] &= ~_BV((y%8)); 
+}
+
+void Adafruit_SSD1306::invertDisplay(bool i)
+{
+	command(i ? SSD1306_INVERTDISPLAY : SSD1306_NORMALDISPLAY);
+}
+
+// Send the display buffer out to the display
+void Adafruit_SSD1306::display(void)
+{
+	command(SSD1306_SETLOWCOLUMN | 0x0);  // low col = 0
+	command(SSD1306_SETHIGHCOLUMN | 0x0);  // hi col = 0
+	command(SSD1306_SETSTARTLINE | 0x0); // line #0
+	sendDisplayBuffer();
+}
+
+// Clear the display buffer. Requires a display() call at some point afterwards
+void Adafruit_SSD1306::clearDisplay(void)
+{
+	std::fill(buffer.begin(),buffer.end(),0);
+}
+
+void Adafruit_SSD1306::splash(void)
+{
+#ifndef NO_SPLASH_ADAFRUIT
+	uint8_t adaFruitLogo[64 * 128 / 8] =
+	{ 
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80,
+		0x80, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x80, 0x80, 0xC0, 0xC0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x80, 0xC0, 0xE0, 0xF0, 0xF8, 0xFC, 0xF8, 0xE0, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x80, 0x80,
+		0x80, 0x80, 0x00, 0x80, 0x80, 0x00, 0x00, 0x00, 0x00, 0x80, 0x80, 0x80, 0x80, 0x80, 0x00, 0xFF,
+		0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x80, 0x80, 0x80, 0x80, 0x00, 0x00, 0x80, 0x80, 0x00, 0x00,
+		0x80, 0xFF, 0xFF, 0x80, 0x80, 0x00, 0x80, 0x80, 0x00, 0x80, 0x80, 0x80, 0x80, 0x00, 0x80, 0x80,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x80, 0x00, 0x00, 0x8C, 0x8E, 0x84, 0x00, 0x00, 0x80, 0xF8,
+		0xF8, 0xF8, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0xF0, 0xF0, 0xF0, 0xF0, 0xF0, 0xF0, 0xF0, 0xF0, 0xF0, 0xF0, 0xF0, 0xF0, 0xE0, 0xE0, 0xC0, 0x80,
+		0x00, 0xE0, 0xFC, 0xFE, 0xFF, 0xFF, 0xFF, 0x7F, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFE, 0xFF, 0xC7, 0x01, 0x01,
+		0x01, 0x01, 0x83, 0xFF, 0xFF, 0x00, 0x00, 0x7C, 0xFE, 0xC7, 0x01, 0x01, 0x01, 0x01, 0x83, 0xFF,
+		0xFF, 0xFF, 0x00, 0x38, 0xFE, 0xC7, 0x83, 0x01, 0x01, 0x01, 0x83, 0xC7, 0xFF, 0xFF, 0x00, 0x00,
+		0x01, 0xFF, 0xFF, 0x01, 0x01, 0x00, 0xFF, 0xFF, 0x07, 0x01, 0x01, 0x01, 0x00, 0x00, 0x7F, 0xFF,
+		0x80, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0x7F, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x01, 0xFF,
+		0xFF, 0xFF, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x03, 0x0F, 0x3F, 0x7F, 0x7F, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xE7, 0xC7, 0xC7, 0x8F,
+		0x8F, 0x9F, 0xBF, 0xFF, 0xFF, 0xC3, 0xC0, 0xF0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFC, 0xFC, 0xFC,
+		0xFC, 0xFC, 0xFC, 0xFC, 0xFC, 0xF8, 0xF8, 0xF0, 0xF0, 0xE0, 0xC0, 0x00, 0x01, 0x03, 0x03, 0x03,
+		0x03, 0x03, 0x01, 0x03, 0x03, 0x00, 0x00, 0x00, 0x00, 0x01, 0x03, 0x03, 0x03, 0x03, 0x01, 0x01,
+		0x03, 0x01, 0x00, 0x00, 0x00, 0x01, 0x03, 0x03, 0x03, 0x03, 0x01, 0x01, 0x03, 0x03, 0x00, 0x00,
+		0x00, 0x03, 0x03, 0x00, 0x00, 0x00, 0x03, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01,
+		0x03, 0x03, 0x03, 0x03, 0x03, 0x01, 0x00, 0x00, 0x00, 0x01, 0x03, 0x01, 0x00, 0x00, 0x00, 0x03,
+		0x03, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		// 128x32^^^  128x64vvv
+		0x00, 0x00, 0x00, 0x80, 0xC0, 0xE0, 0xF0, 0xF9, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x3F, 0x1F, 0x0F,
+		0x87, 0xC7, 0xF7, 0xFF, 0xFF, 0x1F, 0x1F, 0x3D, 0xFC, 0xF8, 0xF8, 0xF8, 0xF8, 0x7C, 0x7D, 0xFF,
+		0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x7F, 0x3F, 0x0F, 0x07, 0x00, 0x30, 0x30, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0xFE, 0xFE, 0xFC, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0xC0, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x30, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0xC0, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x7F, 0x7F, 0x3F, 0x1F,
+		0x0F, 0x07, 0x1F, 0x7F, 0xFF, 0xFF, 0xF8, 0xF8, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xF8, 0xE0,
+		0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFE, 0xFE, 0x00, 0x00,
+		0x00, 0xFC, 0xFE, 0xFC, 0x0C, 0x06, 0x06, 0x0E, 0xFC, 0xF8, 0x00, 0x00, 0xF0, 0xF8, 0x1C, 0x0E,
+		0x06, 0x06, 0x06, 0x0C, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0xFE, 0xFE, 0x00, 0x00, 0x00, 0x00, 0xFC,
+		0xFE, 0xFC, 0x00, 0x18, 0x3C, 0x7E, 0x66, 0xE6, 0xCE, 0x84, 0x00, 0x00, 0x06, 0xFF, 0xFF, 0x06,
+		0x06, 0xFC, 0xFE, 0xFC, 0x0C, 0x06, 0x06, 0x06, 0x00, 0x00, 0xFE, 0xFE, 0x00, 0x00, 0xC0, 0xF8,
+		0xFC, 0x4E, 0x46, 0x46, 0x46, 0x4E, 0x7C, 0x78, 0x40, 0x18, 0x3C, 0x76, 0xE6, 0xCE, 0xCC, 0x80,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x01, 0x07, 0x0F, 0x1F, 0x1F, 0x3F, 0x3F, 0x3F, 0x3F, 0x1F, 0x0F, 0x03,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x0F, 0x00, 0x00,
+		0x00, 0x0F, 0x0F, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x0F, 0x00, 0x00, 0x03, 0x07, 0x0E, 0x0C,
+		0x18, 0x18, 0x0C, 0x06, 0x0F, 0x0F, 0x0F, 0x00, 0x00, 0x01, 0x0F, 0x0E, 0x0C, 0x18, 0x0C, 0x0F,
+		0x07, 0x01, 0x00, 0x04, 0x0E, 0x0C, 0x18, 0x0C, 0x0F, 0x07, 0x00, 0x00, 0x00, 0x0F, 0x0F, 0x00,
+		0x00, 0x0F, 0x0F, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x0F, 0x00, 0x00, 0x00, 0x07,
+		0x07, 0x0C, 0x0C, 0x18, 0x1C, 0x0C, 0x06, 0x06, 0x00, 0x04, 0x0E, 0x0C, 0x18, 0x0C, 0x0F, 0x07,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+	};
+	
+	std::copy(
+		&adaFruitLogo[0]
+		, &adaFruitLogo[0] + (_rawHeight == 32 ? sizeof(adaFruitLogo)/2 : sizeof(adaFruitLogo))
+		, buffer.begin()
+		);
+#endif
+}
diff --git a/ext/Adafruit_SSD1306.h b/ext/Adafruit_SSD1306.h
new file mode 100644
index 0000000..3d84f9f
--- /dev/null
+++ b/ext/Adafruit_SSD1306.h
@@ -0,0 +1,220 @@
+/*********************************************************************
+This is a library for our Monochrome OLEDs based on SSD1306 drivers
+
+  Pick one up today in the adafruit shop!
+  ------> http://www.adafruit.com/category/63_98
+
+These displays use SPI to communicate, 4 or 5 pins are required to  
+interface
+
+Adafruit invests time and resources providing this open source code, 
+please support Adafruit and open-source hardware by purchasing 
+products from Adafruit!
+
+Written by Limor Fried/Ladyada  for Adafruit Industries.  
+BSD license, check license.txt for more information
+All text above, and the splash screen must be included in any redistribution
+*********************************************************************/
+
+/*
+ *  Modified by Neal Horman 7/14/2012 for use in mbed
+ */
+
+#ifndef _ADAFRUIT_SSD1306_H_
+#define _ADAFRUIT_SSD1306_H_
+
+#include "mbed.h"
+#include "Adafruit_GFX.h"
+
+#include <vector>
+#include <algorithm>
+
+// A DigitalOut sub-class that provides a constructed default state
+class DigitalOut2 : public DigitalOut
+{
+public:
+	DigitalOut2(PinName pin, bool active = false) : DigitalOut(pin) { write(active); };
+	DigitalOut2& operator= (int value) { write(value); return *this; };
+	DigitalOut2& operator= (DigitalOut2& rhs) { write(rhs.read()); return *this; };
+	operator int() { return read(); };
+};
+
+#define SSD1306_EXTERNALVCC 0x1
+#define SSD1306_SWITCHCAPVCC 0x2
+
+/** The pure base class for the SSD1306 display driver.
+ *
+ * You should derive from this for a new transport interface type,
+ * such as the SPI and I2C drivers.
+ */
+class Adafruit_SSD1306 : public Adafruit_GFX
+{
+public:
+	Adafruit_SSD1306(PinName RST, uint8_t rawHeight = 32, uint8_t rawWidth = 128)
+		: Adafruit_GFX(rawWidth,rawHeight)
+		, rst(RST,false)
+	{
+		buffer.resize(rawHeight * rawWidth / 8);
+	};
+
+	void begin(uint8_t switchvcc = SSD1306_SWITCHCAPVCC);
+	
+	// These must be implemented in the derived transport driver
+	virtual void command(uint8_t c) = 0;
+	virtual void data(uint8_t c) = 0;
+	virtual void drawPixel(int16_t x, int16_t y, uint16_t color);
+
+	/// Clear the display buffer    
+	void clearDisplay(void);
+	virtual void invertDisplay(bool i);
+
+	/// Cause the display to be updated with the buffer content.
+	void display();
+	/// Fill the buffer with the AdaFruit splash screen.
+	virtual void splash();
+    
+protected:
+	virtual void sendDisplayBuffer() = 0;
+	DigitalOut2 rst;
+
+	// the memory buffer for the LCD
+	std::vector<uint8_t> buffer;
+};
+
+
+/** This is the SPI SSD1306 display driver transport class
+ *
+ */
+class Adafruit_SSD1306_Spi : public Adafruit_SSD1306
+{
+public:
+	/** Create a SSD1306 SPI transport display driver instance with the specified DC, RST, and CS pins, as well as the display dimentions
+	 *
+	 * Required parameters
+	 * @param spi - a reference to an initialized SPI object
+	 * @param DC (Data/Command) pin name
+	 * @param RST (Reset) pin name
+	 * @param CS (Chip Select) pin name
+	 *
+	 * Optional parameters
+	 * @param rawHeight - the vertical number of pixels for the display, defaults to 32
+	 * @param rawWidth - the horizonal number of pixels for the display, defaults to 128
+	 */
+	Adafruit_SSD1306_Spi(SPI &spi, PinName DC, PinName RST, PinName CS, uint8_t rawHieght = 32, uint8_t rawWidth = 128)
+	    : Adafruit_SSD1306(RST, rawHieght, rawWidth)
+	    , cs(CS,true)
+	    , dc(DC,false)
+	    , mspi(spi)
+	    {
+		    begin();
+		    splash();
+		    display();
+	    };
+
+	virtual void command(uint8_t c)
+	{
+	    cs = 1;
+	    dc = 0;
+	    cs = 0;
+	    mspi.write(c);
+	    cs = 1;
+	};
+
+	virtual void data(uint8_t c)
+	{
+	    cs = 1;
+	    dc = 1;
+	    cs = 0;
+	    mspi.write(c);
+	    cs = 1;
+	};
+
+protected:
+	virtual void sendDisplayBuffer()
+	{
+		cs = 1;
+		dc = 1;
+		cs = 0;
+
+		for(uint16_t i=0, q=buffer.size(); i<q; i++)
+			mspi.write(buffer[i]);
+
+		if(height() == 32)
+		{
+			for(uint16_t i=0, q=buffer.size(); i<q; i++)
+				mspi.write(0);
+		}
+
+		cs = 1;
+	};
+
+	DigitalOut2 cs, dc;
+	SPI &mspi;
+};
+
+/** This is the I2C SSD1306 display driver transport class
+ *
+ */
+class Adafruit_SSD1306_I2c : public Adafruit_SSD1306
+{
+public:
+	#define SSD_I2C_ADDRESS     0x78
+	/** Create a SSD1306 I2C transport display driver instance with the specified RST pin name, the I2C address, as well as the display dimensions
+	 *
+	 * Required parameters
+	 * @param i2c - A reference to an initialized I2C object
+	 * @param RST - The Reset pin name
+	 *
+	 * Optional parameters
+	 * @param i2cAddress - The i2c address of the display
+	 * @param rawHeight - The vertical number of pixels for the display, defaults to 32
+	 * @param rawWidth - The horizonal number of pixels for the display, defaults to 128
+	 */
+	Adafruit_SSD1306_I2c(I2C &i2c, PinName RST, uint8_t i2cAddress = SSD_I2C_ADDRESS, uint8_t rawHeight = 32, uint8_t rawWidth = 128)
+	    : Adafruit_SSD1306(RST, rawHeight, rawWidth)
+	    , mi2c(i2c)
+	    , mi2cAddress(i2cAddress)
+	    {
+		    begin();
+		    splash();
+		    display();
+	    };
+
+	virtual void command(uint8_t c)
+	{
+		char buff[2];
+		buff[0] = 0; // Command Mode
+		buff[1] = c;
+		mi2c.write(mi2cAddress, buff, sizeof(buff));
+	}
+
+	virtual void data(uint8_t c)
+	{
+		char buff[2];
+		buff[0] = 0x40; // Data Mode
+		buff[1] = c;
+		mi2c.write(mi2cAddress, buff, sizeof(buff));
+	};
+
+protected:
+	virtual void sendDisplayBuffer()
+	{
+		char buff[17];
+		buff[0] = 0x40; // Data Mode
+
+		// send display buffer in 16 byte chunks
+		for(uint16_t i=0, q=buffer.size(); i<q; i+=16 ) 
+		{	uint8_t x ;
+
+			// TODO - this will segfault if buffer.size() % 16 != 0
+			for(x=1; x<sizeof(buff); x++) 
+				buff[x] = buffer[i+x-1];
+			mi2c.write(mi2cAddress, buff, sizeof(buff));
+		}
+	};
+
+	I2C &mi2c;
+	uint8_t mi2cAddress;
+};
+
+#endif
\ No newline at end of file
diff --git a/ext/AnalogIn.h b/ext/AnalogIn.h
new file mode 100644
index 0000000..ca1f5e6
--- /dev/null
+++ b/ext/AnalogIn.h
@@ -0,0 +1,103 @@
+/* mbed Microcontroller Library

+ * Copyright (c) 2006-2013 ARM Limited

+ *

+ * Licensed under the Apache License, Version 2.0 (the "License");

+ * you may not use this file except in compliance with the License.

+ * You may obtain a copy of the License at

+ *

+ *     http://www.apache.org/licenses/LICENSE-2.0

+ *

+ * Unless required by applicable law or agreed to in writing, software

+ * distributed under the License is distributed on an "AS IS" BASIS,

+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

+ * See the License for the specific language governing permissions and

+ * limitations under the License.

+ */

+#ifndef MBED_ANALOGIN_H

+#define MBED_ANALOGIN_H

+

+#include "platform.h"

+

+#if DEVICE_ANALOGIN

+

+#include "analogin_api.h"

+

+namespace mbed {

+

+/** An analog input, used for reading the voltage on a pin

+ *

+ * Example:

+ * @code

+ * // Print messages when the AnalogIn is greater than 50%

+ *

+ * #include "mbed.h"

+ *

+ * AnalogIn temperature(p20);

+ *

+ * int main() {

+ *     while(1) {

+ *         if(temperature > 0.5) {

+ *             printf("Too hot! (%f)", temperature.read());

+ *         }

+ *     }

+ * }

+ * @endcode

+ */

+class AnalogIn {

+

+public:

+

+    /** Create an AnalogIn, connected to the specified pin

+     *

+     * @param pin AnalogIn pin to connect to

+     * @param name (optional) A string to identify the object

+     */

+    AnalogIn(PinName pin) {

+        analogin_init(&_adc, pin);

+    }

+

+    /** Read the input voltage, represented as a float in the range [0.0, 1.0]

+     *

+     * @returns A floating-point value representing the current input voltage, measured as a percentage

+     */

+    float read() {

+        return analogin_read(&_adc);

+    }

+

+    /** Read the input voltage, represented as an unsigned short in the range [0x0, 0xFFFF]

+     *

+     * @returns

+     *   16-bit unsigned short representing the current input voltage, normalised to a 16-bit value

+     */

+    unsigned short read_u16() {

+        return analogin_read_u16(&_adc);

+    }

+

+#ifdef MBED_OPERATORS

+    /** An operator shorthand for read()

+     *

+     * The float() operator can be used as a shorthand for read() to simplify common code sequences

+     *

+     * Example:

+     * @code

+     * float x = volume.read();

+     * float x = volume;

+     *

+     * if(volume.read() > 0.25) { ... }

+     * if(volume > 0.25) { ... }

+     * @endcode

+     */

+    operator float() {

+        return read();

+    }

+#endif

+

+protected:

+    analogin_t _adc;

+};

+

+} // namespace mbed

+

+#endif

+

+#endif

diff --git a/ext/AnalogOut.h b/ext/AnalogOut.h
new file mode 100644
index 0000000..7ee0a2b
--- /dev/null
+++ b/ext/AnalogOut.h
@@ -0,0 +1,121 @@
+/* mbed Microcontroller Library

+ * Copyright (c) 2006-2013 ARM Limited

+ *

+ * Licensed under the Apache License, Version 2.0 (the "License");

+ * you may not use this file except in compliance with the License.

+ * You may obtain a copy of the License at

+ *

+ *     http://www.apache.org/licenses/LICENSE-2.0

+ *

+ * Unless required by applicable law or agreed to in writing, software

+ * distributed under the License is distributed on an "AS IS" BASIS,

+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

+ * See the License for the specific language governing permissions and

+ * limitations under the License.

+ */

+#ifndef MBED_ANALOGOUT_H

+#define MBED_ANALOGOUT_H

+

+#include "platform.h"

+

+#if DEVICE_ANALOGOUT

+

+#include "analogout_api.h"

+

+namespace mbed {

+

+/** An analog output, used for setting the voltage on a pin

+ *

+ * Example:

+ * @code

+ * // Make a sawtooth output

+ *

+ * #include "mbed.h"

+ *

+ * AnalogOut tri(p18);

+ * int main() {

+ *     while(1) {

+ *         tri = tri + 0.01;

+ *         wait_us(1);

+ *         if(tri == 1) {

+ *             tri = 0;

+ *         }

+ *     }

+ * }

+ * @endcode

+ */

+class AnalogOut {

+

+public:

+

+    /** Create an AnalogOut connected to the specified pin

+     *

+     *  @param AnalogOut pin to connect to (18)

+     */

+    AnalogOut(PinName pin) {

+        analogout_init(&_dac, pin);

+    }

+

+    /** Set the output voltage, specified as a percentage (float)

+     *

+     *  @param value A floating-point value representing the output voltage,

+     *    specified as a percentage. The value should lie between

+     *    0.0f (representing 0v / 0%) and 1.0f (representing 3.3v / 100%).

+     *    Values outside this range will be saturated to 0.0f or 1.0f.

+     */

+    void write(float value) {

+        analogout_write(&_dac, value);

+    }

+

+    /** Set the output voltage, represented as an unsigned short in the range [0x0, 0xFFFF]

+     *

+     *  @param value 16-bit unsigned short representing the output voltage,

+     *            normalised to a 16-bit value (0x0000 = 0v, 0xFFFF = 3.3v)

+     */

+    void write_u16(unsigned short value) {

+        analogout_write_u16(&_dac, value);

+    }

+

+    /** Return the current output voltage setting, measured as a percentage (float)

+     *

+     *  @returns

+     *    A floating-point value representing the current voltage being output on the pin,

+     *    measured as a percentage. The returned value will lie between

+     *    0.0f (representing 0v / 0%) and 1.0f (representing 3.3v / 100%).

+     *

+     *  @note

+     *    This value may not match exactly the value set by a previous write().

+     */

+    float read() {

+        return analogout_read(&_dac);

+    }

+

+#ifdef MBED_OPERATORS

+    /** An operator shorthand for write()

+     */

+    AnalogOut& operator= (float percent) {

+        write(percent);

+        return *this;

+    }

+

+    AnalogOut& operator= (AnalogOut& rhs) {

+        write(rhs.read());

+        return *this;

+    }

+

+    /** An operator shorthand for read()

+     */

+    operator float() {

+        return read();

+    }

+#endif

+

+protected:

+    dac_t _dac;

+};

+

+} // namespace mbed

+

+#endif

+

+#endif

diff --git a/ext/BusIn.h b/ext/BusIn.h
new file mode 100644
index 0000000..a6d75ec
--- /dev/null
+++ b/ext/BusIn.h
@@ -0,0 +1,98 @@
+/* mbed Microcontroller Library

+ * Copyright (c) 2006-2013 ARM Limited

+ *

+ * Licensed under the Apache License, Version 2.0 (the "License");

+ * you may not use this file except in compliance with the License.

+ * You may obtain a copy of the License at

+ *

+ *     http://www.apache.org/licenses/LICENSE-2.0

+ *

+ * Unless required by applicable law or agreed to in writing, software

+ * distributed under the License is distributed on an "AS IS" BASIS,

+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

+ * See the License for the specific language governing permissions and

+ * limitations under the License.

+ */

+#ifndef MBED_BUSIN_H

+#define MBED_BUSIN_H

+

+#include "platform.h"

+#include "DigitalIn.h"

+

+namespace mbed {

+

+/** A digital input bus, used for reading the state of a collection of pins

+ */

+class BusIn {

+

+public:

+    /* Group: Configuration Methods */

+

+    /** Create an BusIn, connected to the specified pins

+     *

+     * @param <n> DigitalIn pin to connect to bus bit <n> (p5-p30, NC)

+     *

+     * @note

+     *  It is only required to specify as many pin variables as is required

+     *  for the bus; the rest will default to NC (not connected)

+     */

+    BusIn(PinName p0, PinName p1 = NC, PinName p2 = NC, PinName p3 = NC,

+          PinName p4 = NC, PinName p5 = NC, PinName p6 = NC, PinName p7 = NC,

+          PinName p8 = NC, PinName p9 = NC, PinName p10 = NC, PinName p11 = NC,

+          PinName p12 = NC, PinName p13 = NC, PinName p14 = NC, PinName p15 = NC);

+

+    BusIn(PinName pins[16]);

+

+    virtual ~BusIn();

+

+    /** Read the value of the input bus

+     *

+     *  @returns

+     *   An integer with each bit corresponding to the value read from the associated DigitalIn pin

+     */

+    int read();

+

+    /** Set the input pin mode

+     *

+     *  @param mode PullUp, PullDown, PullNone

+     */

+    void mode(PinMode pull);

+

+    /** Binary mask of bus pins connected to actual pins (not NC pins)

+     *  If bus pin is in NC state make corresponding bit will be cleared (set to 0), else bit will be set to 1

+     *

+     *  @returns

+     *    Binary mask of connected pins

+     */

+    int mask() {

+        return _nc_mask;

+    }

+

+#ifdef MBED_OPERATORS

+    /** A shorthand for read()

+     */

+    operator int();

+

+    /** Access to particular bit in random-iterator fashion

+     */

+    DigitalIn & operator[] (int index);

+#endif

+

+protected:

+    DigitalIn* _pin[16];

+

+    /** Mask of bus's NC pins

+     * If bit[n] is set to 1 - pin is connected

+     * if bit[n] is cleared - pin is not connected (NC)

+     */

+    int _nc_mask;

+

+    /* disallow copy constructor and assignment operators */

+private:

+    BusIn(const BusIn&);

+    BusIn & operator = (const BusIn&);

+};

+

+} // namespace mbed

+

+#endif

diff --git a/ext/BusInOut.h b/ext/BusInOut.h
new file mode 100644
index 0000000..42f2d17
--- /dev/null
+++ b/ext/BusInOut.h
@@ -0,0 +1,117 @@
+/* mbed Microcontroller Library

+ * Copyright (c) 2006-2013 ARM Limited

+ *

+ * Licensed under the Apache License, Version 2.0 (the "License");

+ * you may not use this file except in compliance with the License.

+ * You may obtain a copy of the License at

+ *

+ *     http://www.apache.org/licenses/LICENSE-2.0

+ *

+ * Unless required by applicable law or agreed to in writing, software

+ * distributed under the License is distributed on an "AS IS" BASIS,

+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

+ * See the License for the specific language governing permissions and

+ * limitations under the License.

+ */

+#ifndef MBED_BUSINOUT_H

+#define MBED_BUSINOUT_H

+

+#include "DigitalInOut.h"

+

+namespace mbed {

+

+/** A digital input output bus, used for setting the state of a collection of pins

+ */

+class BusInOut {

+

+public:

+

+    /** Create an BusInOut, connected to the specified pins

+     *

+     *  @param p<n> DigitalInOut pin to connect to bus bit p<n> (p5-p30, NC)

+     *

+     *  @note

+     *  It is only required to specify as many pin variables as is required

+     *  for the bus; the rest will default to NC (not connected)

+     */

+    BusInOut(PinName p0, PinName p1 = NC, PinName p2 = NC, PinName p3 = NC,

+             PinName p4 = NC, PinName p5 = NC, PinName p6 = NC, PinName p7 = NC,

+             PinName p8 = NC, PinName p9 = NC, PinName p10 = NC, PinName p11 = NC,

+             PinName p12 = NC, PinName p13 = NC, PinName p14 = NC, PinName p15 = NC);

+

+    BusInOut(PinName pins[16]);

+

+    virtual ~BusInOut();

+

+    /* Group: Access Methods */

+

+    /** Write the value to the output bus

+     *

+     *  @param value An integer specifying a bit to write for every corresponding DigitalInOut pin

+     */

+    void write(int value);

+

+    /** Read the value currently output on the bus

+     *

+     *  @returns

+     *    An integer with each bit corresponding to associated DigitalInOut pin setting

+     */

+    int read();

+

+    /** Set as an output

+     */

+    void output();

+

+    /** Set as an input

+     */

+    void input();

+

+    /** Set the input pin mode

+     *

+     *  @param mode PullUp, PullDown, PullNone

+     */

+    void mode(PinMode pull);

+

+    /** Binary mask of bus pins connected to actual pins (not NC pins)

+     *  If bus pin is in NC state make corresponding bit will be cleared (set to 0), else bit will be set to 1

+     *

+     *  @returns

+     *    Binary mask of connected pins

+     */

+    int mask() {

+        return _nc_mask;

+    }

+

+#ifdef MBED_OPERATORS

+     /** A shorthand for write()

+     */

+    BusInOut& operator= (int v);

+    BusInOut& operator= (BusInOut& rhs);

+

+    /** Access to particular bit in random-iterator fashion

+    */

+    DigitalInOut& operator[] (int index);

+

+    /** A shorthand for read()

+     */

+    operator int();

+#endif

+

+protected:

+    DigitalInOut* _pin[16];

+

+    /** Mask of bus's NC pins

+     * If bit[n] is set to 1 - pin is connected

+     * if bit[n] is cleared - pin is not connected (NC)

+     */

+    int _nc_mask;

+

+    /* disallow copy constructor and assignment operators */

+private:

+    BusInOut(const BusInOut&);

+    BusInOut & operator = (const BusInOut&);

+};

+

+} // namespace mbed

+

+#endif

diff --git a/ext/BusOut.h b/ext/BusOut.h
new file mode 100644
index 0000000..4823eb1
--- /dev/null
+++ b/ext/BusOut.h
@@ -0,0 +1,101 @@
+/* mbed Microcontroller Library

+ * Copyright (c) 2006-2013 ARM Limited

+ *

+ * Licensed under the Apache License, Version 2.0 (the "License");

+ * you may not use this file except in compliance with the License.

+ * You may obtain a copy of the License at

+ *

+ *     http://www.apache.org/licenses/LICENSE-2.0

+ *

+ * Unless required by applicable law or agreed to in writing, software

+ * distributed under the License is distributed on an "AS IS" BASIS,

+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

+ * See the License for the specific language governing permissions and

+ * limitations under the License.

+ */

+#ifndef MBED_BUSOUT_H

+#define MBED_BUSOUT_H

+

+#include "DigitalOut.h"

+

+namespace mbed {

+

+/** A digital output bus, used for setting the state of a collection of pins

+ */

+class BusOut {

+

+public:

+

+    /** Create an BusOut, connected to the specified pins

+     *

+     *  @param p<n> DigitalOut pin to connect to bus bit <n> (p5-p30, NC)

+     *

+     *  @note

+     *  It is only required to specify as many pin variables as is required

+     *  for the bus; the rest will default to NC (not connected)

+     */

+    BusOut(PinName p0, PinName p1 = NC, PinName p2 = NC, PinName p3 = NC,

+           PinName p4 = NC, PinName p5 = NC, PinName p6 = NC, PinName p7 = NC,

+           PinName p8 = NC, PinName p9 = NC, PinName p10 = NC, PinName p11 = NC,

+           PinName p12 = NC, PinName p13 = NC, PinName p14 = NC, PinName p15 = NC);

+

+    BusOut(PinName pins[16]);

+

+    virtual ~BusOut();

+

+    /** Write the value to the output bus

+     *

+     *  @param value An integer specifying a bit to write for every corresponding DigitalOut pin

+     */

+    void write(int value);

+

+    /** Read the value currently output on the bus

+     *

+     *  @returns

+     *    An integer with each bit corresponding to associated DigitalOut pin setting

+     */

+    int read();

+

+    /** Binary mask of bus pins connected to actual pins (not NC pins)

+     *  If bus pin is in NC state make corresponding bit will be cleared (set to 0), else bit will be set to 1

+     *

+     *  @returns

+     *    Binary mask of connected pins

+     */

+    int mask() {

+        return _nc_mask;

+    }

+

+#ifdef MBED_OPERATORS

+    /** A shorthand for write()

+     */

+    BusOut& operator= (int v);

+    BusOut& operator= (BusOut& rhs);

+

+    /** Access to particular bit in random-iterator fashion

+     */

+    DigitalOut& operator[] (int index);

+

+    /** A shorthand for read()

+     */

+    operator int();

+#endif

+

+protected:

+    DigitalOut* _pin[16];

+

+    /** Mask of bus's NC pins

+     * If bit[n] is set to 1 - pin is connected

+     * if bit[n] is cleared - pin is not connected (NC)

+     */

+    int _nc_mask;

+

+   /* disallow copy constructor and assignment operators */

+private:

+    BusOut(const BusOut&);

+    BusOut & operator = (const BusOut&);

+};

+

+} // namespace mbed

+

+#endif

diff --git a/ext/CAN.h b/ext/CAN.h
new file mode 100644
index 0000000..5b6d381
--- /dev/null
+++ b/ext/CAN.h
@@ -0,0 +1,243 @@
+/* mbed Microcontroller Library

+ * Copyright (c) 2006-2013 ARM Limited

+ *

+ * Licensed under the Apache License, Version 2.0 (the "License");

+ * you may not use this file except in compliance with the License.

+ * You may obtain a copy of the License at

+ *

+ *     http://www.apache.org/licenses/LICENSE-2.0

+ *

+ * Unless required by applicable law or agreed to in writing, software

+ * distributed under the License is distributed on an "AS IS" BASIS,

+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

+ * See the License for the specific language governing permissions and

+ * limitations under the License.

+ */

+#ifndef MBED_CAN_H

+#define MBED_CAN_H

+

+#include "platform.h"

+

+#if DEVICE_CAN

+

+#include "can_api.h"

+#include "can_helper.h"

+#include "FunctionPointer.h"

+

+namespace mbed {

+

+/** CANMessage class

+ */

+class CANMessage : public CAN_Message {

+

+public:

+    /** Creates empty CAN message.

+     */

+    CANMessage() : CAN_Message() {

+        len    = 8;

+        type   = CANData;

+        format = CANStandard;

+        id     = 0;

+        memset(data, 0, 8);

+    }

+

+    /** Creates CAN message with specific content.

+     */

+    CANMessage(int _id, const char *_data, char _len = 8, CANType _type = CANData, CANFormat _format = CANStandard) {

+      len    = _len & 0xF;

+      type   = _type;

+      format = _format;

+      id     = _id;

+      memcpy(data, _data, _len);

+    }

+

+    /** Creates CAN remote message.

+     */

+    CANMessage(int _id, CANFormat _format = CANStandard) {

+      len    = 0;

+      type   = CANRemote;

+      format = _format;

+      id     = _id;

+      memset(data, 0, 8);

+    }

+};

+

+/** A can bus client, used for communicating with can devices

+ */

+class CAN {

+

+public:

+    /** Creates an CAN interface connected to specific pins.

+     *

+     *  @param rd read from transmitter

+     *  @param td transmit to transmitter

+     *

+     * Example:

+     * @code

+     * #include "mbed.h"

+     *

+     * Ticker ticker;

+     * DigitalOut led1(LED1);

+     * DigitalOut led2(LED2);

+     * CAN can1(p9, p10);

+     * CAN can2(p30, p29);

+     *

+     * char counter = 0;

+     *

+     * void send() {

+     *     if(can1.write(CANMessage(1337, &counter, 1))) {

+     *         printf("Message sent: %d\n", counter);

+     *         counter++;

+     *     }

+     *     led1 = !led1;

+     * }

+     *

+     * int main() {

+     *     ticker.attach(&send, 1);

+     *    CANMessage msg;

+     *     while(1) {

+     *         if(can2.read(msg)) {

+     *             printf("Message received: %d\n\n", msg.data[0]);

+     *             led2 = !led2;

+     *         }

+     *         wait(0.2);

+     *     }

+     * }

+     * @endcode

+     */

+    CAN(PinName rd, PinName td);

+    virtual ~CAN();

+

+    /** Set the frequency of the CAN interface

+     *

+     *  @param hz The bus frequency in hertz

+     *

+     *  @returns

+     *    1 if successful,

+     *    0 otherwise

+     */

+    int frequency(int hz);

+

+    /** Write a CANMessage to the bus.

+     *

+     *  @param msg The CANMessage to write.

+     *

+     *  @returns

+     *    0 if write failed,

+     *    1 if write was successful

+     */

+    int write(CANMessage msg);

+

+    /** Read a CANMessage from the bus.

+     *

+     *  @param msg A CANMessage to read to.

+     *  @param handle message filter handle (0 for any message)

+     *

+     *  @returns

+     *    0 if no message arrived,

+     *    1 if message arrived

+     */

+    int read(CANMessage &msg, int handle = 0);

+

+    /** Reset CAN interface.

+     *

+     * To use after error overflow.

+     */

+    void reset();

+

+    /** Puts or removes the CAN interface into silent monitoring mode

+     *

+     *  @param silent boolean indicating whether to go into silent mode or not

+     */

+    void monitor(bool silent);

+

+    enum Mode {

+        Reset = 0,

+        Normal,

+        Silent,

+        LocalTest,

+        GlobalTest,

+        SilentTest

+    };

+

+    /** Change CAN operation to the specified mode

+     *

+     *  @param mode The new operation mode (CAN::Normal, CAN::Silent, CAN::LocalTest, CAN::GlobalTest, CAN::SilentTest)

+     *

+     *  @returns

+     *    0 if mode change failed or unsupported,

+     *    1 if mode change was successful

+     */

+    int mode(Mode mode);

+

+    /** Filter out incomming messages

+     *

+     *  @param id the id to filter on

+     *  @param mask the mask applied to the id

+     *  @param format format to filter on (Default CANAny)

+     *  @param handle message filter handle (Optional)

+     *

+     *  @returns

+     *    0 if filter change failed or unsupported,

+     *    new filter handle if successful

+     */

+    int filter(unsigned int id, unsigned int mask, CANFormat format = CANAny, int handle = 0);

+

+    /** Returns number of read errors to detect read overflow errors.

+     */

+    unsigned char rderror();

+

+    /** Returns number of write errors to detect write overflow errors.

+     */

+    unsigned char tderror();

+

+    enum IrqType {

+        RxIrq = 0,

+        TxIrq,

+        EwIrq,

+        DoIrq,

+        WuIrq,

+        EpIrq,

+        AlIrq,

+        BeIrq,

+        IdIrq

+    };

+

+    /** Attach a function to call whenever a CAN frame received interrupt is

+     *  generated.

+     *

+     *  @param fptr A pointer to a void function, or 0 to set as none

+     *  @param event Which CAN interrupt to attach the member function to (CAN::RxIrq for message received, CAN::TxIrq for transmitted or aborted, CAN::EwIrq for error warning, CAN::DoIrq for data overrun, CAN::WuIrq for wake-up, CAN::EpIrq for error passive, CAN::AlIrq for arbitration lost, CAN::BeIrq for bus error)

+     */

+    void attach(void (*fptr)(void), IrqType type=RxIrq);

+

+   /** Attach a member function to call whenever a CAN frame received interrupt

+    *  is generated.

+    *

+    *  @param tptr pointer to the object to call the member function on

+    *  @param mptr pointer to the member function to be called

+    *  @param event Which CAN interrupt to attach the member function to (CAN::RxIrq for message received, TxIrq for transmitted or aborted, EwIrq for error warning, DoIrq for data overrun, WuIrq for wake-up, EpIrq for error passive, AlIrq for arbitration lost, BeIrq for bus error)

+    */

+   template<typename T>

+   void attach(T* tptr, void (T::*mptr)(void), IrqType type=RxIrq) {

+        if((mptr != NULL) && (tptr != NULL)) {

+            _irq[type].attach(tptr, mptr);

+            can_irq_set(&_can, (CanIrqType)type, 1);

+        }

+        else {

+            can_irq_set(&_can, (CanIrqType)type, 0);

+        }

+    }

+

+    static void _irq_handler(uint32_t id, CanIrqType type);

+

+protected:

+    can_t           _can;

+    FunctionPointer _irq[9];

+};

+

+} // namespace mbed

+

+#endif

+

+#endif    // MBED_CAN_H

diff --git a/ext/CThunk.h b/ext/CThunk.h
new file mode 100644
index 0000000..96f3331
--- /dev/null
+++ b/ext/CThunk.h
@@ -0,0 +1,202 @@
+/* General C++ Object Thunking class
+ *
+ * - allows direct callbacks to non-static C++ class functions
+ * - keeps track for the corresponding class instance
+ * - supports an optional context parameter for the called function
+ * - ideally suited for class object receiving interrupts (NVIC_SetVector)
+ *
+ * Copyright (c) 2014-2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef __CTHUNK_H__
+#define __CTHUNK_H__
+
+#define CTHUNK_ADDRESS 1
+
+#if defined(__CORTEX_M3) || defined(__CORTEX_M4) || defined(__thumb2__)
+#define CTHUNK_VARIABLES volatile uint32_t code[1]
+/**
+* CTHUNK disassembly for Cortex-M3/M4 (thumb2):
+* * ldm.w pc,{r0,r1,r2,pc}
+*
+* This instruction loads the arguments for the static thunking function to r0-r2, and
+* branches to that function by loading its address into PC.
+*
+* This is safe for both regular calling and interrupt calling, since it only touches scratch registers
+* which should be saved by the caller, and are automatically saved as part of the IRQ context switch.
+*/
+#define CTHUNK_ASSIGMENT m_thunk.code[0] = 0x8007E89F
+
+#elif defined(__CORTEX_M0PLUS) || defined(__CORTEX_M0)
+/*
+* CTHUNK disassembly for Cortex M0 (thumb):
+* * push {r0,r1,r2,r3,r4,lr} save touched registers and return address
+* * movs r4,#4 set up address to load arguments from (immediately following this code block) (1)
+* * add r4,pc set up address to load arguments from (immediately following this code block) (2)
+* * ldm r4!,{r0,r1,r2,r3} load arguments for static thunk function
+* * blx r3 call static thunk function
+* * pop {r0,r1,r2,r3,r4,pc} restore scratch registers and return from function
+*/
+#define CTHUNK_VARIABLES volatile uint32_t code[3]
+#define CTHUNK_ASSIGMENT do {                              \
+                             m_thunk.code[0] = 0x2404B51F; \
+                             m_thunk.code[1] = 0xCC0F447C; \
+                             m_thunk.code[2] = 0xBD1F4798; \
+                         } while (0)
+
+#else
+#error "Target is not currently suported."
+#endif
+
+/* IRQ/Exception compatible thunk entry function */
+typedef void (*CThunkEntry)(void);
+
+template<class T>
+class CThunk
+{
+    public:
+        typedef void (T::*CCallbackSimple)(void);
+        typedef void (T::*CCallback)(void* context);
+
+        inline CThunk(T *instance)
+        {
+            init(instance, NULL, NULL);
+        }
+
+        inline CThunk(T *instance, CCallback callback)
+        {
+            init(instance, callback, NULL);
+        }
+
+        ~CThunk() {
+
+        }
+
+        inline CThunk(T *instance, CCallbackSimple callback)
+        {
+            init(instance, (CCallback)callback, NULL);
+        }
+
+        inline CThunk(T &instance, CCallback callback)
+        {
+            init(instance, callback, NULL);
+        }
+
+        inline CThunk(T &instance, CCallbackSimple callback)
+        {
+            init(instance, (CCallback)callback, NULL);
+        }
+
+        inline CThunk(T &instance, CCallback callback, void* context)
+        {
+            init(instance, callback, context);
+        }
+
+        inline void callback(CCallback callback)
+        {
+            m_callback = callback;
+        }
+
+        inline void callback(CCallbackSimple callback)
+        {
+            m_callback = (CCallback)callback;
+        }
+
+        inline void context(void* context)
+        {
+            m_thunk.context = (uint32_t)context;
+        }
+
+        inline void context(uint32_t context)
+        {
+            m_thunk.context = context;
+        }
+        
+        inline uint32_t entry(void)
+        {
+            return (((uint32_t)&m_thunk)|CTHUNK_ADDRESS);
+        }
+
+        /* get thunk entry point for connecting rhunk to an IRQ table */
+        inline operator CThunkEntry(void)
+        {
+            return (CThunkEntry)entry();
+        }
+
+        /* get thunk entry point for connecting rhunk to an IRQ table */
+        inline operator uint32_t(void)
+        {
+            return entry();
+        }
+
+        /* simple test function */
+        inline void call(void)
+        {
+            (((CThunkEntry)(entry()))());
+        }
+
+    private:
+        T* m_instance;
+        volatile CCallback m_callback;
+
+// TODO: this needs proper fix, to refactor toolchain header file and all its use
+// PACKED there is not defined properly for IAR
+#if defined (__ICCARM__)
+        typedef __packed struct
+        {
+            CTHUNK_VARIABLES;
+            volatile uint32_t instance;
+            volatile uint32_t context;
+            volatile uint32_t callback;
+            volatile uint32_t trampoline;
+        }  CThunkTrampoline;
+#else
+        typedef struct
+        {
+            CTHUNK_VARIABLES;
+            volatile uint32_t instance;
+            volatile uint32_t context;
+            volatile uint32_t callback;
+            volatile uint32_t trampoline;
+        } __attribute__((__packed__)) CThunkTrampoline;
+#endif
+
+        static void trampoline(T* instance, void* context, CCallback* callback)
+        {
+            if(instance && *callback) {
+                (static_cast<T*>(instance)->**callback)(context);
+            }
+        }
+
+        volatile CThunkTrampoline m_thunk;
+
+        inline void init(T *instance, CCallback callback, void* context)
+        {
+            /* remember callback - need to add this level of redirection
+               as pointer size for member functions differs between platforms */
+            m_callback = callback;
+
+            /* populate thunking trampoline */
+            CTHUNK_ASSIGMENT;
+            m_thunk.context = (uint32_t)context;
+            m_thunk.instance = (uint32_t)instance;
+            m_thunk.callback = (uint32_t)&m_callback;
+            m_thunk.trampoline = (uint32_t)&trampoline;
+
+            __ISB();
+            __DSB();
+        }
+};
+
+#endif/*__CTHUNK_H__*/
diff --git a/ext/CallChain.h b/ext/CallChain.h
new file mode 100644
index 0000000..37b000a
--- /dev/null
+++ b/ext/CallChain.h
@@ -0,0 +1,181 @@
+/* mbed Microcontroller Library

+ * Copyright (c) 2006-2013 ARM Limited

+ *

+ * Licensed under the Apache License, Version 2.0 (the "License");

+ * you may not use this file except in compliance with the License.

+ * You may obtain a copy of the License at

+ *

+ *     http://www.apache.org/licenses/LICENSE-2.0

+ *

+ * Unless required by applicable law or agreed to in writing, software

+ * distributed under the License is distributed on an "AS IS" BASIS,

+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

+ * See the License for the specific language governing permissions and

+ * limitations under the License.

+ */

+#ifndef MBED_CALLCHAIN_H

+#define MBED_CALLCHAIN_H

+

+#include "FunctionPointer.h"

+#include <string.h>

+

+namespace mbed {

+

+/** Group one or more functions in an instance of a CallChain, then call them in

+ * sequence using CallChain::call(). Used mostly by the interrupt chaining code,

+ * but can be used for other purposes.

+ *

+ * Example:

+ * @code

+ * #include "mbed.h"

+ *

+ * CallChain chain;

+ *

+ * void first(void) {

+ *     printf("'first' function.\n");

+ * }

+ *

+ * void second(void) {

+ *     printf("'second' function.\n");

+ * }

+ *

+ * class Test {

+ * public:

+ *     void f(void) {

+ *         printf("A::f (class member).\n");

+ *     }

+ * };

+ *

+ * int main() {

+ *     Test test;

+ *

+ *     chain.add(second);

+ *     chain.add_front(first);

+ *     chain.add(&test, &Test::f);

+ *     chain.call();

+ * }

+ * @endcode

+ */

+

+typedef FunctionPointer* pFunctionPointer_t;

+

+class CallChain {

+public:

+    /** Create an empty chain

+     *

+     *  @param size (optional) Initial size of the chain

+     */

+    CallChain(int size = 4);

+    virtual ~CallChain();

+

+    /** Add a function at the end of the chain

+     *

+     *  @param function A pointer to a void function

+     *

+     *  @returns

+     *  The function object created for 'function'

+     */

+    pFunctionPointer_t add(void (*function)(void));

+

+    /** Add a function at the end of the chain

+     *

+     *  @param tptr pointer to the object to call the member function on

+     *  @param mptr pointer to the member function to be called

+     *

+     *  @returns

+     *  The function object created for 'tptr' and 'mptr'

+     */

+    template<typename T>

+    pFunctionPointer_t add(T *tptr, void (T::*mptr)(void)) {

+        return common_add(new FunctionPointer(tptr, mptr));

+    }

+

+    /** Add a function at the beginning of the chain

+     *

+     *  @param function A pointer to a void function

+     *

+     *  @returns

+     *  The function object created for 'function'

+     */

+    pFunctionPointer_t add_front(void (*function)(void));

+

+    /** Add a function at the beginning of the chain

+     *

+     *  @param tptr pointer to the object to call the member function on

+     *  @param mptr pointer to the member function to be called

+     *

+     *  @returns

+     *  The function object created for 'tptr' and 'mptr'

+     */

+    template<typename T>

+    pFunctionPointer_t add_front(T *tptr, void (T::*mptr)(void)) {

+        return common_add_front(new FunctionPointer(tptr, mptr));

+    }

+

+    /** Get the number of functions in the chain

+     */

+    int size() const;

+

+    /** Get a function object from the chain

+     *

+     *  @param i function object index

+     *

+     *  @returns

+     *  The function object at position 'i' in the chain

+     */

+    pFunctionPointer_t get(int i) const;

+

+    /** Look for a function object in the call chain

+     *

+     *  @param f the function object to search

+     *

+     *  @returns

+     *  The index of the function object if found, -1 otherwise.

+     */

+    int find(pFunctionPointer_t f) const;

+

+    /** Clear the call chain (remove all functions in the chain).

+     */

+    void clear();

+

+    /** Remove a function object from the chain

+     *

+     *  @arg f the function object to remove

+     *

+     *  @returns

+     *  true if the function object was found and removed, false otherwise.

+     */

+    bool remove(pFunctionPointer_t f);

+

+    /** Call all the functions in the chain in sequence

+     */

+    void call();

+

+#ifdef MBED_OPERATORS

+    void operator ()(void) {

+        call();

+    }

+    pFunctionPointer_t operator [](int i) const {

+        return get(i);

+    }

+#endif

+

+private:

+    void _check_size();

+    pFunctionPointer_t common_add(pFunctionPointer_t pf);

+    pFunctionPointer_t common_add_front(pFunctionPointer_t pf);

+

+    pFunctionPointer_t* _chain;

+    int _size;

+    int _elements;

+

+    /* disallow copy constructor and assignment operators */

+private:

+    CallChain(const CallChain&);

+    CallChain & operator = (const CallChain&);

+};

+

+} // namespace mbed

+

+#endif

+

diff --git a/ext/CircularBuffer.h b/ext/CircularBuffer.h
new file mode 100644
index 0000000..e9f3f1c
--- /dev/null
+++ b/ext/CircularBuffer.h
@@ -0,0 +1,98 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_CIRCULARBUFFER_H
+#define MBED_CIRCULARBUFFER_H
+
+namespace mbed {
+
+/** Templated Circular buffer class
+ */
+template<typename T, uint32_t BufferSize, typename CounterType = uint32_t>
+class CircularBuffer {
+public:
+    CircularBuffer() : _head(0), _tail(0), _full(false) {
+    }
+
+    ~CircularBuffer() {
+    }
+
+    /** Push the transaction to the buffer. This overwrites the buffer if it's
+     *  full
+     *
+     * @param data Data to be pushed to the buffer
+     */
+    void push(const T& data) {
+        if (full()) {
+            _tail++;
+            _tail %= BufferSize;
+        }
+        _pool[_head++] = data;
+        _head %= BufferSize;
+        if (_head == _tail) {
+            _full = true;
+        }
+    }
+
+    /** Pop the transaction from the buffer
+     *
+     * @param data Data to be pushed to the buffer
+     * @return True if the buffer is not empty and data contains a transaction, false otherwise
+     */
+    bool pop(T& data) {
+        if (!empty()) {
+            data = _pool[_tail++];
+            _tail %= BufferSize;
+            _full = false;
+            return true;
+        }
+        return false;
+    }
+
+    /** Check if the buffer is empty
+     *
+     * @return True if the buffer is empty, false if not
+     */
+    bool empty() {
+        return (_head == _tail) && !_full;
+    }
+
+    /** Check if the buffer is full
+     *
+     * @return True if the buffer is full, false if not
+     */
+    bool full() {
+        return _full;
+    }
+
+    /** Reset the buffer
+     *
+     */
+    void reset() {
+        _head = 0;
+        _tail = 0;
+        _full = false;
+    }
+
+private:
+    T _pool[BufferSize];
+    volatile CounterType _head;
+    volatile CounterType _tail;
+    volatile bool _full;
+};
+
+}
+
+#endif
diff --git a/ext/DigitalIn.h b/ext/DigitalIn.h
new file mode 100644
index 0000000..8706fe1
--- /dev/null
+++ b/ext/DigitalIn.h
@@ -0,0 +1,107 @@
+/* mbed Microcontroller Library

+ * Copyright (c) 2006-2013 ARM Limited

+ *

+ * Licensed under the Apache License, Version 2.0 (the "License");

+ * you may not use this file except in compliance with the License.

+ * You may obtain a copy of the License at

+ *

+ *     http://www.apache.org/licenses/LICENSE-2.0

+ *

+ * Unless required by applicable law or agreed to in writing, software

+ * distributed under the License is distributed on an "AS IS" BASIS,

+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

+ * See the License for the specific language governing permissions and

+ * limitations under the License.

+ */

+#ifndef MBED_DIGITALIN_H

+#define MBED_DIGITALIN_H

+

+#include "platform.h"

+

+#include "gpio_api.h"

+

+namespace mbed {

+

+/** A digital input, used for reading the state of a pin

+ *

+ * Example:

+ * @code

+ * // Flash an LED while a DigitalIn is true

+ *

+ * #include "mbed.h"

+ *

+ * DigitalIn enable(p5);

+ * DigitalOut led(LED1);

+ *

+ * int main() {

+ *     while(1) {

+ *         if(enable) {

+ *             led = !led;

+ *         }

+ *         wait(0.25);

+ *     }

+ * }

+ * @endcode

+ */

+class DigitalIn {

+

+public:

+    /** Create a DigitalIn connected to the specified pin

+     *

+     *  @param pin DigitalIn pin to connect to

+     */

+    DigitalIn(PinName pin) : gpio() {

+        gpio_init_in(&gpio, pin);

+    }

+

+    /** Create a DigitalIn connected to the specified pin

+     *

+     *  @param pin DigitalIn pin to connect to

+     *  @param mode the initial mode of the pin

+     */

+    DigitalIn(PinName pin, PinMode mode) : gpio() {

+        gpio_init_in_ex(&gpio, pin, mode);

+    }

+    /** Read the input, represented as 0 or 1 (int)

+     *

+     *  @returns

+     *    An integer representing the state of the input pin,

+     *    0 for logical 0, 1 for logical 1

+     */

+    int read() {

+        return gpio_read(&gpio);

+    }

+

+    /** Set the input pin mode

+     *

+     *  @param mode PullUp, PullDown, PullNone, OpenDrain

+     */

+    void mode(PinMode pull) {

+        gpio_mode(&gpio, pull);

+    }

+

+    /** Return the output setting, represented as 0 or 1 (int)

+     *

+     *  @returns

+     *    Non zero value if pin is connected to uc GPIO

+     *    0 if gpio object was initialized with NC

+     */

+    int is_connected() {

+        return gpio_is_connected(&gpio);

+    }

+

+#ifdef MBED_OPERATORS

+    /** An operator shorthand for read()

+     */

+    operator int() {

+        return read();

+    }

+#endif

+

+protected:

+    gpio_t gpio;

+};

+

+} // namespace mbed

+

+#endif

diff --git a/ext/DigitalInOut.h b/ext/DigitalInOut.h
new file mode 100644
index 0000000..50b8a27
--- /dev/null
+++ b/ext/DigitalInOut.h
@@ -0,0 +1,124 @@
+/* mbed Microcontroller Library

+ * Copyright (c) 2006-2013 ARM Limited

+ *

+ * Licensed under the Apache License, Version 2.0 (the "License");

+ * you may not use this file except in compliance with the License.

+ * You may obtain a copy of the License at

+ *

+ *     http://www.apache.org/licenses/LICENSE-2.0

+ *

+ * Unless required by applicable law or agreed to in writing, software

+ * distributed under the License is distributed on an "AS IS" BASIS,

+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

+ * See the License for the specific language governing permissions and

+ * limitations under the License.

+ */

+#ifndef MBED_DIGITALINOUT_H

+#define MBED_DIGITALINOUT_H

+

+#include "platform.h"

+

+#include "gpio_api.h"

+

+namespace mbed {

+

+/** A digital input/output, used for setting or reading a bi-directional pin

+ */

+class DigitalInOut {

+

+public:

+    /** Create a DigitalInOut connected to the specified pin

+     *

+     *  @param pin DigitalInOut pin to connect to

+     */

+    DigitalInOut(PinName pin) : gpio() {

+        gpio_init_in(&gpio, pin);

+    }

+

+    /** Create a DigitalInOut connected to the specified pin

+     *

+     *  @param pin DigitalInOut pin to connect to

+     *  @param direction the initial direction of the pin

+     *  @param mode the initial mode of the pin

+     *  @param value the initial value of the pin if is an output

+     */

+    DigitalInOut(PinName pin, PinDirection direction, PinMode mode, int value) : gpio() {

+        gpio_init_inout(&gpio, pin, direction, mode, value);

+    }

+

+    /** Set the output, specified as 0 or 1 (int)

+     *

+     *  @param value An integer specifying the pin output value,

+     *      0 for logical 0, 1 (or any other non-zero value) for logical 1

+     */

+    void write(int value) {

+        gpio_write(&gpio, value);

+    }

+

+    /** Return the output setting, represented as 0 or 1 (int)

+     *

+     *  @returns

+     *    an integer representing the output setting of the pin if it is an output,

+     *    or read the input if set as an input

+     */

+    int read() {

+        return gpio_read(&gpio);

+    }

+

+    /** Set as an output

+     */

+    void output() {

+        gpio_dir(&gpio, PIN_OUTPUT);

+    }

+

+    /** Set as an input

+     */

+    void input() {

+        gpio_dir(&gpio, PIN_INPUT);

+    }

+

+    /** Set the input pin mode

+     *

+     *  @param mode PullUp, PullDown, PullNone, OpenDrain

+     */

+    void mode(PinMode pull) {

+        gpio_mode(&gpio, pull);

+    }

+

+    /** Return the output setting, represented as 0 or 1 (int)

+     *

+     *  @returns

+     *    Non zero value if pin is connected to uc GPIO

+     *    0 if gpio object was initialized with NC

+     */

+    int is_connected() {

+        return gpio_is_connected(&gpio);

+    }

+

+#ifdef MBED_OPERATORS

+    /** A shorthand for write()

+     */

+    DigitalInOut& operator= (int value) {

+        write(value);

+        return *this;

+    }

+

+    DigitalInOut& operator= (DigitalInOut& rhs) {

+        write(rhs.read());

+        return *this;

+    }

+

+    /** A shorthand for read()

+     */

+    operator int() {

+        return read();

+    }

+#endif

+

+protected:

+    gpio_t gpio;

+};

+

+} // namespace mbed

+

+#endif

diff --git a/ext/DigitalOut.h b/ext/DigitalOut.h
new file mode 100644
index 0000000..fd848ef
--- /dev/null
+++ b/ext/DigitalOut.h
@@ -0,0 +1,116 @@
+/* mbed Microcontroller Library

+ * Copyright (c) 2006-2013 ARM Limited

+ *

+ * Licensed under the Apache License, Version 2.0 (the "License");

+ * you may not use this file except in compliance with the License.

+ * You may obtain a copy of the License at

+ *

+ *     http://www.apache.org/licenses/LICENSE-2.0

+ *

+ * Unless required by applicable law or agreed to in writing, software

+ * distributed under the License is distributed on an "AS IS" BASIS,

+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

+ * See the License for the specific language governing permissions and

+ * limitations under the License.

+ */

+#ifndef MBED_DIGITALOUT_H

+#define MBED_DIGITALOUT_H

+

+#include "platform.h"

+#include "gpio_api.h"

+

+namespace mbed {

+

+/** A digital output, used for setting the state of a pin

+ *

+ * Example:

+ * @code

+ * // Toggle a LED

+ * #include "mbed.h"

+ *

+ * DigitalOut led(LED1);

+ *

+ * int main() {

+ *     while(1) {

+ *         led = !led;

+ *         wait(0.2);

+ *     }

+ * }

+ * @endcode

+ */

+class DigitalOut {

+

+public:

+    /** Create a DigitalOut connected to the specified pin

+     *

+     *  @param pin DigitalOut pin to connect to

+     */

+    DigitalOut(PinName pin) : gpio() {

+        gpio_init_out(&gpio, pin);

+    }

+

+    /** Create a DigitalOut connected to the specified pin

+     *

+     *  @param pin DigitalOut pin to connect to

+     *  @param value the initial pin value

+     */

+    DigitalOut(PinName pin, int value) : gpio() {

+        gpio_init_out_ex(&gpio, pin, value);

+    }

+

+    /** Set the output, specified as 0 or 1 (int)

+     *

+     *  @param value An integer specifying the pin output value,

+     *      0 for logical 0, 1 (or any other non-zero value) for logical 1

+     */

+    void write(int value) {

+        gpio_write(&gpio, value);

+    }

+

+    /** Return the output setting, represented as 0 or 1 (int)

+     *

+     *  @returns

+     *    an integer representing the output setting of the pin,

+     *    0 for logical 0, 1 for logical 1

+     */

+    int read() {

+        return gpio_read(&gpio);

+    }

+

+    /** Return the output setting, represented as 0 or 1 (int)

+     *

+     *  @returns

+     *    Non zero value if pin is connected to uc GPIO

+     *    0 if gpio object was initialized with NC

+     */

+    int is_connected() {

+        return gpio_is_connected(&gpio);

+    }

+

+#ifdef MBED_OPERATORS

+    /** A shorthand for write()

+     */

+    DigitalOut& operator= (int value) {

+        write(value);

+        return *this;

+    }

+

+    DigitalOut& operator= (DigitalOut& rhs) {

+        write(rhs.read());

+        return *this;

+    }

+

+    /** A shorthand for read()

+     */

+    operator int() {

+        return read();

+    }

+#endif

+

+protected:

+    gpio_t gpio;

+};

+

+} // namespace mbed

+

+#endif

diff --git a/ext/DirHandle.h b/ext/DirHandle.h
new file mode 100644
index 0000000..564a01a
--- /dev/null
+++ b/ext/DirHandle.h
@@ -0,0 +1,104 @@
+/* mbed Microcontroller Library

+ * Copyright (c) 2006-2013 ARM Limited

+ *

+ * Licensed under the Apache License, Version 2.0 (the "License");

+ * you may not use this file except in compliance with the License.

+ * You may obtain a copy of the License at

+ *

+ *     http://www.apache.org/licenses/LICENSE-2.0

+ *

+ * Unless required by applicable law or agreed to in writing, software

+ * distributed under the License is distributed on an "AS IS" BASIS,

+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

+ * See the License for the specific language governing permissions and

+ * limitations under the License.

+ */

+#ifndef MBED_DIRHANDLE_H

+#define MBED_DIRHANDLE_H

+

+#if defined(__ARMCC_VERSION) || defined(__ICCARM__)

+#   define NAME_MAX 255

+typedef int mode_t;

+

+#else

+#   include <sys/syslimits.h>

+#endif

+

+#include "FileHandle.h"

+

+struct dirent {

+    char d_name[NAME_MAX+1];

+};

+

+namespace mbed {

+

+/** Represents a directory stream. Objects of this type are returned

+ *  by a FileSystemLike's opendir method. Implementations must define

+ *  at least closedir, readdir and rewinddir.

+ *

+ *  If a FileSystemLike class defines the opendir method, then the

+ *  directories of an object of that type can be accessed by

+ *  DIR *d = opendir("/example/directory") (or opendir("/example")

+ *  to open the root of the filesystem), and then using readdir(d) etc.

+ *

+ *  The root directory is considered to contain all FileLike and

+ *  FileSystemLike objects, so the DIR* returned by opendir("/") will

+ *  reflect this.

+ */

+class DirHandle {

+

+public:

+    /** Closes the directory.

+     *

+     *  @returns

+     *    0 on success,

+     *   -1 on error.

+     */

+    virtual int closedir()=0;

+

+    /** Return the directory entry at the current position, and

+     *  advances the position to the next entry.

+     *

+     * @returns

+     *  A pointer to a dirent structure representing the

+     *  directory entry at the current position, or NULL on reaching

+     *  end of directory or error.

+     */

+    virtual struct dirent *readdir()=0;

+

+    /** Resets the position to the beginning of the directory.

+     */

+    virtual void rewinddir()=0;

+

+    /** Returns the current position of the DirHandle.

+     *

+     * @returns

+     *   the current position,

+     *  -1 on error.

+     */

+    virtual off_t telldir() { return -1; }

+

+    /** Sets the position of the DirHandle.

+     *

+     *  @param location The location to seek to. Must be a value returned by telldir.

+     */

+    virtual void seekdir(off_t location) { }

+

+    virtual ~DirHandle() {}

+};

+

+} // namespace mbed

+

+typedef mbed::DirHandle DIR;

+

+extern "C" {

+    DIR *opendir(const char*);

+    struct dirent *readdir(DIR *);

+    int closedir(DIR*);

+    void rewinddir(DIR*);

+    long telldir(DIR*);

+    void seekdir(DIR*, long);

+    int mkdir(const char *name, mode_t n);

+};

+

+#endif /* MBED_DIRHANDLE_H */

diff --git a/ext/Ethernet.h b/ext/Ethernet.h
new file mode 100644
index 0000000..75212cf
--- /dev/null
+++ b/ext/Ethernet.h
@@ -0,0 +1,170 @@
+/* mbed Microcontroller Library

+ * Copyright (c) 2006-2013 ARM Limited

+ *

+ * Licensed under the Apache License, Version 2.0 (the "License");

+ * you may not use this file except in compliance with the License.

+ * You may obtain a copy of the License at

+ *

+ *     http://www.apache.org/licenses/LICENSE-2.0

+ *

+ * Unless required by applicable law or agreed to in writing, software

+ * distributed under the License is distributed on an "AS IS" BASIS,

+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

+ * See the License for the specific language governing permissions and

+ * limitations under the License.

+ */

+#ifndef MBED_ETHERNET_H

+#define MBED_ETHERNET_H

+

+#include "platform.h"

+

+#if DEVICE_ETHERNET

+

+namespace mbed {

+

+/** An ethernet interface, to use with the ethernet pins.

+ *

+ * Example:

+ * @code

+ * // Read destination and source from every ethernet packet

+ *

+ * #include "mbed.h"

+ *

+ * Ethernet eth;

+ *

+ * int main() {

+ *     char buf[0x600];

+ *

+ *     while(1) {

+ *         int size = eth.receive();

+ *         if(size > 0) {

+ *             eth.read(buf, size);

+ *             printf("Destination:  %02X:%02X:%02X:%02X:%02X:%02X\n",

+ *                     buf[0], buf[1], buf[2], buf[3], buf[4], buf[5]);

+ *             printf("Source: %02X:%02X:%02X:%02X:%02X:%02X\n",

+ *                     buf[6], buf[7], buf[8], buf[9], buf[10], buf[11]);

+ *         }

+ *

+ *         wait(1);

+ *     }

+ * }

+ * @endcode

+ */

+class Ethernet {

+

+public:

+

+    /** Initialise the ethernet interface.

+     */

+    Ethernet();

+

+    /** Powers the hardware down.

+     */

+    virtual ~Ethernet();

+

+    enum Mode {

+        AutoNegotiate,

+        HalfDuplex10,

+        FullDuplex10,

+        HalfDuplex100,

+        FullDuplex100

+    };

+

+    /** Writes into an outgoing ethernet packet.

+     *

+     *  It will append size bytes of data to the previously written bytes.

+     *

+     *  @param data An array to write.

+     *  @param size The size of data.

+     *

+     *  @returns

+     *   The number of written bytes.

+     */

+    int write(const char *data, int size);

+

+    /** Send an outgoing ethernet packet.

+     *

+     *  After filling in the data in an ethernet packet it must be send.

+     *  Send will provide a new packet to write to.

+     *

+     *  @returns

+     *    0 if the sending was failed,

+     *    or the size of the packet successfully sent.

+     */

+    int send();

+

+    /** Recevies an arrived ethernet packet.

+     *

+     *  Receiving an ethernet packet will drop the last received ethernet packet

+     *  and make a new ethernet packet ready to read.

+     *  If no ethernet packet is arrived it will return 0.

+     *

+     *  @returns

+     *    0 if no ethernet packet is arrived,

+     *    or the size of the arrived packet.

+     */

+    int receive();

+

+    /** Read from an recevied ethernet packet.

+     *

+     *  After receive returnd a number bigger than 0it is

+     *  possible to read bytes from this packet.

+     *  Read will write up to size bytes into data.

+     *

+     *  It is possible to use read multible times.

+     *  Each time read will start reading after the last read byte before.

+     *

+     *  @returns

+     *  The number of byte read.

+     */

+    int read(char *data, int size);

+

+    /** Gives the ethernet address of the mbed.

+     *

+     *  @param mac Must be a pointer to a 6 byte char array to copy the ethernet address in.

+     */

+    void address(char *mac);

+

+    /** Returns if an ethernet link is pressent or not. It takes a wile after Ethernet initializion to show up.

+     *

+     *  @returns

+     *   0 if no ethernet link is pressent,

+     *   1 if an ethernet link is pressent.

+     *

+     * Example:

+     * @code

+     * // Using the Ethernet link function

+     * #include "mbed.h"

+     *

+     * Ethernet eth;

+     *

+     * int main() {

+     *     wait(1); // Needed after startup.

+     *     if (eth.link()) {

+     *          printf("online\n");

+     *     } else {

+     *          printf("offline\n");

+     *     }

+     * }

+     * @endcode

+     */

+    int link();

+

+    /** Sets the speed and duplex parameters of an ethernet link

+     *

+     * - AutoNegotiate      Auto negotiate speed and duplex

+     * - HalfDuplex10       10 Mbit, half duplex

+     * - FullDuplex10       10 Mbit, full duplex

+     * - HalfDuplex100      100 Mbit, half duplex

+     * - FullDuplex100      100 Mbit, full duplex

+     *

+     *  @param mode the speed and duplex mode to set the link to:

+     */

+    void set_link(Mode mode);

+};

+

+} // namespace mbed

+

+#endif

+

+#endif

diff --git a/ext/FileBase.h b/ext/FileBase.h
new file mode 100644
index 0000000..7acaa78
--- /dev/null
+++ b/ext/FileBase.h
@@ -0,0 +1,80 @@
+/* mbed Microcontroller Library

+ * Copyright (c) 2006-2013 ARM Limited

+ *

+ * Licensed under the Apache License, Version 2.0 (the "License");

+ * you may not use this file except in compliance with the License.

+ * You may obtain a copy of the License at

+ *

+ *     http://www.apache.org/licenses/LICENSE-2.0

+ *

+ * Unless required by applicable law or agreed to in writing, software

+ * distributed under the License is distributed on an "AS IS" BASIS,

+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

+ * See the License for the specific language governing permissions and

+ * limitations under the License.

+ */

+#ifndef MBED_FILEBASE_H

+#define MBED_FILEBASE_H

+

+typedef int FILEHANDLE;

+

+#include <stdio.h>

+

+#if defined(__ARMCC_VERSION) || defined(__ICCARM__)

+#    define O_RDONLY 0

+#    define O_WRONLY 1

+#    define O_RDWR   2

+#    define O_CREAT  0x0200

+#    define O_TRUNC  0x0400

+#    define O_APPEND 0x0008

+

+#    define NAME_MAX 255

+

+typedef int mode_t;

+typedef int ssize_t;

+typedef long off_t;

+

+#else

+#    include <sys/fcntl.h>

+#    include <sys/types.h>

+#    include <sys/syslimits.h>

+#endif

+

+#include "platform.h"

+

+namespace mbed {

+

+typedef enum {

+    FilePathType,

+    FileSystemPathType

+} PathType;

+

+class FileBase {

+public:

+    FileBase(const char *name, PathType t);

+

+    virtual ~FileBase();

+

+    const char* getName(void);

+    PathType    getPathType(void);

+

+    static FileBase *lookup(const char *name, unsigned int len);

+

+    static FileBase *get(int n);

+

+protected:

+    static FileBase *_head;

+

+    FileBase   *_next;

+    const char *_name;

+    PathType    _path_type;

+

+    /* disallow copy constructor and assignment operators */

+private:

+    FileBase(const FileBase&);

+    FileBase & operator = (const FileBase&);

+};

+

+} // namespace mbed

+

+#endif

diff --git a/ext/FileHandle.h b/ext/FileHandle.h
new file mode 100644
index 0000000..fd25fa5
--- /dev/null
+++ b/ext/FileHandle.h
@@ -0,0 +1,119 @@
+/* mbed Microcontroller Library

+ * Copyright (c) 2006-2013 ARM Limited

+ *

+ * Licensed under the Apache License, Version 2.0 (the "License");

+ * you may not use this file except in compliance with the License.

+ * You may obtain a copy of the License at

+ *

+ *     http://www.apache.org/licenses/LICENSE-2.0

+ *

+ * Unless required by applicable law or agreed to in writing, software

+ * distributed under the License is distributed on an "AS IS" BASIS,

+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

+ * See the License for the specific language governing permissions and

+ * limitations under the License.

+ */

+#ifndef MBED_FILEHANDLE_H

+#define MBED_FILEHANDLE_H

+

+typedef int FILEHANDLE;

+

+#include <stdio.h>

+

+#if defined(__ARMCC_VERSION) || defined(__ICCARM__)

+typedef int ssize_t;

+typedef long off_t;

+

+#else

+#   include <sys/types.h>

+#endif

+

+namespace mbed {

+

+/** An OO equivalent of the internal FILEHANDLE variable

+ *  and associated _sys_* functions.

+ *

+ * FileHandle is an abstract class, needing at least sys_write and

+ *  sys_read to be implmented for a simple interactive device.

+ *

+ * No one ever directly tals to/instanciates a FileHandle - it gets

+ *  created by FileSystem, and wrapped up by stdio.

+ */

+class FileHandle {

+

+public:

+    /** Write the contents of a buffer to the file

+     *

+     *  @param buffer the buffer to write from

+     *  @param length the number of characters to write

+     *

+     *  @returns

+     *  The number of characters written (possibly 0) on success, -1 on error.

+     */

+    virtual ssize_t write(const void* buffer, size_t length) = 0;

+

+    /** Close the file

+     *

+     *  @returns

+     *  Zero on success, -1 on error.

+     */

+    virtual int close() = 0;

+

+    /** Function read

+     *  Reads the contents of the file into a buffer

+     *

+     *  @param buffer the buffer to read in to

+     *  @param length the number of characters to read

+     *

+     *  @returns

+     *  The number of characters read (zero at end of file) on success, -1 on error.

+     */

+    virtual ssize_t read(void* buffer, size_t length) = 0;

+

+    /** Check if the handle is for a interactive terminal device.

+     * If so, line buffered behaviour is used by default

+     *

+     *  @returns

+     *    1 if it is a terminal,

+     *    0 otherwise

+     */

+    virtual int isatty() = 0;

+

+    /** Move the file position to a given offset from a given location.

+     *

+     *  @param offset The offset from whence to move to

+     *  @param whence SEEK_SET for the start of the file, SEEK_CUR for the

+     *   current file position, or SEEK_END for the end of the file.

+     *

+     *  @returns

+     *    new file position on success,

+     *    -1 on failure or unsupported

+     */

+    virtual off_t lseek(off_t offset, int whence) = 0;

+

+    /** Flush any buffers associated with the FileHandle, ensuring it

+     *  is up to date on disk

+     *

+     *  @returns

+     *    0 on success or un-needed,

+     *   -1 on error

+     */

+    virtual int fsync() = 0;

+

+    virtual off_t flen() {

+        /* remember our current position */

+        off_t pos = lseek(0, SEEK_CUR);

+        if(pos == -1) return -1;

+        /* seek to the end to get the file length */

+        off_t res = lseek(0, SEEK_END);

+        /* return to our old position */

+        lseek(pos, SEEK_SET);

+        return res;

+    }

+

+    virtual ~FileHandle();

+};

+

+} // namespace mbed

+

+#endif

diff --git a/ext/FileLike.h b/ext/FileLike.h
new file mode 100644
index 0000000..6eb7939
--- /dev/null
+++ b/ext/FileLike.h
@@ -0,0 +1,44 @@
+/* mbed Microcontroller Library

+ * Copyright (c) 2006-2013 ARM Limited

+ *

+ * Licensed under the Apache License, Version 2.0 (the "License");

+ * you may not use this file except in compliance with the License.

+ * You may obtain a copy of the License at

+ *

+ *     http://www.apache.org/licenses/LICENSE-2.0

+ *

+ * Unless required by applicable law or agreed to in writing, software

+ * distributed under the License is distributed on an "AS IS" BASIS,

+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

+ * See the License for the specific language governing permissions and

+ * limitations under the License.

+ */

+#ifndef MBED_FILELIKE_H

+#define MBED_FILELIKE_H

+

+#include "FileBase.h"

+#include "FileHandle.h"

+

+namespace mbed {

+

+/* Class FileLike

+ *  A file-like object is one that can be opened with fopen by

+ *  fopen("/name", mode). It is intersection of the classes Base and

+ *  FileHandle.

+ */

+class FileLike : public FileHandle, public FileBase {

+

+public:

+    /* Constructor FileLike

+     *

+     * Variables

+     *  name - The name to use to open the file.

+     */

+    FileLike(const char *name);

+

+    virtual ~FileLike();

+};

+

+} // namespace mbed

+

+#endif

diff --git a/ext/FilePath.h b/ext/FilePath.h
new file mode 100644
index 0000000..45e3391
--- /dev/null
+++ b/ext/FilePath.h
@@ -0,0 +1,46 @@
+/* mbed Microcontroller Library

+ * Copyright (c) 2006-2013 ARM Limited

+ *

+ * Licensed under the Apache License, Version 2.0 (the "License");

+ * you may not use this file except in compliance with the License.

+ * You may obtain a copy of the License at

+ *

+ *     http://www.apache.org/licenses/LICENSE-2.0

+ *

+ * Unless required by applicable law or agreed to in writing, software

+ * distributed under the License is distributed on an "AS IS" BASIS,

+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

+ * See the License for the specific language governing permissions and

+ * limitations under the License.

+ */

+#ifndef MBED_FILEPATH_H

+#define MBED_FILEPATH_H

+

+#include "platform.h"

+

+#include "FileSystemLike.h"

+#include "FileLike.h"

+

+namespace mbed {

+

+class FilePath {

+public:

+    FilePath(const char* file_path);

+

+    const char* fileName(void);

+

+    bool          isFileSystem(void);

+    FileSystemLike* fileSystem(void);

+

+    bool    isFile(void);

+    FileLike* file(void);

+    bool    exists(void);

+

+private:

+    const char* file_name;

+    FileBase* fb;

+};

+

+} // namespace mbed

+

+#endif

diff --git a/ext/FileSystemLike.h b/ext/FileSystemLike.h
new file mode 100644
index 0000000..1b6b501
--- /dev/null
+++ b/ext/FileSystemLike.h
@@ -0,0 +1,104 @@
+/* mbed Microcontroller Library

+ * Copyright (c) 2006-2013 ARM Limited

+ *

+ * Licensed under the Apache License, Version 2.0 (the "License");

+ * you may not use this file except in compliance with the License.

+ * You may obtain a copy of the License at

+ *

+ *     http://www.apache.org/licenses/LICENSE-2.0

+ *

+ * Unless required by applicable law or agreed to in writing, software

+ * distributed under the License is distributed on an "AS IS" BASIS,

+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

+ * See the License for the specific language governing permissions and

+ * limitations under the License.

+ */

+#ifndef MBED_FILESYSTEMLIKE_H

+#define MBED_FILESYSTEMLIKE_H

+

+#include "platform.h"

+

+#include "FileBase.h"

+#include "FileHandle.h"

+#include "DirHandle.h"

+

+namespace mbed {

+

+/** A filesystem-like object is one that can be used to open files

+ *  though it by fopen("/name/filename", mode)

+ *

+ *  Implementations must define at least open (the default definitions

+ *  of the rest of the functions just return error values).

+ */

+class FileSystemLike : public FileBase {

+

+public:

+    /** FileSystemLike constructor

+     *

+     *  @param name The name to use for the filesystem.

+     */

+    FileSystemLike(const char *name);

+

+    virtual ~FileSystemLike();

+

+    static DirHandle *opendir();

+    friend class BaseDirHandle;

+

+    /** Opens a file from the filesystem

+     *

+     *  @param filename The name of the file to open.

+     *  @param flags One of O_RDONLY, O_WRONLY, or O_RDWR, OR'd with

+     *    zero or more of O_CREAT, O_TRUNC, or O_APPEND.

+     *

+     *  @returns

+     *    A pointer to a FileHandle object representing the

+     *   file on success, or NULL on failure.

+     */

+    virtual FileHandle *open(const char *filename, int flags) = 0;

+

+    /** Remove a file from the filesystem.

+     *

+     *  @param filename the name of the file to remove.

+     *  @param returns 0 on success, -1 on failure.

+     */

+    virtual int remove(const char *filename) { return -1; };

+

+    /** Rename a file in the filesystem.

+     *

+     *  @param oldname the name of the file to rename.

+     *  @param newname the name to rename it to.

+     *

+     *  @returns

+     *    0 on success,

+     *   -1 on failure.

+     */

+    virtual int rename(const char *oldname, const char *newname) { return -1; };

+

+    /** Opens a directory in the filesystem and returns a DirHandle

+     *   representing the directory stream.

+     *

+     *  @param name The name of the directory to open.

+     *

+     *  @returns

+     *    A DirHandle representing the directory stream, or

+     *   NULL on failure.

+     */

+    virtual DirHandle *opendir(const char *name) { return NULL; };

+

+    /** Creates a directory in the filesystem.

+     *

+     *  @param name The name of the directory to create.

+     *  @param mode The permissions to create the directory with.

+     *

+     *  @returns

+     *    0 on success,

+     *   -1 on failure.

+     */

+    virtual int mkdir(const char *name, mode_t mode) { return -1; }

+

+    // TODO other filesystem functions (mkdir, rm, rn, ls etc)

+};

+

+} // namespace mbed

+

+#endif

diff --git a/ext/FunctionPointer.h b/ext/FunctionPointer.h
new file mode 100644
index 0000000..7b6be7a
--- /dev/null
+++ b/ext/FunctionPointer.h
@@ -0,0 +1,202 @@
+/* mbed Microcontroller Library

+ * Copyright (c) 2006-2015 ARM Limited

+ *

+ * Licensed under the Apache License, Version 2.0 (the "License");

+ * you may not use this file except in compliance with the License.

+ * You may obtain a copy of the License at

+ *

+ *     http://www.apache.org/licenses/LICENSE-2.0

+ *

+ * Unless required by applicable law or agreed to in writing, software

+ * distributed under the License is distributed on an "AS IS" BASIS,

+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

+ * See the License for the specific language governing permissions and

+ * limitations under the License.

+ */

+#ifndef MBED_FUNCTIONPOINTER_H

+#define MBED_FUNCTIONPOINTER_H

+

+#include <string.h>

+#include <stdint.h>

+

+namespace mbed {

+

+/* If we had variaditic templates, this wouldn't be a problem, but until C++11 is enabled, we are stuck with multiple classes... */

+

+/** A class for storing and calling a pointer to a static or member function

+ */

+template <typename R, typename A1>

+class FunctionPointerArg1{

+public:

+    /** Create a FunctionPointer, attaching a static function

+     *

+     *  @param function The static function to attach (default is none)

+     */

+    FunctionPointerArg1(R (*function)(A1) = 0) {

+        attach(function);

+    }

+

+    /** Create a FunctionPointer, attaching a member function

+     *

+     *  @param object The object pointer to invoke the member function on (i.e. the this pointer)

+     *  @param function The address of the member function to attach

+     */

+    template<typename T>

+    FunctionPointerArg1(T *object, R (T::*member)(A1)) {

+        attach(object, member);

+    }

+

+    /** Attach a static function

+     *

+     *  @param function The static function to attach (default is none)

+     */

+    void attach(R (*function)(A1)) {

+        _p.function = function;

+        _membercaller = 0;

+    }

+

+    /** Attach a member function

+     *

+     *  @param object The object pointer to invoke the member function on (i.e. the this pointer)

+     *  @param function The address of the member function to attach

+     */

+    template<typename T>

+    void attach(T *object, R (T::*member)(A1)) {

+        _p.object = static_cast<void*>(object);

+        *reinterpret_cast<R (T::**)(A1)>(_member) = member;

+        _membercaller = &FunctionPointerArg1::membercaller<T>;

+    }

+

+    /** Call the attached static or member function

+     */

+    R call(A1 a) {

+        if (_membercaller == 0 && _p.function) {

+           return _p.function(a);

+        } else if (_membercaller && _p.object) {

+           return _membercaller(_p.object, _member, a);

+        }

+        return (R)0;

+    }

+

+    /** Get registered static function

+     */

+    R(*get_function(A1))() {

+        return _membercaller ? (R(*)(A1))0 : (R(*)(A1))_p.function;

+    }

+

+#ifdef MBED_OPERATORS

+    R operator ()(A1 a) {

+        return call(a);

+    }

+    operator bool(void) const {

+        return (_membercaller != NULL ? _p.object : (void*)_p.function) != NULL;

+    }

+#endif

+private:

+    template<typename T>

+    static R membercaller(void *object, uintptr_t *member, A1 a) {

+        T* o = static_cast<T*>(object);

+        R (T::**m)(A1) = reinterpret_cast<R (T::**)(A1)>(member);

+        return (o->**m)(a);

+    }

+

+    union {

+        R (*function)(A1); // static function pointer

+        void *object;      // object this pointer

+    } _p;

+    uintptr_t _member[4]; // aligned raw member function pointer storage - converted back by registered _membercaller

+    R (*_membercaller)(void*, uintptr_t*, A1); // registered membercaller function to convert back and call _m.member on _object

+};

+

+/** A class for storing and calling a pointer to a static or member function (R ()(void))

+ */

+template <typename R>

+class FunctionPointerArg1<R, void>{

+public:

+    /** Create a FunctionPointer, attaching a static function

+     *

+     *  @param function The static function to attach (default is none)

+     */

+    FunctionPointerArg1(R (*function)(void) = 0) {

+        attach(function);

+    }

+

+    /** Create a FunctionPointer, attaching a member function

+     *

+     *  @param object The object pointer to invoke the member function on (i.e. the this pointer)

+     *  @param function The address of the void member function to attach

+     */

+    template<typename T>

+    FunctionPointerArg1(T *object, R (T::*member)(void)) {

+        attach(object, member);

+    }

+

+    /** Attach a static function

+     *

+     *  @param function The void static function to attach (default is none)

+     */

+    void attach(R (*function)(void)) {

+        _p.function = function;

+        _membercaller = 0;

+    }

+

+    /** Attach a member function

+     *

+     *  @param object The object pointer to invoke the member function on (i.e. the this pointer)

+     *  @param function The address of the void member function to attach

+     */

+    template<typename T>

+    void attach(T *object, R (T::*member)(void)) {

+        _p.object = static_cast<void*>(object);

+        *reinterpret_cast<R (T::**)(void)>(_member) = member;

+        _membercaller = &FunctionPointerArg1::membercaller<T>;

+    }

+

+    /** Call the attached static or member function

+     */

+    R call(){

+        if (_membercaller == 0 && _p.function) {

+            return _p.function();

+        } else if (_membercaller && _p.object) {

+            return _membercaller(_p.object, _member);

+        }

+        return (R)0;

+    }

+

+    /** Get registered static function

+     */

+    R(*get_function())() {

+        return _membercaller ? (R(*)())0 : (R(*)())_p.function;

+    }

+

+#ifdef MBED_OPERATORS

+    R operator ()(void) {

+        return call();

+    }

+    operator bool(void) const {

+        return (_membercaller != NULL ? _p.object : (void*)_p.function) != NULL;

+    }

+#endif

+

+private:

+    template<typename T>

+    static R membercaller(void *object, uintptr_t *member) {

+        T* o = static_cast<T*>(object);

+        R (T::**m)(void) = reinterpret_cast<R (T::**)(void)>(member);

+        return (o->**m)();

+    }

+

+    union {

+        R (*function)(void); // static function pointer

+        void *object;        // object this pointer

+    } _p;

+    uintptr_t _member[4]; // aligned raw member function pointer storage - converted back by registered _membercaller

+    R (*_membercaller)(void*, uintptr_t*); // registered membercaller function to convert back and call _m.member on _object

+};

+

+typedef FunctionPointerArg1<void, void> FunctionPointer;

+typedef FunctionPointerArg1<void, int> event_callback_t;

+

+} // namespace mbed

+

+#endif

diff --git a/ext/I2C.h b/ext/I2C.h
new file mode 100644
index 0000000..7981cef
--- /dev/null
+++ b/ext/I2C.h
@@ -0,0 +1,176 @@
+/* mbed Microcontroller Library

+ * Copyright (c) 2006-2015 ARM Limited

+ *

+ * Licensed under the Apache License, Version 2.0 (the "License");

+ * you may not use this file except in compliance with the License.

+ * You may obtain a copy of the License at

+ *

+ *     http://www.apache.org/licenses/LICENSE-2.0

+ *

+ * Unless required by applicable law or agreed to in writing, software

+ * distributed under the License is distributed on an "AS IS" BASIS,

+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

+ * See the License for the specific language governing permissions and

+ * limitations under the License.

+ */

+#ifndef MBED_I2C_H

+#define MBED_I2C_H

+

+#include "platform.h"

+

+#if DEVICE_I2C

+

+#include "i2c_api.h"

+

+#if DEVICE_I2C_ASYNCH

+#include "CThunk.h"

+#include "dma_api.h"

+#include "FunctionPointer.h"

+#endif

+

+namespace mbed {

+

+/** An I2C Master, used for communicating with I2C slave devices

+ *

+ * Example:

+ * @code

+ * // Read from I2C slave at address 0x62

+ *

+ * #include "mbed.h"

+ *

+ * I2C i2c(p28, p27);

+ *

+ * int main() {

+ *     int address = 0x62;

+ *     char data[2];

+ *     i2c.read(address, data, 2);

+ * }

+ * @endcode

+ */

+class I2C {

+

+public:

+    enum RxStatus {

+        NoData,

+        MasterGeneralCall,

+        MasterWrite,

+        MasterRead

+    };

+

+    enum Acknowledge {

+        NoACK = 0,

+        ACK   = 1

+    };

+

+    /** Create an I2C Master interface, connected to the specified pins

+     *

+     *  @param sda I2C data line pin

+     *  @param scl I2C clock line pin

+     */

+    I2C(PinName sda, PinName scl);

+

+    /** Set the frequency of the I2C interface

+     *

+     *  @param hz The bus frequency in hertz

+     */

+    void frequency(int hz);

+

+    /** Read from an I2C slave

+     *

+     * Performs a complete read transaction. The bottom bit of

+     * the address is forced to 1 to indicate a read.

+     *

+     *  @param address 8-bit I2C slave address [ addr | 1 ]

+     *  @param data Pointer to the byte-array to read data in to

+     *  @param length Number of bytes to read

+     *  @param repeated Repeated start, true - don't send stop at end

+     *

+     *  @returns

+     *       0 on success (ack),

+     *   non-0 on failure (nack)

+     */

+    int read(int address, char *data, int length, bool repeated = false);

+

+    /** Read a single byte from the I2C bus

+     *

+     *  @param ack indicates if the byte is to be acknowledged (1 = acknowledge)

+     *

+     *  @returns

+     *    the byte read

+     */

+    int read(int ack);

+

+    /** Write to an I2C slave

+     *

+     * Performs a complete write transaction. The bottom bit of

+     * the address is forced to 0 to indicate a write.

+     *

+     *  @param address 8-bit I2C slave address [ addr | 0 ]

+     *  @param data Pointer to the byte-array data to send

+     *  @param length Number of bytes to send

+     *  @param repeated Repeated start, true - do not send stop at end

+     *

+     *  @returns

+     *       0 on success (ack),

+     *   non-0 on failure (nack)

+     */

+    int write(int address, const char *data, int length, bool repeated = false);

+

+    /** Write single byte out on the I2C bus

+     *

+     *  @param data data to write out on bus

+     *

+     *  @returns

+     *    '1' if an ACK was received,

+     *    '0' otherwise

+     */

+    int write(int data);

+

+    /** Creates a start condition on the I2C bus

+     */

+

+    void start(void);

+

+    /** Creates a stop condition on the I2C bus

+     */

+    void stop(void);

+

+#if DEVICE_I2C_ASYNCH

+

+    /** Start non-blocking I2C transfer.

+     *

+     * @param address   8/10 bit I2c slave address

+     * @param tx_buffer The TX buffer with data to be transfered

+     * @param tx_length The length of TX buffer in bytes

+     * @param rx_buffer The RX buffer which is used for received data

+     * @param rx_length The length of RX buffer in bytes

+     * @param event     The logical OR of events to modify

+     * @param callback  The event callback function

+     * @param repeated Repeated start, true - do not send stop at end

+     * @return Zero if the transfer has started, or -1 if I2C peripheral is busy

+     */

+    int transfer(int address, const char *tx_buffer, int tx_length, char *rx_buffer, int rx_length, const event_callback_t& callback, int event = I2C_EVENT_TRANSFER_COMPLETE, bool repeated = false);

+

+    /** Abort the on-going I2C transfer

+     */

+    void abort_transfer();

+protected:

+    void irq_handler_asynch(void);

+    event_callback_t _callback;

+    CThunk<I2C> _irq;

+    DMAUsage _usage;

+#endif

+

+protected:

+    void aquire();

+

+    i2c_t _i2c;

+    static I2C  *_owner;

+    int         _hz;

+};

+

+} // namespace mbed

+

+#endif

+

+#endif

diff --git a/ext/I2CSlave.h b/ext/I2CSlave.h
new file mode 100644
index 0000000..ddf9d5f
--- /dev/null
+++ b/ext/I2CSlave.h
@@ -0,0 +1,154 @@
+/* mbed Microcontroller Library

+ * Copyright (c) 2006-2013 ARM Limited

+ *

+ * Licensed under the Apache License, Version 2.0 (the "License");

+ * you may not use this file except in compliance with the License.

+ * You may obtain a copy of the License at

+ *

+ *     http://www.apache.org/licenses/LICENSE-2.0

+ *

+ * Unless required by applicable law or agreed to in writing, software

+ * distributed under the License is distributed on an "AS IS" BASIS,

+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

+ * See the License for the specific language governing permissions and

+ * limitations under the License.

+ */

+#ifndef MBED_I2C_SLAVE_H

+#define MBED_I2C_SLAVE_H

+

+#include "platform.h"

+

+#if DEVICE_I2CSLAVE

+

+#include "i2c_api.h"

+

+namespace mbed {

+

+/** An I2C Slave, used for communicating with an I2C Master device

+ *

+ * Example:

+ * @code

+ * // Simple I2C responder

+ * #include <mbed.h>

+ *

+ * I2CSlave slave(p9, p10);

+ *

+ * int main() {

+ *     char buf[10];

+ *     char msg[] = "Slave!";

+ *

+ *     slave.address(0xA0);

+ *     while (1) {

+ *         int i = slave.receive();

+ *         switch (i) {

+ *             case I2CSlave::ReadAddressed:

+ *                 slave.write(msg, strlen(msg) + 1); // Includes null char

+ *                 break;

+ *             case I2CSlave::WriteGeneral:

+ *                 slave.read(buf, 10);

+ *                 printf("Read G: %s\n", buf);

+ *                 break;

+ *             case I2CSlave::WriteAddressed:

+ *                 slave.read(buf, 10);

+ *                 printf("Read A: %s\n", buf);

+ *                 break;

+ *         }

+ *         for(int i = 0; i < 10; i++) buf[i] = 0;    // Clear buffer

+ *     }

+ * }

+ * @endcode

+ */

+class I2CSlave {

+

+public:

+    enum RxStatus {

+        NoData         = 0,

+        ReadAddressed  = 1,

+        WriteGeneral   = 2,

+        WriteAddressed = 3

+    };

+

+    /** Create an I2C Slave interface, connected to the specified pins.

+     *

+     *  @param sda I2C data line pin

+     *  @param scl I2C clock line pin

+     */

+    I2CSlave(PinName sda, PinName scl);

+

+    /** Set the frequency of the I2C interface

+     *

+     *  @param hz The bus frequency in hertz

+     */

+    void frequency(int hz);

+

+    /** Checks to see if this I2C Slave has been addressed.

+     *

+     *  @returns

+     *  A status indicating if the device has been addressed, and how

+     *  - NoData            - the slave has not been addressed

+     *  - ReadAddressed     - the master has requested a read from this slave

+     *  - WriteAddressed    - the master is writing to this slave

+     *  - WriteGeneral      - the master is writing to all slave

+     */

+    int receive(void);

+

+    /** Read from an I2C master.

+     *

+     *  @param data pointer to the byte array to read data in to

+     *  @param length maximum number of bytes to read

+     *

+     *  @returns

+     *       0 on success,

+     *   non-0 otherwise

+     */

+    int read(char *data, int length);

+

+    /** Read a single byte from an I2C master.

+     *

+     *  @returns

+     *    the byte read

+     */

+    int read(void);

+

+    /** Write to an I2C master.

+     *

+     *  @param data pointer to the byte array to be transmitted

+     *  @param length the number of bytes to transmite

+     *

+     *  @returns

+     *       0 on success,

+     *   non-0 otherwise

+     */

+    int write(const char *data, int length);

+

+    /** Write a single byte to an I2C master.

+     *

+     *  @data the byte to write

+     *

+     *  @returns

+     *    '1' if an ACK was received,

+     *    '0' otherwise

+     */

+    int write(int data);

+

+    /** Sets the I2C slave address.

+     *

+     *  @param address The address to set for the slave (ignoring the least

+     *  signifcant bit). If set to 0, the slave will only respond to the

+     *  general call address.

+     */

+    void address(int address);

+

+    /** Reset the I2C slave back into the known ready receiving state.

+     */

+    void stop(void);

+

+protected:

+    i2c_t _i2c;

+};

+

+} // namespace mbed

+

+#endif

+

+#endif

diff --git a/ext/InterruptIn.h b/ext/InterruptIn.h
new file mode 100644
index 0000000..55a0255
--- /dev/null
+++ b/ext/InterruptIn.h
@@ -0,0 +1,135 @@
+/* mbed Microcontroller Library

+ * Copyright (c) 2006-2013 ARM Limited

+ *

+ * Licensed under the Apache License, Version 2.0 (the "License");

+ * you may not use this file except in compliance with the License.

+ * You may obtain a copy of the License at

+ *

+ *     http://www.apache.org/licenses/LICENSE-2.0

+ *

+ * Unless required by applicable law or agreed to in writing, software

+ * distributed under the License is distributed on an "AS IS" BASIS,

+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

+ * See the License for the specific language governing permissions and

+ * limitations under the License.

+ */

+#ifndef MBED_INTERRUPTIN_H

+#define MBED_INTERRUPTIN_H

+

+#include "platform.h"

+

+#if DEVICE_INTERRUPTIN

+

+#include "gpio_api.h"

+#include "gpio_irq_api.h"

+#include "FunctionPointer.h"

+

+namespace mbed {

+

+/** A digital interrupt input, used to call a function on a rising or falling edge

+ *

+ * Example:

+ * @code

+ * // Flash an LED while waiting for events

+ *

+ * #include "mbed.h"

+ *

+ * InterruptIn event(p16);

+ * DigitalOut led(LED1);

+ *

+ * void trigger() {

+ *     printf("triggered!\n");

+ * }

+ *

+ * int main() {

+ *     event.rise(&trigger);

+ *     while(1) {

+ *         led = !led;

+ *         wait(0.25);

+ *     }

+ * }

+ * @endcode

+ */

+class InterruptIn {

+

+public:

+

+    /** Create an InterruptIn connected to the specified pin

+     *

+     *  @param pin InterruptIn pin to connect to

+     *  @param name (optional) A string to identify the object

+     */

+    InterruptIn(PinName pin);

+    virtual ~InterruptIn();

+

+     int read();

+#ifdef MBED_OPERATORS

+    operator int();

+

+#endif

+

+    /** Attach a function to call when a rising edge occurs on the input

+     *

+     *  @param fptr A pointer to a void function, or 0 to set as none

+     */

+    void rise(void (*fptr)(void));

+

+    /** Attach a member function to call when a rising edge occurs on the input

+     *

+     *  @param tptr pointer to the object to call the member function on

+     *  @param mptr pointer to the member function to be called

+     */

+    template<typename T>

+    void rise(T* tptr, void (T::*mptr)(void)) {

+        _rise.attach(tptr, mptr);

+        gpio_irq_set(&gpio_irq, IRQ_RISE, 1);

+    }

+

+    /** Attach a function to call when a falling edge occurs on the input

+     *

+     *  @param fptr A pointer to a void function, or 0 to set as none

+     */

+    void fall(void (*fptr)(void));

+

+    /** Attach a member function to call when a falling edge occurs on the input

+     *

+     *  @param tptr pointer to the object to call the member function on

+     *  @param mptr pointer to the member function to be called

+     */

+    template<typename T>

+    void fall(T* tptr, void (T::*mptr)(void)) {

+        _fall.attach(tptr, mptr);

+        gpio_irq_set(&gpio_irq, IRQ_FALL, 1);

+    }

+

+    /** Set the input pin mode

+     *

+     *  @param mode PullUp, PullDown, PullNone

+     */

+    void mode(PinMode pull);

+

+    /** Enable IRQ. This method depends on hw implementation, might enable one

+     *  port interrupts. For further information, check gpio_irq_enable().

+     */

+    void enable_irq();

+

+    /** Disable IRQ. This method depends on hw implementation, might disable one

+     *  port interrupts. For further information, check gpio_irq_disable().

+     */

+    void disable_irq();

+

+    static void _irq_handler(uint32_t id, gpio_irq_event event);

+

+protected:

+    gpio_t gpio;

+    gpio_irq_t gpio_irq;

+

+    FunctionPointer _rise;

+    FunctionPointer _fall;

+};

+

+} // namespace mbed

+

+#endif

+

+#endif

diff --git a/ext/InterruptManager.h b/ext/InterruptManager.h
new file mode 100644
index 0000000..b9c3b9f
--- /dev/null
+++ b/ext/InterruptManager.h
@@ -0,0 +1,143 @@
+#ifndef MBED_INTERRUPTMANAGER_H

+#define MBED_INTERRUPTMANAGER_H

+

+#include "cmsis.h"

+#include "CallChain.h"

+#include <string.h>

+

+namespace mbed {

+

+/** Use this singleton if you need to chain interrupt handlers.

+ *

+ * Example (for LPC1768):

+ * @code

+ * #include "InterruptManager.h"

+ * #include "mbed.h"

+ *

+ * Ticker flipper;

+ * DigitalOut led1(LED1);

+ * DigitalOut led2(LED2);

+ *

+ * void flip(void) {

+ *     led1 = !led1;

+ * }

+ *

+ * void handler(void) {

+ *     led2 = !led1;

+ * }

+ *

+ * int main() {

+ *     led1 = led2 = 0;

+ *     flipper.attach(&flip, 1.0);

+ *     InterruptManager::get()->add_handler(handler, TIMER3_IRQn);

+ * }

+ * @endcode

+ */

+class InterruptManager {

+public:

+    /** Return the only instance of this class

+     */

+    static InterruptManager* get();

+

+    /** Destroy the current instance of the interrupt manager

+     */

+    static void destroy();

+

+    /** Add a handler for an interrupt at the end of the handler list

+     *

+     *  @param function the handler to add

+     *  @param irq interrupt number

+     *

+     *  @returns

+     *  The function object created for 'function'

+     */

+    pFunctionPointer_t add_handler(void (*function)(void), IRQn_Type irq) {

+        return add_common(function, irq);

+    }

+

+    /** Add a handler for an interrupt at the beginning of the handler list

+     *

+     *  @param function the handler to add

+     *  @param irq interrupt number

+     *

+     *  @returns

+     *  The function object created for 'function'

+     */

+    pFunctionPointer_t add_handler_front(void (*function)(void), IRQn_Type irq) {

+        return add_common(function, irq, true);

+    }

+

+    /** Add a handler for an interrupt at the end of the handler list

+     *

+     *  @param tptr pointer to the object that has the handler function

+     *  @param mptr pointer to the actual handler function

+     *  @param irq interrupt number

+     *

+     *  @returns

+     *  The function object created for 'tptr' and 'mptr'

+     */

+    template<typename T>

+    pFunctionPointer_t add_handler(T* tptr, void (T::*mptr)(void), IRQn_Type irq) {

+        return add_common(tptr, mptr, irq);

+    }

+

+    /** Add a handler for an interrupt at the beginning of the handler list

+     *

+     *  @param tptr pointer to the object that has the handler function

+     *  @param mptr pointer to the actual handler function

+     *  @param irq interrupt number

+     *

+     *  @returns

+     *  The function object created for 'tptr' and 'mptr'

+     */

+    template<typename T>

+    pFunctionPointer_t add_handler_front(T* tptr, void (T::*mptr)(void), IRQn_Type irq) {

+        return add_common(tptr, mptr, irq, true);

+    }

+

+    /** Remove a handler from an interrupt

+     *

+     *  @param handler the function object for the handler to remove

+     *  @param irq the interrupt number

+     *

+     *  @returns

+     *  true if the handler was found and removed, false otherwise

+     */

+    bool remove_handler(pFunctionPointer_t handler, IRQn_Type irq);

+

+private:

+    InterruptManager();

+    ~InterruptManager();

+

+    // We declare the copy contructor and the assignment operator, but we don't

+    // implement them. This way, if someone tries to copy/assign our instance,

+    // he will get an error at compile time.

+    InterruptManager(const InterruptManager&);

+    InterruptManager& operator =(const InterruptManager&);

+

+    template<typename T>

+    pFunctionPointer_t add_common(T *tptr, void (T::*mptr)(void), IRQn_Type irq, bool front=false) {

+        int irq_pos = get_irq_index(irq);

+        bool change = must_replace_vector(irq);

+

+        pFunctionPointer_t pf = front ? _chains[irq_pos]->add_front(tptr, mptr) : _chains[irq_pos]->add(tptr, mptr);

+        if (change)

+            NVIC_SetVector(irq, (uint32_t)&InterruptManager::static_irq_helper);

+        return pf;

+    }

+

+    pFunctionPointer_t add_common(void (*function)(void), IRQn_Type irq, bool front=false);

+    bool must_replace_vector(IRQn_Type irq);

+    int get_irq_index(IRQn_Type irq);

+    void irq_helper();

+    void add_helper(void (*function)(void), IRQn_Type irq, bool front=false);

+    static void static_irq_helper();

+

+    CallChain* _chains[NVIC_NUM_VECTORS];

+    static InterruptManager* _instance;

+};

+

+} // namespace mbed

+

+#endif

+

diff --git a/ext/LocalFileSystem.h b/ext/LocalFileSystem.h
new file mode 100644
index 0000000..75f13e4
--- /dev/null
+++ b/ext/LocalFileSystem.h
@@ -0,0 +1,103 @@
+/* mbed Microcontroller Library

+ * Copyright (c) 2006-2013 ARM Limited

+ *

+ * Licensed under the Apache License, Version 2.0 (the "License");

+ * you may not use this file except in compliance with the License.

+ * You may obtain a copy of the License at

+ *

+ *     http://www.apache.org/licenses/LICENSE-2.0

+ *

+ * Unless required by applicable law or agreed to in writing, software

+ * distributed under the License is distributed on an "AS IS" BASIS,

+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

+ * See the License for the specific language governing permissions and

+ * limitations under the License.

+ */

+#ifndef MBED_LOCALFILESYSTEM_H

+#define MBED_LOCALFILESYSTEM_H

+

+#include "platform.h"

+

+#if DEVICE_LOCALFILESYSTEM

+

+#include "FileSystemLike.h"

+

+namespace mbed {

+

+FILEHANDLE local_file_open(const char* name, int flags);

+

+class LocalFileHandle : public FileHandle {

+

+public:

+    LocalFileHandle(FILEHANDLE fh);

+

+    virtual int close();

+

+    virtual ssize_t write(const void *buffer, size_t length);

+

+    virtual ssize_t read(void *buffer, size_t length);

+

+    virtual int isatty();

+

+    virtual off_t lseek(off_t position, int whence);

+

+    virtual int fsync();

+

+    virtual off_t flen();

+

+protected:

+    FILEHANDLE _fh;

+    int pos;

+};

+

+/** A filesystem for accessing the local mbed Microcontroller USB disk drive

+ *

+ *  This allows programs to read and write files on the same disk drive that is used to program the

+ *  mbed Microcontroller. Once created, the standard C file access functions are used to open,

+ *  read and write files.

+ *

+ * Example:

+ * @code

+ * #include "mbed.h"

+ *

+ * LocalFileSystem local("local");               // Create the local filesystem under the name "local"

+ *

+ * int main() {

+ *     FILE *fp = fopen("/local/out.txt", "w");  // Open "out.txt" on the local file system for writing

+ *     fprintf(fp, "Hello World!");

+ *     fclose(fp);

+ *     remove("/local/out.txt");                 // Removes the file "out.txt" from the local file system

+ *

+ *     DIR *d = opendir("/local");               // Opens the root directory of the local file system

+ *     struct dirent *p;

+ *     while((p = readdir(d)) != NULL) {         // Print the names of the files in the local file system

+ *       printf("%s\n", p->d_name);              // to stdout.

+ *     }

+ *     closedir(d);

+ * }

+ * @endcode

+ *

+ * @note

+ *  If the microcontroller program makes an access to the local drive, it will be marked as "removed"

+ *  on the Host computer. This means it is no longer accessible from the Host Computer.

+ *

+ *  The drive will only re-appear when the microcontroller program exists. Note that if the program does

+ *  not exit, you will need to hold down reset on the mbed Microcontroller to be able to see the drive again!

+ */

+class LocalFileSystem : public FileSystemLike {

+

+public:

+    LocalFileSystem(const char* n) : FileSystemLike(n) {

+

+    }

+

+    virtual FileHandle *open(const char* name, int flags);

+    virtual int remove(const char *filename);

+    virtual DirHandle *opendir(const char *name);

+};

+

+} // namespace mbed

+

+#endif

+

+#endif

diff --git a/ext/LowPowerTicker.h b/ext/LowPowerTicker.h
new file mode 100644
index 0000000..540788c
--- /dev/null
+++ b/ext/LowPowerTicker.h
@@ -0,0 +1,44 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_LOWPOWERTICKER_H
+#define MBED_LOWPOWERTICKER_H
+
+#include "platform.h"
+#include "Ticker.h"
+
+#if DEVICE_LOWPOWERTIMER
+
+#include "lp_ticker_api.h"
+
+namespace mbed {
+
+/** Low Power Ticker
+ */
+class LowPowerTicker : public Ticker {
+
+public:
+    LowPowerTicker() : Ticker(get_lp_ticker_data()) {
+    }
+
+    virtual ~LowPowerTicker() {
+    }
+};
+
+} // namespace mbed
+
+#endif
+
+#endif
diff --git a/ext/LowPowerTimeout.h b/ext/LowPowerTimeout.h
new file mode 100644
index 0000000..c81e049
--- /dev/null
+++ b/ext/LowPowerTimeout.h
@@ -0,0 +1,42 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_LOWPOWERTIMEOUT_H
+#define MBED_LOWPOWERTIMEOUT_H
+
+#include "platform.h"
+
+#if DEVICE_LOWPOWERTIMER
+
+#include "lp_ticker_api.h"
+#include "LowPowerTicker.h"
+
+namespace mbed {
+
+/** Low Power Timout
+ */
+class LowPowerTimeout : public LowPowerTicker {
+
+private:
+    virtual void handler(void) {
+        _function.call();
+    }
+};
+
+}
+
+#endif
+
+#endif
diff --git a/ext/LowPowerTimer.h b/ext/LowPowerTimer.h
new file mode 100644
index 0000000..ad7782b
--- /dev/null
+++ b/ext/LowPowerTimer.h
@@ -0,0 +1,42 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_LOWPOWERTIMER_H
+#define MBED_LOWPOWERTIMER_H
+
+#include "platform.h"
+#include "Timer.h"
+
+#if DEVICE_LOWPOWERTIMER
+
+#include "lp_ticker_api.h"
+
+namespace mbed {
+
+/** Low power timer
+ */
+class LowPowerTimer : public Timer {
+
+public:
+    LowPowerTimer() : Timer(get_lp_ticker_data()) {
+    }
+
+};
+
+} // namespace mbed
+
+#endif
+
+#endif
diff --git a/ext/PortIn.h b/ext/PortIn.h
new file mode 100644
index 0000000..0134273
--- /dev/null
+++ b/ext/PortIn.h
@@ -0,0 +1,93 @@
+/* mbed Microcontroller Library

+ * Copyright (c) 2006-2013 ARM Limited

+ *

+ * Licensed under the Apache License, Version 2.0 (the "License");

+ * you may not use this file except in compliance with the License.

+ * You may obtain a copy of the License at

+ *

+ *     http://www.apache.org/licenses/LICENSE-2.0

+ *

+ * Unless required by applicable law or agreed to in writing, software

+ * distributed under the License is distributed on an "AS IS" BASIS,

+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

+ * See the License for the specific language governing permissions and

+ * limitations under the License.

+ */

+#ifndef MBED_PORTIN_H

+#define MBED_PORTIN_H

+

+#include "platform.h"

+

+#if DEVICE_PORTIN

+

+#include "port_api.h"

+

+namespace mbed {

+

+/** A multiple pin digital input

+ *

+ *  Example:

+ * @code

+ * // Switch on an LED if any of mbed pins 21-26 is high

+ *

+ * #include "mbed.h"

+ *

+ * PortIn     p(Port2, 0x0000003F);   // p21-p26

+ * DigitalOut ind(LED4);

+ *

+ * int main() {

+ *     while(1) {

+ *         int pins = p.read();

+ *         if(pins) {

+ *             ind = 1;

+ *         } else {

+ *             ind = 0;

+ *         }

+ *     }

+ * }

+ * @endcode

+ */

+class PortIn {

+public:

+

+    /** Create an PortIn, connected to the specified port

+     *

+     *  @param port Port to connect to (Port0-Port5)

+     *  @param mask A bitmask to identify which bits in the port should be included (0 - ignore)

+        */

+    PortIn(PortName port, int mask = 0xFFFFFFFF) {

+        port_init(&_port, port, mask, PIN_INPUT);

+    }

+

+    /** Read the value currently output on the port

+     *

+     *  @returns

+     *    An integer with each bit corresponding to associated port pin setting

+     */

+    int read() {

+        return port_read(&_port);

+    }

+

+    /** Set the input pin mode

+     *

+     *  @param mode PullUp, PullDown, PullNone, OpenDrain

+     */

+    void mode(PinMode mode) {

+        port_mode(&_port, mode);

+    }

+

+    /** A shorthand for read()

+     */

+    operator int() {

+        return read();

+    }

+

+private:

+    port_t _port;

+};

+

+} // namespace mbed

+

+#endif

+

+#endif

diff --git a/ext/PortInOut.h b/ext/PortInOut.h
new file mode 100644
index 0000000..909490f
--- /dev/null
+++ b/ext/PortInOut.h
@@ -0,0 +1,104 @@
+/* mbed Microcontroller Library

+ * Copyright (c) 2006-2013 ARM Limited

+ *

+ * Licensed under the Apache License, Version 2.0 (the "License");

+ * you may not use this file except in compliance with the License.

+ * You may obtain a copy of the License at

+ *

+ *     http://www.apache.org/licenses/LICENSE-2.0

+ *

+ * Unless required by applicable law or agreed to in writing, software

+ * distributed under the License is distributed on an "AS IS" BASIS,

+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

+ * See the License for the specific language governing permissions and

+ * limitations under the License.

+ */

+#ifndef MBED_PORTINOUT_H

+#define MBED_PORTINOUT_H

+

+#include "platform.h"

+

+#if DEVICE_PORTINOUT

+

+#include "port_api.h"

+

+namespace mbed {

+

+/** A multiple pin digital in/out used to set/read multiple bi-directional pins

+ */

+class PortInOut {

+public:

+

+    /** Create an PortInOut, connected to the specified port

+     *

+     *  @param port Port to connect to (Port0-Port5)

+     *  @param mask A bitmask to identify which bits in the port should be included (0 - ignore)

+     */

+    PortInOut(PortName port, int mask = 0xFFFFFFFF) {

+        port_init(&_port, port, mask, PIN_INPUT);

+    }

+

+    /** Write the value to the output port

+     *

+     *  @param value An integer specifying a bit to write for every corresponding port pin

+     */

+    void write(int value) {

+        port_write(&_port, value);

+    }

+

+    /** Read the value currently output on the port

+     *

+     *  @returns

+     *    An integer with each bit corresponding to associated port pin setting

+     */

+    int read() {

+        return port_read(&_port);

+    }

+

+    /** Set as an output

+     */

+    void output() {

+        port_dir(&_port, PIN_OUTPUT);

+    }

+

+    /** Set as an input

+     */

+    void input() {

+        port_dir(&_port, PIN_INPUT);

+    }

+

+    /** Set the input pin mode

+     *

+     *  @param mode PullUp, PullDown, PullNone, OpenDrain

+     */

+    void mode(PinMode mode) {

+        port_mode(&_port, mode);

+    }

+

+    /** A shorthand for write()

+     */

+    PortInOut& operator= (int value) {

+        write(value);

+        return *this;

+    }

+

+    PortInOut& operator= (PortInOut& rhs) {

+        write(rhs.read());

+        return *this;

+    }

+

+    /** A shorthand for read()

+     */

+    operator int() {

+        return read();

+    }

+

+private:

+    port_t _port;

+};

+

+} // namespace mbed

+

+#endif

+

+#endif

diff --git a/ext/PortOut.h b/ext/PortOut.h
new file mode 100644
index 0000000..2e3b1b1
--- /dev/null
+++ b/ext/PortOut.h
@@ -0,0 +1,104 @@
+/* mbed Microcontroller Library

+ * Copyright (c) 2006-2013 ARM Limited

+ *

+ * Licensed under the Apache License, Version 2.0 (the "License");

+ * you may not use this file except in compliance with the License.

+ * You may obtain a copy of the License at

+ *

+ *     http://www.apache.org/licenses/LICENSE-2.0

+ *

+ * Unless required by applicable law or agreed to in writing, software

+ * distributed under the License is distributed on an "AS IS" BASIS,

+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

+ * See the License for the specific language governing permissions and

+ * limitations under the License.

+ */

+#ifndef MBED_PORTOUT_H

+#define MBED_PORTOUT_H

+

+#include "platform.h"

+

+#if DEVICE_PORTOUT

+

+#include "port_api.h"

+

+namespace mbed {

+/** A multiple pin digital out

+ *

+ * Example:

+ * @code

+ * // Toggle all four LEDs

+ *

+ * #include "mbed.h"

+ *

+ * // LED1 = P1.18  LED2 = P1.20  LED3 = P1.21  LED4 = P1.23

+ * #define LED_MASK 0x00B40000

+ *

+ * PortOut ledport(Port1, LED_MASK);

+ *

+ * int main() {

+ *     while(1) {

+ *         ledport = LED_MASK;

+ *         wait(1);

+ *         ledport = 0;

+ *         wait(1);

+ *     }

+ * }

+ * @endcode

+ */

+class PortOut {

+public:

+

+    /** Create an PortOut, connected to the specified port

+     *

+     *  @param port Port to connect to (Port0-Port5)

+     *  @param mask A bitmask to identify which bits in the port should be included (0 - ignore)

+     */

+    PortOut(PortName port, int mask = 0xFFFFFFFF) {

+        port_init(&_port, port, mask, PIN_OUTPUT);

+    }

+

+    /** Write the value to the output port

+     *

+     *  @param value An integer specifying a bit to write for every corresponding PortOut pin

+     */

+    void write(int value) {

+        port_write(&_port, value);

+    }

+

+    /** Read the value currently output on the port

+     *

+     *  @returns

+     *    An integer with each bit corresponding to associated PortOut pin setting

+     */

+    int read() {

+        return port_read(&_port);

+    }

+

+    /** A shorthand for write()

+     */

+    PortOut& operator= (int value) {

+        write(value);

+        return *this;

+    }

+

+    PortOut& operator= (PortOut& rhs) {

+        write(rhs.read());

+        return *this;

+    }

+

+    /** A shorthand for read()

+     */

+    operator int() {

+        return read();

+    }

+

+private:

+    port_t _port;

+};

+

+} // namespace mbed

+

+#endif

+

+#endif

diff --git a/ext/PwmOut.h b/ext/PwmOut.h
new file mode 100644
index 0000000..ef3c60b
--- /dev/null
+++ b/ext/PwmOut.h
@@ -0,0 +1,158 @@
+/* mbed Microcontroller Library

+ * Copyright (c) 2006-2013 ARM Limited

+ *

+ * Licensed under the Apache License, Version 2.0 (the "License");

+ * you may not use this file except in compliance with the License.

+ * You may obtain a copy of the License at

+ *

+ *     http://www.apache.org/licenses/LICENSE-2.0

+ *

+ * Unless required by applicable law or agreed to in writing, software

+ * distributed under the License is distributed on an "AS IS" BASIS,

+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

+ * See the License for the specific language governing permissions and

+ * limitations under the License.

+ */

+#ifndef MBED_PWMOUT_H

+#define MBED_PWMOUT_H

+

+#include "platform.h"

+

+#if DEVICE_PWMOUT

+#include "pwmout_api.h"

+

+namespace mbed {

+

+/** A pulse-width modulation digital output

+ *

+ * Example

+ * @code

+ * // Fade a led on.

+ * #include "mbed.h"

+ *

+ * PwmOut led(LED1);

+ *

+ * int main() {

+ *     while(1) {

+ *         led = led + 0.01;

+ *         wait(0.2);

+ *         if(led == 1.0) {

+ *             led = 0;

+ *         }

+ *     }

+ * }

+ * @endcode

+ *

+ * @note

+ *  On the LPC1768 and LPC2368, the PWMs all share the same

+ *  period - if you change the period for one, you change it for all.

+ *  Although routines that change the period maintain the duty cycle

+ *  for its PWM, all other PWMs will require their duty cycle to be

+ *  refreshed.

+ */

+class PwmOut {

+

+public:

+

+    /** Create a PwmOut connected to the specified pin

+     *

+     *  @param pin PwmOut pin to connect to

+     */

+    PwmOut(PinName pin) {

+        pwmout_init(&_pwm, pin);

+    }

+

+    /** Set the ouput duty-cycle, specified as a percentage (float)

+     *

+     *  @param value A floating-point value representing the output duty-cycle,

+     *    specified as a percentage. The value should lie between

+     *    0.0f (representing on 0%) and 1.0f (representing on 100%).

+     *    Values outside this range will be saturated to 0.0f or 1.0f.

+     */

+    void write(float value) {

+        pwmout_write(&_pwm, value);

+    }

+

+    /** Return the current output duty-cycle setting, measured as a percentage (float)

+     *

+     *  @returns

+     *    A floating-point value representing the current duty-cycle being output on the pin,

+     *    measured as a percentage. The returned value will lie between

+     *    0.0f (representing on 0%) and 1.0f (representing on 100%).

+     *

+     *  @note

+     *  This value may not match exactly the value set by a previous <write>.

+     */

+    float read() {

+        return pwmout_read(&_pwm);

+    }

+

+    /** Set the PWM period, specified in seconds (float), keeping the duty cycle the same.

+     *

+     *  @note

+     *   The resolution is currently in microseconds; periods smaller than this

+     *   will be set to zero.

+     */

+    void period(float seconds) {

+        pwmout_period(&_pwm, seconds);

+    }

+

+    /** Set the PWM period, specified in milli-seconds (int), keeping the duty cycle the same.

+     */

+    void period_ms(int ms) {

+        pwmout_period_ms(&_pwm, ms);

+    }

+

+    /** Set the PWM period, specified in micro-seconds (int), keeping the duty cycle the same.

+     */

+    void period_us(int us) {

+        pwmout_period_us(&_pwm, us);

+    }

+

+    /** Set the PWM pulsewidth, specified in seconds (float), keeping the period the same.

+     */

+    void pulsewidth(float seconds) {

+        pwmout_pulsewidth(&_pwm, seconds);

+    }

+

+    /** Set the PWM pulsewidth, specified in milli-seconds (int), keeping the period the same.

+     */

+    void pulsewidth_ms(int ms) {

+        pwmout_pulsewidth_ms(&_pwm, ms);

+    }

+

+    /** Set the PWM pulsewidth, specified in micro-seconds (int), keeping the period the same.

+     */

+    void pulsewidth_us(int us) {

+        pwmout_pulsewidth_us(&_pwm, us);

+    }

+

+#ifdef MBED_OPERATORS

+    /** A operator shorthand for write()

+     */

+    PwmOut& operator= (float value) {

+        write(value);

+        return *this;

+    }

+

+    PwmOut& operator= (PwmOut& rhs) {

+        write(rhs.read());

+        return *this;

+    }

+

+    /** An operator shorthand for read()

+     */

+    operator float() {

+        return read();

+    }

+#endif

+

+protected:

+    pwmout_t _pwm;

+};

+

+} // namespace mbed

+

+#endif

+

+#endif

diff --git a/ext/RawSerial.h b/ext/RawSerial.h
new file mode 100644
index 0000000..a5182bb
--- /dev/null
+++ b/ext/RawSerial.h
@@ -0,0 +1,90 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_RAW_SERIAL_H
+#define MBED_RAW_SERIAL_H
+
+#include "platform.h"
+
+#if DEVICE_SERIAL
+
+#include "SerialBase.h"
+#include "serial_api.h"
+
+namespace mbed {
+
+/** A serial port (UART) for communication with other serial devices
+ * This is a variation of the Serial class that doesn't use streams,
+ * thus making it safe to use in interrupt handlers with the RTOS.
+ *
+ * Can be used for Full Duplex communication, or Simplex by specifying
+ * one pin as NC (Not Connected)
+ *
+ * Example:
+ * @code
+ * // Send a char to the PC
+ *
+ * #include "mbed.h"
+ *
+ * RawSerial pc(USBTX, USBRX);
+ *
+ * int main() {
+ *     pc.putc('A');
+ * }
+ * @endcode
+ */
+class RawSerial: public SerialBase {
+
+public:
+    /** Create a RawSerial port, connected to the specified transmit and receive pins
+     *
+     *  @param tx Transmit pin
+     *  @param rx Receive pin
+     *
+     *  @note
+     *    Either tx or rx may be specified as NC if unused
+     */
+    RawSerial(PinName tx, PinName rx);
+
+    /** Write a char to the serial port
+     *
+     * @param c The char to write
+     *
+     * @returns The written char or -1 if an error occured
+     */
+    int putc(int c);
+
+    /** Read a char from the serial port
+     *
+     * @returns The char read from the serial port
+     */
+    int getc();
+
+    /** Write a string to the serial port
+     *
+     * @param str The string to write
+     *
+     * @returns 0 if the write succeeds, EOF for error
+     */
+    int puts(const char *str);
+
+    int printf(const char *format, ...);
+};
+
+} // namespace mbed
+
+#endif
+
+#endif
diff --git a/ext/SPI.h b/ext/SPI.h
new file mode 100644
index 0000000..09a49b3
--- /dev/null
+++ b/ext/SPI.h
@@ -0,0 +1,245 @@
+/* mbed Microcontroller Library

+ * Copyright (c) 2006-2015 ARM Limited

+ *

+ * Licensed under the Apache License, Version 2.0 (the "License");

+ * you may not use this file except in compliance with the License.

+ * You may obtain a copy of the License at

+ *

+ *     http://www.apache.org/licenses/LICENSE-2.0

+ *

+ * Unless required by applicable law or agreed to in writing, software

+ * distributed under the License is distributed on an "AS IS" BASIS,

+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

+ * See the License for the specific language governing permissions and

+ * limitations under the License.

+ */

+#ifndef MBED_SPI_H

+#define MBED_SPI_H

+

+#include "platform.h"

+

+#if DEVICE_SPI

+

+#include "spi_api.h"

+

+#if DEVICE_SPI_ASYNCH

+#include "CThunk.h"

+#include "dma_api.h"

+#include "CircularBuffer.h"

+#include "FunctionPointer.h"

+#include "Transaction.h"

+#endif

+

+namespace mbed {

+

+/** A SPI Master, used for communicating with SPI slave devices

+ *

+ * The default format is set to 8-bits, mode 0, and a clock frequency of 1MHz

+ *

+ * Most SPI devices will also require Chip Select and Reset signals. These

+ * can be controlled using <DigitalOut> pins

+ *

+ * Example:

+ * @code

+ * // Send a byte to a SPI slave, and record the response

+ *

+ * #include "mbed.h"

+ *

+ * // hardware ssel (where applicable)

+ * //SPI device(p5, p6, p7, p8); // mosi, miso, sclk, ssel

+ *

+ * // software ssel

+ * SPI device(p5, p6, p7); // mosi, miso, sclk

+ * DigitalOut cs(p8); // ssel

+ *

+ * int main() {

+ *     // hardware ssel (where applicable)

+ *     //int response = device.write(0xFF);

+ *

+ *     // software ssel

+ *     cs = 0;

+ *     int response = device.write(0xFF);

+ *     cs = 1;

+ * }

+ * @endcode

+ */

+class SPI {

+

+public:

+

+    /** Create a SPI master connected to the specified pins

+     *

+     *  mosi or miso can be specfied as NC if not used

+     *

+     *  @param mosi SPI Master Out, Slave In pin

+     *  @param miso SPI Master In, Slave Out pin

+     *  @param sclk SPI Clock pin

+     *  @param ssel SPI chip select pin

+     */

+    SPI(PinName mosi, PinName miso, PinName sclk, PinName ssel=NC);

+

+    /** Configure the data transmission format

+     *

+     *  @param bits Number of bits per SPI frame (4 - 16)

+     *  @param mode Clock polarity and phase mode (0 - 3)

+     *

+     * @code

+     * mode | POL PHA

+     * -----+--------

+     *   0  |  0   0

+     *   1  |  0   1

+     *   2  |  1   0

+     *   3  |  1   1

+     * @endcode

+     */

+    void format(int bits, int mode = 0);

+

+    /** Set the spi bus clock frequency

+     *

+     *  @param hz SCLK frequency in hz (default = 1MHz)

+     */

+    void frequency(int hz = 1000000);

+

+    /** Write to the SPI Slave and return the response

+     *

+     *  @param value Data to be sent to the SPI slave

+     *

+     *  @returns

+     *    Response from the SPI slave

+    */

+    virtual int write(int value);

+

+#if DEVICE_SPI_ASYNCH

+

+    /** Start non-blocking SPI transfer using 8bit buffers.

+     *

+     * @param tx_buffer The TX buffer with data to be transfered. If NULL is passed,

+     *                  the default SPI value is sent

+     * @param tx_length The length of TX buffer in bytes

+     * @param rx_buffer The RX buffer which is used for received data. If NULL is passed,

+     *                  received data are ignored

+     * @param rx_length The length of RX buffer in bytes

+     * @param callback  The event callback function

+     * @param event     The logical OR of events to modify. Look at spi hal header file for SPI events.

+     * @return Zero if the transfer has started, or -1 if SPI peripheral is busy

+     */

+    template<typename Type>

+    int transfer(const Type *tx_buffer, int tx_length, Type *rx_buffer, int rx_length, const event_callback_t& callback, int event = SPI_EVENT_COMPLETE) {

+        if (spi_active(&_spi)) {

+            return queue_transfer(tx_buffer, tx_length, rx_buffer, rx_length, sizeof(Type)*8, callback, event);

+        }

+        start_transfer(tx_buffer, tx_length, rx_buffer, rx_length, sizeof(Type)*8, callback, event);

+        return 0;

+    }

+

+    /** Abort the on-going SPI transfer, and continue with transfer's in the queue if any.

+     */

+    void abort_transfer();

+

+    /** Clear the transaction buffer

+     */

+    void clear_transfer_buffer();

+

+    /** Clear the transaction buffer and abort on-going transfer.

+     */

+    void abort_all_transfers();

+

+    /** Configure DMA usage suggestion for non-blocking transfers

+     *

+     *  @param usage The usage DMA hint for peripheral

+     *  @return Zero if the usage was set, -1 if a transaction is on-going

+    */

+    int set_dma_usage(DMAUsage usage);

+

+protected:

+    /** SPI IRQ handler

+     *

+    */

+    void irq_handler_asynch(void);

+

+    /** Common transfer method

+     *

+     * @param tx_buffer The TX buffer with data to be transfered. If NULL is passed,

+     *                  the default SPI value is sent

+     * @param tx_length The length of TX buffer in bytes

+     * @param rx_buffer The RX buffer which is used for received data. If NULL is passed,

+     *                  received data are ignored

+     * @param rx_length The length of RX buffer in bytes

+     * @param bit_width The buffers element width

+     * @param callback  The event callback function

+     * @param event     The logical OR of events to modify

+     * @return Zero if the transfer has started or was added to the queue, or -1 if SPI peripheral is busy/buffer is full

+    */

+    int transfer(const void *tx_buffer, int tx_length, void *rx_buffer, int rx_length, unsigned char bit_width, const event_callback_t& callback, int event);

+

+    /**

+     *

+     * @param tx_buffer The TX buffer with data to be transfered. If NULL is passed,

+     *                  the default SPI value is sent

+     * @param tx_length The length of TX buffer in bytes

+     * @param rx_buffer The RX buffer which is used for received data. If NULL is passed,

+     *                  received data are ignored

+     * @param rx_length The length of RX buffer in bytes

+     * @param bit_width The buffers element width

+     * @param callback  The event callback function

+     * @param event     The logical OR of events to modify

+     * @return Zero if a transfer was added to the queue, or -1 if the queue is full

+    */

+    int queue_transfer(const void *tx_buffer, int tx_length, void *rx_buffer, int rx_length, unsigned char bit_width, const event_callback_t& callback, int event);

+

+    /** Configures a callback, spi peripheral and initiate a new transfer

+     *

+     * @param tx_buffer The TX buffer with data to be transfered. If NULL is passed,

+     *                  the default SPI value is sent

+     * @param tx_length The length of TX buffer in bytes

+     * @param rx_buffer The RX buffer which is used for received data. If NULL is passed,

+     *                  received data are ignored

+     * @param rx_length The length of RX buffer in bytes

+     * @param bit_width The buffers element width

+     * @param callback  The event callback function

+     * @param event     The logical OR of events to modify

+    */

+    void start_transfer(const void *tx_buffer, int tx_length, void *rx_buffer, int rx_length, unsigned char bit_width, const event_callback_t& callback, int event);

+

+#if TRANSACTION_QUEUE_SIZE_SPI

+

+    /** Start a new transaction

+     *

+     *  @param data Transaction data

+    */

+    void start_transaction(transaction_t *data);

+

+    /** Dequeue a transaction

+     *

+    */

+    void dequeue_transaction();

+    static CircularBuffer<Transaction<SPI>, TRANSACTION_QUEUE_SIZE_SPI> _transaction_buffer;

+#endif

+

+#endif

+

+public:

+    virtual ~SPI() {

+    }

+

+protected:

+    spi_t _spi;

+

+#if DEVICE_SPI_ASYNCH

+    CThunk<SPI> _irq;

+    event_callback_t _callback;

+    DMAUsage _usage;

+#endif

+

+    void aquire(void);

+    static SPI *_owner;

+    int _bits;

+    int _mode;

+    int _hz;

+};

+

+} // namespace mbed

+

+#endif

+

+#endif

diff --git a/ext/SPISlave.h b/ext/SPISlave.h
new file mode 100644
index 0000000..dc89dd1
--- /dev/null
+++ b/ext/SPISlave.h
@@ -0,0 +1,122 @@
+/* mbed Microcontroller Library

+ * Copyright (c) 2006-2013 ARM Limited

+ *

+ * Licensed under the Apache License, Version 2.0 (the "License");

+ * you may not use this file except in compliance with the License.

+ * You may obtain a copy of the License at

+ *

+ *     http://www.apache.org/licenses/LICENSE-2.0

+ *

+ * Unless required by applicable law or agreed to in writing, software

+ * distributed under the License is distributed on an "AS IS" BASIS,

+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

+ * See the License for the specific language governing permissions and

+ * limitations under the License.

+ */

+#ifndef MBED_SPISLAVE_H

+#define MBED_SPISLAVE_H

+

+#include "platform.h"

+

+#if DEVICE_SPISLAVE

+

+#include "spi_api.h"

+

+namespace mbed {

+

+/** A SPI slave, used for communicating with a SPI Master device

+ *

+ * The default format is set to 8-bits, mode 0, and a clock frequency of 1MHz

+ *

+ * Example:

+ * @code

+ * // Reply to a SPI master as slave

+ *

+ * #include "mbed.h"

+ *

+ * SPISlave device(p5, p6, p7, p8); // mosi, miso, sclk, ssel

+ *

+ * int main() {

+ *     device.reply(0x00);              // Prime SPI with first reply

+ *     while(1) {

+ *         if(device.receive()) {

+ *             int v = device.read();   // Read byte from master

+ *             v = (v + 1) % 0x100;     // Add one to it, modulo 256

+ *             device.reply(v);         // Make this the next reply

+ *         }

+ *     }

+ * }

+ * @endcode

+ */

+class SPISlave {

+

+public:

+

+    /** Create a SPI slave connected to the specified pins

+     *

+     *  mosi or miso can be specfied as NC if not used

+     *

+     *  @param mosi SPI Master Out, Slave In pin

+     *  @param miso SPI Master In, Slave Out pin

+     *  @param sclk SPI Clock pin

+     *  @param ssel SPI chip select pin

+     */

+    SPISlave(PinName mosi, PinName miso, PinName sclk, PinName ssel);

+

+    /** Configure the data transmission format

+     *

+     *  @param bits Number of bits per SPI frame (4 - 16)

+     *  @param mode Clock polarity and phase mode (0 - 3)

+     *

+     * @code

+     * mode | POL PHA

+     * -----+--------

+     *   0  |  0   0

+     *   1  |  0   1

+     *   2  |  1   0

+     *   3  |  1   1

+     * @endcode

+     */

+    void format(int bits, int mode = 0);

+

+    /** Set the spi bus clock frequency

+     *

+     *  @param hz SCLK frequency in hz (default = 1MHz)

+     */

+    void frequency(int hz = 1000000);

+

+    /** Polls the SPI to see if data has been received

+     *

+     *  @returns

+     *    0 if no data,

+     *    1 otherwise

+     */

+    int receive(void);

+

+    /** Retrieve  data from receive buffer as slave

+     *

+     *  @returns

+     *    the data in the receive buffer

+     */

+    int read(void);

+

+    /** Fill the transmission buffer with the value to be written out

+     *  as slave on the next received message from the master.

+     *

+     *  @param value the data to be transmitted next

+     */

+    void reply(int value);

+

+protected:

+    spi_t _spi;

+

+    int _bits;

+    int _mode;

+    int _hz;

+};

+

+} // namespace mbed

+

+#endif

+

+#endif

diff --git a/ext/Serial.h b/ext/Serial.h
new file mode 100644
index 0000000..7e04ce1
--- /dev/null
+++ b/ext/Serial.h
@@ -0,0 +1,74 @@
+/* mbed Microcontroller Library

+ * Copyright (c) 2006-2013 ARM Limited

+ *

+ * Licensed under the Apache License, Version 2.0 (the "License");

+ * you may not use this file except in compliance with the License.

+ * You may obtain a copy of the License at

+ *

+ *     http://www.apache.org/licenses/LICENSE-2.0

+ *

+ * Unless required by applicable law or agreed to in writing, software

+ * distributed under the License is distributed on an "AS IS" BASIS,

+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

+ * See the License for the specific language governing permissions and

+ * limitations under the License.

+ */

+#ifndef MBED_SERIAL_H

+#define MBED_SERIAL_H

+

+#include "platform.h"

+

+#if DEVICE_SERIAL

+

+#include "Stream.h"

+#include "SerialBase.h"

+#include "serial_api.h"

+

+namespace mbed {

+

+/** A serial port (UART) for communication with other serial devices

+ *

+ * Can be used for Full Duplex communication, or Simplex by specifying

+ * one pin as NC (Not Connected)

+ *

+ * Example:

+ * @code

+ * // Print "Hello World" to the PC

+ *

+ * #include "mbed.h"

+ *

+ * Serial pc(USBTX, USBRX);

+ *

+ * int main() {

+ *     pc.printf("Hello World\n");

+ * }

+ * @endcode

+ */

+class Serial : public SerialBase, public Stream {

+

+public:

+#if DEVICE_SERIAL_ASYNCH

+    using SerialBase::read;

+    using SerialBase::write;

+#endif

+

+    /** Create a Serial port, connected to the specified transmit and receive pins

+     *

+     *  @param tx Transmit pin

+     *  @param rx Receive pin

+     *

+     *  @note

+     *    Either tx or rx may be specified as NC if unused

+     */

+    Serial(PinName tx, PinName rx, const char *name=NULL);

+

+protected:

+    virtual int _getc();

+    virtual int _putc(int c);

+};

+

+} // namespace mbed

+

+#endif

+

+#endif

diff --git a/ext/SerialBase.h b/ext/SerialBase.h
new file mode 100644
index 0000000..51aeb33
--- /dev/null
+++ b/ext/SerialBase.h
@@ -0,0 +1,223 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_SERIALBASE_H
+#define MBED_SERIALBASE_H
+
+#include "platform.h"
+
+#if DEVICE_SERIAL
+
+#include "Stream.h"
+#include "FunctionPointer.h"
+#include "serial_api.h"
+
+#if DEVICE_SERIAL_ASYNCH
+#include "CThunk.h"
+#include "dma_api.h"
+#endif
+
+namespace mbed {
+
+/** A base class for serial port implementations
+ * Can't be instantiated directly (use Serial or RawSerial)
+ */
+class SerialBase {
+
+public:
+    /** Set the baud rate of the serial port
+     *
+     *  @param baudrate The baudrate of the serial port (default = 9600).
+     */
+    void baud(int baudrate);
+
+    enum Parity {
+        None = 0,
+        Odd,
+        Even,
+        Forced1,
+        Forced0
+    };
+
+    enum IrqType {
+        RxIrq = 0,
+        TxIrq
+    };
+
+    enum Flow {
+        Disabled = 0,
+        RTS,
+        CTS,
+        RTSCTS
+    };
+
+    /** Set the transmission format used by the serial port
+     *
+     *  @param bits The number of bits in a word (5-8; default = 8)
+     *  @param parity The parity used (SerialBase::None, SerialBase::Odd, SerialBase::Even, SerialBase::Forced1, SerialBase::Forced0; default = SerialBase::None)
+     *  @param stop The number of stop bits (1 or 2; default = 1)
+     */
+    void format(int bits=8, Parity parity=SerialBase::None, int stop_bits=1);
+
+    /** Determine if there is a character available to read
+     *
+     *  @returns
+     *    1 if there is a character available to read,
+     *    0 otherwise
+     */
+    int readable();
+
+    /** Determine if there is space available to write a character
+     *
+     *  @returns
+     *    1 if there is space to write a character,
+     *    0 otherwise
+     */
+    int writeable();
+
+    /** Attach a function to call whenever a serial interrupt is generated
+     *
+     *  @param fptr A pointer to a void function, or 0 to set as none
+     *  @param type Which serial interrupt to attach the member function to (Seriall::RxIrq for receive, TxIrq for transmit buffer empty)
+     */
+    void attach(void (*fptr)(void), IrqType type=RxIrq);
+
+    /** Attach a member function to call whenever a serial interrupt is generated
+     *
+     *  @param tptr pointer to the object to call the member function on
+     *  @param mptr pointer to the member function to be called
+     *  @param type Which serial interrupt to attach the member function to (Seriall::RxIrq for receive, TxIrq for transmit buffer empty)
+     */
+    template<typename T>
+    void attach(T* tptr, void (T::*mptr)(void), IrqType type=RxIrq) {
+        if((mptr != NULL) && (tptr != NULL)) {
+            _irq[type].attach(tptr, mptr);
+            serial_irq_set(&_serial, (SerialIrq)type, 1);
+        } else {
+            serial_irq_set(&_serial, (SerialIrq)type, 0);
+        }
+    }
+
+    /** Generate a break condition on the serial line
+     */
+    void send_break();
+
+#if DEVICE_SERIAL_FC
+    /** Set the flow control type on the serial port
+     *
+     *  @param type the flow control type (Disabled, RTS, CTS, RTSCTS)
+     *  @param flow1 the first flow control pin (RTS for RTS or RTSCTS, CTS for CTS)
+     *  @param flow2 the second flow control pin (CTS for RTSCTS)
+     */
+    void set_flow_control(Flow type, PinName flow1=NC, PinName flow2=NC);
+#endif
+
+    static void _irq_handler(uint32_t id, SerialIrq irq_type);
+
+#if DEVICE_SERIAL_ASYNCH
+
+    /** Begin asynchronous write using 8bit buffer. The completition invokes registered TX event callback
+     *
+     *  @param buffer   The buffer where received data will be stored
+     *  @param length   The buffer length in bytes
+     *  @param callback The event callback function
+     *  @param event    The logical OR of TX events
+     */
+    int write(const uint8_t *buffer, int length, const event_callback_t& callback, int event = SERIAL_EVENT_TX_COMPLETE);
+
+    /** Begin asynchronous write using 16bit buffer. The completition invokes registered TX event callback
+     *
+     *  @param buffer   The buffer where received data will be stored
+     *  @param length   The buffer length in bytes
+     *  @param callback The event callback function
+     *  @param event    The logical OR of TX events
+     */
+    int write(const uint16_t *buffer, int length, const event_callback_t& callback, int event = SERIAL_EVENT_TX_COMPLETE);
+
+    /** Abort the on-going write transfer
+     */
+    void abort_write();
+
+    /** Begin asynchronous reading using 8bit buffer. The completition invokes registred RX event callback.
+     *
+     *  @param buffer     The buffer where received data will be stored
+     *  @param length     The buffer length in bytes
+     *  @param callback   The event callback function
+     *  @param event      The logical OR of RX events
+     *  @param char_match The matching character
+     */
+    int read(uint8_t *buffer, int length, const event_callback_t& callback, int event = SERIAL_EVENT_RX_COMPLETE, unsigned char char_match = SERIAL_RESERVED_CHAR_MATCH);
+
+    /** Begin asynchronous reading using 16bit buffer. The completition invokes registred RX event callback.
+     *
+     *  @param buffer     The buffer where received data will be stored
+     *  @param length     The buffer length in bytes
+     *  @param callback   The event callback function
+     *  @param event      The logical OR of RX events
+     *  @param char_match The matching character
+     */
+    int read(uint16_t *buffer, int length, const event_callback_t& callback, int event = SERIAL_EVENT_RX_COMPLETE, unsigned char char_match = SERIAL_RESERVED_CHAR_MATCH);
+
+    /** Abort the on-going read transfer
+     */
+    void abort_read();
+
+    /** Configure DMA usage suggestion for non-blocking TX transfers
+     *
+     *  @param usage The usage DMA hint for peripheral
+     *  @return Zero if the usage was set, -1 if a transaction is on-going
+     */
+    int set_dma_usage_tx(DMAUsage usage);
+
+    /** Configure DMA usage suggestion for non-blocking RX transfers
+     *
+     *  @param usage The usage DMA hint for peripheral
+     *  @return Zero if the usage was set, -1 if a transaction is on-going
+     */
+    int set_dma_usage_rx(DMAUsage usage);
+
+protected:
+    void start_read(void *buffer, int buffer_size, char buffer_width, const event_callback_t& callback, int event, unsigned char char_match);
+    void start_write(const void *buffer, int buffer_size, char buffer_width, const event_callback_t& callback, int event);
+    void interrupt_handler_asynch(void);
+#endif
+
+protected:
+    SerialBase(PinName tx, PinName rx);
+    virtual ~SerialBase() {
+    }
+
+    int _base_getc();
+    int _base_putc(int c);
+
+#if DEVICE_SERIAL_ASYNCH
+    CThunk<SerialBase> _thunk_irq;
+    event_callback_t _tx_callback;
+    event_callback_t _rx_callback;
+    DMAUsage _tx_usage;
+    DMAUsage _rx_usage;
+#endif
+
+    serial_t        _serial;
+    FunctionPointer _irq[2];
+    int             _baud;
+
+};
+
+} // namespace mbed
+
+#endif
+
+#endif
diff --git a/ext/Stream.h b/ext/Stream.h
new file mode 100644
index 0000000..b9c7e14
--- /dev/null
+++ b/ext/Stream.h
@@ -0,0 +1,68 @@
+/* mbed Microcontroller Library

+ * Copyright (c) 2006-2013 ARM Limited

+ *

+ * Licensed under the Apache License, Version 2.0 (the "License");

+ * you may not use this file except in compliance with the License.

+ * You may obtain a copy of the License at

+ *

+ *     http://www.apache.org/licenses/LICENSE-2.0

+ *

+ * Unless required by applicable law or agreed to in writing, software

+ * distributed under the License is distributed on an "AS IS" BASIS,

+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

+ * See the License for the specific language governing permissions and

+ * limitations under the License.

+ */

+#ifndef MBED_STREAM_H

+#define MBED_STREAM_H

+

+#include "platform.h"

+#include "FileLike.h"

+#include <cstdarg>

+

+namespace mbed {

+

+extern void mbed_set_unbuffered_stream(FILE *_file);

+extern int mbed_getc(FILE *_file);

+extern char* mbed_gets(char *s, int size, FILE *_file);

+

+class Stream : public FileLike {

+

+public:

+    Stream(const char *name=NULL);

+    virtual ~Stream();

+

+    int putc(int c);

+    int puts(const char *s);

+    int getc();

+    char *gets(char *s, int size);

+    int printf(const char* format, ...);

+    int scanf(const char* format, ...);

+    int vprintf(const char* format, std::va_list args);

+    int vscanf(const char* format, std::va_list args);

+

+    operator std::FILE*() {return _file;}

+

+protected:

+    virtual int close();

+    virtual ssize_t write(const void* buffer, size_t length);

+    virtual ssize_t read(void* buffer, size_t length);

+    virtual off_t lseek(off_t offset, int whence);

+    virtual int isatty();

+    virtual int fsync();

+    virtual off_t flen();

+

+    virtual int _putc(int c) = 0;

+    virtual int _getc() = 0;

+

+    std::FILE *_file;

+

+    /* disallow copy constructor and assignment operators */

+private:

+    Stream(const Stream&);

+    Stream & operator = (const Stream&);

+};

+

+} // namespace mbed

+

+#endif

diff --git a/ext/TARGET_LPC1768/LPC17xx.h b/ext/TARGET_LPC1768/LPC17xx.h
new file mode 100644
index 0000000..8c4050b
--- /dev/null
+++ b/ext/TARGET_LPC1768/LPC17xx.h
@@ -0,0 +1,1035 @@
+/**************************************************************************//**

+ * @file     LPC17xx.h

+ * @brief    CMSIS Cortex-M3 Core Peripheral Access Layer Header File for 

+ *           NXP LPC17xx Device Series

+ * @version: V1.09

+ * @date:    17. March 2010

+

+ *

+ * @note

+ * Copyright (C) 2009 ARM Limited. All rights reserved.

+ *

+ * @par

+ * ARM Limited (ARM) is supplying this software for use with Cortex-M 

+ * processor based microcontrollers.  This file can be freely distributed 

+ * within development tools that are supporting such ARM based processors. 

+ *

+ * @par

+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED

+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF

+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.

+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR

+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.

+ *

+ ******************************************************************************/

+

+

+#ifndef __LPC17xx_H__

+#define __LPC17xx_H__

+

+/*

+ * ==========================================================================

+ * ---------- Interrupt Number Definition -----------------------------------

+ * ==========================================================================

+ */

+

+typedef enum IRQn

+{

+/******  Cortex-M3 Processor Exceptions Numbers ***************************************************/

+  NonMaskableInt_IRQn           = -14,      /*!< 2 Non Maskable Interrupt                         */

+  MemoryManagement_IRQn         = -12,      /*!< 4 Cortex-M3 Memory Management Interrupt          */

+  BusFault_IRQn                 = -11,      /*!< 5 Cortex-M3 Bus Fault Interrupt                  */

+  UsageFault_IRQn               = -10,      /*!< 6 Cortex-M3 Usage Fault Interrupt                */

+  SVCall_IRQn                   = -5,       /*!< 11 Cortex-M3 SV Call Interrupt                   */

+  DebugMonitor_IRQn             = -4,       /*!< 12 Cortex-M3 Debug Monitor Interrupt             */

+  PendSV_IRQn                   = -2,       /*!< 14 Cortex-M3 Pend SV Interrupt                   */

+  SysTick_IRQn                  = -1,       /*!< 15 Cortex-M3 System Tick Interrupt               */

+

+/******  LPC17xx Specific Interrupt Numbers *******************************************************/

+  WDT_IRQn                      = 0,        /*!< Watchdog Timer Interrupt                         */

+  TIMER0_IRQn                   = 1,        /*!< Timer0 Interrupt                                 */

+  TIMER1_IRQn                   = 2,        /*!< Timer1 Interrupt                                 */

+  TIMER2_IRQn                   = 3,        /*!< Timer2 Interrupt                                 */

+  TIMER3_IRQn                   = 4,        /*!< Timer3 Interrupt                                 */

+  UART0_IRQn                    = 5,        /*!< UART0 Interrupt                                  */

+  UART1_IRQn                    = 6,        /*!< UART1 Interrupt                                  */

+  UART2_IRQn                    = 7,        /*!< UART2 Interrupt                                  */

+  UART3_IRQn                    = 8,        /*!< UART3 Interrupt                                  */

+  PWM1_IRQn                     = 9,        /*!< PWM1 Interrupt                                   */

+  I2C0_IRQn                     = 10,       /*!< I2C0 Interrupt                                   */

+  I2C1_IRQn                     = 11,       /*!< I2C1 Interrupt                                   */

+  I2C2_IRQn                     = 12,       /*!< I2C2 Interrupt                                   */

+  SPI_IRQn                      = 13,       /*!< SPI Interrupt                                    */

+  SSP0_IRQn                     = 14,       /*!< SSP0 Interrupt                                   */

+  SSP1_IRQn                     = 15,       /*!< SSP1 Interrupt                                   */

+  PLL0_IRQn                     = 16,       /*!< PLL0 Lock (Main PLL) Interrupt                   */

+  RTC_IRQn                      = 17,       /*!< Real Time Clock Interrupt                        */

+  EINT0_IRQn                    = 18,       /*!< External Interrupt 0 Interrupt                   */

+  EINT1_IRQn                    = 19,       /*!< External Interrupt 1 Interrupt                   */

+  EINT2_IRQn                    = 20,       /*!< External Interrupt 2 Interrupt                   */

+  EINT3_IRQn                    = 21,       /*!< External Interrupt 3 Interrupt                   */

+  ADC_IRQn                      = 22,       /*!< A/D Converter Interrupt                          */

+  BOD_IRQn                      = 23,       /*!< Brown-Out Detect Interrupt                       */

+  USB_IRQn                      = 24,       /*!< USB Interrupt                                    */

+  CAN_IRQn                      = 25,       /*!< CAN Interrupt                                    */

+  DMA_IRQn                      = 26,       /*!< General Purpose DMA Interrupt                    */

+  I2S_IRQn                      = 27,       /*!< I2S Interrupt                                    */

+  ENET_IRQn                     = 28,       /*!< Ethernet Interrupt                               */

+  RIT_IRQn                      = 29,       /*!< Repetitive Interrupt Timer Interrupt             */

+  MCPWM_IRQn                    = 30,       /*!< Motor Control PWM Interrupt                      */

+  QEI_IRQn                      = 31,       /*!< Quadrature Encoder Interface Interrupt           */

+  PLL1_IRQn                     = 32,       /*!< PLL1 Lock (USB PLL) Interrupt                    */

+  USBActivity_IRQn              = 33,       /* USB Activity interrupt                             */

+  CANActivity_IRQn              = 34,       /* CAN Activity interrupt                             */

+} IRQn_Type;

+

+

+/*

+ * ==========================================================================

+ * ----------- Processor and Core Peripheral Section ------------------------

+ * ==========================================================================

+ */

+

+/* Configuration of the Cortex-M3 Processor and Core Peripherals */

+#define __MPU_PRESENT             1         /*!< MPU present or not                               */

+#define __NVIC_PRIO_BITS          5         /*!< Number of Bits used for Priority Levels          */

+#define __Vendor_SysTickConfig    0         /*!< Set to 1 if different SysTick Config is used     */

+

+

+#include "core_cm3.h"                       /* Cortex-M3 processor and core peripherals           */

+#include "system_LPC17xx.h"                 /* System Header                                      */

+

+

+/******************************************************************************/

+/*                Device Specific Peripheral registers structures             */

+/******************************************************************************/

+

+#if defined ( __CC_ARM   )

+#pragma anon_unions

+#endif

+

+/*------------- System Control (SC) ------------------------------------------*/

+typedef struct

+{

+  __IO uint32_t FLASHCFG;               /* Flash Accelerator Module           */

+       uint32_t RESERVED0[31];

+  __IO uint32_t PLL0CON;                /* Clocking and Power Control         */

+  __IO uint32_t PLL0CFG;

+  __I  uint32_t PLL0STAT;

+  __O  uint32_t PLL0FEED;

+       uint32_t RESERVED1[4];

+  __IO uint32_t PLL1CON;

+  __IO uint32_t PLL1CFG;

+  __I  uint32_t PLL1STAT;

+  __O  uint32_t PLL1FEED;

+       uint32_t RESERVED2[4];

+  __IO uint32_t PCON;

+  __IO uint32_t PCONP;

+       uint32_t RESERVED3[15];

+  __IO uint32_t CCLKCFG;

+  __IO uint32_t USBCLKCFG;

+  __IO uint32_t CLKSRCSEL;

+  __IO uint32_t	CANSLEEPCLR;

+  __IO uint32_t	CANWAKEFLAGS;

+       uint32_t RESERVED4[10];

+  __IO uint32_t EXTINT;                 /* External Interrupts                */

+       uint32_t RESERVED5;

+  __IO uint32_t EXTMODE;

+  __IO uint32_t EXTPOLAR;

+       uint32_t RESERVED6[12];

+  __IO uint32_t RSID;                   /* Reset                              */

+       uint32_t RESERVED7[7];

+  __IO uint32_t SCS;                    /* Syscon Miscellaneous Registers     */

+  __IO uint32_t IRCTRIM;                /* Clock Dividers                     */

+  __IO uint32_t PCLKSEL0;

+  __IO uint32_t PCLKSEL1;

+       uint32_t RESERVED8[4];

+  __IO uint32_t USBIntSt;               /* USB Device/OTG Interrupt Register  */

+  __IO uint32_t DMAREQSEL;

+  __IO uint32_t CLKOUTCFG;              /* Clock Output Configuration         */

+ } LPC_SC_TypeDef;

+

+/*------------- Pin Connect Block (PINCON) -----------------------------------*/

+typedef struct

+{

+  __IO uint32_t PINSEL0;

+  __IO uint32_t PINSEL1;

+  __IO uint32_t PINSEL2;

+  __IO uint32_t PINSEL3;

+  __IO uint32_t PINSEL4;

+  __IO uint32_t PINSEL5;

+  __IO uint32_t PINSEL6;

+  __IO uint32_t PINSEL7;

+  __IO uint32_t PINSEL8;

+  __IO uint32_t PINSEL9;

+  __IO uint32_t PINSEL10;

+       uint32_t RESERVED0[5];

+  __IO uint32_t PINMODE0;

+  __IO uint32_t PINMODE1;

+  __IO uint32_t PINMODE2;

+  __IO uint32_t PINMODE3;

+  __IO uint32_t PINMODE4;

+  __IO uint32_t PINMODE5;

+  __IO uint32_t PINMODE6;

+  __IO uint32_t PINMODE7;

+  __IO uint32_t PINMODE8;

+  __IO uint32_t PINMODE9;

+  __IO uint32_t PINMODE_OD0;

+  __IO uint32_t PINMODE_OD1;

+  __IO uint32_t PINMODE_OD2;

+  __IO uint32_t PINMODE_OD3;

+  __IO uint32_t PINMODE_OD4;

+  __IO uint32_t I2CPADCFG;

+} LPC_PINCON_TypeDef;

+

+/*------------- General Purpose Input/Output (GPIO) --------------------------*/

+typedef struct

+{

+  union {

+    __IO uint32_t FIODIR;

+    struct {

+      __IO uint16_t FIODIRL;

+      __IO uint16_t FIODIRH;

+    };

+    struct {

+      __IO uint8_t  FIODIR0;

+      __IO uint8_t  FIODIR1;

+      __IO uint8_t  FIODIR2;

+      __IO uint8_t  FIODIR3;

+    };

+  };

+  uint32_t RESERVED0[3];

+  union {

+    __IO uint32_t FIOMASK;

+    struct {

+      __IO uint16_t FIOMASKL;

+      __IO uint16_t FIOMASKH;

+    };

+    struct {

+      __IO uint8_t  FIOMASK0;

+      __IO uint8_t  FIOMASK1;

+      __IO uint8_t  FIOMASK2;

+      __IO uint8_t  FIOMASK3;

+    };

+  };

+  union {

+    __IO uint32_t FIOPIN;

+    struct {

+      __IO uint16_t FIOPINL;

+      __IO uint16_t FIOPINH;

+    };

+    struct {

+      __IO uint8_t  FIOPIN0;

+      __IO uint8_t  FIOPIN1;

+      __IO uint8_t  FIOPIN2;

+      __IO uint8_t  FIOPIN3;

+    };

+  };

+  union {

+    __IO uint32_t FIOSET;

+    struct {

+      __IO uint16_t FIOSETL;

+      __IO uint16_t FIOSETH;

+    };

+    struct {

+      __IO uint8_t  FIOSET0;

+      __IO uint8_t  FIOSET1;

+      __IO uint8_t  FIOSET2;

+      __IO uint8_t  FIOSET3;

+    };

+  };

+  union {

+    __O  uint32_t FIOCLR;

+    struct {

+      __O  uint16_t FIOCLRL;

+      __O  uint16_t FIOCLRH;

+    };

+    struct {

+      __O  uint8_t  FIOCLR0;

+      __O  uint8_t  FIOCLR1;

+      __O  uint8_t  FIOCLR2;

+      __O  uint8_t  FIOCLR3;

+    };

+  };

+} LPC_GPIO_TypeDef;

+

+typedef struct

+{

+  __I  uint32_t IntStatus;

+  __I  uint32_t IO0IntStatR;

+  __I  uint32_t IO0IntStatF;

+  __O  uint32_t IO0IntClr;

+  __IO uint32_t IO0IntEnR;

+  __IO uint32_t IO0IntEnF;

+       uint32_t RESERVED0[3];

+  __I  uint32_t IO2IntStatR;

+  __I  uint32_t IO2IntStatF;

+  __O  uint32_t IO2IntClr;

+  __IO uint32_t IO2IntEnR;

+  __IO uint32_t IO2IntEnF;

+} LPC_GPIOINT_TypeDef;

+

+/*------------- Timer (TIM) --------------------------------------------------*/

+typedef struct

+{

+  __IO uint32_t IR;

+  __IO uint32_t TCR;

+  __IO uint32_t TC;

+  __IO uint32_t PR;

+  __IO uint32_t PC;

+  __IO uint32_t MCR;

+  __IO uint32_t MR0;

+  __IO uint32_t MR1;

+  __IO uint32_t MR2;

+  __IO uint32_t MR3;

+  __IO uint32_t CCR;

+  __I  uint32_t CR0;

+  __I  uint32_t CR1;

+       uint32_t RESERVED0[2];

+  __IO uint32_t EMR;

+       uint32_t RESERVED1[12];

+  __IO uint32_t CTCR;

+} LPC_TIM_TypeDef;

+

+/*------------- Pulse-Width Modulation (PWM) ---------------------------------*/

+typedef struct

+{

+  __IO uint32_t IR;

+  __IO uint32_t TCR;

+  __IO uint32_t TC;

+  __IO uint32_t PR;

+  __IO uint32_t PC;

+  __IO uint32_t MCR;

+  __IO uint32_t MR0;

+  __IO uint32_t MR1;

+  __IO uint32_t MR2;

+  __IO uint32_t MR3;

+  __IO uint32_t CCR;

+  __I  uint32_t CR0;

+  __I  uint32_t CR1;

+  __I  uint32_t CR2;

+  __I  uint32_t CR3;

+       uint32_t RESERVED0;

+  __IO uint32_t MR4;

+  __IO uint32_t MR5;

+  __IO uint32_t MR6;

+  __IO uint32_t PCR;

+  __IO uint32_t LER;

+       uint32_t RESERVED1[7];

+  __IO uint32_t CTCR;

+} LPC_PWM_TypeDef;

+

+/*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/

+typedef struct

+{

+  union {

+  __I  uint8_t  RBR;

+  __O  uint8_t  THR;

+  __IO uint8_t  DLL;

+       uint32_t RESERVED0;

+  };

+  union {

+  __IO uint8_t  DLM;

+  __IO uint32_t IER;

+  };

+  union {

+  __I  uint32_t IIR;

+  __O  uint8_t  FCR;

+  };

+  __IO uint8_t  LCR;

+       uint8_t  RESERVED1[7];

+  __I  uint8_t  LSR;

+       uint8_t  RESERVED2[7];

+  __IO uint8_t  SCR;

+       uint8_t  RESERVED3[3];

+  __IO uint32_t ACR;

+  __IO uint8_t  ICR;

+       uint8_t  RESERVED4[3];

+  __IO uint8_t  FDR;

+       uint8_t  RESERVED5[7];

+  __IO uint8_t  TER;

+       uint8_t  RESERVED6[39];

+  __IO uint32_t FIFOLVL;

+} LPC_UART_TypeDef;

+

+typedef struct

+{

+  union {

+  __I  uint8_t  RBR;

+  __O  uint8_t  THR;

+  __IO uint8_t  DLL;

+       uint32_t RESERVED0;

+  };

+  union {

+  __IO uint8_t  DLM;

+  __IO uint32_t IER;

+  };

+  union {

+  __I  uint32_t IIR;

+  __O  uint8_t  FCR;

+  };

+  __IO uint8_t  LCR;

+       uint8_t  RESERVED1[7];

+  __I  uint8_t  LSR;

+       uint8_t  RESERVED2[7];

+  __IO uint8_t  SCR;

+       uint8_t  RESERVED3[3];

+  __IO uint32_t ACR;

+  __IO uint8_t  ICR;

+       uint8_t  RESERVED4[3];

+  __IO uint8_t  FDR;

+       uint8_t  RESERVED5[7];

+  __IO uint8_t  TER;

+       uint8_t  RESERVED6[39];

+  __IO uint32_t FIFOLVL;

+} LPC_UART0_TypeDef;

+

+typedef struct

+{

+  union {

+  __I  uint8_t  RBR;

+  __O  uint8_t  THR;

+  __IO uint8_t  DLL;

+       uint32_t RESERVED0;

+  };

+  union {

+  __IO uint8_t  DLM;

+  __IO uint32_t IER;

+  };

+  union {

+  __I  uint32_t IIR;

+  __O  uint8_t  FCR;

+  };

+  __IO uint8_t  LCR;

+       uint8_t  RESERVED1[3];

+  __IO uint8_t  MCR;

+       uint8_t  RESERVED2[3];

+  __I  uint8_t  LSR;

+       uint8_t  RESERVED3[3];

+  __I  uint8_t  MSR;

+       uint8_t  RESERVED4[3];

+  __IO uint8_t  SCR;

+       uint8_t  RESERVED5[3];

+  __IO uint32_t ACR;

+       uint32_t RESERVED6;

+  __IO uint32_t FDR;

+       uint32_t RESERVED7;

+  __IO uint8_t  TER;

+       uint8_t  RESERVED8[27];

+  __IO uint8_t  RS485CTRL;

+       uint8_t  RESERVED9[3];

+  __IO uint8_t  ADRMATCH;

+       uint8_t  RESERVED10[3];

+  __IO uint8_t  RS485DLY;

+       uint8_t  RESERVED11[3];

+  __IO uint32_t FIFOLVL;

+} LPC_UART1_TypeDef;

+

+/*------------- Serial Peripheral Interface (SPI) ----------------------------*/

+typedef struct

+{

+  __IO uint32_t SPCR;

+  __I  uint32_t SPSR;

+  __IO uint32_t SPDR;

+  __IO uint32_t SPCCR;

+       uint32_t RESERVED0[3];

+  __IO uint32_t SPINT;

+} LPC_SPI_TypeDef;

+

+/*------------- Synchronous Serial Communication (SSP) -----------------------*/

+typedef struct

+{

+  __IO uint32_t CR0;

+  __IO uint32_t CR1;

+  __IO uint32_t DR;

+  __I  uint32_t SR;

+  __IO uint32_t CPSR;

+  __IO uint32_t IMSC;

+  __IO uint32_t RIS;

+  __IO uint32_t MIS;

+  __IO uint32_t ICR;

+  __IO uint32_t DMACR;

+} LPC_SSP_TypeDef;

+

+/*------------- Inter-Integrated Circuit (I2C) -------------------------------*/

+typedef struct

+{

+  __IO uint32_t I2CONSET;

+  __I  uint32_t I2STAT;

+  __IO uint32_t I2DAT;

+  __IO uint32_t I2ADR0;

+  __IO uint32_t I2SCLH;

+  __IO uint32_t I2SCLL;

+  __O  uint32_t I2CONCLR;

+  __IO uint32_t MMCTRL;

+  __IO uint32_t I2ADR1;

+  __IO uint32_t I2ADR2;

+  __IO uint32_t I2ADR3;

+  __I  uint32_t I2DATA_BUFFER;

+  __IO uint32_t I2MASK0;

+  __IO uint32_t I2MASK1;

+  __IO uint32_t I2MASK2;

+  __IO uint32_t I2MASK3;

+} LPC_I2C_TypeDef;

+

+/*------------- Inter IC Sound (I2S) -----------------------------------------*/

+typedef struct

+{

+  __IO uint32_t I2SDAO;

+  __IO uint32_t I2SDAI;

+  __O  uint32_t I2STXFIFO;

+  __I  uint32_t I2SRXFIFO;

+  __I  uint32_t I2SSTATE;

+  __IO uint32_t I2SDMA1;

+  __IO uint32_t I2SDMA2;

+  __IO uint32_t I2SIRQ;

+  __IO uint32_t I2STXRATE;

+  __IO uint32_t I2SRXRATE;

+  __IO uint32_t I2STXBITRATE;

+  __IO uint32_t I2SRXBITRATE;

+  __IO uint32_t I2STXMODE;

+  __IO uint32_t I2SRXMODE;

+} LPC_I2S_TypeDef;

+

+/*------------- Repetitive Interrupt Timer (RIT) -----------------------------*/

+typedef struct

+{

+  __IO uint32_t RICOMPVAL;

+  __IO uint32_t RIMASK;

+  __IO uint8_t  RICTRL;

+       uint8_t  RESERVED0[3];

+  __IO uint32_t RICOUNTER;

+} LPC_RIT_TypeDef;

+

+/*------------- Real-Time Clock (RTC) ----------------------------------------*/

+typedef struct

+{

+  __IO uint8_t  ILR;

+       uint8_t  RESERVED0[7];

+  __IO uint8_t  CCR;

+       uint8_t  RESERVED1[3];

+  __IO uint8_t  CIIR;

+       uint8_t  RESERVED2[3];

+  __IO uint8_t  AMR;

+       uint8_t  RESERVED3[3];

+  __I  uint32_t CTIME0;

+  __I  uint32_t CTIME1;

+  __I  uint32_t CTIME2;

+  __IO uint8_t  SEC;

+       uint8_t  RESERVED4[3];

+  __IO uint8_t  MIN;

+       uint8_t  RESERVED5[3];

+  __IO uint8_t  HOUR;

+       uint8_t  RESERVED6[3];

+  __IO uint8_t  DOM;

+       uint8_t  RESERVED7[3];

+  __IO uint8_t  DOW;

+       uint8_t  RESERVED8[3];

+  __IO uint16_t DOY;

+       uint16_t RESERVED9;

+  __IO uint8_t  MONTH;

+       uint8_t  RESERVED10[3];

+  __IO uint16_t YEAR;

+       uint16_t RESERVED11;

+  __IO uint32_t CALIBRATION;

+  __IO uint32_t GPREG0;

+  __IO uint32_t GPREG1;

+  __IO uint32_t GPREG2;

+  __IO uint32_t GPREG3;

+  __IO uint32_t GPREG4;

+  __IO uint8_t  RTC_AUXEN;

+       uint8_t  RESERVED12[3];

+  __IO uint8_t  RTC_AUX;

+       uint8_t  RESERVED13[3];

+  __IO uint8_t  ALSEC;

+       uint8_t  RESERVED14[3];

+  __IO uint8_t  ALMIN;

+       uint8_t  RESERVED15[3];

+  __IO uint8_t  ALHOUR;

+       uint8_t  RESERVED16[3];

+  __IO uint8_t  ALDOM;

+       uint8_t  RESERVED17[3];

+  __IO uint8_t  ALDOW;

+       uint8_t  RESERVED18[3];

+  __IO uint16_t ALDOY;

+       uint16_t RESERVED19;

+  __IO uint8_t  ALMON;

+       uint8_t  RESERVED20[3];

+  __IO uint16_t ALYEAR;

+       uint16_t RESERVED21;

+} LPC_RTC_TypeDef;

+

+/*------------- Watchdog Timer (WDT) -----------------------------------------*/

+typedef struct

+{

+  __IO uint8_t  WDMOD;

+       uint8_t  RESERVED0[3];

+  __IO uint32_t WDTC;

+  __O  uint8_t  WDFEED;

+       uint8_t  RESERVED1[3];

+  __I  uint32_t WDTV;

+  __IO uint32_t WDCLKSEL;

+} LPC_WDT_TypeDef;

+

+/*------------- Analog-to-Digital Converter (ADC) ----------------------------*/

+typedef struct

+{

+  __IO uint32_t ADCR;

+  __IO uint32_t ADGDR;

+       uint32_t RESERVED0;

+  __IO uint32_t ADINTEN;

+  __I  uint32_t ADDR0;

+  __I  uint32_t ADDR1;

+  __I  uint32_t ADDR2;

+  __I  uint32_t ADDR3;

+  __I  uint32_t ADDR4;

+  __I  uint32_t ADDR5;

+  __I  uint32_t ADDR6;

+  __I  uint32_t ADDR7;

+  __I  uint32_t ADSTAT;

+  __IO uint32_t ADTRM;

+} LPC_ADC_TypeDef;

+

+/*------------- Digital-to-Analog Converter (DAC) ----------------------------*/

+typedef struct

+{

+  __IO uint32_t DACR;

+  __IO uint32_t DACCTRL;

+  __IO uint16_t DACCNTVAL;

+} LPC_DAC_TypeDef;

+

+/*------------- Motor Control Pulse-Width Modulation (MCPWM) -----------------*/

+typedef struct

+{

+  __I  uint32_t MCCON;

+  __O  uint32_t MCCON_SET;

+  __O  uint32_t MCCON_CLR;

+  __I  uint32_t MCCAPCON;

+  __O  uint32_t MCCAPCON_SET;

+  __O  uint32_t MCCAPCON_CLR;

+  __IO uint32_t MCTIM0;

+  __IO uint32_t MCTIM1;

+  __IO uint32_t MCTIM2;

+  __IO uint32_t MCPER0;

+  __IO uint32_t MCPER1;

+  __IO uint32_t MCPER2;

+  __IO uint32_t MCPW0;

+  __IO uint32_t MCPW1;

+  __IO uint32_t MCPW2;

+  __IO uint32_t MCDEADTIME;

+  __IO uint32_t MCCCP;

+  __IO uint32_t MCCR0;

+  __IO uint32_t MCCR1;

+  __IO uint32_t MCCR2;

+  __I  uint32_t MCINTEN;

+  __O  uint32_t MCINTEN_SET;

+  __O  uint32_t MCINTEN_CLR;

+  __I  uint32_t MCCNTCON;

+  __O  uint32_t MCCNTCON_SET;

+  __O  uint32_t MCCNTCON_CLR;

+  __I  uint32_t MCINTFLAG;

+  __O  uint32_t MCINTFLAG_SET;

+  __O  uint32_t MCINTFLAG_CLR;

+  __O  uint32_t MCCAP_CLR;

+} LPC_MCPWM_TypeDef;

+

+/*------------- Quadrature Encoder Interface (QEI) ---------------------------*/

+typedef struct

+{

+  __O  uint32_t QEICON;

+  __I  uint32_t QEISTAT;

+  __IO uint32_t QEICONF;

+  __I  uint32_t QEIPOS;

+  __IO uint32_t QEIMAXPOS;

+  __IO uint32_t CMPOS0;

+  __IO uint32_t CMPOS1;

+  __IO uint32_t CMPOS2;

+  __I  uint32_t INXCNT;

+  __IO uint32_t INXCMP;

+  __IO uint32_t QEILOAD;

+  __I  uint32_t QEITIME;

+  __I  uint32_t QEIVEL;

+  __I  uint32_t QEICAP;

+  __IO uint32_t VELCOMP;

+  __IO uint32_t FILTER;

+       uint32_t RESERVED0[998];

+  __O  uint32_t QEIIEC;

+  __O  uint32_t QEIIES;

+  __I  uint32_t QEIINTSTAT;

+  __I  uint32_t QEIIE;

+  __O  uint32_t QEICLR;

+  __O  uint32_t QEISET;

+} LPC_QEI_TypeDef;

+

+/*------------- Controller Area Network (CAN) --------------------------------*/

+typedef struct

+{

+  __IO uint32_t mask[512];              /* ID Masks                           */

+} LPC_CANAF_RAM_TypeDef;

+

+typedef struct                          /* Acceptance Filter Registers        */

+{

+  __IO uint32_t AFMR;

+  __IO uint32_t SFF_sa;

+  __IO uint32_t SFF_GRP_sa;

+  __IO uint32_t EFF_sa;

+  __IO uint32_t EFF_GRP_sa;

+  __IO uint32_t ENDofTable;

+  __I  uint32_t LUTerrAd;

+  __I  uint32_t LUTerr;

+  __IO uint32_t FCANIE;

+  __IO uint32_t FCANIC0;

+  __IO uint32_t FCANIC1;

+} LPC_CANAF_TypeDef;

+

+typedef struct                          /* Central Registers                  */

+{

+  __I  uint32_t CANTxSR;

+  __I  uint32_t CANRxSR;

+  __I  uint32_t CANMSR;

+} LPC_CANCR_TypeDef;

+

+typedef struct                          /* Controller Registers               */

+{

+  __IO uint32_t MOD;

+  __O  uint32_t CMR;

+  __IO uint32_t GSR;

+  __I  uint32_t ICR;

+  __IO uint32_t IER;

+  __IO uint32_t BTR;

+  __IO uint32_t EWL;

+  __I  uint32_t SR;

+  __IO uint32_t RFS;

+  __IO uint32_t RID;

+  __IO uint32_t RDA;

+  __IO uint32_t RDB;

+  __IO uint32_t TFI1;

+  __IO uint32_t TID1;

+  __IO uint32_t TDA1;

+  __IO uint32_t TDB1;

+  __IO uint32_t TFI2;

+  __IO uint32_t TID2;

+  __IO uint32_t TDA2;

+  __IO uint32_t TDB2;

+  __IO uint32_t TFI3;

+  __IO uint32_t TID3;

+  __IO uint32_t TDA3;

+  __IO uint32_t TDB3;

+} LPC_CAN_TypeDef;

+

+/*------------- General Purpose Direct Memory Access (GPDMA) -----------------*/

+typedef struct                          /* Common Registers                   */

+{

+  __I  uint32_t DMACIntStat;

+  __I  uint32_t DMACIntTCStat;

+  __O  uint32_t DMACIntTCClear;

+  __I  uint32_t DMACIntErrStat;

+  __O  uint32_t DMACIntErrClr;

+  __I  uint32_t DMACRawIntTCStat;

+  __I  uint32_t DMACRawIntErrStat;

+  __I  uint32_t DMACEnbldChns;

+  __IO uint32_t DMACSoftBReq;

+  __IO uint32_t DMACSoftSReq;

+  __IO uint32_t DMACSoftLBReq;

+  __IO uint32_t DMACSoftLSReq;

+  __IO uint32_t DMACConfig;

+  __IO uint32_t DMACSync;

+} LPC_GPDMA_TypeDef;

+

+typedef struct                          /* Channel Registers                  */

+{

+  __IO uint32_t DMACCSrcAddr;

+  __IO uint32_t DMACCDestAddr;

+  __IO uint32_t DMACCLLI;

+  __IO uint32_t DMACCControl;

+  __IO uint32_t DMACCConfig;

+} LPC_GPDMACH_TypeDef;

+

+/*------------- Universal Serial Bus (USB) -----------------------------------*/

+typedef struct

+{

+  __I  uint32_t HcRevision;             /* USB Host Registers                 */

+  __IO uint32_t HcControl;

+  __IO uint32_t HcCommandStatus;

+  __IO uint32_t HcInterruptStatus;

+  __IO uint32_t HcInterruptEnable;

+  __IO uint32_t HcInterruptDisable;

+  __IO uint32_t HcHCCA;

+  __I  uint32_t HcPeriodCurrentED;

+  __IO uint32_t HcControlHeadED;

+  __IO uint32_t HcControlCurrentED;

+  __IO uint32_t HcBulkHeadED;

+  __IO uint32_t HcBulkCurrentED;

+  __I  uint32_t HcDoneHead;

+  __IO uint32_t HcFmInterval;

+  __I  uint32_t HcFmRemaining;

+  __I  uint32_t HcFmNumber;

+  __IO uint32_t HcPeriodicStart;

+  __IO uint32_t HcLSTreshold;

+  __IO uint32_t HcRhDescriptorA;

+  __IO uint32_t HcRhDescriptorB;

+  __IO uint32_t HcRhStatus;

+  __IO uint32_t HcRhPortStatus1;

+  __IO uint32_t HcRhPortStatus2;

+       uint32_t RESERVED0[40];

+  __I  uint32_t Module_ID;

+

+  __I  uint32_t OTGIntSt;               /* USB On-The-Go Registers            */

+  __IO uint32_t OTGIntEn;

+  __O  uint32_t OTGIntSet;

+  __O  uint32_t OTGIntClr;

+  __IO uint32_t OTGStCtrl;

+  __IO uint32_t OTGTmr;

+       uint32_t RESERVED1[58];

+

+  __I  uint32_t USBDevIntSt;            /* USB Device Interrupt Registers     */

+  __IO uint32_t USBDevIntEn;

+  __O  uint32_t USBDevIntClr;

+  __O  uint32_t USBDevIntSet;

+

+  __O  uint32_t USBCmdCode;             /* USB Device SIE Command Registers   */

+  __I  uint32_t USBCmdData;

+

+  __I  uint32_t USBRxData;              /* USB Device Transfer Registers      */

+  __O  uint32_t USBTxData;

+  __I  uint32_t USBRxPLen;

+  __O  uint32_t USBTxPLen;

+  __IO uint32_t USBCtrl;

+  __O  uint32_t USBDevIntPri;

+

+  __I  uint32_t USBEpIntSt;             /* USB Device Endpoint Interrupt Regs */

+  __IO uint32_t USBEpIntEn;

+  __O  uint32_t USBEpIntClr;

+  __O  uint32_t USBEpIntSet;

+  __O  uint32_t USBEpIntPri;

+

+  __IO uint32_t USBReEp;                /* USB Device Endpoint Realization Reg*/

+  __O  uint32_t USBEpInd;

+  __IO uint32_t USBMaxPSize;

+

+  __I  uint32_t USBDMARSt;              /* USB Device DMA Registers           */

+  __O  uint32_t USBDMARClr;

+  __O  uint32_t USBDMARSet;

+       uint32_t RESERVED2[9];

+  __IO uint32_t USBUDCAH;

+  __I  uint32_t USBEpDMASt;

+  __O  uint32_t USBEpDMAEn;

+  __O  uint32_t USBEpDMADis;

+  __I  uint32_t USBDMAIntSt;

+  __IO uint32_t USBDMAIntEn;

+       uint32_t RESERVED3[2];

+  __I  uint32_t USBEoTIntSt;

+  __O  uint32_t USBEoTIntClr;

+  __O  uint32_t USBEoTIntSet;

+  __I  uint32_t USBNDDRIntSt;

+  __O  uint32_t USBNDDRIntClr;

+  __O  uint32_t USBNDDRIntSet;

+  __I  uint32_t USBSysErrIntSt;

+  __O  uint32_t USBSysErrIntClr;

+  __O  uint32_t USBSysErrIntSet;

+       uint32_t RESERVED4[15];

+

+  union {

+  __I  uint32_t I2C_RX;                 /* USB OTG I2C Registers              */

+  __O  uint32_t I2C_TX;

+  };

+  __I  uint32_t I2C_STS;

+  __IO uint32_t I2C_CTL;

+  __IO uint32_t I2C_CLKHI;

+  __O  uint32_t I2C_CLKLO;

+       uint32_t RESERVED5[824];

+

+  union {

+  __IO uint32_t USBClkCtrl;             /* USB Clock Control Registers        */

+  __IO uint32_t OTGClkCtrl;

+  };

+  union {

+  __I  uint32_t USBClkSt;

+  __I  uint32_t OTGClkSt;

+  };

+} LPC_USB_TypeDef;

+

+/*------------- Ethernet Media Access Controller (EMAC) ----------------------*/

+typedef struct

+{

+  __IO uint32_t MAC1;                   /* MAC Registers                      */

+  __IO uint32_t MAC2;

+  __IO uint32_t IPGT;

+  __IO uint32_t IPGR;

+  __IO uint32_t CLRT;

+  __IO uint32_t MAXF;

+  __IO uint32_t SUPP;

+  __IO uint32_t TEST;

+  __IO uint32_t MCFG;

+  __IO uint32_t MCMD;

+  __IO uint32_t MADR;

+  __O  uint32_t MWTD;

+  __I  uint32_t MRDD;

+  __I  uint32_t MIND;

+       uint32_t RESERVED0[2];

+  __IO uint32_t SA0;

+  __IO uint32_t SA1;

+  __IO uint32_t SA2;

+       uint32_t RESERVED1[45];

+  __IO uint32_t Command;                /* Control Registers                  */

+  __I  uint32_t Status;

+  __IO uint32_t RxDescriptor;

+  __IO uint32_t RxStatus;

+  __IO uint32_t RxDescriptorNumber;

+  __I  uint32_t RxProduceIndex;

+  __IO uint32_t RxConsumeIndex;

+  __IO uint32_t TxDescriptor;

+  __IO uint32_t TxStatus;

+  __IO uint32_t TxDescriptorNumber;

+  __IO uint32_t TxProduceIndex;

+  __I  uint32_t TxConsumeIndex;

+       uint32_t RESERVED2[10];

+  __I  uint32_t TSV0;

+  __I  uint32_t TSV1;

+  __I  uint32_t RSV;

+       uint32_t RESERVED3[3];

+  __IO uint32_t FlowControlCounter;

+  __I  uint32_t FlowControlStatus;

+       uint32_t RESERVED4[34];

+  __IO uint32_t RxFilterCtrl;           /* Rx Filter Registers                */

+  __IO uint32_t RxFilterWoLStatus;

+  __IO uint32_t RxFilterWoLClear;

+       uint32_t RESERVED5;

+  __IO uint32_t HashFilterL;

+  __IO uint32_t HashFilterH;

+       uint32_t RESERVED6[882];

+  __I  uint32_t IntStatus;              /* Module Control Registers           */

+  __IO uint32_t IntEnable;

+  __O  uint32_t IntClear;

+  __O  uint32_t IntSet;

+       uint32_t RESERVED7;

+  __IO uint32_t PowerDown;

+       uint32_t RESERVED8;

+  __IO uint32_t Module_ID;

+} LPC_EMAC_TypeDef;

+

+#if defined ( __CC_ARM   )

+#pragma no_anon_unions

+#endif

+

+

+/******************************************************************************/

+/*                         Peripheral memory map                              */

+/******************************************************************************/

+/* Base addresses                                                             */

+#define LPC_FLASH_BASE        (0x00000000UL)

+#define LPC_RAM_BASE          (0x10000000UL)

+#define LPC_GPIO_BASE         (0x2009C000UL)

+#define LPC_APB0_BASE         (0x40000000UL)

+#define LPC_APB1_BASE         (0x40080000UL)

+#define LPC_AHB_BASE          (0x50000000UL)

+#define LPC_CM3_BASE          (0xE0000000UL)

+

+/* APB0 peripherals                                                           */

+#define LPC_WDT_BASE          (LPC_APB0_BASE + 0x00000)

+#define LPC_TIM0_BASE         (LPC_APB0_BASE + 0x04000)

+#define LPC_TIM1_BASE         (LPC_APB0_BASE + 0x08000)

+#define LPC_UART0_BASE        (LPC_APB0_BASE + 0x0C000)

+#define LPC_UART1_BASE        (LPC_APB0_BASE + 0x10000)

+#define LPC_PWM1_BASE         (LPC_APB0_BASE + 0x18000)

+#define LPC_I2C0_BASE         (LPC_APB0_BASE + 0x1C000)

+#define LPC_SPI_BASE          (LPC_APB0_BASE + 0x20000)

+#define LPC_RTC_BASE          (LPC_APB0_BASE + 0x24000)

+#define LPC_GPIOINT_BASE      (LPC_APB0_BASE + 0x28080)

+#define LPC_PINCON_BASE       (LPC_APB0_BASE + 0x2C000)

+#define LPC_SSP1_BASE         (LPC_APB0_BASE + 0x30000)

+#define LPC_ADC_BASE          (LPC_APB0_BASE + 0x34000)

+#define LPC_CANAF_RAM_BASE    (LPC_APB0_BASE + 0x38000)

+#define LPC_CANAF_BASE        (LPC_APB0_BASE + 0x3C000)

+#define LPC_CANCR_BASE        (LPC_APB0_BASE + 0x40000)

+#define LPC_CAN1_BASE         (LPC_APB0_BASE + 0x44000)

+#define LPC_CAN2_BASE         (LPC_APB0_BASE + 0x48000)

+#define LPC_I2C1_BASE         (LPC_APB0_BASE + 0x5C000)

+

+/* APB1 peripherals                                                           */

+#define LPC_SSP0_BASE         (LPC_APB1_BASE + 0x08000)

+#define LPC_DAC_BASE          (LPC_APB1_BASE + 0x0C000)

+#define LPC_TIM2_BASE         (LPC_APB1_BASE + 0x10000)

+#define LPC_TIM3_BASE         (LPC_APB1_BASE + 0x14000)

+#define LPC_UART2_BASE        (LPC_APB1_BASE + 0x18000)

+#define LPC_UART3_BASE        (LPC_APB1_BASE + 0x1C000)

+#define LPC_I2C2_BASE         (LPC_APB1_BASE + 0x20000)

+#define LPC_I2S_BASE          (LPC_APB1_BASE + 0x28000)

+#define LPC_RIT_BASE          (LPC_APB1_BASE + 0x30000)

+#define LPC_MCPWM_BASE        (LPC_APB1_BASE + 0x38000)

+#define LPC_QEI_BASE          (LPC_APB1_BASE + 0x3C000)

+#define LPC_SC_BASE           (LPC_APB1_BASE + 0x7C000)

+

+/* AHB peripherals                                                            */

+#define LPC_EMAC_BASE         (LPC_AHB_BASE  + 0x00000)

+#define LPC_GPDMA_BASE        (LPC_AHB_BASE  + 0x04000)

+#define LPC_GPDMACH0_BASE     (LPC_AHB_BASE  + 0x04100)

+#define LPC_GPDMACH1_BASE     (LPC_AHB_BASE  + 0x04120)

+#define LPC_GPDMACH2_BASE     (LPC_AHB_BASE  + 0x04140)

+#define LPC_GPDMACH3_BASE     (LPC_AHB_BASE  + 0x04160)

+#define LPC_GPDMACH4_BASE     (LPC_AHB_BASE  + 0x04180)

+#define LPC_GPDMACH5_BASE     (LPC_AHB_BASE  + 0x041A0)

+#define LPC_GPDMACH6_BASE     (LPC_AHB_BASE  + 0x041C0)

+#define LPC_GPDMACH7_BASE     (LPC_AHB_BASE  + 0x041E0)

+#define LPC_USB_BASE          (LPC_AHB_BASE  + 0x0C000)

+

+/* GPIOs                                                                      */

+#define LPC_GPIO0_BASE        (LPC_GPIO_BASE + 0x00000)

+#define LPC_GPIO1_BASE        (LPC_GPIO_BASE + 0x00020)

+#define LPC_GPIO2_BASE        (LPC_GPIO_BASE + 0x00040)

+#define LPC_GPIO3_BASE        (LPC_GPIO_BASE + 0x00060)

+#define LPC_GPIO4_BASE        (LPC_GPIO_BASE + 0x00080)

+

+

+/******************************************************************************/

+/*                         Peripheral declaration                             */

+/******************************************************************************/

+#define LPC_SC                ((LPC_SC_TypeDef        *) LPC_SC_BASE       )

+#define LPC_GPIO0             ((LPC_GPIO_TypeDef      *) LPC_GPIO0_BASE    )

+#define LPC_GPIO1             ((LPC_GPIO_TypeDef      *) LPC_GPIO1_BASE    )

+#define LPC_GPIO2             ((LPC_GPIO_TypeDef      *) LPC_GPIO2_BASE    )

+#define LPC_GPIO3             ((LPC_GPIO_TypeDef      *) LPC_GPIO3_BASE    )

+#define LPC_GPIO4             ((LPC_GPIO_TypeDef      *) LPC_GPIO4_BASE    )

+#define LPC_WDT               ((LPC_WDT_TypeDef       *) LPC_WDT_BASE      )

+#define LPC_TIM0              ((LPC_TIM_TypeDef       *) LPC_TIM0_BASE     )

+#define LPC_TIM1              ((LPC_TIM_TypeDef       *) LPC_TIM1_BASE     )

+#define LPC_TIM2              ((LPC_TIM_TypeDef       *) LPC_TIM2_BASE     )

+#define LPC_TIM3              ((LPC_TIM_TypeDef       *) LPC_TIM3_BASE     )

+#define LPC_RIT               ((LPC_RIT_TypeDef       *) LPC_RIT_BASE      )

+#define LPC_UART0             ((LPC_UART0_TypeDef     *) LPC_UART0_BASE    )

+#define LPC_UART1             ((LPC_UART1_TypeDef     *) LPC_UART1_BASE    )

+#define LPC_UART2             ((LPC_UART_TypeDef      *) LPC_UART2_BASE    )

+#define LPC_UART3             ((LPC_UART_TypeDef      *) LPC_UART3_BASE    )

+#define LPC_PWM1              ((LPC_PWM_TypeDef       *) LPC_PWM1_BASE     )

+#define LPC_I2C0              ((LPC_I2C_TypeDef       *) LPC_I2C0_BASE     )

+#define LPC_I2C1              ((LPC_I2C_TypeDef       *) LPC_I2C1_BASE     )

+#define LPC_I2C2              ((LPC_I2C_TypeDef       *) LPC_I2C2_BASE     )

+#define LPC_I2S               ((LPC_I2S_TypeDef       *) LPC_I2S_BASE      )

+#define LPC_SPI               ((LPC_SPI_TypeDef       *) LPC_SPI_BASE      )

+#define LPC_RTC               ((LPC_RTC_TypeDef       *) LPC_RTC_BASE      )

+#define LPC_GPIOINT           ((LPC_GPIOINT_TypeDef   *) LPC_GPIOINT_BASE  )

+#define LPC_PINCON            ((LPC_PINCON_TypeDef    *) LPC_PINCON_BASE   )

+#define LPC_SSP0              ((LPC_SSP_TypeDef       *) LPC_SSP0_BASE     )

+#define LPC_SSP1              ((LPC_SSP_TypeDef       *) LPC_SSP1_BASE     )

+#define LPC_ADC               ((LPC_ADC_TypeDef       *) LPC_ADC_BASE      )

+#define LPC_DAC               ((LPC_DAC_TypeDef       *) LPC_DAC_BASE      )

+#define LPC_CANAF_RAM         ((LPC_CANAF_RAM_TypeDef *) LPC_CANAF_RAM_BASE)

+#define LPC_CANAF             ((LPC_CANAF_TypeDef     *) LPC_CANAF_BASE    )

+#define LPC_CANCR             ((LPC_CANCR_TypeDef     *) LPC_CANCR_BASE    )

+#define LPC_CAN1              ((LPC_CAN_TypeDef       *) LPC_CAN1_BASE     )

+#define LPC_CAN2              ((LPC_CAN_TypeDef       *) LPC_CAN2_BASE     )

+#define LPC_MCPWM             ((LPC_MCPWM_TypeDef     *) LPC_MCPWM_BASE    )

+#define LPC_QEI               ((LPC_QEI_TypeDef       *) LPC_QEI_BASE      )

+#define LPC_EMAC              ((LPC_EMAC_TypeDef      *) LPC_EMAC_BASE     )

+#define LPC_GPDMA             ((LPC_GPDMA_TypeDef     *) LPC_GPDMA_BASE    )

+#define LPC_GPDMACH0          ((LPC_GPDMACH_TypeDef   *) LPC_GPDMACH0_BASE )

+#define LPC_GPDMACH1          ((LPC_GPDMACH_TypeDef   *) LPC_GPDMACH1_BASE )

+#define LPC_GPDMACH2          ((LPC_GPDMACH_TypeDef   *) LPC_GPDMACH2_BASE )

+#define LPC_GPDMACH3          ((LPC_GPDMACH_TypeDef   *) LPC_GPDMACH3_BASE )

+#define LPC_GPDMACH4          ((LPC_GPDMACH_TypeDef   *) LPC_GPDMACH4_BASE )

+#define LPC_GPDMACH5          ((LPC_GPDMACH_TypeDef   *) LPC_GPDMACH5_BASE )

+#define LPC_GPDMACH6          ((LPC_GPDMACH_TypeDef   *) LPC_GPDMACH6_BASE )

+#define LPC_GPDMACH7          ((LPC_GPDMACH_TypeDef   *) LPC_GPDMACH7_BASE )

+#define LPC_USB               ((LPC_USB_TypeDef       *) LPC_USB_BASE      )

+

+#endif  // __LPC17xx_H__

diff --git a/ext/TARGET_LPC1768/TARGET_NXP/TARGET_LPC176X/PeripheralNames.h b/ext/TARGET_LPC1768/TARGET_NXP/TARGET_LPC176X/PeripheralNames.h
new file mode 100644
index 0000000..9908132
--- /dev/null
+++ b/ext/TARGET_LPC1768/TARGET_NXP/TARGET_LPC176X/PeripheralNames.h
@@ -0,0 +1,111 @@
+/* mbed Microcontroller Library

+ * Copyright (c) 2006-2013 ARM Limited

+ *

+ * Licensed under the Apache License, Version 2.0 (the "License");

+ * you may not use this file except in compliance with the License.

+ * You may obtain a copy of the License at

+ *

+ *     http://www.apache.org/licenses/LICENSE-2.0

+ *

+ * Unless required by applicable law or agreed to in writing, software

+ * distributed under the License is distributed on an "AS IS" BASIS,

+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

+ * See the License for the specific language governing permissions and

+ * limitations under the License.

+ */

+#ifndef MBED_PERIPHERALNAMES_H

+#define MBED_PERIPHERALNAMES_H

+

+#include "cmsis.h"

+#include "PinNames.h"

+

+#ifdef __cplusplus

+extern "C" {

+#endif

+

+typedef enum {

+    UART_0 = (int)LPC_UART0_BASE,

+    UART_1 = (int)LPC_UART1_BASE,

+    UART_2 = (int)LPC_UART2_BASE,

+    UART_3 = (int)LPC_UART3_BASE

+} UARTName;

+

+typedef enum {

+    ADC0_0 = 0,

+    ADC0_1,

+    ADC0_2,

+    ADC0_3,

+    ADC0_4,

+    ADC0_5,

+    ADC0_6,

+    ADC0_7

+} ADCName;

+

+typedef enum {

+    DAC_0 = 0

+} DACName;

+

+typedef enum {

+    SPI_0 = (int)LPC_SSP0_BASE,

+    SPI_1 = (int)LPC_SSP1_BASE

+} SPIName;

+

+typedef enum {

+    I2C_0 = (int)LPC_I2C0_BASE,

+    I2C_1 = (int)LPC_I2C1_BASE,

+    I2C_2 = (int)LPC_I2C2_BASE

+} I2CName;

+

+typedef enum {

+    PWM_1 = 1,

+    PWM_2,

+    PWM_3,

+    PWM_4,

+    PWM_5,

+    PWM_6

+} PWMName;

+

+typedef enum {

+     CAN_1 = (int)LPC_CAN1_BASE,

+     CAN_2 = (int)LPC_CAN2_BASE

+} CANName;

+

+#define STDIO_UART_TX     USBTX

+#define STDIO_UART_RX     USBRX

+#define STDIO_UART        UART_0

+

+// Default peripherals

+#define MBED_SPI0         p5, p6, p7, p8

+#define MBED_SPI1         p11, p12, p13, p14

+

+#define MBED_UART0        p9, p10

+#define MBED_UART1        p13, p14

+#define MBED_UART2        p28, p27

+#define MBED_UARTUSB      USBTX, USBRX

+

+#define MBED_I2C0         p28, p27

+#define MBED_I2C1         p9, p10

+

+#define MBED_CAN0         p30, p29

+

+#define MBED_ANALOGOUT0   p18

+

+#define MBED_ANALOGIN0    p15

+#define MBED_ANALOGIN1    p16

+#define MBED_ANALOGIN2    p17

+#define MBED_ANALOGIN3    p18

+#define MBED_ANALOGIN4    p19

+#define MBED_ANALOGIN5    p20

+

+#define MBED_PWMOUT0      p26

+#define MBED_PWMOUT1      p25

+#define MBED_PWMOUT2      p24

+#define MBED_PWMOUT3      p23

+#define MBED_PWMOUT4      p22

+#define MBED_PWMOUT5      p21

+

+#ifdef __cplusplus

+}

+#endif

+

+#endif

diff --git a/ext/TARGET_LPC1768/TARGET_NXP/TARGET_LPC176X/PortNames.h b/ext/TARGET_LPC1768/TARGET_NXP/TARGET_LPC176X/PortNames.h
new file mode 100644
index 0000000..4a7bf9e
--- /dev/null
+++ b/ext/TARGET_LPC1768/TARGET_NXP/TARGET_LPC176X/PortNames.h
@@ -0,0 +1,34 @@
+/* mbed Microcontroller Library

+ * Copyright (c) 2006-2013 ARM Limited

+ *

+ * Licensed under the Apache License, Version 2.0 (the "License");

+ * you may not use this file except in compliance with the License.

+ * You may obtain a copy of the License at

+ *

+ *     http://www.apache.org/licenses/LICENSE-2.0

+ *

+ * Unless required by applicable law or agreed to in writing, software

+ * distributed under the License is distributed on an "AS IS" BASIS,

+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

+ * See the License for the specific language governing permissions and

+ * limitations under the License.

+ */

+#ifndef MBED_PORTNAMES_H

+#define MBED_PORTNAMES_H

+

+#ifdef __cplusplus

+extern "C" {

+#endif

+

+typedef enum {

+    Port0 = 0,

+    Port1 = 1,

+    Port2 = 2,

+    Port3 = 3,

+    Port4 = 4

+} PortName;

+

+#ifdef __cplusplus

+}

+#endif

+#endif

diff --git a/ext/TARGET_LPC1768/TARGET_NXP/TARGET_LPC176X/TARGET_MBED_LPC1768/PinNames.h b/ext/TARGET_LPC1768/TARGET_NXP/TARGET_LPC176X/TARGET_MBED_LPC1768/PinNames.h
new file mode 100644
index 0000000..f6cec0f
--- /dev/null
+++ b/ext/TARGET_LPC1768/TARGET_NXP/TARGET_LPC176X/TARGET_MBED_LPC1768/PinNames.h
@@ -0,0 +1,139 @@
+/* mbed Microcontroller Library

+ * Copyright (c) 2006-2013 ARM Limited

+ *

+ * Licensed under the Apache License, Version 2.0 (the "License");

+ * you may not use this file except in compliance with the License.

+ * You may obtain a copy of the License at

+ *

+ *     http://www.apache.org/licenses/LICENSE-2.0

+ *

+ * Unless required by applicable law or agreed to in writing, software

+ * distributed under the License is distributed on an "AS IS" BASIS,

+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

+ * See the License for the specific language governing permissions and

+ * limitations under the License.

+ */

+#ifndef MBED_PINNAMES_H

+#define MBED_PINNAMES_H

+

+#include "cmsis.h"

+

+#ifdef __cplusplus

+extern "C" {

+#endif

+

+typedef enum {

+    PIN_INPUT,

+    PIN_OUTPUT

+} PinDirection;

+

+#define PORT_SHIFT  5

+

+typedef enum {

+    // LPC Pin Names

+    P0_0 = LPC_GPIO0_BASE,

+          P0_1, P0_2, P0_3, P0_4, P0_5, P0_6, P0_7, P0_8, P0_9, P0_10, P0_11, P0_12, P0_13, P0_14, P0_15, P0_16, P0_17, P0_18, P0_19, P0_20, P0_21, P0_22, P0_23, P0_24, P0_25, P0_26, P0_27, P0_28, P0_29, P0_30, P0_31,

+    P1_0, P1_1, P1_2, P1_3, P1_4, P1_5, P1_6, P1_7, P1_8, P1_9, P1_10, P1_11, P1_12, P1_13, P1_14, P1_15, P1_16, P1_17, P1_18, P1_19, P1_20, P1_21, P1_22, P1_23, P1_24, P1_25, P1_26, P1_27, P1_28, P1_29, P1_30, P1_31,

+    P2_0, P2_1, P2_2, P2_3, P2_4, P2_5, P2_6, P2_7, P2_8, P2_9, P2_10, P2_11, P2_12, P2_13, P2_14, P2_15, P2_16, P2_17, P2_18, P2_19, P2_20, P2_21, P2_22, P2_23, P2_24, P2_25, P2_26, P2_27, P2_28, P2_29, P2_30, P2_31,

+    P3_0, P3_1, P3_2, P3_3, P3_4, P3_5, P3_6, P3_7, P3_8, P3_9, P3_10, P3_11, P3_12, P3_13, P3_14, P3_15, P3_16, P3_17, P3_18, P3_19, P3_20, P3_21, P3_22, P3_23, P3_24, P3_25, P3_26, P3_27, P3_28, P3_29, P3_30, P3_31,

+    P4_0, P4_1, P4_2, P4_3, P4_4, P4_5, P4_6, P4_7, P4_8, P4_9, P4_10, P4_11, P4_12, P4_13, P4_14, P4_15, P4_16, P4_17, P4_18, P4_19, P4_20, P4_21, P4_22, P4_23, P4_24, P4_25, P4_26, P4_27, P4_28, P4_29, P4_30, P4_31,

+

+    // mbed DIP Pin Names

+    p5 = P0_9,

+    p6 = P0_8,

+    p7 = P0_7,

+    p8 = P0_6,

+    p9 = P0_0,

+    p10 = P0_1,

+    p11 = P0_18,

+    p12 = P0_17,

+    p13 = P0_15,

+    p14 = P0_16,

+    p15 = P0_23,

+    p16 = P0_24,

+    p17 = P0_25,

+    p18 = P0_26,

+    p19 = P1_30,

+    p20 = P1_31,

+    p21 = P2_5,

+    p22 = P2_4,

+    p23 = P2_3,

+    p24 = P2_2,

+    p25 = P2_1,

+    p26 = P2_0,

+    p27 = P0_11,

+    p28 = P0_10,

+    p29 = P0_5,

+    p30 = P0_4,

+

+    // Other mbed Pin Names

+#ifdef MCB1700

+    LED1 = P1_28,

+    LED2 = P1_29,

+    LED3 = P1_31,

+    LED4 = P2_2,

+#else

+    LED1 = P1_18,

+    LED2 = P1_20,

+    LED3 = P1_21,

+    LED4 = P1_23,

+#endif

+    USBTX = P0_2,

+    USBRX = P0_3,

+

+    // Arch Pro Pin Names

+    D0 = P4_29,

+    D1 = P4_28,

+    D2 = P0_4,

+    D3 = P0_5,

+    D4 = P2_2,

+    D5 = P2_3,

+    D6 = P2_4,

+    D7 = P2_5,

+    D8 = P0_0,

+    D9 = P0_1,

+    D10 = P0_6,

+    D11 = P0_9,

+    D12 = P0_8,

+    D13 = P0_7,

+    D14 = P0_27,

+    D15 = P0_28,

+

+    A0 = P0_23,

+    A1 = P0_24,

+    A2 = P0_25,

+    A3 = P0_26,

+    A4 = P1_30,

+    A5 = P1_31,

+

+    I2C_SCL = D15,

+    I2C_SDA = D14,

+

+    // Not connected

+    NC = (int)0xFFFFFFFF

+} PinName;

+

+typedef enum {

+    PullUp = 0,

+    PullDown = 3,

+    PullNone = 2,

+    Repeater = 1,

+    OpenDrain = 4,

+    PullDefault = PullDown

+} PinMode;

+

+// version of PINCON_TypeDef using register arrays

+typedef struct {

+  __IO uint32_t PINSEL[11];

+       uint32_t RESERVED0[5];

+  __IO uint32_t PINMODE[10];

+  __IO uint32_t PINMODE_OD[5];

+} PINCONARRAY_TypeDef;

+

+#define PINCONARRAY ((PINCONARRAY_TypeDef *)LPC_PINCON_BASE)

+

+#ifdef __cplusplus

+}

+#endif

+

+#endif

diff --git a/ext/TARGET_LPC1768/TARGET_NXP/TARGET_LPC176X/TARGET_MBED_LPC1768/device.h b/ext/TARGET_LPC1768/TARGET_NXP/TARGET_LPC176X/TARGET_MBED_LPC1768/device.h
new file mode 100644
index 0000000..a58c4fd
--- /dev/null
+++ b/ext/TARGET_LPC1768/TARGET_NXP/TARGET_LPC176X/TARGET_MBED_LPC1768/device.h
@@ -0,0 +1,60 @@
+/* mbed Microcontroller Library

+ * Copyright (c) 2006-2013 ARM Limited

+ *

+ * Licensed under the Apache License, Version 2.0 (the "License");

+ * you may not use this file except in compliance with the License.

+ * You may obtain a copy of the License at

+ *

+ *     http://www.apache.org/licenses/LICENSE-2.0

+ *

+ * Unless required by applicable law or agreed to in writing, software

+ * distributed under the License is distributed on an "AS IS" BASIS,

+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

+ * See the License for the specific language governing permissions and

+ * limitations under the License.

+ */

+#ifndef MBED_DEVICE_H

+#define MBED_DEVICE_H

+

+#define DEVICE_PORTIN           1

+#define DEVICE_PORTOUT          1

+#define DEVICE_PORTINOUT        1

+

+#define DEVICE_INTERRUPTIN      1

+

+#define DEVICE_ANALOGIN         1

+#define DEVICE_ANALOGOUT        1

+

+#define DEVICE_SERIAL           1

+#define DEVICE_SERIAL_FC        1

+

+#define DEVICE_I2C              1

+#define DEVICE_I2CSLAVE         1

+

+#define DEVICE_SPI              1

+#define DEVICE_SPISLAVE         1

+

+#define DEVICE_CAN              1

+

+#define DEVICE_RTC              1

+

+#define DEVICE_ETHERNET         1

+

+#define DEVICE_PWMOUT           1

+

+#define DEVICE_SEMIHOST         1

+#define DEVICE_LOCALFILESYSTEM  1

+#define DEVICE_ID_LENGTH       32

+#define DEVICE_MAC_OFFSET      20

+

+#define DEVICE_SLEEP            1

+

+#define DEVICE_DEBUG_AWARENESS  1

+

+#define DEVICE_STDIO_MESSAGES   1

+

+#define DEVICE_ERROR_PATTERN    1

+

+#include "objects.h"

+

+#endif

diff --git a/ext/TARGET_LPC1768/TARGET_NXP/TARGET_LPC176X/TARGET_MBED_LPC1768/reserved_pins.h b/ext/TARGET_LPC1768/TARGET_NXP/TARGET_LPC176X/TARGET_MBED_LPC1768/reserved_pins.h
new file mode 100644
index 0000000..0578c9d
--- /dev/null
+++ b/ext/TARGET_LPC1768/TARGET_NXP/TARGET_LPC176X/TARGET_MBED_LPC1768/reserved_pins.h
@@ -0,0 +1,8 @@
+// List of reserved pins for MBED LPC1768

+

+#ifndef RESERVED_PINS_H

+#define RESERVED_PINS_H

+

+#define TARGET_RESERVED_PINS {}

+

+#endif

diff --git a/ext/TARGET_LPC1768/TARGET_NXP/TARGET_LPC176X/gpio_object.h b/ext/TARGET_LPC1768/TARGET_NXP/TARGET_LPC176X/gpio_object.h
new file mode 100644
index 0000000..0c465a9
--- /dev/null
+++ b/ext/TARGET_LPC1768/TARGET_NXP/TARGET_LPC176X/gpio_object.h
@@ -0,0 +1,56 @@
+/* mbed Microcontroller Library

+ * Copyright (c) 2006-2013 ARM Limited

+ *

+ * Licensed under the Apache License, Version 2.0 (the "License");

+ * you may not use this file except in compliance with the License.

+ * You may obtain a copy of the License at

+ *

+ *     http://www.apache.org/licenses/LICENSE-2.0

+ *

+ * Unless required by applicable law or agreed to in writing, software

+ * distributed under the License is distributed on an "AS IS" BASIS,

+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

+ * See the License for the specific language governing permissions and

+ * limitations under the License.

+ */

+#ifndef MBED_GPIO_OBJECT_H

+#define MBED_GPIO_OBJECT_H

+

+#include "mbed_assert.h"

+

+#ifdef __cplusplus

+extern "C" {

+#endif

+

+typedef struct {

+    PinName  pin;

+    uint32_t mask;

+

+    __IO uint32_t *reg_dir;

+    __IO uint32_t *reg_set;

+    __IO uint32_t *reg_clr;

+    __I  uint32_t *reg_in;

+} gpio_t;

+

+static inline void gpio_write(gpio_t *obj, int value) {

+    MBED_ASSERT(obj->pin != (PinName)NC);

+    if (value)

+        *obj->reg_set = obj->mask;

+    else

+        *obj->reg_clr = obj->mask;

+}

+

+static inline int gpio_read(gpio_t *obj) {

+    MBED_ASSERT(obj->pin != (PinName)NC);

+    return ((*obj->reg_in & obj->mask) ? 1 : 0);

+}

+

+static inline int gpio_is_connected(const gpio_t *obj) {

+    return obj->pin != (PinName)NC;

+}

+

+#ifdef __cplusplus

+}

+#endif

+

+#endif

diff --git a/ext/TARGET_LPC1768/TARGET_NXP/TARGET_LPC176X/objects.h b/ext/TARGET_LPC1768/TARGET_NXP/TARGET_LPC176X/objects.h
new file mode 100644
index 0000000..de6caad
--- /dev/null
+++ b/ext/TARGET_LPC1768/TARGET_NXP/TARGET_LPC176X/objects.h
@@ -0,0 +1,78 @@
+/* mbed Microcontroller Library

+ * Copyright (c) 2006-2013 ARM Limited

+ *

+ * Licensed under the Apache License, Version 2.0 (the "License");

+ * you may not use this file except in compliance with the License.

+ * You may obtain a copy of the License at

+ *

+ *     http://www.apache.org/licenses/LICENSE-2.0

+ *

+ * Unless required by applicable law or agreed to in writing, software

+ * distributed under the License is distributed on an "AS IS" BASIS,

+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

+ * See the License for the specific language governing permissions and

+ * limitations under the License.

+ */

+#ifndef MBED_OBJECTS_H

+#define MBED_OBJECTS_H

+

+#include "cmsis.h"

+#include "PortNames.h"

+#include "PeripheralNames.h"

+#include "PinNames.h"

+#include "gpio_object.h"

+

+#ifdef __cplusplus

+extern "C" {

+#endif

+

+struct gpio_irq_s {

+    uint32_t port;

+    uint32_t pin;

+    uint32_t ch;

+};

+

+struct port_s {

+    __IO uint32_t *reg_dir;

+    __IO uint32_t *reg_out;

+    __I  uint32_t *reg_in;

+    PortName port;

+    uint32_t mask;

+};

+

+struct pwmout_s {

+    __IO uint32_t *MR;

+    PWMName pwm;

+};

+

+struct serial_s {

+    LPC_UART_TypeDef *uart;

+    int index;

+};

+

+struct analogin_s {

+    ADCName adc;

+};

+

+struct dac_s {

+    DACName dac;

+};

+

+struct can_s {

+    LPC_CAN_TypeDef *dev;

+    int index;

+};

+

+struct i2c_s {

+    LPC_I2C_TypeDef *i2c;

+};

+

+struct spi_s {

+    LPC_SSP_TypeDef *spi;

+};

+

+#ifdef __cplusplus

+}

+#endif

+

+#endif

diff --git a/ext/TARGET_LPC1768/TOOLCHAIN_GCC_ARM/LPC1768.ld b/ext/TARGET_LPC1768/TOOLCHAIN_GCC_ARM/LPC1768.ld
new file mode 100644
index 0000000..9eb533b
--- /dev/null
+++ b/ext/TARGET_LPC1768/TOOLCHAIN_GCC_ARM/LPC1768.ld
@@ -0,0 +1,172 @@
+/* Linker script for mbed LPC1768 */

+

+/* Linker script to configure memory regions. */

+MEMORY

+{

+  FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 512K

+  RAM (rwx) : ORIGIN = 0x100000C8, LENGTH = (32K - 0xC8)

+

+  USB_RAM(rwx) : ORIGIN = 0x2007C000, LENGTH = 16K

+  ETH_RAM(rwx) : ORIGIN = 0x20080000, LENGTH = 16K

+}

+

+/* Linker script to place sections and symbol values. Should be used together

+ * with other linker script that defines memory regions FLASH and RAM.

+ * It references following symbols, which must be defined in code:

+ *   Reset_Handler : Entry of reset handler

+ * 

+ * It defines following symbols, which code can use without definition:

+ *   __exidx_start

+ *   __exidx_end

+ *   __etext

+ *   __data_start__

+ *   __preinit_array_start

+ *   __preinit_array_end

+ *   __init_array_start

+ *   __init_array_end

+ *   __fini_array_start

+ *   __fini_array_end

+ *   __data_end__

+ *   __bss_start__

+ *   __bss_end__

+ *   __end__

+ *   end

+ *   __HeapLimit

+ *   __StackLimit

+ *   __StackTop

+ *   __stack

+ */

+ENTRY(Reset_Handler)

+

+SECTIONS

+{

+    .text :

+    {

+        KEEP(*(.isr_vector))

+        *(.text*)

+

+        KEEP(*(.init))

+        KEEP(*(.fini))

+

+        /* .ctors */

+        *crtbegin.o(.ctors)

+        *crtbegin?.o(.ctors)

+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)

+        *(SORT(.ctors.*))

+        *(.ctors)

+

+        /* .dtors */

+        *crtbegin.o(.dtors)

+        *crtbegin?.o(.dtors)

+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)

+        *(SORT(.dtors.*))

+        *(.dtors)

+

+        *(.rodata*)

+

+        KEEP(*(.eh_frame*))

+    } > FLASH

+

+    .ARM.extab : 

+    {

+        *(.ARM.extab* .gnu.linkonce.armextab.*)

+    } > FLASH

+

+    __exidx_start = .;

+    .ARM.exidx :

+    {

+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)

+    } > FLASH

+    __exidx_end = .;

+

+    __etext = .;

+        

+    .data : AT (__etext)

+    {

+        __data_start__ = .;

+        Image$$RW_IRAM1$$Base = .;

+        *(vtable)

+        *(.data*)

+

+        . = ALIGN(4);

+        /* preinit data */

+        PROVIDE (__preinit_array_start = .);

+        KEEP(*(.preinit_array))

+        PROVIDE (__preinit_array_end = .);

+

+        . = ALIGN(4);

+        /* init data */

+        PROVIDE (__init_array_start = .);

+        KEEP(*(SORT(.init_array.*)))

+        KEEP(*(.init_array))

+        PROVIDE (__init_array_end = .);

+

+

+        . = ALIGN(4);

+        /* finit data */

+        PROVIDE (__fini_array_start = .);

+        KEEP(*(SORT(.fini_array.*)))

+        KEEP(*(.fini_array))

+        PROVIDE (__fini_array_end = .);

+

+        . = ALIGN(4);

+        /* All data end */

+        __data_end__ = .;

+

+    } > RAM

+

+    

+    .bss :

+    {

+        __bss_start__ = .;

+        *(.bss*)

+        *(COMMON)

+        __bss_end__ = .;

+        Image$$RW_IRAM1$$ZI$$Limit = . ;

+    } > RAM

+

+    

+    .heap :

+    {

+        __end__ = .;

+        end = __end__;

+        *(.heap*)

+        __HeapLimit = .;

+    } > RAM

+

+    /* .stack_dummy section doesn't contains any symbols. It is only

+     * used for linker to calculate size of stack sections, and assign

+     * values to stack symbols later */

+    .stack_dummy :

+    {

+        *(.stack)

+    } > RAM

+

+    /* Set stack top to end of RAM, and stack limit move down by

+     * size of stack_dummy section */

+    __StackTop = ORIGIN(RAM) + LENGTH(RAM);

+    __StackLimit = __StackTop - SIZEOF(.stack_dummy);

+    PROVIDE(__stack = __StackTop);

+    

+    /* Check if data + heap + stack exceeds RAM limit */

+    ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")

+

+

+    /* Code can explicitly ask for data to be 

+       placed in these higher RAM banks where

+       they will be left uninitialized. 

+    */

+    .AHBSRAM0 (NOLOAD):

+    {

+        Image$$RW_IRAM2$$Base = . ;

+        *(AHBSRAM0)

+        Image$$RW_IRAM2$$ZI$$Limit = .;

+    } > USB_RAM

+

+    .AHBSRAM1 (NOLOAD):

+    {

+        Image$$RW_IRAM3$$Base = . ;

+        *(AHBSRAM1)

+        Image$$RW_IRAM3$$ZI$$Limit = .;

+    } > ETH_RAM

+}

diff --git a/ext/TARGET_LPC1768/TOOLCHAIN_GCC_ARM/board.o b/ext/TARGET_LPC1768/TOOLCHAIN_GCC_ARM/board.o
new file mode 100644
index 0000000..10bfb72
--- /dev/null
+++ b/ext/TARGET_LPC1768/TOOLCHAIN_GCC_ARM/board.o
diff --git a/ext/TARGET_LPC1768/TOOLCHAIN_GCC_ARM/cmsis_nvic.o b/ext/TARGET_LPC1768/TOOLCHAIN_GCC_ARM/cmsis_nvic.o
new file mode 100644
index 0000000..6c01b27
--- /dev/null
+++ b/ext/TARGET_LPC1768/TOOLCHAIN_GCC_ARM/cmsis_nvic.o
diff --git a/ext/TARGET_LPC1768/TOOLCHAIN_GCC_ARM/libmbed.a b/ext/TARGET_LPC1768/TOOLCHAIN_GCC_ARM/libmbed.a
new file mode 100644
index 0000000..a2059e0
--- /dev/null
+++ b/ext/TARGET_LPC1768/TOOLCHAIN_GCC_ARM/libmbed.a
diff --git a/ext/TARGET_LPC1768/TOOLCHAIN_GCC_ARM/retarget.o b/ext/TARGET_LPC1768/TOOLCHAIN_GCC_ARM/retarget.o
new file mode 100644
index 0000000..701050f
--- /dev/null
+++ b/ext/TARGET_LPC1768/TOOLCHAIN_GCC_ARM/retarget.o
diff --git a/ext/TARGET_LPC1768/TOOLCHAIN_GCC_ARM/startup_LPC17xx.o b/ext/TARGET_LPC1768/TOOLCHAIN_GCC_ARM/startup_LPC17xx.o
new file mode 100644
index 0000000..2a13253
--- /dev/null
+++ b/ext/TARGET_LPC1768/TOOLCHAIN_GCC_ARM/startup_LPC17xx.o
diff --git a/ext/TARGET_LPC1768/TOOLCHAIN_GCC_ARM/system_LPC17xx.o b/ext/TARGET_LPC1768/TOOLCHAIN_GCC_ARM/system_LPC17xx.o
new file mode 100644
index 0000000..b444203
--- /dev/null
+++ b/ext/TARGET_LPC1768/TOOLCHAIN_GCC_ARM/system_LPC17xx.o
diff --git a/ext/TARGET_LPC1768/arm_common_tables.h b/ext/TARGET_LPC1768/arm_common_tables.h
new file mode 100644
index 0000000..039cc3d
--- /dev/null
+++ b/ext/TARGET_LPC1768/arm_common_tables.h
@@ -0,0 +1,136 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date:        19. March 2015
+* $Revision: 	V.1.4.5
+*
+* Project: 	    CMSIS DSP Library
+* Title:	    arm_common_tables.h
+*
+* Description:	This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#ifndef _ARM_COMMON_TABLES_H
+#define _ARM_COMMON_TABLES_H
+
+#include "arm_math.h"
+
+extern const uint16_t armBitRevTable[1024];
+extern const q15_t armRecipTableQ15[64];
+extern const q31_t armRecipTableQ31[64];
+//extern const q31_t realCoefAQ31[1024];
+//extern const q31_t realCoefBQ31[1024];
+extern const float32_t twiddleCoef_16[32];
+extern const float32_t twiddleCoef_32[64];
+extern const float32_t twiddleCoef_64[128];
+extern const float32_t twiddleCoef_128[256];
+extern const float32_t twiddleCoef_256[512];
+extern const float32_t twiddleCoef_512[1024];
+extern const float32_t twiddleCoef_1024[2048];
+extern const float32_t twiddleCoef_2048[4096];
+extern const float32_t twiddleCoef_4096[8192];
+#define twiddleCoef twiddleCoef_4096
+extern const q31_t twiddleCoef_16_q31[24];
+extern const q31_t twiddleCoef_32_q31[48];
+extern const q31_t twiddleCoef_64_q31[96];
+extern const q31_t twiddleCoef_128_q31[192];
+extern const q31_t twiddleCoef_256_q31[384];
+extern const q31_t twiddleCoef_512_q31[768];
+extern const q31_t twiddleCoef_1024_q31[1536];
+extern const q31_t twiddleCoef_2048_q31[3072];
+extern const q31_t twiddleCoef_4096_q31[6144];
+extern const q15_t twiddleCoef_16_q15[24];
+extern const q15_t twiddleCoef_32_q15[48];
+extern const q15_t twiddleCoef_64_q15[96];
+extern const q15_t twiddleCoef_128_q15[192];
+extern const q15_t twiddleCoef_256_q15[384];
+extern const q15_t twiddleCoef_512_q15[768];
+extern const q15_t twiddleCoef_1024_q15[1536];
+extern const q15_t twiddleCoef_2048_q15[3072];
+extern const q15_t twiddleCoef_4096_q15[6144];
+extern const float32_t twiddleCoef_rfft_32[32];
+extern const float32_t twiddleCoef_rfft_64[64];
+extern const float32_t twiddleCoef_rfft_128[128];
+extern const float32_t twiddleCoef_rfft_256[256];
+extern const float32_t twiddleCoef_rfft_512[512];
+extern const float32_t twiddleCoef_rfft_1024[1024];
+extern const float32_t twiddleCoef_rfft_2048[2048];
+extern const float32_t twiddleCoef_rfft_4096[4096];
+
+
+/* floating-point bit reversal tables */
+#define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20  )
+#define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48  )
+#define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56  )
+#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208 )
+#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440 )
+#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448 )
+#define ARMBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800)
+#define ARMBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808)
+#define ARMBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032)
+
+extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE__16_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE__32_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE__64_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE1024_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH];
+
+/* fixed-point bit reversal tables */
+#define ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH ((uint16_t)12  )
+#define ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH ((uint16_t)24  )
+#define ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH ((uint16_t)56  )
+#define ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH ((uint16_t)112 )
+#define ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH ((uint16_t)240 )
+#define ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH ((uint16_t)480 )
+#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992 )
+#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984)
+#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032)
+
+extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH];
+
+/* Tables for Fast Math Sine and Cosine */
+extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1];
+extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1];
+extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1];
+
+#endif /*  ARM_COMMON_TABLES_H */
diff --git a/ext/TARGET_LPC1768/arm_const_structs.h b/ext/TARGET_LPC1768/arm_const_structs.h
new file mode 100644
index 0000000..726d06e
--- /dev/null
+++ b/ext/TARGET_LPC1768/arm_const_structs.h
@@ -0,0 +1,79 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date:        19. March 2015
+* $Revision: 	V.1.4.5
+*
+* Project: 	    CMSIS DSP Library
+* Title:	    arm_const_structs.h
+*
+* Description:	This file has constant structs that are initialized for
+*              user convenience.  For example, some can be given as
+*              arguments to the arm_cfft_f32() function.
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#ifndef _ARM_CONST_STRUCTS_H
+#define _ARM_CONST_STRUCTS_H
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096;
+
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096;
+
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096;
+
+#endif
diff --git a/ext/TARGET_LPC1768/arm_math.h b/ext/TARGET_LPC1768/arm_math.h
new file mode 100644
index 0000000..e4b2f62
--- /dev/null
+++ b/ext/TARGET_LPC1768/arm_math.h
@@ -0,0 +1,7556 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2015 ARM Limited. All rights reserved.
+*
+* $Date:        19. March 2015
+* $Revision: 	V.1.4.5
+*
+* Project: 	    CMSIS DSP Library
+* Title:	    arm_math.h
+*
+* Description:	Public header file for CMSIS DSP Library
+*
+* Target Processor: Cortex-M7/Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+ * -------------------------------------------------------------------- */
+
+/**
+   \mainpage CMSIS DSP Software Library
+   *
+   * Introduction
+   * ------------
+   *
+   * This user manual describes the CMSIS DSP software library,
+   * a suite of common signal processing functions for use on Cortex-M processor based devices.
+   *
+   * The library is divided into a number of functions each covering a specific category:
+   * - Basic math functions
+   * - Fast math functions
+   * - Complex math functions
+   * - Filters
+   * - Matrix functions
+   * - Transforms
+   * - Motor control functions
+   * - Statistical functions
+   * - Support functions
+   * - Interpolation functions
+   *
+   * The library has separate functions for operating on 8-bit integers, 16-bit integers,
+   * 32-bit integer and 32-bit floating-point values.
+   *
+   * Using the Library
+   * ------------
+   *
+   * The library installer contains prebuilt versions of the libraries in the <code>Lib</code> folder.
+   * - arm_cortexM7lfdp_math.lib (Little endian and Double Precision Floating Point Unit on Cortex-M7)
+   * - arm_cortexM7bfdp_math.lib (Big endian and Double Precision Floating Point Unit on Cortex-M7)
+   * - arm_cortexM7lfsp_math.lib (Little endian and Single Precision Floating Point Unit on Cortex-M7)
+   * - arm_cortexM7bfsp_math.lib (Big endian and Single Precision Floating Point Unit on Cortex-M7)
+   * - arm_cortexM7l_math.lib (Little endian on Cortex-M7)
+   * - arm_cortexM7b_math.lib (Big endian on Cortex-M7)
+   * - arm_cortexM4lf_math.lib (Little endian and Floating Point Unit on Cortex-M4)
+   * - arm_cortexM4bf_math.lib (Big endian and Floating Point Unit on Cortex-M4)
+   * - arm_cortexM4l_math.lib (Little endian on Cortex-M4)
+   * - arm_cortexM4b_math.lib (Big endian on Cortex-M4)
+   * - arm_cortexM3l_math.lib (Little endian on Cortex-M3)
+   * - arm_cortexM3b_math.lib (Big endian on Cortex-M3)
+   * - arm_cortexM0l_math.lib (Little endian on Cortex-M0 / CortexM0+)
+   * - arm_cortexM0b_math.lib (Big endian on Cortex-M0 / CortexM0+)
+   *
+   * The library functions are declared in the public file <code>arm_math.h</code> which is placed in the <code>Include</code> folder.
+   * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single
+   * public header file <code> arm_math.h</code> for Cortex-M7/M4/M3/M0/M0+ with little endian and big endian. Same header file will be used for floating point unit(FPU) variants.
+   * Define the appropriate pre processor MACRO ARM_MATH_CM7 or ARM_MATH_CM4 or  ARM_MATH_CM3 or
+   * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application.
+   *
+   * Examples
+   * --------
+   *
+   * The library ships with a number of examples which demonstrate how to use the library functions.
+   *
+   * Toolchain Support
+   * ------------
+   *
+   * The library has been developed and tested with MDK-ARM version 5.14.0.0
+   * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly.
+   *
+   * Building the Library
+   * ------------
+   *
+   * The library installer contains a project file to re build libraries on MDK-ARM Tool chain in the <code>CMSIS\\DSP_Lib\\Source\\ARM</code> folder.
+   * - arm_cortexM_math.uvprojx
+   *
+   *
+   * The libraries can be built by opening the arm_cortexM_math.uvprojx project in MDK-ARM, selecting a specific target, and defining the optional pre processor MACROs detailed above.
+   *
+   * Pre-processor Macros
+   * ------------
+   *
+   * Each library project have differant pre-processor macros.
+   *
+   * - UNALIGNED_SUPPORT_DISABLE:
+   *
+   * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access
+   *
+   * - ARM_MATH_BIG_ENDIAN:
+   *
+   * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets.
+   *
+   * - ARM_MATH_MATRIX_CHECK:
+   *
+   * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices
+   *
+   * - ARM_MATH_ROUNDING:
+   *
+   * Define macro ARM_MATH_ROUNDING for rounding on support functions
+   *
+   * - ARM_MATH_CMx:
+   *
+   * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target
+   * and ARM_MATH_CM0 for building library on Cortex-M0 target, ARM_MATH_CM0PLUS for building library on Cortex-M0+ target, and
+   * ARM_MATH_CM7 for building the library on cortex-M7.
+   *
+   * - __FPU_PRESENT:
+   *
+   * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for M4bf and M4lf libraries
+   *
+   * <hr>
+   * CMSIS-DSP in ARM::CMSIS Pack
+   * -----------------------------
+   * 
+   * The following files relevant to CMSIS-DSP are present in the <b>ARM::CMSIS</b> Pack directories:
+   * |File/Folder                   |Content                                                                 |
+   * |------------------------------|------------------------------------------------------------------------|
+   * |\b CMSIS\\Documentation\\DSP  | This documentation                                                     |
+   * |\b CMSIS\\DSP_Lib             | Software license agreement (license.txt)                               |
+   * |\b CMSIS\\DSP_Lib\\Examples   | Example projects demonstrating the usage of the library functions      |
+   * |\b CMSIS\\DSP_Lib\\Source     | Source files for rebuilding the library                                |
+   * 
+   * <hr>
+   * Revision History of CMSIS-DSP
+   * ------------
+   * Please refer to \ref ChangeLog_pg.
+   *
+   * Copyright Notice
+   * ------------
+   *
+   * Copyright (C) 2010-2015 ARM Limited. All rights reserved.
+   */
+
+
+/**
+ * @defgroup groupMath Basic Math Functions
+ */
+
+/**
+ * @defgroup groupFastMath Fast Math Functions
+ * This set of functions provides a fast approximation to sine, cosine, and square root.
+ * As compared to most of the other functions in the CMSIS math library, the fast math functions
+ * operate on individual values and not arrays.
+ * There are separate functions for Q15, Q31, and floating-point data.
+ *
+ */
+
+/**
+ * @defgroup groupCmplxMath Complex Math Functions
+ * This set of functions operates on complex data vectors.
+ * The data in the complex arrays is stored in an interleaved fashion
+ * (real, imag, real, imag, ...).
+ * In the API functions, the number of samples in a complex array refers
+ * to the number of complex values; the array contains twice this number of
+ * real values.
+ */
+
+/**
+ * @defgroup groupFilters Filtering Functions
+ */
+
+/**
+ * @defgroup groupMatrix Matrix Functions
+ *
+ * This set of functions provides basic matrix math operations.
+ * The functions operate on matrix data structures.  For example,
+ * the type
+ * definition for the floating-point matrix structure is shown
+ * below:
+ * <pre>
+ *     typedef struct
+ *     {
+ *       uint16_t numRows;     // number of rows of the matrix.
+ *       uint16_t numCols;     // number of columns of the matrix.
+ *       float32_t *pData;     // points to the data of the matrix.
+ *     } arm_matrix_instance_f32;
+ * </pre>
+ * There are similar definitions for Q15 and Q31 data types.
+ *
+ * The structure specifies the size of the matrix and then points to
+ * an array of data.  The array is of size <code>numRows X numCols</code>
+ * and the values are arranged in row order.  That is, the
+ * matrix element (i, j) is stored at:
+ * <pre>
+ *     pData[i*numCols + j]
+ * </pre>
+ *
+ * \par Init Functions
+ * There is an associated initialization function for each type of matrix
+ * data structure.
+ * The initialization function sets the values of the internal structure fields.
+ * Refer to the function <code>arm_mat_init_f32()</code>, <code>arm_mat_init_q31()</code>
+ * and <code>arm_mat_init_q15()</code> for floating-point, Q31 and Q15 types,  respectively.
+ *
+ * \par
+ * Use of the initialization function is optional. However, if initialization function is used
+ * then the instance structure cannot be placed into a const data section.
+ * To place the instance structure in a const data
+ * section, manually initialize the data structure.  For example:
+ * <pre>
+ * <code>arm_matrix_instance_f32 S = {nRows, nColumns, pData};</code>
+ * <code>arm_matrix_instance_q31 S = {nRows, nColumns, pData};</code>
+ * <code>arm_matrix_instance_q15 S = {nRows, nColumns, pData};</code>
+ * </pre>
+ * where <code>nRows</code> specifies the number of rows, <code>nColumns</code>
+ * specifies the number of columns, and <code>pData</code> points to the
+ * data array.
+ *
+ * \par Size Checking
+ * By default all of the matrix functions perform size checking on the input and
+ * output matrices.  For example, the matrix addition function verifies that the
+ * two input matrices and the output matrix all have the same number of rows and
+ * columns.  If the size check fails the functions return:
+ * <pre>
+ *     ARM_MATH_SIZE_MISMATCH
+ * </pre>
+ * Otherwise the functions return
+ * <pre>
+ *     ARM_MATH_SUCCESS
+ * </pre>
+ * There is some overhead associated with this matrix size checking.
+ * The matrix size checking is enabled via the \#define
+ * <pre>
+ *     ARM_MATH_MATRIX_CHECK
+ * </pre>
+ * within the library project settings.  By default this macro is defined
+ * and size checking is enabled.  By changing the project settings and
+ * undefining this macro size checking is eliminated and the functions
+ * run a bit faster.  With size checking disabled the functions always
+ * return <code>ARM_MATH_SUCCESS</code>.
+ */
+
+/**
+ * @defgroup groupTransforms Transform Functions
+ */
+
+/**
+ * @defgroup groupController Controller Functions
+ */
+
+/**
+ * @defgroup groupStats Statistics Functions
+ */
+/**
+ * @defgroup groupSupport Support Functions
+ */
+
+/**
+ * @defgroup groupInterpolation Interpolation Functions
+ * These functions perform 1- and 2-dimensional interpolation of data.
+ * Linear interpolation is used for 1-dimensional data and
+ * bilinear interpolation is used for 2-dimensional data.
+ */
+
+/**
+ * @defgroup groupExamples Examples
+ */
+#ifndef _ARM_MATH_H
+#define _ARM_MATH_H
+
+#define __CMSIS_GENERIC         /* disable NVIC and Systick functions */
+
+#if defined(ARM_MATH_CM7)
+  #include "core_cm7.h"
+#elif defined (ARM_MATH_CM4)
+  #include "core_cm4.h"
+#elif defined (ARM_MATH_CM3)
+  #include "core_cm3.h"
+#elif defined (ARM_MATH_CM0)
+  #include "core_cm0.h"
+#define ARM_MATH_CM0_FAMILY
+  #elif defined (ARM_MATH_CM0PLUS)
+#include "core_cm0plus.h"
+  #define ARM_MATH_CM0_FAMILY
+#else
+  #error "Define according the used Cortex core ARM_MATH_CM7, ARM_MATH_CM4, ARM_MATH_CM3, ARM_MATH_CM0PLUS or ARM_MATH_CM0"
+#endif
+
+#undef  __CMSIS_GENERIC         /* enable NVIC and Systick functions */
+#include "string.h"
+#include "math.h"
+#ifdef	__cplusplus
+extern "C"
+{
+#endif
+
+
+  /**
+   * @brief Macros required for reciprocal calculation in Normalized LMS
+   */
+
+#define DELTA_Q31 			(0x100)
+#define DELTA_Q15 			0x5
+#define INDEX_MASK 			0x0000003F
+#ifndef PI
+#define PI					3.14159265358979f
+#endif
+
+  /**
+   * @brief Macros required for SINE and COSINE Fast math approximations
+   */
+
+#define FAST_MATH_TABLE_SIZE  512
+#define FAST_MATH_Q31_SHIFT   (32 - 10)
+#define FAST_MATH_Q15_SHIFT   (16 - 10)
+#define CONTROLLER_Q31_SHIFT  (32 - 9)
+#define TABLE_SIZE  256
+#define TABLE_SPACING_Q31	   0x400000
+#define TABLE_SPACING_Q15	   0x80
+
+  /**
+   * @brief Macros required for SINE and COSINE Controller functions
+   */
+  /* 1.31(q31) Fixed value of 2/360 */
+  /* -1 to +1 is divided into 360 values so total spacing is (2/360) */
+#define INPUT_SPACING			0xB60B61
+
+  /**
+   * @brief Macro for Unaligned Support
+   */
+#ifndef UNALIGNED_SUPPORT_DISABLE
+    #define ALIGN4
+#else
+  #if defined  (__GNUC__)
+    #define ALIGN4 __attribute__((aligned(4)))
+  #else
+    #define ALIGN4 __align(4)
+  #endif
+#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
+
+  /**
+   * @brief Error status returned by some functions in the library.
+   */
+
+  typedef enum
+  {
+    ARM_MATH_SUCCESS = 0,                /**< No error */
+    ARM_MATH_ARGUMENT_ERROR = -1,        /**< One or more arguments are incorrect */
+    ARM_MATH_LENGTH_ERROR = -2,          /**< Length of data buffer is incorrect */
+    ARM_MATH_SIZE_MISMATCH = -3,         /**< Size of matrices is not compatible with the operation. */
+    ARM_MATH_NANINF = -4,                /**< Not-a-number (NaN) or infinity is generated */
+    ARM_MATH_SINGULAR = -5,              /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */
+    ARM_MATH_TEST_FAILURE = -6           /**< Test Failed  */
+  } arm_status;
+
+  /**
+   * @brief 8-bit fractional data type in 1.7 format.
+   */
+  typedef int8_t q7_t;
+
+  /**
+   * @brief 16-bit fractional data type in 1.15 format.
+   */
+  typedef int16_t q15_t;
+
+  /**
+   * @brief 32-bit fractional data type in 1.31 format.
+   */
+  typedef int32_t q31_t;
+
+  /**
+   * @brief 64-bit fractional data type in 1.63 format.
+   */
+  typedef int64_t q63_t;
+
+  /**
+   * @brief 32-bit floating-point type definition.
+   */
+  typedef float float32_t;
+
+  /**
+   * @brief 64-bit floating-point type definition.
+   */
+  typedef double float64_t;
+
+  /**
+   * @brief definition to read/write two 16 bit values.
+   */
+#if defined __CC_ARM
+  #define __SIMD32_TYPE int32_t __packed
+  #define CMSIS_UNUSED __attribute__((unused))
+#elif defined __ICCARM__
+  #define __SIMD32_TYPE int32_t __packed
+  #define CMSIS_UNUSED
+#elif defined __GNUC__
+  #define __SIMD32_TYPE int32_t
+  #define CMSIS_UNUSED __attribute__((unused))
+#elif defined __CSMC__			/* Cosmic */
+  #define __SIMD32_TYPE int32_t
+  #define CMSIS_UNUSED
+#elif defined __TASKING__
+  #define __SIMD32_TYPE __unaligned int32_t
+  #define CMSIS_UNUSED
+#else
+  #error Unknown compiler
+#endif
+
+#define __SIMD32(addr)  (*(__SIMD32_TYPE **) & (addr))
+#define __SIMD32_CONST(addr)  ((__SIMD32_TYPE *)(addr))
+
+#define _SIMD32_OFFSET(addr)  (*(__SIMD32_TYPE *)  (addr))
+
+#define __SIMD64(addr)  (*(int64_t **) & (addr))
+
+#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY)
+  /**
+   * @brief definition to pack two 16 bit values.
+   */
+#define __PKHBT(ARG1, ARG2, ARG3)      ( (((int32_t)(ARG1) <<  0) & (int32_t)0x0000FFFF) | \
+                                         (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000)  )
+#define __PKHTB(ARG1, ARG2, ARG3)      ( (((int32_t)(ARG1) <<  0) & (int32_t)0xFFFF0000) | \
+                                         (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF)  )
+
+#endif
+
+
+   /**
+   * @brief definition to pack four 8 bit values.
+   */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) <<  0) & (int32_t)0x000000FF) |	\
+                                (((int32_t)(v1) <<  8) & (int32_t)0x0000FF00) |	\
+							    (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) |	\
+							    (((int32_t)(v3) << 24) & (int32_t)0xFF000000)  )
+#else
+
+#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) <<  0) & (int32_t)0x000000FF) |	\
+                                (((int32_t)(v2) <<  8) & (int32_t)0x0000FF00) |	\
+							    (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) |	\
+							    (((int32_t)(v0) << 24) & (int32_t)0xFF000000)  )
+
+#endif
+
+
+  /**
+   * @brief Clips Q63 to Q31 values.
+   */
+  static __INLINE q31_t clip_q63_to_q31(
+  q63_t x)
+  {
+    return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
+      ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x;
+  }
+
+  /**
+   * @brief Clips Q63 to Q15 values.
+   */
+  static __INLINE q15_t clip_q63_to_q15(
+  q63_t x)
+  {
+    return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
+      ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15);
+  }
+
+  /**
+   * @brief Clips Q31 to Q7 values.
+   */
+  static __INLINE q7_t clip_q31_to_q7(
+  q31_t x)
+  {
+    return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ?
+      ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x;
+  }
+
+  /**
+   * @brief Clips Q31 to Q15 values.
+   */
+  static __INLINE q15_t clip_q31_to_q15(
+  q31_t x)
+  {
+    return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ?
+      ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x;
+  }
+
+  /**
+   * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format.
+   */
+
+  static __INLINE q63_t mult32x64(
+  q63_t x,
+  q31_t y)
+  {
+    return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) +
+            (((q63_t) (x >> 32) * y)));
+  }
+
+
+//#if defined (ARM_MATH_CM0_FAMILY) && defined ( __CC_ARM   )
+//#define __CLZ __clz
+//#endif
+
+//note: function can be removed when all toolchain support __CLZ for Cortex-M0
+#if defined (ARM_MATH_CM0_FAMILY) && ((defined (__ICCARM__))  )
+
+  static __INLINE uint32_t __CLZ(
+  q31_t data);
+
+
+  static __INLINE uint32_t __CLZ(
+  q31_t data)
+  {
+    uint32_t count = 0;
+    uint32_t mask = 0x80000000;
+
+    while((data & mask) == 0)
+    {
+      count += 1u;
+      mask = mask >> 1u;
+    }
+
+    return (count);
+
+  }
+
+#endif
+
+  /**
+   * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type.
+   */
+
+  static __INLINE uint32_t arm_recip_q31(
+  q31_t in,
+  q31_t * dst,
+  q31_t * pRecipTable)
+  {
+
+    uint32_t out, tempVal;
+    uint32_t index, i;
+    uint32_t signBits;
+
+    if(in > 0)
+    {
+      signBits = __CLZ(in) - 1;
+    }
+    else
+    {
+      signBits = __CLZ(-in) - 1;
+    }
+
+    /* Convert input sample to 1.31 format */
+    in = in << signBits;
+
+    /* calculation of index for initial approximated Val */
+    index = (uint32_t) (in >> 24u);
+    index = (index & INDEX_MASK);
+
+    /* 1.31 with exp 1 */
+    out = pRecipTable[index];
+
+    /* calculation of reciprocal value */
+    /* running approximation for two iterations */
+    for (i = 0u; i < 2u; i++)
+    {
+      tempVal = (q31_t) (((q63_t) in * out) >> 31u);
+      tempVal = 0x7FFFFFFF - tempVal;
+      /*      1.31 with exp 1 */
+      //out = (q31_t) (((q63_t) out * tempVal) >> 30u);
+      out = (q31_t) clip_q63_to_q31(((q63_t) out * tempVal) >> 30u);
+    }
+
+    /* write output */
+    *dst = out;
+
+    /* return num of signbits of out = 1/in value */
+    return (signBits + 1u);
+
+  }
+
+  /**
+   * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type.
+   */
+  static __INLINE uint32_t arm_recip_q15(
+  q15_t in,
+  q15_t * dst,
+  q15_t * pRecipTable)
+  {
+
+    uint32_t out = 0, tempVal = 0;
+    uint32_t index = 0, i = 0;
+    uint32_t signBits = 0;
+
+    if(in > 0)
+    {
+      signBits = __CLZ(in) - 17;
+    }
+    else
+    {
+      signBits = __CLZ(-in) - 17;
+    }
+
+    /* Convert input sample to 1.15 format */
+    in = in << signBits;
+
+    /* calculation of index for initial approximated Val */
+    index = in >> 8;
+    index = (index & INDEX_MASK);
+
+    /*      1.15 with exp 1  */
+    out = pRecipTable[index];
+
+    /* calculation of reciprocal value */
+    /* running approximation for two iterations */
+    for (i = 0; i < 2; i++)
+    {
+      tempVal = (q15_t) (((q31_t) in * out) >> 15);
+      tempVal = 0x7FFF - tempVal;
+      /*      1.15 with exp 1 */
+      out = (q15_t) (((q31_t) out * tempVal) >> 14);
+    }
+
+    /* write output */
+    *dst = out;
+
+    /* return num of signbits of out = 1/in value */
+    return (signBits + 1);
+
+  }
+
+
+  /*
+   * @brief C custom defined intrinisic function for only M0 processors
+   */
+#if defined(ARM_MATH_CM0_FAMILY)
+
+  static __INLINE q31_t __SSAT(
+  q31_t x,
+  uint32_t y)
+  {
+    int32_t posMax, negMin;
+    uint32_t i;
+
+    posMax = 1;
+    for (i = 0; i < (y - 1); i++)
+    {
+      posMax = posMax * 2;
+    }
+
+    if(x > 0)
+    {
+      posMax = (posMax - 1);
+
+      if(x > posMax)
+      {
+        x = posMax;
+      }
+    }
+    else
+    {
+      negMin = -posMax;
+
+      if(x < negMin)
+      {
+        x = negMin;
+      }
+    }
+    return (x);
+
+
+  }
+
+#endif /* end of ARM_MATH_CM0_FAMILY */
+
+
+
+  /*
+   * @brief C custom defined intrinsic function for M3 and M0 processors
+   */
+#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY)
+
+  /*
+   * @brief C custom defined QADD8 for M3 and M0 processors
+   */
+  static __INLINE q31_t __QADD8(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum;
+    q7_t r, s, t, u;
+
+    r = (q7_t) x;
+    s = (q7_t) y;
+
+    r = __SSAT((q31_t) (r + s), 8);
+    s = __SSAT(((q31_t) (((x << 16) >> 24) + ((y << 16) >> 24))), 8);
+    t = __SSAT(((q31_t) (((x << 8) >> 24) + ((y << 8) >> 24))), 8);
+    u = __SSAT(((q31_t) ((x >> 24) + (y >> 24))), 8);
+
+    sum =
+      (((q31_t) u << 24) & 0xFF000000) | (((q31_t) t << 16) & 0x00FF0000) |
+      (((q31_t) s << 8) & 0x0000FF00) | (r & 0x000000FF);
+
+    return sum;
+
+  }
+
+  /*
+   * @brief C custom defined QSUB8 for M3 and M0 processors
+   */
+  static __INLINE q31_t __QSUB8(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum;
+    q31_t r, s, t, u;
+
+    r = (q7_t) x;
+    s = (q7_t) y;
+
+    r = __SSAT((r - s), 8);
+    s = __SSAT(((q31_t) (((x << 16) >> 24) - ((y << 16) >> 24))), 8) << 8;
+    t = __SSAT(((q31_t) (((x << 8) >> 24) - ((y << 8) >> 24))), 8) << 16;
+    u = __SSAT(((q31_t) ((x >> 24) - (y >> 24))), 8) << 24;
+
+    sum =
+      (u & 0xFF000000) | (t & 0x00FF0000) | (s & 0x0000FF00) | (r &
+                                                                0x000000FF);
+
+    return sum;
+  }
+
+  /*
+   * @brief C custom defined QADD16 for M3 and M0 processors
+   */
+
+  /*
+   * @brief C custom defined QADD16 for M3 and M0 processors
+   */
+  static __INLINE q31_t __QADD16(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum;
+    q31_t r, s;
+
+    r = (q15_t) x;
+    s = (q15_t) y;
+
+    r = __SSAT(r + s, 16);
+    s = __SSAT(((q31_t) ((x >> 16) + (y >> 16))), 16) << 16;
+
+    sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+    return sum;
+
+  }
+
+  /*
+   * @brief C custom defined SHADD16 for M3 and M0 processors
+   */
+  static __INLINE q31_t __SHADD16(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum;
+    q31_t r, s;
+
+    r = (q15_t) x;
+    s = (q15_t) y;
+
+    r = ((r >> 1) + (s >> 1));
+    s = ((q31_t) ((x >> 17) + (y >> 17))) << 16;
+
+    sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+    return sum;
+
+  }
+
+  /*
+   * @brief C custom defined QSUB16 for M3 and M0 processors
+   */
+  static __INLINE q31_t __QSUB16(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum;
+    q31_t r, s;
+
+    r = (q15_t) x;
+    s = (q15_t) y;
+
+    r = __SSAT(r - s, 16);
+    s = __SSAT(((q31_t) ((x >> 16) - (y >> 16))), 16) << 16;
+
+    sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+    return sum;
+  }
+
+  /*
+   * @brief C custom defined SHSUB16 for M3 and M0 processors
+   */
+  static __INLINE q31_t __SHSUB16(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t diff;
+    q31_t r, s;
+
+    r = (q15_t) x;
+    s = (q15_t) y;
+
+    r = ((r >> 1) - (s >> 1));
+    s = (((x >> 17) - (y >> 17)) << 16);
+
+    diff = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+    return diff;
+  }
+
+  /*
+   * @brief C custom defined QASX for M3 and M0 processors
+   */
+  static __INLINE q31_t __QASX(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum = 0;
+
+    sum =
+      ((sum +
+        clip_q31_to_q15((q31_t) ((q15_t) (x >> 16) + (q15_t) y))) << 16) +
+      clip_q31_to_q15((q31_t) ((q15_t) x - (q15_t) (y >> 16)));
+
+    return sum;
+  }
+
+  /*
+   * @brief C custom defined SHASX for M3 and M0 processors
+   */
+  static __INLINE q31_t __SHASX(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum;
+    q31_t r, s;
+
+    r = (q15_t) x;
+    s = (q15_t) y;
+
+    r = ((r >> 1) - (y >> 17));
+    s = (((x >> 17) + (s >> 1)) << 16);
+
+    sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+    return sum;
+  }
+
+
+  /*
+   * @brief C custom defined QSAX for M3 and M0 processors
+   */
+  static __INLINE q31_t __QSAX(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum = 0;
+
+    sum =
+      ((sum +
+        clip_q31_to_q15((q31_t) ((q15_t) (x >> 16) - (q15_t) y))) << 16) +
+      clip_q31_to_q15((q31_t) ((q15_t) x + (q15_t) (y >> 16)));
+
+    return sum;
+  }
+
+  /*
+   * @brief C custom defined SHSAX for M3 and M0 processors
+   */
+  static __INLINE q31_t __SHSAX(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum;
+    q31_t r, s;
+
+    r = (q15_t) x;
+    s = (q15_t) y;
+
+    r = ((r >> 1) + (y >> 17));
+    s = (((x >> 17) - (s >> 1)) << 16);
+
+    sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+    return sum;
+  }
+
+  /*
+   * @brief C custom defined SMUSDX for M3 and M0 processors
+   */
+  static __INLINE q31_t __SMUSDX(
+  q31_t x,
+  q31_t y)
+  {
+
+    return ((q31_t) (((q15_t) x * (q15_t) (y >> 16)) -
+                     ((q15_t) (x >> 16) * (q15_t) y)));
+  }
+
+  /*
+   * @brief C custom defined SMUADX for M3 and M0 processors
+   */
+  static __INLINE q31_t __SMUADX(
+  q31_t x,
+  q31_t y)
+  {
+
+    return ((q31_t) (((q15_t) x * (q15_t) (y >> 16)) +
+                     ((q15_t) (x >> 16) * (q15_t) y)));
+  }
+
+  /*
+   * @brief C custom defined QADD for M3 and M0 processors
+   */
+  static __INLINE q31_t __QADD(
+  q31_t x,
+  q31_t y)
+  {
+    return clip_q63_to_q31((q63_t) x + y);
+  }
+
+  /*
+   * @brief C custom defined QSUB for M3 and M0 processors
+   */
+  static __INLINE q31_t __QSUB(
+  q31_t x,
+  q31_t y)
+  {
+    return clip_q63_to_q31((q63_t) x - y);
+  }
+
+  /*
+   * @brief C custom defined SMLAD for M3 and M0 processors
+   */
+  static __INLINE q31_t __SMLAD(
+  q31_t x,
+  q31_t y,
+  q31_t sum)
+  {
+
+    return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) +
+            ((q15_t) x * (q15_t) y));
+  }
+
+  /*
+   * @brief C custom defined SMLADX for M3 and M0 processors
+   */
+  static __INLINE q31_t __SMLADX(
+  q31_t x,
+  q31_t y,
+  q31_t sum)
+  {
+
+    return (sum + ((q15_t) (x >> 16) * (q15_t) (y)) +
+            ((q15_t) x * (q15_t) (y >> 16)));
+  }
+
+  /*
+   * @brief C custom defined SMLSDX for M3 and M0 processors
+   */
+  static __INLINE q31_t __SMLSDX(
+  q31_t x,
+  q31_t y,
+  q31_t sum)
+  {
+
+    return (sum - ((q15_t) (x >> 16) * (q15_t) (y)) +
+            ((q15_t) x * (q15_t) (y >> 16)));
+  }
+
+  /*
+   * @brief C custom defined SMLALD for M3 and M0 processors
+   */
+  static __INLINE q63_t __SMLALD(
+  q31_t x,
+  q31_t y,
+  q63_t sum)
+  {
+
+    return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) +
+            ((q15_t) x * (q15_t) y));
+  }
+
+  /*
+   * @brief C custom defined SMLALDX for M3 and M0 processors
+   */
+  static __INLINE q63_t __SMLALDX(
+  q31_t x,
+  q31_t y,
+  q63_t sum)
+  {
+
+    return (sum + ((q15_t) (x >> 16) * (q15_t) y)) +
+      ((q15_t) x * (q15_t) (y >> 16));
+  }
+
+  /*
+   * @brief C custom defined SMUAD for M3 and M0 processors
+   */
+  static __INLINE q31_t __SMUAD(
+  q31_t x,
+  q31_t y)
+  {
+
+    return (((x >> 16) * (y >> 16)) +
+            (((x << 16) >> 16) * ((y << 16) >> 16)));
+  }
+
+  /*
+   * @brief C custom defined SMUSD for M3 and M0 processors
+   */
+  static __INLINE q31_t __SMUSD(
+  q31_t x,
+  q31_t y)
+  {
+
+    return (-((x >> 16) * (y >> 16)) +
+            (((x << 16) >> 16) * ((y << 16) >> 16)));
+  }
+
+
+  /*
+   * @brief C custom defined SXTB16 for M3 and M0 processors
+   */
+  static __INLINE q31_t __SXTB16(
+  q31_t x)
+  {
+
+    return ((((x << 24) >> 24) & 0x0000FFFF) |
+            (((x << 8) >> 8) & 0xFFFF0000));
+  }
+
+
+#endif /* defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */
+
+
+  /**
+   * @brief Instance structure for the Q7 FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;        /**< number of filter coefficients in the filter. */
+    q7_t *pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q7_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/
+  } arm_fir_instance_q7;
+
+  /**
+   * @brief Instance structure for the Q15 FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;         /**< number of filter coefficients in the filter. */
+    q15_t *pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q15_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/
+  } arm_fir_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;         /**< number of filter coefficients in the filter. */
+    q31_t *pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q31_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps. */
+  } arm_fir_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;     /**< number of filter coefficients in the filter. */
+    float32_t *pState;    /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    float32_t *pCoeffs;   /**< points to the coefficient array. The array is of length numTaps. */
+  } arm_fir_instance_f32;
+
+
+  /**
+   * @brief Processing function for the Q7 FIR filter.
+   * @param[in] *S points to an instance of the Q7 FIR filter structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+  void arm_fir_q7(
+  const arm_fir_instance_q7 * S,
+  q7_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q7 FIR filter.
+   * @param[in,out] *S points to an instance of the Q7 FIR structure.
+   * @param[in] numTaps  Number of filter coefficients in the filter.
+   * @param[in] *pCoeffs points to the filter coefficients.
+   * @param[in] *pState points to the state buffer.
+   * @param[in] blockSize number of samples that are processed.
+   * @return none
+   */
+  void arm_fir_init_q7(
+  arm_fir_instance_q7 * S,
+  uint16_t numTaps,
+  q7_t * pCoeffs,
+  q7_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q15 FIR filter.
+   * @param[in] *S points to an instance of the Q15 FIR structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+  void arm_fir_q15(
+  const arm_fir_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4.
+   * @param[in] *S points to an instance of the Q15 FIR filter structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+  void arm_fir_fast_q15(
+  const arm_fir_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the Q15 FIR filter.
+   * @param[in,out] *S points to an instance of the Q15 FIR filter structure.
+   * @param[in] numTaps  Number of filter coefficients in the filter. Must be even and greater than or equal to 4.
+   * @param[in] *pCoeffs points to the filter coefficients.
+   * @param[in] *pState points to the state buffer.
+   * @param[in] blockSize number of samples that are processed at a time.
+   * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if
+   * <code>numTaps</code> is not a supported value.
+   */
+
+  arm_status arm_fir_init_q15(
+  arm_fir_instance_q15 * S,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q31 FIR filter.
+   * @param[in] *S points to an instance of the Q31 FIR filter structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+  void arm_fir_q31(
+  const arm_fir_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4.
+   * @param[in] *S points to an instance of the Q31 FIR structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+  void arm_fir_fast_q31(
+  const arm_fir_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the Q31 FIR filter.
+   * @param[in,out] *S points to an instance of the Q31 FIR structure.
+   * @param[in] 	numTaps  Number of filter coefficients in the filter.
+   * @param[in] 	*pCoeffs points to the filter coefficients.
+   * @param[in] 	*pState points to the state buffer.
+   * @param[in] 	blockSize number of samples that are processed at a time.
+   * @return 		none.
+   */
+  void arm_fir_init_q31(
+  arm_fir_instance_q31 * S,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the floating-point FIR filter.
+   * @param[in] *S points to an instance of the floating-point FIR structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+  void arm_fir_f32(
+  const arm_fir_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the floating-point FIR filter.
+   * @param[in,out] *S points to an instance of the floating-point FIR filter structure.
+   * @param[in] 	numTaps  Number of filter coefficients in the filter.
+   * @param[in] 	*pCoeffs points to the filter coefficients.
+   * @param[in] 	*pState points to the state buffer.
+   * @param[in] 	blockSize number of samples that are processed at a time.
+   * @return    	none.
+   */
+  void arm_fir_init_f32(
+  arm_fir_instance_f32 * S,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Instance structure for the Q15 Biquad cascade filter.
+   */
+  typedef struct
+  {
+    int8_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    q15_t *pState;            /**< Points to the array of state coefficients.  The array is of length 4*numStages. */
+    q15_t *pCoeffs;           /**< Points to the array of coefficients.  The array is of length 5*numStages. */
+    int8_t postShift;         /**< Additional shift, in bits, applied to each output sample. */
+
+  } arm_biquad_casd_df1_inst_q15;
+
+
+  /**
+   * @brief Instance structure for the Q31 Biquad cascade filter.
+   */
+  typedef struct
+  {
+    uint32_t numStages;      /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    q31_t *pState;           /**< Points to the array of state coefficients.  The array is of length 4*numStages. */
+    q31_t *pCoeffs;          /**< Points to the array of coefficients.  The array is of length 5*numStages. */
+    uint8_t postShift;       /**< Additional shift, in bits, applied to each output sample. */
+
+  } arm_biquad_casd_df1_inst_q31;
+
+  /**
+   * @brief Instance structure for the floating-point Biquad cascade filter.
+   */
+  typedef struct
+  {
+    uint32_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    float32_t *pState;          /**< Points to the array of state coefficients.  The array is of length 4*numStages. */
+    float32_t *pCoeffs;         /**< Points to the array of coefficients.  The array is of length 5*numStages. */
+
+
+  } arm_biquad_casd_df1_inst_f32;
+
+
+
+  /**
+   * @brief Processing function for the Q15 Biquad cascade filter.
+   * @param[in]  *S points to an instance of the Q15 Biquad cascade structure.
+   * @param[in]  *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in]  blockSize number of samples to process.
+   * @return     none.
+   */
+
+  void arm_biquad_cascade_df1_q15(
+  const arm_biquad_casd_df1_inst_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the Q15 Biquad cascade filter.
+   * @param[in,out] *S           points to an instance of the Q15 Biquad cascade structure.
+   * @param[in]     numStages    number of 2nd order stages in the filter.
+   * @param[in]     *pCoeffs     points to the filter coefficients.
+   * @param[in]     *pState      points to the state buffer.
+   * @param[in]     postShift    Shift to be applied to the output. Varies according to the coefficients format
+   * @return        none
+   */
+
+  void arm_biquad_cascade_df1_init_q15(
+  arm_biquad_casd_df1_inst_q15 * S,
+  uint8_t numStages,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  int8_t postShift);
+
+
+  /**
+   * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4.
+   * @param[in]  *S points to an instance of the Q15 Biquad cascade structure.
+   * @param[in]  *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in]  blockSize number of samples to process.
+   * @return     none.
+   */
+
+  void arm_biquad_cascade_df1_fast_q15(
+  const arm_biquad_casd_df1_inst_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q31 Biquad cascade filter
+   * @param[in]  *S         points to an instance of the Q31 Biquad cascade structure.
+   * @param[in]  *pSrc      points to the block of input data.
+   * @param[out] *pDst      points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   * @return     none.
+   */
+
+  void arm_biquad_cascade_df1_q31(
+  const arm_biquad_casd_df1_inst_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4.
+   * @param[in]  *S         points to an instance of the Q31 Biquad cascade structure.
+   * @param[in]  *pSrc      points to the block of input data.
+   * @param[out] *pDst      points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   * @return     none.
+   */
+
+  void arm_biquad_cascade_df1_fast_q31(
+  const arm_biquad_casd_df1_inst_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the Q31 Biquad cascade filter.
+   * @param[in,out] *S           points to an instance of the Q31 Biquad cascade structure.
+   * @param[in]     numStages      number of 2nd order stages in the filter.
+   * @param[in]     *pCoeffs     points to the filter coefficients.
+   * @param[in]     *pState      points to the state buffer.
+   * @param[in]     postShift    Shift to be applied to the output. Varies according to the coefficients format
+   * @return        none
+   */
+
+  void arm_biquad_cascade_df1_init_q31(
+  arm_biquad_casd_df1_inst_q31 * S,
+  uint8_t numStages,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  int8_t postShift);
+
+  /**
+   * @brief Processing function for the floating-point Biquad cascade filter.
+   * @param[in]  *S         points to an instance of the floating-point Biquad cascade structure.
+   * @param[in]  *pSrc      points to the block of input data.
+   * @param[out] *pDst      points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   * @return     none.
+   */
+
+  void arm_biquad_cascade_df1_f32(
+  const arm_biquad_casd_df1_inst_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the floating-point Biquad cascade filter.
+   * @param[in,out] *S           points to an instance of the floating-point Biquad cascade structure.
+   * @param[in]     numStages    number of 2nd order stages in the filter.
+   * @param[in]     *pCoeffs     points to the filter coefficients.
+   * @param[in]     *pState      points to the state buffer.
+   * @return        none
+   */
+
+  void arm_biquad_cascade_df1_init_f32(
+  arm_biquad_casd_df1_inst_f32 * S,
+  uint8_t numStages,
+  float32_t * pCoeffs,
+  float32_t * pState);
+
+
+  /**
+   * @brief Instance structure for the floating-point matrix structure.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;     /**< number of rows of the matrix.     */
+    uint16_t numCols;     /**< number of columns of the matrix.  */
+    float32_t *pData;     /**< points to the data of the matrix. */
+  } arm_matrix_instance_f32;
+
+
+  /**
+   * @brief Instance structure for the floating-point matrix structure.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;     /**< number of rows of the matrix.     */
+    uint16_t numCols;     /**< number of columns of the matrix.  */
+    float64_t *pData;     /**< points to the data of the matrix. */
+  } arm_matrix_instance_f64;
+
+  /**
+   * @brief Instance structure for the Q15 matrix structure.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;     /**< number of rows of the matrix.     */
+    uint16_t numCols;     /**< number of columns of the matrix.  */
+    q15_t *pData;         /**< points to the data of the matrix. */
+
+  } arm_matrix_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 matrix structure.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;     /**< number of rows of the matrix.     */
+    uint16_t numCols;     /**< number of columns of the matrix.  */
+    q31_t *pData;         /**< points to the data of the matrix. */
+
+  } arm_matrix_instance_q31;
+
+
+
+  /**
+   * @brief Floating-point matrix addition.
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_add_f32(
+  const arm_matrix_instance_f32 * pSrcA,
+  const arm_matrix_instance_f32 * pSrcB,
+  arm_matrix_instance_f32 * pDst);
+
+  /**
+   * @brief Q15 matrix addition.
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_add_q15(
+  const arm_matrix_instance_q15 * pSrcA,
+  const arm_matrix_instance_q15 * pSrcB,
+  arm_matrix_instance_q15 * pDst);
+
+  /**
+   * @brief Q31 matrix addition.
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_add_q31(
+  const arm_matrix_instance_q31 * pSrcA,
+  const arm_matrix_instance_q31 * pSrcB,
+  arm_matrix_instance_q31 * pDst);
+
+  /**
+   * @brief Floating-point, complex, matrix multiplication.
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_cmplx_mult_f32(
+  const arm_matrix_instance_f32 * pSrcA,
+  const arm_matrix_instance_f32 * pSrcB,
+  arm_matrix_instance_f32 * pDst);
+
+  /**
+   * @brief Q15, complex,  matrix multiplication.
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_cmplx_mult_q15(
+  const arm_matrix_instance_q15 * pSrcA,
+  const arm_matrix_instance_q15 * pSrcB,
+  arm_matrix_instance_q15 * pDst,
+  q15_t * pScratch);
+
+  /**
+   * @brief Q31, complex, matrix multiplication.
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_cmplx_mult_q31(
+  const arm_matrix_instance_q31 * pSrcA,
+  const arm_matrix_instance_q31 * pSrcB,
+  arm_matrix_instance_q31 * pDst);
+
+
+  /**
+   * @brief Floating-point matrix transpose.
+   * @param[in]  *pSrc points to the input matrix
+   * @param[out] *pDst points to the output matrix
+   * @return 	The function returns either  <code>ARM_MATH_SIZE_MISMATCH</code>
+   * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_trans_f32(
+  const arm_matrix_instance_f32 * pSrc,
+  arm_matrix_instance_f32 * pDst);
+
+
+  /**
+   * @brief Q15 matrix transpose.
+   * @param[in]  *pSrc points to the input matrix
+   * @param[out] *pDst points to the output matrix
+   * @return 	The function returns either  <code>ARM_MATH_SIZE_MISMATCH</code>
+   * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_trans_q15(
+  const arm_matrix_instance_q15 * pSrc,
+  arm_matrix_instance_q15 * pDst);
+
+  /**
+   * @brief Q31 matrix transpose.
+   * @param[in]  *pSrc points to the input matrix
+   * @param[out] *pDst points to the output matrix
+   * @return 	The function returns either  <code>ARM_MATH_SIZE_MISMATCH</code>
+   * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_trans_q31(
+  const arm_matrix_instance_q31 * pSrc,
+  arm_matrix_instance_q31 * pDst);
+
+
+  /**
+   * @brief Floating-point matrix multiplication
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_mult_f32(
+  const arm_matrix_instance_f32 * pSrcA,
+  const arm_matrix_instance_f32 * pSrcB,
+  arm_matrix_instance_f32 * pDst);
+
+  /**
+   * @brief Q15 matrix multiplication
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @param[in]		 *pState points to the array for storing intermediate results
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_mult_q15(
+  const arm_matrix_instance_q15 * pSrcA,
+  const arm_matrix_instance_q15 * pSrcB,
+  arm_matrix_instance_q15 * pDst,
+  q15_t * pState);
+
+  /**
+   * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
+   * @param[in]       *pSrcA  points to the first input matrix structure
+   * @param[in]       *pSrcB  points to the second input matrix structure
+   * @param[out]      *pDst   points to output matrix structure
+   * @param[in]		  *pState points to the array for storing intermediate results
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_mult_fast_q15(
+  const arm_matrix_instance_q15 * pSrcA,
+  const arm_matrix_instance_q15 * pSrcB,
+  arm_matrix_instance_q15 * pDst,
+  q15_t * pState);
+
+  /**
+   * @brief Q31 matrix multiplication
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_mult_q31(
+  const arm_matrix_instance_q31 * pSrcA,
+  const arm_matrix_instance_q31 * pSrcB,
+  arm_matrix_instance_q31 * pDst);
+
+  /**
+   * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_mult_fast_q31(
+  const arm_matrix_instance_q31 * pSrcA,
+  const arm_matrix_instance_q31 * pSrcB,
+  arm_matrix_instance_q31 * pDst);
+
+
+  /**
+   * @brief Floating-point matrix subtraction
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_sub_f32(
+  const arm_matrix_instance_f32 * pSrcA,
+  const arm_matrix_instance_f32 * pSrcB,
+  arm_matrix_instance_f32 * pDst);
+
+  /**
+   * @brief Q15 matrix subtraction
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_sub_q15(
+  const arm_matrix_instance_q15 * pSrcA,
+  const arm_matrix_instance_q15 * pSrcB,
+  arm_matrix_instance_q15 * pDst);
+
+  /**
+   * @brief Q31 matrix subtraction
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_sub_q31(
+  const arm_matrix_instance_q31 * pSrcA,
+  const arm_matrix_instance_q31 * pSrcB,
+  arm_matrix_instance_q31 * pDst);
+
+  /**
+   * @brief Floating-point matrix scaling.
+   * @param[in]  *pSrc points to the input matrix
+   * @param[in]  scale scale factor
+   * @param[out] *pDst points to the output matrix
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_scale_f32(
+  const arm_matrix_instance_f32 * pSrc,
+  float32_t scale,
+  arm_matrix_instance_f32 * pDst);
+
+  /**
+   * @brief Q15 matrix scaling.
+   * @param[in]       *pSrc points to input matrix
+   * @param[in]       scaleFract fractional portion of the scale factor
+   * @param[in]       shift number of bits to shift the result by
+   * @param[out]      *pDst points to output matrix
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_scale_q15(
+  const arm_matrix_instance_q15 * pSrc,
+  q15_t scaleFract,
+  int32_t shift,
+  arm_matrix_instance_q15 * pDst);
+
+  /**
+   * @brief Q31 matrix scaling.
+   * @param[in]       *pSrc points to input matrix
+   * @param[in]       scaleFract fractional portion of the scale factor
+   * @param[in]       shift number of bits to shift the result by
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_scale_q31(
+  const arm_matrix_instance_q31 * pSrc,
+  q31_t scaleFract,
+  int32_t shift,
+  arm_matrix_instance_q31 * pDst);
+
+
+  /**
+   * @brief  Q31 matrix initialization.
+   * @param[in,out] *S             points to an instance of the floating-point matrix structure.
+   * @param[in]     nRows          number of rows in the matrix.
+   * @param[in]     nColumns       number of columns in the matrix.
+   * @param[in]     *pData	       points to the matrix data array.
+   * @return        none
+   */
+
+  void arm_mat_init_q31(
+  arm_matrix_instance_q31 * S,
+  uint16_t nRows,
+  uint16_t nColumns,
+  q31_t * pData);
+
+  /**
+   * @brief  Q15 matrix initialization.
+   * @param[in,out] *S             points to an instance of the floating-point matrix structure.
+   * @param[in]     nRows          number of rows in the matrix.
+   * @param[in]     nColumns       number of columns in the matrix.
+   * @param[in]     *pData	       points to the matrix data array.
+   * @return        none
+   */
+
+  void arm_mat_init_q15(
+  arm_matrix_instance_q15 * S,
+  uint16_t nRows,
+  uint16_t nColumns,
+  q15_t * pData);
+
+  /**
+   * @brief  Floating-point matrix initialization.
+   * @param[in,out] *S             points to an instance of the floating-point matrix structure.
+   * @param[in]     nRows          number of rows in the matrix.
+   * @param[in]     nColumns       number of columns in the matrix.
+   * @param[in]     *pData	       points to the matrix data array.
+   * @return        none
+   */
+
+  void arm_mat_init_f32(
+  arm_matrix_instance_f32 * S,
+  uint16_t nRows,
+  uint16_t nColumns,
+  float32_t * pData);
+
+
+
+  /**
+   * @brief Instance structure for the Q15 PID Control.
+   */
+  typedef struct
+  {
+    q15_t A0;    /**< The derived gain, A0 = Kp + Ki + Kd . */
+#ifdef ARM_MATH_CM0_FAMILY
+    q15_t A1;
+    q15_t A2;
+#else
+    q31_t A1;           /**< The derived gain A1 = -Kp - 2Kd | Kd.*/
+#endif
+    q15_t state[3];       /**< The state array of length 3. */
+    q15_t Kp;           /**< The proportional gain. */
+    q15_t Ki;           /**< The integral gain. */
+    q15_t Kd;           /**< The derivative gain. */
+  } arm_pid_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 PID Control.
+   */
+  typedef struct
+  {
+    q31_t A0;            /**< The derived gain, A0 = Kp + Ki + Kd . */
+    q31_t A1;            /**< The derived gain, A1 = -Kp - 2Kd. */
+    q31_t A2;            /**< The derived gain, A2 = Kd . */
+    q31_t state[3];      /**< The state array of length 3. */
+    q31_t Kp;            /**< The proportional gain. */
+    q31_t Ki;            /**< The integral gain. */
+    q31_t Kd;            /**< The derivative gain. */
+
+  } arm_pid_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point PID Control.
+   */
+  typedef struct
+  {
+    float32_t A0;          /**< The derived gain, A0 = Kp + Ki + Kd . */
+    float32_t A1;          /**< The derived gain, A1 = -Kp - 2Kd. */
+    float32_t A2;          /**< The derived gain, A2 = Kd . */
+    float32_t state[3];    /**< The state array of length 3. */
+    float32_t Kp;               /**< The proportional gain. */
+    float32_t Ki;               /**< The integral gain. */
+    float32_t Kd;               /**< The derivative gain. */
+  } arm_pid_instance_f32;
+
+
+
+  /**
+   * @brief  Initialization function for the floating-point PID Control.
+   * @param[in,out] *S      points to an instance of the PID structure.
+   * @param[in]     resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.
+   * @return none.
+   */
+  void arm_pid_init_f32(
+  arm_pid_instance_f32 * S,
+  int32_t resetStateFlag);
+
+  /**
+   * @brief  Reset function for the floating-point PID Control.
+   * @param[in,out] *S is an instance of the floating-point PID Control structure
+   * @return none
+   */
+  void arm_pid_reset_f32(
+  arm_pid_instance_f32 * S);
+
+
+  /**
+   * @brief  Initialization function for the Q31 PID Control.
+   * @param[in,out] *S points to an instance of the Q15 PID structure.
+   * @param[in]     resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.
+   * @return none.
+   */
+  void arm_pid_init_q31(
+  arm_pid_instance_q31 * S,
+  int32_t resetStateFlag);
+
+
+  /**
+   * @brief  Reset function for the Q31 PID Control.
+   * @param[in,out] *S points to an instance of the Q31 PID Control structure
+   * @return none
+   */
+
+  void arm_pid_reset_q31(
+  arm_pid_instance_q31 * S);
+
+  /**
+   * @brief  Initialization function for the Q15 PID Control.
+   * @param[in,out] *S points to an instance of the Q15 PID structure.
+   * @param[in] resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.
+   * @return none.
+   */
+  void arm_pid_init_q15(
+  arm_pid_instance_q15 * S,
+  int32_t resetStateFlag);
+
+  /**
+   * @brief  Reset function for the Q15 PID Control.
+   * @param[in,out] *S points to an instance of the q15 PID Control structure
+   * @return none
+   */
+  void arm_pid_reset_q15(
+  arm_pid_instance_q15 * S);
+
+
+  /**
+   * @brief Instance structure for the floating-point Linear Interpolate function.
+   */
+  typedef struct
+  {
+    uint32_t nValues;           /**< nValues */
+    float32_t x1;               /**< x1 */
+    float32_t xSpacing;         /**< xSpacing */
+    float32_t *pYData;          /**< pointer to the table of Y values */
+  } arm_linear_interp_instance_f32;
+
+  /**
+   * @brief Instance structure for the floating-point bilinear interpolation function.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;   /**< number of rows in the data table. */
+    uint16_t numCols;   /**< number of columns in the data table. */
+    float32_t *pData;   /**< points to the data table. */
+  } arm_bilinear_interp_instance_f32;
+
+   /**
+   * @brief Instance structure for the Q31 bilinear interpolation function.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;   /**< number of rows in the data table. */
+    uint16_t numCols;   /**< number of columns in the data table. */
+    q31_t *pData;       /**< points to the data table. */
+  } arm_bilinear_interp_instance_q31;
+
+   /**
+   * @brief Instance structure for the Q15 bilinear interpolation function.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;   /**< number of rows in the data table. */
+    uint16_t numCols;   /**< number of columns in the data table. */
+    q15_t *pData;       /**< points to the data table. */
+  } arm_bilinear_interp_instance_q15;
+
+   /**
+   * @brief Instance structure for the Q15 bilinear interpolation function.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;   /**< number of rows in the data table. */
+    uint16_t numCols;   /**< number of columns in the data table. */
+    q7_t *pData;                /**< points to the data table. */
+  } arm_bilinear_interp_instance_q7;
+
+
+  /**
+   * @brief Q7 vector multiplication.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst  points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_mult_q7(
+  q7_t * pSrcA,
+  q7_t * pSrcB,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q15 vector multiplication.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst  points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_mult_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q31 vector multiplication.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_mult_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Floating-point vector multiplication.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_mult_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+
+
+
+
+  /**
+   * @brief Instance structure for the Q15 CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t fftLen;                 /**< length of the FFT. */
+    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    q15_t *pTwiddle;                     /**< points to the Sin twiddle factor table. */
+    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+  } arm_cfft_radix2_instance_q15;
+
+/* Deprecated */
+  arm_status arm_cfft_radix2_init_q15(
+  arm_cfft_radix2_instance_q15 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+/* Deprecated */
+  void arm_cfft_radix2_q15(
+  const arm_cfft_radix2_instance_q15 * S,
+  q15_t * pSrc);
+
+
+
+  /**
+   * @brief Instance structure for the Q15 CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t fftLen;                 /**< length of the FFT. */
+    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    q15_t *pTwiddle;                 /**< points to the twiddle factor table. */
+    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+  } arm_cfft_radix4_instance_q15;
+
+/* Deprecated */
+  arm_status arm_cfft_radix4_init_q15(
+  arm_cfft_radix4_instance_q15 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+/* Deprecated */
+  void arm_cfft_radix4_q15(
+  const arm_cfft_radix4_instance_q15 * S,
+  q15_t * pSrc);
+
+  /**
+   * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t fftLen;                 /**< length of the FFT. */
+    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    q31_t *pTwiddle;                     /**< points to the Twiddle factor table. */
+    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+  } arm_cfft_radix2_instance_q31;
+
+/* Deprecated */
+  arm_status arm_cfft_radix2_init_q31(
+  arm_cfft_radix2_instance_q31 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+/* Deprecated */
+  void arm_cfft_radix2_q31(
+  const arm_cfft_radix2_instance_q31 * S,
+  q31_t * pSrc);
+
+  /**
+   * @brief Instance structure for the Q31 CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t fftLen;                 /**< length of the FFT. */
+    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    q31_t *pTwiddle;                 /**< points to the twiddle factor table. */
+    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+  } arm_cfft_radix4_instance_q31;
+
+/* Deprecated */
+  void arm_cfft_radix4_q31(
+  const arm_cfft_radix4_instance_q31 * S,
+  q31_t * pSrc);
+
+/* Deprecated */
+  arm_status arm_cfft_radix4_init_q31(
+  arm_cfft_radix4_instance_q31 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+  /**
+   * @brief Instance structure for the floating-point CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t fftLen;                   /**< length of the FFT. */
+    uint8_t ifftFlag;                  /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;            /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    float32_t *pTwiddle;               /**< points to the Twiddle factor table. */
+    uint16_t *pBitRevTable;            /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;         /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;             /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+    float32_t onebyfftLen;                 /**< value of 1/fftLen. */
+  } arm_cfft_radix2_instance_f32;
+
+/* Deprecated */
+  arm_status arm_cfft_radix2_init_f32(
+  arm_cfft_radix2_instance_f32 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+/* Deprecated */
+  void arm_cfft_radix2_f32(
+  const arm_cfft_radix2_instance_f32 * S,
+  float32_t * pSrc);
+
+  /**
+   * @brief Instance structure for the floating-point CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t fftLen;                   /**< length of the FFT. */
+    uint8_t ifftFlag;                  /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;            /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    float32_t *pTwiddle;               /**< points to the Twiddle factor table. */
+    uint16_t *pBitRevTable;            /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;         /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;             /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+    float32_t onebyfftLen;                 /**< value of 1/fftLen. */
+  } arm_cfft_radix4_instance_f32;
+
+/* Deprecated */
+  arm_status arm_cfft_radix4_init_f32(
+  arm_cfft_radix4_instance_f32 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+/* Deprecated */
+  void arm_cfft_radix4_f32(
+  const arm_cfft_radix4_instance_f32 * S,
+  float32_t * pSrc);
+
+  /**
+   * @brief Instance structure for the fixed-point CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t fftLen;                   /**< length of the FFT. */
+    const q15_t *pTwiddle;             /**< points to the Twiddle factor table. */
+    const uint16_t *pBitRevTable;      /**< points to the bit reversal table. */
+    uint16_t bitRevLength;             /**< bit reversal table length. */
+  } arm_cfft_instance_q15;
+
+void arm_cfft_q15( 
+    const arm_cfft_instance_q15 * S, 
+    q15_t * p1,
+    uint8_t ifftFlag,
+    uint8_t bitReverseFlag);  
+
+  /**
+   * @brief Instance structure for the fixed-point CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t fftLen;                   /**< length of the FFT. */
+    const q31_t *pTwiddle;             /**< points to the Twiddle factor table. */
+    const uint16_t *pBitRevTable;      /**< points to the bit reversal table. */
+    uint16_t bitRevLength;             /**< bit reversal table length. */
+  } arm_cfft_instance_q31;
+
+void arm_cfft_q31( 
+    const arm_cfft_instance_q31 * S, 
+    q31_t * p1,
+    uint8_t ifftFlag,
+    uint8_t bitReverseFlag);  
+  
+  /**
+   * @brief Instance structure for the floating-point CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t fftLen;                   /**< length of the FFT. */
+    const float32_t *pTwiddle;         /**< points to the Twiddle factor table. */
+    const uint16_t *pBitRevTable;      /**< points to the bit reversal table. */
+    uint16_t bitRevLength;             /**< bit reversal table length. */
+  } arm_cfft_instance_f32;
+
+  void arm_cfft_f32(
+  const arm_cfft_instance_f32 * S,
+  float32_t * p1,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+  /**
+   * @brief Instance structure for the Q15 RFFT/RIFFT function.
+   */
+
+  typedef struct
+  {
+    uint32_t fftLenReal;                      /**< length of the real FFT. */
+    uint8_t ifftFlagR;                        /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+    uint8_t bitReverseFlagR;                  /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+    uint32_t twidCoefRModifier;               /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    q15_t *pTwiddleAReal;                     /**< points to the real twiddle factor table. */
+    q15_t *pTwiddleBReal;                     /**< points to the imag twiddle factor table. */
+    const arm_cfft_instance_q15 *pCfft;       /**< points to the complex FFT instance. */
+  } arm_rfft_instance_q15;
+
+  arm_status arm_rfft_init_q15(
+  arm_rfft_instance_q15 * S,
+  uint32_t fftLenReal,
+  uint32_t ifftFlagR,
+  uint32_t bitReverseFlag);
+
+  void arm_rfft_q15(
+  const arm_rfft_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst);
+
+  /**
+   * @brief Instance structure for the Q31 RFFT/RIFFT function.
+   */
+
+  typedef struct
+  {
+    uint32_t fftLenReal;                        /**< length of the real FFT. */
+    uint8_t ifftFlagR;                          /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+    uint8_t bitReverseFlagR;                    /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+    uint32_t twidCoefRModifier;                 /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    q31_t *pTwiddleAReal;                       /**< points to the real twiddle factor table. */
+    q31_t *pTwiddleBReal;                       /**< points to the imag twiddle factor table. */
+    const arm_cfft_instance_q31 *pCfft;         /**< points to the complex FFT instance. */
+  } arm_rfft_instance_q31;
+
+  arm_status arm_rfft_init_q31(
+  arm_rfft_instance_q31 * S,
+  uint32_t fftLenReal,
+  uint32_t ifftFlagR,
+  uint32_t bitReverseFlag);
+
+  void arm_rfft_q31(
+  const arm_rfft_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst);
+
+  /**
+   * @brief Instance structure for the floating-point RFFT/RIFFT function.
+   */
+
+  typedef struct
+  {
+    uint32_t fftLenReal;                        /**< length of the real FFT. */
+    uint16_t fftLenBy2;                         /**< length of the complex FFT. */
+    uint8_t ifftFlagR;                          /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+    uint8_t bitReverseFlagR;                    /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+    uint32_t twidCoefRModifier;                     /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    float32_t *pTwiddleAReal;                   /**< points to the real twiddle factor table. */
+    float32_t *pTwiddleBReal;                   /**< points to the imag twiddle factor table. */
+    arm_cfft_radix4_instance_f32 *pCfft;        /**< points to the complex FFT instance. */
+  } arm_rfft_instance_f32;
+
+  arm_status arm_rfft_init_f32(
+  arm_rfft_instance_f32 * S,
+  arm_cfft_radix4_instance_f32 * S_CFFT,
+  uint32_t fftLenReal,
+  uint32_t ifftFlagR,
+  uint32_t bitReverseFlag);
+
+  void arm_rfft_f32(
+  const arm_rfft_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst);
+
+  /**
+   * @brief Instance structure for the floating-point RFFT/RIFFT function.
+   */
+
+typedef struct
+  {
+    arm_cfft_instance_f32 Sint;      /**< Internal CFFT structure. */
+    uint16_t fftLenRFFT;                        /**< length of the real sequence */
+	float32_t * pTwiddleRFFT;					/**< Twiddle factors real stage  */
+  } arm_rfft_fast_instance_f32 ;
+
+arm_status arm_rfft_fast_init_f32 (
+	arm_rfft_fast_instance_f32 * S,
+	uint16_t fftLen);
+
+void arm_rfft_fast_f32(
+  arm_rfft_fast_instance_f32 * S,
+  float32_t * p, float32_t * pOut,
+  uint8_t ifftFlag);
+
+  /**
+   * @brief Instance structure for the floating-point DCT4/IDCT4 function.
+   */
+
+  typedef struct
+  {
+    uint16_t N;                         /**< length of the DCT4. */
+    uint16_t Nby2;                      /**< half of the length of the DCT4. */
+    float32_t normalize;                /**< normalizing factor. */
+    float32_t *pTwiddle;                /**< points to the twiddle factor table. */
+    float32_t *pCosFactor;              /**< points to the cosFactor table. */
+    arm_rfft_instance_f32 *pRfft;        /**< points to the real FFT instance. */
+    arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */
+  } arm_dct4_instance_f32;
+
+  /**
+   * @brief  Initialization function for the floating-point DCT4/IDCT4.
+   * @param[in,out] *S         points to an instance of floating-point DCT4/IDCT4 structure.
+   * @param[in]     *S_RFFT    points to an instance of floating-point RFFT/RIFFT structure.
+   * @param[in]     *S_CFFT    points to an instance of floating-point CFFT/CIFFT structure.
+   * @param[in]     N          length of the DCT4.
+   * @param[in]     Nby2       half of the length of the DCT4.
+   * @param[in]     normalize  normalizing factor.
+   * @return		arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLenReal</code> is not a supported transform length.
+   */
+
+  arm_status arm_dct4_init_f32(
+  arm_dct4_instance_f32 * S,
+  arm_rfft_instance_f32 * S_RFFT,
+  arm_cfft_radix4_instance_f32 * S_CFFT,
+  uint16_t N,
+  uint16_t Nby2,
+  float32_t normalize);
+
+  /**
+   * @brief Processing function for the floating-point DCT4/IDCT4.
+   * @param[in]       *S             points to an instance of the floating-point DCT4/IDCT4 structure.
+   * @param[in]       *pState        points to state buffer.
+   * @param[in,out]   *pInlineBuffer points to the in-place input and output buffer.
+   * @return none.
+   */
+
+  void arm_dct4_f32(
+  const arm_dct4_instance_f32 * S,
+  float32_t * pState,
+  float32_t * pInlineBuffer);
+
+  /**
+   * @brief Instance structure for the Q31 DCT4/IDCT4 function.
+   */
+
+  typedef struct
+  {
+    uint16_t N;                         /**< length of the DCT4. */
+    uint16_t Nby2;                      /**< half of the length of the DCT4. */
+    q31_t normalize;                    /**< normalizing factor. */
+    q31_t *pTwiddle;                    /**< points to the twiddle factor table. */
+    q31_t *pCosFactor;                  /**< points to the cosFactor table. */
+    arm_rfft_instance_q31 *pRfft;        /**< points to the real FFT instance. */
+    arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */
+  } arm_dct4_instance_q31;
+
+  /**
+   * @brief  Initialization function for the Q31 DCT4/IDCT4.
+   * @param[in,out] *S         points to an instance of Q31 DCT4/IDCT4 structure.
+   * @param[in]     *S_RFFT    points to an instance of Q31 RFFT/RIFFT structure
+   * @param[in]     *S_CFFT    points to an instance of Q31 CFFT/CIFFT structure
+   * @param[in]     N          length of the DCT4.
+   * @param[in]     Nby2       half of the length of the DCT4.
+   * @param[in]     normalize  normalizing factor.
+   * @return		arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.
+   */
+
+  arm_status arm_dct4_init_q31(
+  arm_dct4_instance_q31 * S,
+  arm_rfft_instance_q31 * S_RFFT,
+  arm_cfft_radix4_instance_q31 * S_CFFT,
+  uint16_t N,
+  uint16_t Nby2,
+  q31_t normalize);
+
+  /**
+   * @brief Processing function for the Q31 DCT4/IDCT4.
+   * @param[in]       *S             points to an instance of the Q31 DCT4 structure.
+   * @param[in]       *pState        points to state buffer.
+   * @param[in,out]   *pInlineBuffer points to the in-place input and output buffer.
+   * @return none.
+   */
+
+  void arm_dct4_q31(
+  const arm_dct4_instance_q31 * S,
+  q31_t * pState,
+  q31_t * pInlineBuffer);
+
+  /**
+   * @brief Instance structure for the Q15 DCT4/IDCT4 function.
+   */
+
+  typedef struct
+  {
+    uint16_t N;                         /**< length of the DCT4. */
+    uint16_t Nby2;                      /**< half of the length of the DCT4. */
+    q15_t normalize;                    /**< normalizing factor. */
+    q15_t *pTwiddle;                    /**< points to the twiddle factor table. */
+    q15_t *pCosFactor;                  /**< points to the cosFactor table. */
+    arm_rfft_instance_q15 *pRfft;        /**< points to the real FFT instance. */
+    arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */
+  } arm_dct4_instance_q15;
+
+  /**
+   * @brief  Initialization function for the Q15 DCT4/IDCT4.
+   * @param[in,out] *S         points to an instance of Q15 DCT4/IDCT4 structure.
+   * @param[in]     *S_RFFT    points to an instance of Q15 RFFT/RIFFT structure.
+   * @param[in]     *S_CFFT    points to an instance of Q15 CFFT/CIFFT structure.
+   * @param[in]     N          length of the DCT4.
+   * @param[in]     Nby2       half of the length of the DCT4.
+   * @param[in]     normalize  normalizing factor.
+   * @return		arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.
+   */
+
+  arm_status arm_dct4_init_q15(
+  arm_dct4_instance_q15 * S,
+  arm_rfft_instance_q15 * S_RFFT,
+  arm_cfft_radix4_instance_q15 * S_CFFT,
+  uint16_t N,
+  uint16_t Nby2,
+  q15_t normalize);
+
+  /**
+   * @brief Processing function for the Q15 DCT4/IDCT4.
+   * @param[in]       *S             points to an instance of the Q15 DCT4 structure.
+   * @param[in]       *pState        points to state buffer.
+   * @param[in,out]   *pInlineBuffer points to the in-place input and output buffer.
+   * @return none.
+   */
+
+  void arm_dct4_q15(
+  const arm_dct4_instance_q15 * S,
+  q15_t * pState,
+  q15_t * pInlineBuffer);
+
+  /**
+   * @brief Floating-point vector addition.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_add_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q7 vector addition.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_add_q7(
+  q7_t * pSrcA,
+  q7_t * pSrcB,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q15 vector addition.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_add_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q31 vector addition.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_add_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Floating-point vector subtraction.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_sub_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q7 vector subtraction.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_sub_q7(
+  q7_t * pSrcA,
+  q7_t * pSrcB,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q15 vector subtraction.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_sub_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q31 vector subtraction.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_sub_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Multiplies a floating-point vector by a scalar.
+   * @param[in]       *pSrc points to the input vector
+   * @param[in]       scale scale factor to be applied
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_scale_f32(
+  float32_t * pSrc,
+  float32_t scale,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Multiplies a Q7 vector by a scalar.
+   * @param[in]       *pSrc points to the input vector
+   * @param[in]       scaleFract fractional portion of the scale value
+   * @param[in]       shift number of bits to shift the result by
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_scale_q7(
+  q7_t * pSrc,
+  q7_t scaleFract,
+  int8_t shift,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Multiplies a Q15 vector by a scalar.
+   * @param[in]       *pSrc points to the input vector
+   * @param[in]       scaleFract fractional portion of the scale value
+   * @param[in]       shift number of bits to shift the result by
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_scale_q15(
+  q15_t * pSrc,
+  q15_t scaleFract,
+  int8_t shift,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Multiplies a Q31 vector by a scalar.
+   * @param[in]       *pSrc points to the input vector
+   * @param[in]       scaleFract fractional portion of the scale value
+   * @param[in]       shift number of bits to shift the result by
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_scale_q31(
+  q31_t * pSrc,
+  q31_t scaleFract,
+  int8_t shift,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q7 vector absolute value.
+   * @param[in]       *pSrc points to the input buffer
+   * @param[out]      *pDst points to the output buffer
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_abs_q7(
+  q7_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Floating-point vector absolute value.
+   * @param[in]       *pSrc points to the input buffer
+   * @param[out]      *pDst points to the output buffer
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_abs_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q15 vector absolute value.
+   * @param[in]       *pSrc points to the input buffer
+   * @param[out]      *pDst points to the output buffer
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_abs_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q31 vector absolute value.
+   * @param[in]       *pSrc points to the input buffer
+   * @param[out]      *pDst points to the output buffer
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_abs_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Dot product of floating-point vectors.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[in]       blockSize number of samples in each vector
+   * @param[out]      *result output result returned here
+   * @return none.
+   */
+
+  void arm_dot_prod_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  uint32_t blockSize,
+  float32_t * result);
+
+  /**
+   * @brief Dot product of Q7 vectors.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[in]       blockSize number of samples in each vector
+   * @param[out]      *result output result returned here
+   * @return none.
+   */
+
+  void arm_dot_prod_q7(
+  q7_t * pSrcA,
+  q7_t * pSrcB,
+  uint32_t blockSize,
+  q31_t * result);
+
+  /**
+   * @brief Dot product of Q15 vectors.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[in]       blockSize number of samples in each vector
+   * @param[out]      *result output result returned here
+   * @return none.
+   */
+
+  void arm_dot_prod_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  uint32_t blockSize,
+  q63_t * result);
+
+  /**
+   * @brief Dot product of Q31 vectors.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[in]       blockSize number of samples in each vector
+   * @param[out]      *result output result returned here
+   * @return none.
+   */
+
+  void arm_dot_prod_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  uint32_t blockSize,
+  q63_t * result);
+
+  /**
+   * @brief  Shifts the elements of a Q7 vector a specified number of bits.
+   * @param[in]  *pSrc points to the input vector
+   * @param[in]  shiftBits number of bits to shift.  A positive value shifts left; a negative value shifts right.
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_shift_q7(
+  q7_t * pSrc,
+  int8_t shiftBits,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Shifts the elements of a Q15 vector a specified number of bits.
+   * @param[in]  *pSrc points to the input vector
+   * @param[in]  shiftBits number of bits to shift.  A positive value shifts left; a negative value shifts right.
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_shift_q15(
+  q15_t * pSrc,
+  int8_t shiftBits,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Shifts the elements of a Q31 vector a specified number of bits.
+   * @param[in]  *pSrc points to the input vector
+   * @param[in]  shiftBits number of bits to shift.  A positive value shifts left; a negative value shifts right.
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_shift_q31(
+  q31_t * pSrc,
+  int8_t shiftBits,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Adds a constant offset to a floating-point vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[in]  offset is the offset to be added
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_offset_f32(
+  float32_t * pSrc,
+  float32_t offset,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Adds a constant offset to a Q7 vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[in]  offset is the offset to be added
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_offset_q7(
+  q7_t * pSrc,
+  q7_t offset,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Adds a constant offset to a Q15 vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[in]  offset is the offset to be added
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_offset_q15(
+  q15_t * pSrc,
+  q15_t offset,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Adds a constant offset to a Q31 vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[in]  offset is the offset to be added
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_offset_q31(
+  q31_t * pSrc,
+  q31_t offset,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Negates the elements of a floating-point vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_negate_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Negates the elements of a Q7 vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_negate_q7(
+  q7_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Negates the elements of a Q15 vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_negate_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Negates the elements of a Q31 vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_negate_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+  /**
+   * @brief  Copies the elements of a floating-point vector.
+   * @param[in]  *pSrc input pointer
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_copy_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Copies the elements of a Q7 vector.
+   * @param[in]  *pSrc input pointer
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_copy_q7(
+  q7_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Copies the elements of a Q15 vector.
+   * @param[in]  *pSrc input pointer
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_copy_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Copies the elements of a Q31 vector.
+   * @param[in]  *pSrc input pointer
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_copy_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+  /**
+   * @brief  Fills a constant value into a floating-point vector.
+   * @param[in]  value input value to be filled
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_fill_f32(
+  float32_t value,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Fills a constant value into a Q7 vector.
+   * @param[in]  value input value to be filled
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_fill_q7(
+  q7_t value,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Fills a constant value into a Q15 vector.
+   * @param[in]  value input value to be filled
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_fill_q15(
+  q15_t value,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Fills a constant value into a Q31 vector.
+   * @param[in]  value input value to be filled
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_fill_q31(
+  q31_t value,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+/**
+ * @brief Convolution of floating-point sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written.  Length srcALen+srcBLen-1.
+ * @return none.
+ */
+
+  void arm_conv_f32(
+  float32_t * pSrcA,
+  uint32_t srcALen,
+  float32_t * pSrcB,
+  uint32_t srcBLen,
+  float32_t * pDst);
+
+
+  /**
+   * @brief Convolution of Q15 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
+   * @param[in]  *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]  *pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+   * @return none.
+   */
+
+
+  void arm_conv_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+/**
+ * @brief Convolution of Q15 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written.  Length srcALen+srcBLen-1.
+ * @return none.
+ */
+
+  void arm_conv_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst);
+
+  /**
+   * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
+   * @return none.
+   */
+
+  void arm_conv_fast_q15(
+			  q15_t * pSrcA,
+			 uint32_t srcALen,
+			  q15_t * pSrcB,
+			 uint32_t srcBLen,
+			 q15_t * pDst);
+
+  /**
+   * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
+   * @param[in]  *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]  *pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+   * @return none.
+   */
+
+  void arm_conv_fast_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+
+  /**
+   * @brief Convolution of Q31 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
+   * @return none.
+   */
+
+  void arm_conv_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst);
+
+  /**
+   * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
+   * @return none.
+   */
+
+  void arm_conv_fast_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst);
+
+
+    /**
+   * @brief Convolution of Q7 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
+   * @param[in]  *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]  *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+   * @return none.
+   */
+
+  void arm_conv_opt_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+
+  /**
+   * @brief Convolution of Q7 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
+   * @return none.
+   */
+
+  void arm_conv_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst);
+
+
+  /**
+   * @brief Partial convolution of floating-point sequences.
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_f32(
+  float32_t * pSrcA,
+  uint32_t srcALen,
+  float32_t * pSrcB,
+  uint32_t srcBLen,
+  float32_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints);
+
+    /**
+   * @brief Partial convolution of Q15 sequences.
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @param[in]       * pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]       * pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+/**
+   * @brief Partial convolution of Q15 sequences.
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints);
+
+  /**
+   * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_fast_q15(
+				        q15_t * pSrcA,
+				       uint32_t srcALen,
+				        q15_t * pSrcB,
+				       uint32_t srcBLen,
+				       q15_t * pDst,
+				       uint32_t firstIndex,
+				       uint32_t numPoints);
+
+
+  /**
+   * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @param[in]       * pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]       * pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_fast_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+  /**
+   * @brief Partial convolution of Q31 sequences.
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints);
+
+
+  /**
+   * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_fast_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints);
+
+
+  /**
+   * @brief Partial convolution of Q7 sequences
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @param[in]  *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]  *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_opt_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+/**
+   * @brief Partial convolution of Q7 sequences.
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints);
+
+
+
+  /**
+   * @brief Instance structure for the Q15 FIR decimator.
+   */
+
+  typedef struct
+  {
+    uint8_t M;                      /**< decimation factor. */
+    uint16_t numTaps;               /**< number of coefficients in the filter. */
+    q15_t *pCoeffs;                  /**< points to the coefficient array. The array is of length numTaps.*/
+    q15_t *pState;                   /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+  } arm_fir_decimate_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 FIR decimator.
+   */
+
+  typedef struct
+  {
+    uint8_t M;                  /**< decimation factor. */
+    uint16_t numTaps;           /**< number of coefficients in the filter. */
+    q31_t *pCoeffs;              /**< points to the coefficient array. The array is of length numTaps.*/
+    q31_t *pState;               /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+
+  } arm_fir_decimate_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point FIR decimator.
+   */
+
+  typedef struct
+  {
+    uint8_t M;                          /**< decimation factor. */
+    uint16_t numTaps;                   /**< number of coefficients in the filter. */
+    float32_t *pCoeffs;                  /**< points to the coefficient array. The array is of length numTaps.*/
+    float32_t *pState;                   /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+
+  } arm_fir_decimate_instance_f32;
+
+
+
+  /**
+   * @brief Processing function for the floating-point FIR decimator.
+   * @param[in] *S points to an instance of the floating-point FIR decimator structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none
+   */
+
+  void arm_fir_decimate_f32(
+  const arm_fir_decimate_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the floating-point FIR decimator.
+   * @param[in,out] *S points to an instance of the floating-point FIR decimator structure.
+   * @param[in] numTaps  number of coefficients in the filter.
+   * @param[in] M  decimation factor.
+   * @param[in] *pCoeffs points to the filter coefficients.
+   * @param[in] *pState points to the state buffer.
+   * @param[in] blockSize number of input samples to process per call.
+   * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * <code>blockSize</code> is not a multiple of <code>M</code>.
+   */
+
+  arm_status arm_fir_decimate_init_f32(
+  arm_fir_decimate_instance_f32 * S,
+  uint16_t numTaps,
+  uint8_t M,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q15 FIR decimator.
+   * @param[in] *S points to an instance of the Q15 FIR decimator structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none
+   */
+
+  void arm_fir_decimate_q15(
+  const arm_fir_decimate_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
+   * @param[in] *S points to an instance of the Q15 FIR decimator structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none
+   */
+
+  void arm_fir_decimate_fast_q15(
+  const arm_fir_decimate_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+
+  /**
+   * @brief  Initialization function for the Q15 FIR decimator.
+   * @param[in,out] *S points to an instance of the Q15 FIR decimator structure.
+   * @param[in] numTaps  number of coefficients in the filter.
+   * @param[in] M  decimation factor.
+   * @param[in] *pCoeffs points to the filter coefficients.
+   * @param[in] *pState points to the state buffer.
+   * @param[in] blockSize number of input samples to process per call.
+   * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * <code>blockSize</code> is not a multiple of <code>M</code>.
+   */
+
+  arm_status arm_fir_decimate_init_q15(
+  arm_fir_decimate_instance_q15 * S,
+  uint16_t numTaps,
+  uint8_t M,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q31 FIR decimator.
+   * @param[in] *S points to an instance of the Q31 FIR decimator structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none
+   */
+
+  void arm_fir_decimate_q31(
+  const arm_fir_decimate_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
+   * @param[in] *S points to an instance of the Q31 FIR decimator structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none
+   */
+
+  void arm_fir_decimate_fast_q31(
+  arm_fir_decimate_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q31 FIR decimator.
+   * @param[in,out] *S points to an instance of the Q31 FIR decimator structure.
+   * @param[in] numTaps  number of coefficients in the filter.
+   * @param[in] M  decimation factor.
+   * @param[in] *pCoeffs points to the filter coefficients.
+   * @param[in] *pState points to the state buffer.
+   * @param[in] blockSize number of input samples to process per call.
+   * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * <code>blockSize</code> is not a multiple of <code>M</code>.
+   */
+
+  arm_status arm_fir_decimate_init_q31(
+  arm_fir_decimate_instance_q31 * S,
+  uint16_t numTaps,
+  uint8_t M,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  uint32_t blockSize);
+
+
+
+  /**
+   * @brief Instance structure for the Q15 FIR interpolator.
+   */
+
+  typedef struct
+  {
+    uint8_t L;                      /**< upsample factor. */
+    uint16_t phaseLength;           /**< length of each polyphase filter component. */
+    q15_t *pCoeffs;                 /**< points to the coefficient array. The array is of length L*phaseLength. */
+    q15_t *pState;                  /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
+  } arm_fir_interpolate_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 FIR interpolator.
+   */
+
+  typedef struct
+  {
+    uint8_t L;                      /**< upsample factor. */
+    uint16_t phaseLength;           /**< length of each polyphase filter component. */
+    q31_t *pCoeffs;                  /**< points to the coefficient array. The array is of length L*phaseLength. */
+    q31_t *pState;                   /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
+  } arm_fir_interpolate_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point FIR interpolator.
+   */
+
+  typedef struct
+  {
+    uint8_t L;                     /**< upsample factor. */
+    uint16_t phaseLength;          /**< length of each polyphase filter component. */
+    float32_t *pCoeffs;             /**< points to the coefficient array. The array is of length L*phaseLength. */
+    float32_t *pState;              /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */
+  } arm_fir_interpolate_instance_f32;
+
+
+  /**
+   * @brief Processing function for the Q15 FIR interpolator.
+   * @param[in] *S        points to an instance of the Q15 FIR interpolator structure.
+   * @param[in] *pSrc     points to the block of input data.
+   * @param[out] *pDst    points to the block of output data.
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none.
+   */
+
+  void arm_fir_interpolate_q15(
+  const arm_fir_interpolate_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q15 FIR interpolator.
+   * @param[in,out] *S        points to an instance of the Q15 FIR interpolator structure.
+   * @param[in]     L         upsample factor.
+   * @param[in]     numTaps   number of filter coefficients in the filter.
+   * @param[in]     *pCoeffs  points to the filter coefficient buffer.
+   * @param[in]     *pState   points to the state buffer.
+   * @param[in]     blockSize number of input samples to process per call.
+   * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
+   */
+
+  arm_status arm_fir_interpolate_init_q15(
+  arm_fir_interpolate_instance_q15 * S,
+  uint8_t L,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q31 FIR interpolator.
+   * @param[in] *S        points to an instance of the Q15 FIR interpolator structure.
+   * @param[in] *pSrc     points to the block of input data.
+   * @param[out] *pDst    points to the block of output data.
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none.
+   */
+
+  void arm_fir_interpolate_q31(
+  const arm_fir_interpolate_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the Q31 FIR interpolator.
+   * @param[in,out] *S        points to an instance of the Q31 FIR interpolator structure.
+   * @param[in]     L         upsample factor.
+   * @param[in]     numTaps   number of filter coefficients in the filter.
+   * @param[in]     *pCoeffs  points to the filter coefficient buffer.
+   * @param[in]     *pState   points to the state buffer.
+   * @param[in]     blockSize number of input samples to process per call.
+   * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
+   */
+
+  arm_status arm_fir_interpolate_init_q31(
+  arm_fir_interpolate_instance_q31 * S,
+  uint8_t L,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the floating-point FIR interpolator.
+   * @param[in] *S        points to an instance of the floating-point FIR interpolator structure.
+   * @param[in] *pSrc     points to the block of input data.
+   * @param[out] *pDst    points to the block of output data.
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none.
+   */
+
+  void arm_fir_interpolate_f32(
+  const arm_fir_interpolate_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the floating-point FIR interpolator.
+   * @param[in,out] *S        points to an instance of the floating-point FIR interpolator structure.
+   * @param[in]     L         upsample factor.
+   * @param[in]     numTaps   number of filter coefficients in the filter.
+   * @param[in]     *pCoeffs  points to the filter coefficient buffer.
+   * @param[in]     *pState   points to the state buffer.
+   * @param[in]     blockSize number of input samples to process per call.
+   * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
+   */
+
+  arm_status arm_fir_interpolate_init_f32(
+  arm_fir_interpolate_instance_f32 * S,
+  uint8_t L,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  uint32_t blockSize);
+
+  /**
+   * @brief Instance structure for the high precision Q31 Biquad cascade filter.
+   */
+
+  typedef struct
+  {
+    uint8_t numStages;       /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    q63_t *pState;           /**< points to the array of state coefficients.  The array is of length 4*numStages. */
+    q31_t *pCoeffs;          /**< points to the array of coefficients.  The array is of length 5*numStages. */
+    uint8_t postShift;       /**< additional shift, in bits, applied to each output sample. */
+
+  } arm_biquad_cas_df1_32x64_ins_q31;
+
+
+  /**
+   * @param[in]  *S        points to an instance of the high precision Q31 Biquad cascade filter structure.
+   * @param[in]  *pSrc     points to the block of input data.
+   * @param[out] *pDst     points to the block of output data
+   * @param[in]  blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_biquad_cas_df1_32x64_q31(
+  const arm_biquad_cas_df1_32x64_ins_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @param[in,out] *S           points to an instance of the high precision Q31 Biquad cascade filter structure.
+   * @param[in]     numStages    number of 2nd order stages in the filter.
+   * @param[in]     *pCoeffs     points to the filter coefficients.
+   * @param[in]     *pState      points to the state buffer.
+   * @param[in]     postShift    shift to be applied to the output. Varies according to the coefficients format
+   * @return        none
+   */
+
+  void arm_biquad_cas_df1_32x64_init_q31(
+  arm_biquad_cas_df1_32x64_ins_q31 * S,
+  uint8_t numStages,
+  q31_t * pCoeffs,
+  q63_t * pState,
+  uint8_t postShift);
+
+
+
+  /**
+   * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
+   */
+
+  typedef struct
+  {
+    uint8_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    float32_t *pState;         /**< points to the array of state coefficients.  The array is of length 2*numStages. */
+    float32_t *pCoeffs;        /**< points to the array of coefficients.  The array is of length 5*numStages. */
+  } arm_biquad_cascade_df2T_instance_f32;
+
+
+
+  /**
+   * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
+   */
+
+  typedef struct
+  {
+    uint8_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    float32_t *pState;         /**< points to the array of state coefficients.  The array is of length 4*numStages. */
+    float32_t *pCoeffs;        /**< points to the array of coefficients.  The array is of length 5*numStages. */
+  } arm_biquad_cascade_stereo_df2T_instance_f32;
+
+
+
+  /**
+   * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
+   */
+
+  typedef struct
+  {
+    uint8_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    float64_t *pState;         /**< points to the array of state coefficients.  The array is of length 2*numStages. */
+    float64_t *pCoeffs;        /**< points to the array of coefficients.  The array is of length 5*numStages. */
+  } arm_biquad_cascade_df2T_instance_f64;
+
+
+  /**
+   * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
+   * @param[in]  *S        points to an instance of the filter data structure.
+   * @param[in]  *pSrc     points to the block of input data.
+   * @param[out] *pDst     points to the block of output data
+   * @param[in]  blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_biquad_cascade_df2T_f32(
+  const arm_biquad_cascade_df2T_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels
+   * @param[in]  *S        points to an instance of the filter data structure.
+   * @param[in]  *pSrc     points to the block of input data.
+   * @param[out] *pDst     points to the block of output data
+   * @param[in]  blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_biquad_cascade_stereo_df2T_f32(
+  const arm_biquad_cascade_stereo_df2T_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
+   * @param[in]  *S        points to an instance of the filter data structure.
+   * @param[in]  *pSrc     points to the block of input data.
+   * @param[out] *pDst     points to the block of output data
+   * @param[in]  blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_biquad_cascade_df2T_f64(
+  const arm_biquad_cascade_df2T_instance_f64 * S,
+  float64_t * pSrc,
+  float64_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+   * @param[in,out] *S           points to an instance of the filter data structure.
+   * @param[in]     numStages    number of 2nd order stages in the filter.
+   * @param[in]     *pCoeffs     points to the filter coefficients.
+   * @param[in]     *pState      points to the state buffer.
+   * @return        none
+   */
+
+  void arm_biquad_cascade_df2T_init_f32(
+  arm_biquad_cascade_df2T_instance_f32 * S,
+  uint8_t numStages,
+  float32_t * pCoeffs,
+  float32_t * pState);
+
+
+  /**
+   * @brief  Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+   * @param[in,out] *S           points to an instance of the filter data structure.
+   * @param[in]     numStages    number of 2nd order stages in the filter.
+   * @param[in]     *pCoeffs     points to the filter coefficients.
+   * @param[in]     *pState      points to the state buffer.
+   * @return        none
+   */
+
+  void arm_biquad_cascade_stereo_df2T_init_f32(
+  arm_biquad_cascade_stereo_df2T_instance_f32 * S,
+  uint8_t numStages,
+  float32_t * pCoeffs,
+  float32_t * pState);
+
+
+  /**
+   * @brief  Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+   * @param[in,out] *S           points to an instance of the filter data structure.
+   * @param[in]     numStages    number of 2nd order stages in the filter.
+   * @param[in]     *pCoeffs     points to the filter coefficients.
+   * @param[in]     *pState      points to the state buffer.
+   * @return        none
+   */
+
+  void arm_biquad_cascade_df2T_init_f64(
+  arm_biquad_cascade_df2T_instance_f64 * S,
+  uint8_t numStages,
+  float64_t * pCoeffs,
+  float64_t * pState);
+
+
+
+  /**
+   * @brief Instance structure for the Q15 FIR lattice filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numStages;                          /**< number of filter stages. */
+    q15_t *pState;                               /**< points to the state variable array. The array is of length numStages. */
+    q15_t *pCoeffs;                              /**< points to the coefficient array. The array is of length numStages. */
+  } arm_fir_lattice_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 FIR lattice filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numStages;                          /**< number of filter stages. */
+    q31_t *pState;                               /**< points to the state variable array. The array is of length numStages. */
+    q31_t *pCoeffs;                              /**< points to the coefficient array. The array is of length numStages. */
+  } arm_fir_lattice_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point FIR lattice filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numStages;                  /**< number of filter stages. */
+    float32_t *pState;                   /**< points to the state variable array. The array is of length numStages. */
+    float32_t *pCoeffs;                  /**< points to the coefficient array. The array is of length numStages. */
+  } arm_fir_lattice_instance_f32;
+
+  /**
+   * @brief Initialization function for the Q15 FIR lattice filter.
+   * @param[in] *S points to an instance of the Q15 FIR lattice structure.
+   * @param[in] numStages  number of filter stages.
+   * @param[in] *pCoeffs points to the coefficient buffer.  The array is of length numStages.
+   * @param[in] *pState points to the state buffer.  The array is of length numStages.
+   * @return none.
+   */
+
+  void arm_fir_lattice_init_q15(
+  arm_fir_lattice_instance_q15 * S,
+  uint16_t numStages,
+  q15_t * pCoeffs,
+  q15_t * pState);
+
+
+  /**
+   * @brief Processing function for the Q15 FIR lattice filter.
+   * @param[in] *S points to an instance of the Q15 FIR lattice structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+  void arm_fir_lattice_q15(
+  const arm_fir_lattice_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Initialization function for the Q31 FIR lattice filter.
+   * @param[in] *S points to an instance of the Q31 FIR lattice structure.
+   * @param[in] numStages  number of filter stages.
+   * @param[in] *pCoeffs points to the coefficient buffer.  The array is of length numStages.
+   * @param[in] *pState points to the state buffer.   The array is of length numStages.
+   * @return none.
+   */
+
+  void arm_fir_lattice_init_q31(
+  arm_fir_lattice_instance_q31 * S,
+  uint16_t numStages,
+  q31_t * pCoeffs,
+  q31_t * pState);
+
+
+  /**
+   * @brief Processing function for the Q31 FIR lattice filter.
+   * @param[in]  *S        points to an instance of the Q31 FIR lattice structure.
+   * @param[in]  *pSrc     points to the block of input data.
+   * @param[out] *pDst     points to the block of output data
+   * @param[in]  blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_fir_lattice_q31(
+  const arm_fir_lattice_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+/**
+ * @brief Initialization function for the floating-point FIR lattice filter.
+ * @param[in] *S points to an instance of the floating-point FIR lattice structure.
+ * @param[in] numStages  number of filter stages.
+ * @param[in] *pCoeffs points to the coefficient buffer.  The array is of length numStages.
+ * @param[in] *pState points to the state buffer.  The array is of length numStages.
+ * @return none.
+ */
+
+  void arm_fir_lattice_init_f32(
+  arm_fir_lattice_instance_f32 * S,
+  uint16_t numStages,
+  float32_t * pCoeffs,
+  float32_t * pState);
+
+  /**
+   * @brief Processing function for the floating-point FIR lattice filter.
+   * @param[in]  *S        points to an instance of the floating-point FIR lattice structure.
+   * @param[in]  *pSrc     points to the block of input data.
+   * @param[out] *pDst     points to the block of output data
+   * @param[in]  blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_fir_lattice_f32(
+  const arm_fir_lattice_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Instance structure for the Q15 IIR lattice filter.
+   */
+  typedef struct
+  {
+    uint16_t numStages;                         /**< number of stages in the filter. */
+    q15_t *pState;                              /**< points to the state variable array. The array is of length numStages+blockSize. */
+    q15_t *pkCoeffs;                            /**< points to the reflection coefficient array. The array is of length numStages. */
+    q15_t *pvCoeffs;                            /**< points to the ladder coefficient array. The array is of length numStages+1. */
+  } arm_iir_lattice_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 IIR lattice filter.
+   */
+  typedef struct
+  {
+    uint16_t numStages;                         /**< number of stages in the filter. */
+    q31_t *pState;                              /**< points to the state variable array. The array is of length numStages+blockSize. */
+    q31_t *pkCoeffs;                            /**< points to the reflection coefficient array. The array is of length numStages. */
+    q31_t *pvCoeffs;                            /**< points to the ladder coefficient array. The array is of length numStages+1. */
+  } arm_iir_lattice_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point IIR lattice filter.
+   */
+  typedef struct
+  {
+    uint16_t numStages;                         /**< number of stages in the filter. */
+    float32_t *pState;                          /**< points to the state variable array. The array is of length numStages+blockSize. */
+    float32_t *pkCoeffs;                        /**< points to the reflection coefficient array. The array is of length numStages. */
+    float32_t *pvCoeffs;                        /**< points to the ladder coefficient array. The array is of length numStages+1. */
+  } arm_iir_lattice_instance_f32;
+
+  /**
+   * @brief Processing function for the floating-point IIR lattice filter.
+   * @param[in] *S points to an instance of the floating-point IIR lattice structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_iir_lattice_f32(
+  const arm_iir_lattice_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Initialization function for the floating-point IIR lattice filter.
+   * @param[in] *S points to an instance of the floating-point IIR lattice structure.
+   * @param[in] numStages number of stages in the filter.
+   * @param[in] *pkCoeffs points to the reflection coefficient buffer.  The array is of length numStages.
+   * @param[in] *pvCoeffs points to the ladder coefficient buffer.  The array is of length numStages+1.
+   * @param[in] *pState points to the state buffer.  The array is of length numStages+blockSize-1.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_iir_lattice_init_f32(
+  arm_iir_lattice_instance_f32 * S,
+  uint16_t numStages,
+  float32_t * pkCoeffs,
+  float32_t * pvCoeffs,
+  float32_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q31 IIR lattice filter.
+   * @param[in] *S points to an instance of the Q31 IIR lattice structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_iir_lattice_q31(
+  const arm_iir_lattice_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Initialization function for the Q31 IIR lattice filter.
+   * @param[in] *S points to an instance of the Q31 IIR lattice structure.
+   * @param[in] numStages number of stages in the filter.
+   * @param[in] *pkCoeffs points to the reflection coefficient buffer.  The array is of length numStages.
+   * @param[in] *pvCoeffs points to the ladder coefficient buffer.  The array is of length numStages+1.
+   * @param[in] *pState points to the state buffer.  The array is of length numStages+blockSize.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_iir_lattice_init_q31(
+  arm_iir_lattice_instance_q31 * S,
+  uint16_t numStages,
+  q31_t * pkCoeffs,
+  q31_t * pvCoeffs,
+  q31_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q15 IIR lattice filter.
+   * @param[in] *S points to an instance of the Q15 IIR lattice structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_iir_lattice_q15(
+  const arm_iir_lattice_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the Q15 IIR lattice filter.
+ * @param[in] *S points to an instance of the fixed-point Q15 IIR lattice structure.
+ * @param[in] numStages  number of stages in the filter.
+ * @param[in] *pkCoeffs points to reflection coefficient buffer.  The array is of length numStages.
+ * @param[in] *pvCoeffs points to ladder coefficient buffer.  The array is of length numStages+1.
+ * @param[in] *pState points to state buffer.  The array is of length numStages+blockSize.
+ * @param[in] blockSize number of samples to process per call.
+ * @return none.
+ */
+
+  void arm_iir_lattice_init_q15(
+  arm_iir_lattice_instance_q15 * S,
+  uint16_t numStages,
+  q15_t * pkCoeffs,
+  q15_t * pvCoeffs,
+  q15_t * pState,
+  uint32_t blockSize);
+
+  /**
+   * @brief Instance structure for the floating-point LMS filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;    /**< number of coefficients in the filter. */
+    float32_t *pState;   /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    float32_t *pCoeffs;  /**< points to the coefficient array. The array is of length numTaps. */
+    float32_t mu;        /**< step size that controls filter coefficient updates. */
+  } arm_lms_instance_f32;
+
+  /**
+   * @brief Processing function for floating-point LMS filter.
+   * @param[in]  *S points to an instance of the floating-point LMS filter structure.
+   * @param[in]  *pSrc points to the block of input data.
+   * @param[in]  *pRef points to the block of reference data.
+   * @param[out] *pOut points to the block of output data.
+   * @param[out] *pErr points to the block of error data.
+   * @param[in]  blockSize number of samples to process.
+   * @return     none.
+   */
+
+  void arm_lms_f32(
+  const arm_lms_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pRef,
+  float32_t * pOut,
+  float32_t * pErr,
+  uint32_t blockSize);
+
+  /**
+   * @brief Initialization function for floating-point LMS filter.
+   * @param[in] *S points to an instance of the floating-point LMS filter structure.
+   * @param[in] numTaps  number of filter coefficients.
+   * @param[in] *pCoeffs points to the coefficient buffer.
+   * @param[in] *pState points to state buffer.
+   * @param[in] mu step size that controls filter coefficient updates.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_lms_init_f32(
+  arm_lms_instance_f32 * S,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  float32_t mu,
+  uint32_t blockSize);
+
+  /**
+   * @brief Instance structure for the Q15 LMS filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;    /**< number of coefficients in the filter. */
+    q15_t *pState;       /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q15_t *pCoeffs;      /**< points to the coefficient array. The array is of length numTaps. */
+    q15_t mu;            /**< step size that controls filter coefficient updates. */
+    uint32_t postShift;  /**< bit shift applied to coefficients. */
+  } arm_lms_instance_q15;
+
+
+  /**
+   * @brief Initialization function for the Q15 LMS filter.
+   * @param[in] *S points to an instance of the Q15 LMS filter structure.
+   * @param[in] numTaps  number of filter coefficients.
+   * @param[in] *pCoeffs points to the coefficient buffer.
+   * @param[in] *pState points to the state buffer.
+   * @param[in] mu step size that controls filter coefficient updates.
+   * @param[in] blockSize number of samples to process.
+   * @param[in] postShift bit shift applied to coefficients.
+   * @return    none.
+   */
+
+  void arm_lms_init_q15(
+  arm_lms_instance_q15 * S,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  q15_t mu,
+  uint32_t blockSize,
+  uint32_t postShift);
+
+  /**
+   * @brief Processing function for Q15 LMS filter.
+   * @param[in] *S points to an instance of the Q15 LMS filter structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[in] *pRef points to the block of reference data.
+   * @param[out] *pOut points to the block of output data.
+   * @param[out] *pErr points to the block of error data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_lms_q15(
+  const arm_lms_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pRef,
+  q15_t * pOut,
+  q15_t * pErr,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Instance structure for the Q31 LMS filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;    /**< number of coefficients in the filter. */
+    q31_t *pState;       /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q31_t *pCoeffs;      /**< points to the coefficient array. The array is of length numTaps. */
+    q31_t mu;            /**< step size that controls filter coefficient updates. */
+    uint32_t postShift;  /**< bit shift applied to coefficients. */
+
+  } arm_lms_instance_q31;
+
+  /**
+   * @brief Processing function for Q31 LMS filter.
+   * @param[in]  *S points to an instance of the Q15 LMS filter structure.
+   * @param[in]  *pSrc points to the block of input data.
+   * @param[in]  *pRef points to the block of reference data.
+   * @param[out] *pOut points to the block of output data.
+   * @param[out] *pErr points to the block of error data.
+   * @param[in]  blockSize number of samples to process.
+   * @return     none.
+   */
+
+  void arm_lms_q31(
+  const arm_lms_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pRef,
+  q31_t * pOut,
+  q31_t * pErr,
+  uint32_t blockSize);
+
+  /**
+   * @brief Initialization function for Q31 LMS filter.
+   * @param[in] *S points to an instance of the Q31 LMS filter structure.
+   * @param[in] numTaps  number of filter coefficients.
+   * @param[in] *pCoeffs points to coefficient buffer.
+   * @param[in] *pState points to state buffer.
+   * @param[in] mu step size that controls filter coefficient updates.
+   * @param[in] blockSize number of samples to process.
+   * @param[in] postShift bit shift applied to coefficients.
+   * @return none.
+   */
+
+  void arm_lms_init_q31(
+  arm_lms_instance_q31 * S,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  q31_t mu,
+  uint32_t blockSize,
+  uint32_t postShift);
+
+  /**
+   * @brief Instance structure for the floating-point normalized LMS filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;     /**< number of coefficients in the filter. */
+    float32_t *pState;    /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    float32_t *pCoeffs;   /**< points to the coefficient array. The array is of length numTaps. */
+    float32_t mu;        /**< step size that control filter coefficient updates. */
+    float32_t energy;    /**< saves previous frame energy. */
+    float32_t x0;        /**< saves previous input sample. */
+  } arm_lms_norm_instance_f32;
+
+  /**
+   * @brief Processing function for floating-point normalized LMS filter.
+   * @param[in] *S points to an instance of the floating-point normalized LMS filter structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[in] *pRef points to the block of reference data.
+   * @param[out] *pOut points to the block of output data.
+   * @param[out] *pErr points to the block of error data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_lms_norm_f32(
+  arm_lms_norm_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pRef,
+  float32_t * pOut,
+  float32_t * pErr,
+  uint32_t blockSize);
+
+  /**
+   * @brief Initialization function for floating-point normalized LMS filter.
+   * @param[in] *S points to an instance of the floating-point LMS filter structure.
+   * @param[in] numTaps  number of filter coefficients.
+   * @param[in] *pCoeffs points to coefficient buffer.
+   * @param[in] *pState points to state buffer.
+   * @param[in] mu step size that controls filter coefficient updates.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_lms_norm_init_f32(
+  arm_lms_norm_instance_f32 * S,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  float32_t mu,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Instance structure for the Q31 normalized LMS filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;     /**< number of coefficients in the filter. */
+    q31_t *pState;        /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q31_t *pCoeffs;       /**< points to the coefficient array. The array is of length numTaps. */
+    q31_t mu;             /**< step size that controls filter coefficient updates. */
+    uint8_t postShift;    /**< bit shift applied to coefficients. */
+    q31_t *recipTable;    /**< points to the reciprocal initial value table. */
+    q31_t energy;         /**< saves previous frame energy. */
+    q31_t x0;             /**< saves previous input sample. */
+  } arm_lms_norm_instance_q31;
+
+  /**
+   * @brief Processing function for Q31 normalized LMS filter.
+   * @param[in] *S points to an instance of the Q31 normalized LMS filter structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[in] *pRef points to the block of reference data.
+   * @param[out] *pOut points to the block of output data.
+   * @param[out] *pErr points to the block of error data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_lms_norm_q31(
+  arm_lms_norm_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pRef,
+  q31_t * pOut,
+  q31_t * pErr,
+  uint32_t blockSize);
+
+  /**
+   * @brief Initialization function for Q31 normalized LMS filter.
+   * @param[in] *S points to an instance of the Q31 normalized LMS filter structure.
+   * @param[in] numTaps  number of filter coefficients.
+   * @param[in] *pCoeffs points to coefficient buffer.
+   * @param[in] *pState points to state buffer.
+   * @param[in] mu step size that controls filter coefficient updates.
+   * @param[in] blockSize number of samples to process.
+   * @param[in] postShift bit shift applied to coefficients.
+   * @return none.
+   */
+
+  void arm_lms_norm_init_q31(
+  arm_lms_norm_instance_q31 * S,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  q31_t mu,
+  uint32_t blockSize,
+  uint8_t postShift);
+
+  /**
+   * @brief Instance structure for the Q15 normalized LMS filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;    /**< Number of coefficients in the filter. */
+    q15_t *pState;        /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q15_t *pCoeffs;       /**< points to the coefficient array. The array is of length numTaps. */
+    q15_t mu;            /**< step size that controls filter coefficient updates. */
+    uint8_t postShift;   /**< bit shift applied to coefficients. */
+    q15_t *recipTable;   /**< Points to the reciprocal initial value table. */
+    q15_t energy;        /**< saves previous frame energy. */
+    q15_t x0;            /**< saves previous input sample. */
+  } arm_lms_norm_instance_q15;
+
+  /**
+   * @brief Processing function for Q15 normalized LMS filter.
+   * @param[in] *S points to an instance of the Q15 normalized LMS filter structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[in] *pRef points to the block of reference data.
+   * @param[out] *pOut points to the block of output data.
+   * @param[out] *pErr points to the block of error data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_lms_norm_q15(
+  arm_lms_norm_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pRef,
+  q15_t * pOut,
+  q15_t * pErr,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Initialization function for Q15 normalized LMS filter.
+   * @param[in] *S points to an instance of the Q15 normalized LMS filter structure.
+   * @param[in] numTaps  number of filter coefficients.
+   * @param[in] *pCoeffs points to coefficient buffer.
+   * @param[in] *pState points to state buffer.
+   * @param[in] mu step size that controls filter coefficient updates.
+   * @param[in] blockSize number of samples to process.
+   * @param[in] postShift bit shift applied to coefficients.
+   * @return none.
+   */
+
+  void arm_lms_norm_init_q15(
+  arm_lms_norm_instance_q15 * S,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  q15_t mu,
+  uint32_t blockSize,
+  uint8_t postShift);
+
+  /**
+   * @brief Correlation of floating-point sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @return none.
+   */
+
+  void arm_correlate_f32(
+  float32_t * pSrcA,
+  uint32_t srcALen,
+  float32_t * pSrcB,
+  uint32_t srcBLen,
+  float32_t * pDst);
+
+
+   /**
+   * @brief Correlation of Q15 sequences
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @param[in]  *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @return none.
+   */
+  void arm_correlate_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  q15_t * pScratch);
+
+
+  /**
+   * @brief Correlation of Q15 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @return none.
+   */
+
+  void arm_correlate_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst);
+
+  /**
+   * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @return none.
+   */
+
+  void arm_correlate_fast_q15(
+			       q15_t * pSrcA,
+			      uint32_t srcALen,
+			       q15_t * pSrcB,
+			      uint32_t srcBLen,
+			      q15_t * pDst);
+
+
+
+  /**
+   * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @param[in]  *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @return none.
+   */
+
+  void arm_correlate_fast_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  q15_t * pScratch);
+
+  /**
+   * @brief Correlation of Q31 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @return none.
+   */
+
+  void arm_correlate_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst);
+
+  /**
+   * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @return none.
+   */
+
+  void arm_correlate_fast_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst);
+
+
+
+ /**
+   * @brief Correlation of Q7 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @param[in]  *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]  *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+   * @return none.
+   */
+
+  void arm_correlate_opt_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+  /**
+   * @brief Correlation of Q7 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @return none.
+   */
+
+  void arm_correlate_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst);
+
+
+  /**
+   * @brief Instance structure for the floating-point sparse FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;             /**< number of coefficients in the filter. */
+    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
+    float32_t *pState;            /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+    float32_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/
+    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
+    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
+  } arm_fir_sparse_instance_f32;
+
+  /**
+   * @brief Instance structure for the Q31 sparse FIR filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;             /**< number of coefficients in the filter. */
+    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
+    q31_t *pState;                /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+    q31_t *pCoeffs;               /**< points to the coefficient array. The array is of length numTaps.*/
+    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
+    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
+  } arm_fir_sparse_instance_q31;
+
+  /**
+   * @brief Instance structure for the Q15 sparse FIR filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;             /**< number of coefficients in the filter. */
+    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
+    q15_t *pState;                /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+    q15_t *pCoeffs;               /**< points to the coefficient array. The array is of length numTaps.*/
+    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
+    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
+  } arm_fir_sparse_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q7 sparse FIR filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;             /**< number of coefficients in the filter. */
+    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
+    q7_t *pState;                 /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+    q7_t *pCoeffs;                /**< points to the coefficient array. The array is of length numTaps.*/
+    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
+    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
+  } arm_fir_sparse_instance_q7;
+
+  /**
+   * @brief Processing function for the floating-point sparse FIR filter.
+   * @param[in]  *S          points to an instance of the floating-point sparse FIR structure.
+   * @param[in]  *pSrc       points to the block of input data.
+   * @param[out] *pDst       points to the block of output data
+   * @param[in]  *pScratchIn points to a temporary buffer of size blockSize.
+   * @param[in]  blockSize   number of input samples to process per call.
+   * @return none.
+   */
+
+  void arm_fir_sparse_f32(
+  arm_fir_sparse_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  float32_t * pScratchIn,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the floating-point sparse FIR filter.
+   * @param[in,out] *S         points to an instance of the floating-point sparse FIR structure.
+   * @param[in]     numTaps    number of nonzero coefficients in the filter.
+   * @param[in]     *pCoeffs   points to the array of filter coefficients.
+   * @param[in]     *pState    points to the state buffer.
+   * @param[in]     *pTapDelay points to the array of offset times.
+   * @param[in]     maxDelay   maximum offset time supported.
+   * @param[in]     blockSize  number of samples that will be processed per block.
+   * @return none
+   */
+
+  void arm_fir_sparse_init_f32(
+  arm_fir_sparse_instance_f32 * S,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  int32_t * pTapDelay,
+  uint16_t maxDelay,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q31 sparse FIR filter.
+   * @param[in]  *S          points to an instance of the Q31 sparse FIR structure.
+   * @param[in]  *pSrc       points to the block of input data.
+   * @param[out] *pDst       points to the block of output data
+   * @param[in]  *pScratchIn points to a temporary buffer of size blockSize.
+   * @param[in]  blockSize   number of input samples to process per call.
+   * @return none.
+   */
+
+  void arm_fir_sparse_q31(
+  arm_fir_sparse_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  q31_t * pScratchIn,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the Q31 sparse FIR filter.
+   * @param[in,out] *S         points to an instance of the Q31 sparse FIR structure.
+   * @param[in]     numTaps    number of nonzero coefficients in the filter.
+   * @param[in]     *pCoeffs   points to the array of filter coefficients.
+   * @param[in]     *pState    points to the state buffer.
+   * @param[in]     *pTapDelay points to the array of offset times.
+   * @param[in]     maxDelay   maximum offset time supported.
+   * @param[in]     blockSize  number of samples that will be processed per block.
+   * @return none
+   */
+
+  void arm_fir_sparse_init_q31(
+  arm_fir_sparse_instance_q31 * S,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  int32_t * pTapDelay,
+  uint16_t maxDelay,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q15 sparse FIR filter.
+   * @param[in]  *S           points to an instance of the Q15 sparse FIR structure.
+   * @param[in]  *pSrc        points to the block of input data.
+   * @param[out] *pDst        points to the block of output data
+   * @param[in]  *pScratchIn  points to a temporary buffer of size blockSize.
+   * @param[in]  *pScratchOut points to a temporary buffer of size blockSize.
+   * @param[in]  blockSize    number of input samples to process per call.
+   * @return none.
+   */
+
+  void arm_fir_sparse_q15(
+  arm_fir_sparse_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  q15_t * pScratchIn,
+  q31_t * pScratchOut,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q15 sparse FIR filter.
+   * @param[in,out] *S         points to an instance of the Q15 sparse FIR structure.
+   * @param[in]     numTaps    number of nonzero coefficients in the filter.
+   * @param[in]     *pCoeffs   points to the array of filter coefficients.
+   * @param[in]     *pState    points to the state buffer.
+   * @param[in]     *pTapDelay points to the array of offset times.
+   * @param[in]     maxDelay   maximum offset time supported.
+   * @param[in]     blockSize  number of samples that will be processed per block.
+   * @return none
+   */
+
+  void arm_fir_sparse_init_q15(
+  arm_fir_sparse_instance_q15 * S,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  int32_t * pTapDelay,
+  uint16_t maxDelay,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q7 sparse FIR filter.
+   * @param[in]  *S           points to an instance of the Q7 sparse FIR structure.
+   * @param[in]  *pSrc        points to the block of input data.
+   * @param[out] *pDst        points to the block of output data
+   * @param[in]  *pScratchIn  points to a temporary buffer of size blockSize.
+   * @param[in]  *pScratchOut points to a temporary buffer of size blockSize.
+   * @param[in]  blockSize    number of input samples to process per call.
+   * @return none.
+   */
+
+  void arm_fir_sparse_q7(
+  arm_fir_sparse_instance_q7 * S,
+  q7_t * pSrc,
+  q7_t * pDst,
+  q7_t * pScratchIn,
+  q31_t * pScratchOut,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the Q7 sparse FIR filter.
+   * @param[in,out] *S         points to an instance of the Q7 sparse FIR structure.
+   * @param[in]     numTaps    number of nonzero coefficients in the filter.
+   * @param[in]     *pCoeffs   points to the array of filter coefficients.
+   * @param[in]     *pState    points to the state buffer.
+   * @param[in]     *pTapDelay points to the array of offset times.
+   * @param[in]     maxDelay   maximum offset time supported.
+   * @param[in]     blockSize  number of samples that will be processed per block.
+   * @return none
+   */
+
+  void arm_fir_sparse_init_q7(
+  arm_fir_sparse_instance_q7 * S,
+  uint16_t numTaps,
+  q7_t * pCoeffs,
+  q7_t * pState,
+  int32_t * pTapDelay,
+  uint16_t maxDelay,
+  uint32_t blockSize);
+
+
+  /*
+   * @brief  Floating-point sin_cos function.
+   * @param[in]  theta    input value in degrees
+   * @param[out] *pSinVal points to the processed sine output.
+   * @param[out] *pCosVal points to the processed cos output.
+   * @return none.
+   */
+
+  void arm_sin_cos_f32(
+  float32_t theta,
+  float32_t * pSinVal,
+  float32_t * pCcosVal);
+
+  /*
+   * @brief  Q31 sin_cos function.
+   * @param[in]  theta    scaled input value in degrees
+   * @param[out] *pSinVal points to the processed sine output.
+   * @param[out] *pCosVal points to the processed cosine output.
+   * @return none.
+   */
+
+  void arm_sin_cos_q31(
+  q31_t theta,
+  q31_t * pSinVal,
+  q31_t * pCosVal);
+
+
+  /**
+   * @brief  Floating-point complex conjugate.
+   * @param[in]  *pSrc points to the input vector
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_conj_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q31 complex conjugate.
+   * @param[in]  *pSrc points to the input vector
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_conj_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q15 complex conjugate.
+   * @param[in]  *pSrc points to the input vector
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_conj_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t numSamples);
+
+
+
+  /**
+   * @brief  Floating-point complex magnitude squared
+   * @param[in]  *pSrc points to the complex input vector
+   * @param[out]  *pDst points to the real output vector
+   * @param[in]  numSamples number of complex samples in the input vector
+   * @return none.
+   */
+
+  void arm_cmplx_mag_squared_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q31 complex magnitude squared
+   * @param[in]  *pSrc points to the complex input vector
+   * @param[out]  *pDst points to the real output vector
+   * @param[in]  numSamples number of complex samples in the input vector
+   * @return none.
+   */
+
+  void arm_cmplx_mag_squared_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q15 complex magnitude squared
+   * @param[in]  *pSrc points to the complex input vector
+   * @param[out]  *pDst points to the real output vector
+   * @param[in]  numSamples number of complex samples in the input vector
+   * @return none.
+   */
+
+  void arm_cmplx_mag_squared_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t numSamples);
+
+
+ /**
+   * @ingroup groupController
+   */
+
+  /**
+   * @defgroup PID PID Motor Control
+   *
+   * A Proportional Integral Derivative (PID) controller is a generic feedback control
+   * loop mechanism widely used in industrial control systems.
+   * A PID controller is the most commonly used type of feedback controller.
+   *
+   * This set of functions implements (PID) controllers
+   * for Q15, Q31, and floating-point data types.  The functions operate on a single sample
+   * of data and each call to the function returns a single processed value.
+   * <code>S</code> points to an instance of the PID control data structure.  <code>in</code>
+   * is the input sample value. The functions return the output value.
+   *
+   * \par Algorithm:
+   * <pre>
+   *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
+   *    A0 = Kp + Ki + Kd
+   *    A1 = (-Kp ) - (2 * Kd )
+   *    A2 = Kd  </pre>
+   *
+   * \par
+   * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant
+   *
+   * \par
+   * \image html PID.gif "Proportional Integral Derivative Controller"
+   *
+   * \par
+   * The PID controller calculates an "error" value as the difference between
+   * the measured output and the reference input.
+   * The controller attempts to minimize the error by adjusting the process control inputs.
+   * The proportional value determines the reaction to the current error,
+   * the integral value determines the reaction based on the sum of recent errors,
+   * and the derivative value determines the reaction based on the rate at which the error has been changing.
+   *
+   * \par Instance Structure
+   * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure.
+   * A separate instance structure must be defined for each PID Controller.
+   * There are separate instance structure declarations for each of the 3 supported data types.
+   *
+   * \par Reset Functions
+   * There is also an associated reset function for each data type which clears the state array.
+   *
+   * \par Initialization Functions
+   * There is also an associated initialization function for each data type.
+   * The initialization function performs the following operations:
+   * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains.
+   * - Zeros out the values in the state buffer.
+   *
+   * \par
+   * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function.
+   *
+   * \par Fixed-Point Behavior
+   * Care must be taken when using the fixed-point versions of the PID Controller functions.
+   * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.
+   * Refer to the function specific documentation below for usage guidelines.
+   */
+
+  /**
+   * @addtogroup PID
+   * @{
+   */
+
+  /**
+   * @brief  Process function for the floating-point PID Control.
+   * @param[in,out] *S is an instance of the floating-point PID Control structure
+   * @param[in] in input sample to process
+   * @return out processed output sample.
+   */
+
+
+  static __INLINE float32_t arm_pid_f32(
+  arm_pid_instance_f32 * S,
+  float32_t in)
+  {
+    float32_t out;
+
+    /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]  */
+    out = (S->A0 * in) +
+      (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]);
+
+    /* Update state */
+    S->state[1] = S->state[0];
+    S->state[0] = in;
+    S->state[2] = out;
+
+    /* return to application */
+    return (out);
+
+  }
+
+  /**
+   * @brief  Process function for the Q31 PID Control.
+   * @param[in,out] *S points to an instance of the Q31 PID Control structure
+   * @param[in] in input sample to process
+   * @return out processed output sample.
+   *
+   * <b>Scaling and Overflow Behavior:</b>
+   * \par
+   * The function is implemented using an internal 64-bit accumulator.
+   * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.
+   * Thus, if the accumulator result overflows it wraps around rather than clip.
+   * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions.
+   * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format.
+   */
+
+  static __INLINE q31_t arm_pid_q31(
+  arm_pid_instance_q31 * S,
+  q31_t in)
+  {
+    q63_t acc;
+    q31_t out;
+
+    /* acc = A0 * x[n]  */
+    acc = (q63_t) S->A0 * in;
+
+    /* acc += A1 * x[n-1] */
+    acc += (q63_t) S->A1 * S->state[0];
+
+    /* acc += A2 * x[n-2]  */
+    acc += (q63_t) S->A2 * S->state[1];
+
+    /* convert output to 1.31 format to add y[n-1] */
+    out = (q31_t) (acc >> 31u);
+
+    /* out += y[n-1] */
+    out += S->state[2];
+
+    /* Update state */
+    S->state[1] = S->state[0];
+    S->state[0] = in;
+    S->state[2] = out;
+
+    /* return to application */
+    return (out);
+
+  }
+
+  /**
+   * @brief  Process function for the Q15 PID Control.
+   * @param[in,out] *S points to an instance of the Q15 PID Control structure
+   * @param[in] in input sample to process
+   * @return out processed output sample.
+   *
+   * <b>Scaling and Overflow Behavior:</b>
+   * \par
+   * The function is implemented using a 64-bit internal accumulator.
+   * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result.
+   * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.
+   * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.
+   * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.
+   * Lastly, the accumulator is saturated to yield a result in 1.15 format.
+   */
+
+  static __INLINE q15_t arm_pid_q15(
+  arm_pid_instance_q15 * S,
+  q15_t in)
+  {
+    q63_t acc;
+    q15_t out;
+
+#ifndef ARM_MATH_CM0_FAMILY
+    __SIMD32_TYPE *vstate;
+
+    /* Implementation of PID controller */
+
+    /* acc = A0 * x[n]  */
+    acc = (q31_t) __SMUAD(S->A0, in);
+
+    /* acc += A1 * x[n-1] + A2 * x[n-2]  */
+    vstate = __SIMD32_CONST(S->state);
+    acc = __SMLALD(S->A1, (q31_t) *vstate, acc);
+
+#else
+    /* acc = A0 * x[n]  */
+    acc = ((q31_t) S->A0) * in;
+
+    /* acc += A1 * x[n-1] + A2 * x[n-2]  */
+    acc += (q31_t) S->A1 * S->state[0];
+    acc += (q31_t) S->A2 * S->state[1];
+
+#endif
+
+    /* acc += y[n-1] */
+    acc += (q31_t) S->state[2] << 15;
+
+    /* saturate the output */
+    out = (q15_t) (__SSAT((acc >> 15), 16));
+
+    /* Update state */
+    S->state[1] = S->state[0];
+    S->state[0] = in;
+    S->state[2] = out;
+
+    /* return to application */
+    return (out);
+
+  }
+
+  /**
+   * @} end of PID group
+   */
+
+
+  /**
+   * @brief Floating-point matrix inverse.
+   * @param[in]  *src points to the instance of the input floating-point matrix structure.
+   * @param[out] *dst points to the instance of the output floating-point matrix structure.
+   * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
+   * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.
+   */
+
+  arm_status arm_mat_inverse_f32(
+  const arm_matrix_instance_f32 * src,
+  arm_matrix_instance_f32 * dst);
+
+
+  /**
+   * @brief Floating-point matrix inverse.
+   * @param[in]  *src points to the instance of the input floating-point matrix structure.
+   * @param[out] *dst points to the instance of the output floating-point matrix structure.
+   * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
+   * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.
+   */
+
+  arm_status arm_mat_inverse_f64(
+  const arm_matrix_instance_f64 * src,
+  arm_matrix_instance_f64 * dst);
+
+
+
+  /**
+   * @ingroup groupController
+   */
+
+
+  /**
+   * @defgroup clarke Vector Clarke Transform
+   * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector.
+   * Generally the Clarke transform uses three-phase currents <code>Ia, Ib and Ic</code> to calculate currents
+   * in the two-phase orthogonal stator axis <code>Ialpha</code> and <code>Ibeta</code>.
+   * When <code>Ialpha</code> is superposed with <code>Ia</code> as shown in the figure below
+   * \image html clarke.gif Stator current space vector and its components in (a,b).
+   * and <code>Ia + Ib + Ic = 0</code>, in this condition <code>Ialpha</code> and <code>Ibeta</code>
+   * can be calculated using only <code>Ia</code> and <code>Ib</code>.
+   *
+   * The function operates on a single sample of data and each call to the function returns the processed output.
+   * The library provides separate functions for Q31 and floating-point data types.
+   * \par Algorithm
+   * \image html clarkeFormula.gif
+   * where <code>Ia</code> and <code>Ib</code> are the instantaneous stator phases and
+   * <code>pIalpha</code> and <code>pIbeta</code> are the two coordinates of time invariant vector.
+   * \par Fixed-Point Behavior
+   * Care must be taken when using the Q31 version of the Clarke transform.
+   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+   * Refer to the function specific documentation below for usage guidelines.
+   */
+
+  /**
+   * @addtogroup clarke
+   * @{
+   */
+
+  /**
+   *
+   * @brief  Floating-point Clarke transform
+   * @param[in]       Ia       input three-phase coordinate <code>a</code>
+   * @param[in]       Ib       input three-phase coordinate <code>b</code>
+   * @param[out]      *pIalpha points to output two-phase orthogonal vector axis alpha
+   * @param[out]      *pIbeta  points to output two-phase orthogonal vector axis beta
+   * @return none.
+   */
+
+  static __INLINE void arm_clarke_f32(
+  float32_t Ia,
+  float32_t Ib,
+  float32_t * pIalpha,
+  float32_t * pIbeta)
+  {
+    /* Calculate pIalpha using the equation, pIalpha = Ia */
+    *pIalpha = Ia;
+
+    /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */
+    *pIbeta =
+      ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib);
+
+  }
+
+  /**
+   * @brief  Clarke transform for Q31 version
+   * @param[in]       Ia       input three-phase coordinate <code>a</code>
+   * @param[in]       Ib       input three-phase coordinate <code>b</code>
+   * @param[out]      *pIalpha points to output two-phase orthogonal vector axis alpha
+   * @param[out]      *pIbeta  points to output two-phase orthogonal vector axis beta
+   * @return none.
+   *
+   * <b>Scaling and Overflow Behavior:</b>
+   * \par
+   * The function is implemented using an internal 32-bit accumulator.
+   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+   * There is saturation on the addition, hence there is no risk of overflow.
+   */
+
+  static __INLINE void arm_clarke_q31(
+  q31_t Ia,
+  q31_t Ib,
+  q31_t * pIalpha,
+  q31_t * pIbeta)
+  {
+    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
+
+    /* Calculating pIalpha from Ia by equation pIalpha = Ia */
+    *pIalpha = Ia;
+
+    /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */
+    product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30);
+
+    /* Intermediate product is calculated by (2/sqrt(3) * Ib) */
+    product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30);
+
+    /* pIbeta is calculated by adding the intermediate products */
+    *pIbeta = __QADD(product1, product2);
+  }
+
+  /**
+   * @} end of clarke group
+   */
+
+  /**
+   * @brief  Converts the elements of the Q7 vector to Q31 vector.
+   * @param[in]  *pSrc     input pointer
+   * @param[out]  *pDst    output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_q7_to_q31(
+  q7_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+
+
+  /**
+   * @ingroup groupController
+   */
+
+  /**
+   * @defgroup inv_clarke Vector Inverse Clarke Transform
+   * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases.
+   *
+   * The function operates on a single sample of data and each call to the function returns the processed output.
+   * The library provides separate functions for Q31 and floating-point data types.
+   * \par Algorithm
+   * \image html clarkeInvFormula.gif
+   * where <code>pIa</code> and <code>pIb</code> are the instantaneous stator phases and
+   * <code>Ialpha</code> and <code>Ibeta</code> are the two coordinates of time invariant vector.
+   * \par Fixed-Point Behavior
+   * Care must be taken when using the Q31 version of the Clarke transform.
+   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+   * Refer to the function specific documentation below for usage guidelines.
+   */
+
+  /**
+   * @addtogroup inv_clarke
+   * @{
+   */
+
+   /**
+   * @brief  Floating-point Inverse Clarke transform
+   * @param[in]       Ialpha  input two-phase orthogonal vector axis alpha
+   * @param[in]       Ibeta   input two-phase orthogonal vector axis beta
+   * @param[out]      *pIa    points to output three-phase coordinate <code>a</code>
+   * @param[out]      *pIb    points to output three-phase coordinate <code>b</code>
+   * @return none.
+   */
+
+
+  static __INLINE void arm_inv_clarke_f32(
+  float32_t Ialpha,
+  float32_t Ibeta,
+  float32_t * pIa,
+  float32_t * pIb)
+  {
+    /* Calculating pIa from Ialpha by equation pIa = Ialpha */
+    *pIa = Ialpha;
+
+    /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */
+    *pIb = -0.5 * Ialpha + (float32_t) 0.8660254039 *Ibeta;
+
+  }
+
+  /**
+   * @brief  Inverse Clarke transform for Q31 version
+   * @param[in]       Ialpha  input two-phase orthogonal vector axis alpha
+   * @param[in]       Ibeta   input two-phase orthogonal vector axis beta
+   * @param[out]      *pIa    points to output three-phase coordinate <code>a</code>
+   * @param[out]      *pIb    points to output three-phase coordinate <code>b</code>
+   * @return none.
+   *
+   * <b>Scaling and Overflow Behavior:</b>
+   * \par
+   * The function is implemented using an internal 32-bit accumulator.
+   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+   * There is saturation on the subtraction, hence there is no risk of overflow.
+   */
+
+  static __INLINE void arm_inv_clarke_q31(
+  q31_t Ialpha,
+  q31_t Ibeta,
+  q31_t * pIa,
+  q31_t * pIb)
+  {
+    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
+
+    /* Calculating pIa from Ialpha by equation pIa = Ialpha */
+    *pIa = Ialpha;
+
+    /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */
+    product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31);
+
+    /* Intermediate product is calculated by (1/sqrt(3) * pIb) */
+    product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31);
+
+    /* pIb is calculated by subtracting the products */
+    *pIb = __QSUB(product2, product1);
+
+  }
+
+  /**
+   * @} end of inv_clarke group
+   */
+
+  /**
+   * @brief  Converts the elements of the Q7 vector to Q15 vector.
+   * @param[in]  *pSrc     input pointer
+   * @param[out] *pDst     output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_q7_to_q15(
+  q7_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+
+  /**
+   * @ingroup groupController
+   */
+
+  /**
+   * @defgroup park Vector Park Transform
+   *
+   * Forward Park transform converts the input two-coordinate vector to flux and torque components.
+   * The Park transform can be used to realize the transformation of the <code>Ialpha</code> and the <code>Ibeta</code> currents
+   * from the stationary to the moving reference frame and control the spatial relationship between
+   * the stator vector current and rotor flux vector.
+   * If we consider the d axis aligned with the rotor flux, the diagram below shows the
+   * current vector and the relationship from the two reference frames:
+   * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame"
+   *
+   * The function operates on a single sample of data and each call to the function returns the processed output.
+   * The library provides separate functions for Q31 and floating-point data types.
+   * \par Algorithm
+   * \image html parkFormula.gif
+   * where <code>Ialpha</code> and <code>Ibeta</code> are the stator vector components,
+   * <code>pId</code> and <code>pIq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the
+   * cosine and sine values of theta (rotor flux position).
+   * \par Fixed-Point Behavior
+   * Care must be taken when using the Q31 version of the Park transform.
+   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+   * Refer to the function specific documentation below for usage guidelines.
+   */
+
+  /**
+   * @addtogroup park
+   * @{
+   */
+
+  /**
+   * @brief Floating-point Park transform
+   * @param[in]       Ialpha input two-phase vector coordinate alpha
+   * @param[in]       Ibeta  input two-phase vector coordinate beta
+   * @param[out]      *pId   points to output	rotor reference frame d
+   * @param[out]      *pIq   points to output	rotor reference frame q
+   * @param[in]       sinVal sine value of rotation angle theta
+   * @param[in]       cosVal cosine value of rotation angle theta
+   * @return none.
+   *
+   * The function implements the forward Park transform.
+   *
+   */
+
+  static __INLINE void arm_park_f32(
+  float32_t Ialpha,
+  float32_t Ibeta,
+  float32_t * pId,
+  float32_t * pIq,
+  float32_t sinVal,
+  float32_t cosVal)
+  {
+    /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */
+    *pId = Ialpha * cosVal + Ibeta * sinVal;
+
+    /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */
+    *pIq = -Ialpha * sinVal + Ibeta * cosVal;
+
+  }
+
+  /**
+   * @brief  Park transform for Q31 version
+   * @param[in]       Ialpha input two-phase vector coordinate alpha
+   * @param[in]       Ibeta  input two-phase vector coordinate beta
+   * @param[out]      *pId   points to output rotor reference frame d
+   * @param[out]      *pIq   points to output rotor reference frame q
+   * @param[in]       sinVal sine value of rotation angle theta
+   * @param[in]       cosVal cosine value of rotation angle theta
+   * @return none.
+   *
+   * <b>Scaling and Overflow Behavior:</b>
+   * \par
+   * The function is implemented using an internal 32-bit accumulator.
+   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+   * There is saturation on the addition and subtraction, hence there is no risk of overflow.
+   */
+
+
+  static __INLINE void arm_park_q31(
+  q31_t Ialpha,
+  q31_t Ibeta,
+  q31_t * pId,
+  q31_t * pIq,
+  q31_t sinVal,
+  q31_t cosVal)
+  {
+    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
+    q31_t product3, product4;                    /* Temporary variables used to store intermediate results */
+
+    /* Intermediate product is calculated by (Ialpha * cosVal) */
+    product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31);
+
+    /* Intermediate product is calculated by (Ibeta * sinVal) */
+    product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31);
+
+
+    /* Intermediate product is calculated by (Ialpha * sinVal) */
+    product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31);
+
+    /* Intermediate product is calculated by (Ibeta * cosVal) */
+    product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31);
+
+    /* Calculate pId by adding the two intermediate products 1 and 2 */
+    *pId = __QADD(product1, product2);
+
+    /* Calculate pIq by subtracting the two intermediate products 3 from 4 */
+    *pIq = __QSUB(product4, product3);
+  }
+
+  /**
+   * @} end of park group
+   */
+
+  /**
+   * @brief  Converts the elements of the Q7 vector to floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[out]  *pDst is output pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @return none.
+   */
+  void arm_q7_to_float(
+  q7_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @ingroup groupController
+   */
+
+  /**
+   * @defgroup inv_park Vector Inverse Park transform
+   * Inverse Park transform converts the input flux and torque components to two-coordinate vector.
+   *
+   * The function operates on a single sample of data and each call to the function returns the processed output.
+   * The library provides separate functions for Q31 and floating-point data types.
+   * \par Algorithm
+   * \image html parkInvFormula.gif
+   * where <code>pIalpha</code> and <code>pIbeta</code> are the stator vector components,
+   * <code>Id</code> and <code>Iq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the
+   * cosine and sine values of theta (rotor flux position).
+   * \par Fixed-Point Behavior
+   * Care must be taken when using the Q31 version of the Park transform.
+   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+   * Refer to the function specific documentation below for usage guidelines.
+   */
+
+  /**
+   * @addtogroup inv_park
+   * @{
+   */
+
+   /**
+   * @brief  Floating-point Inverse Park transform
+   * @param[in]       Id        input coordinate of rotor reference frame d
+   * @param[in]       Iq        input coordinate of rotor reference frame q
+   * @param[out]      *pIalpha  points to output two-phase orthogonal vector axis alpha
+   * @param[out]      *pIbeta   points to output two-phase orthogonal vector axis beta
+   * @param[in]       sinVal    sine value of rotation angle theta
+   * @param[in]       cosVal    cosine value of rotation angle theta
+   * @return none.
+   */
+
+  static __INLINE void arm_inv_park_f32(
+  float32_t Id,
+  float32_t Iq,
+  float32_t * pIalpha,
+  float32_t * pIbeta,
+  float32_t sinVal,
+  float32_t cosVal)
+  {
+    /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */
+    *pIalpha = Id * cosVal - Iq * sinVal;
+
+    /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */
+    *pIbeta = Id * sinVal + Iq * cosVal;
+
+  }
+
+
+  /**
+   * @brief  Inverse Park transform for	Q31 version
+   * @param[in]       Id        input coordinate of rotor reference frame d
+   * @param[in]       Iq        input coordinate of rotor reference frame q
+   * @param[out]      *pIalpha  points to output two-phase orthogonal vector axis alpha
+   * @param[out]      *pIbeta   points to output two-phase orthogonal vector axis beta
+   * @param[in]       sinVal    sine value of rotation angle theta
+   * @param[in]       cosVal    cosine value of rotation angle theta
+   * @return none.
+   *
+   * <b>Scaling and Overflow Behavior:</b>
+   * \par
+   * The function is implemented using an internal 32-bit accumulator.
+   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+   * There is saturation on the addition, hence there is no risk of overflow.
+   */
+
+
+  static __INLINE void arm_inv_park_q31(
+  q31_t Id,
+  q31_t Iq,
+  q31_t * pIalpha,
+  q31_t * pIbeta,
+  q31_t sinVal,
+  q31_t cosVal)
+  {
+    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
+    q31_t product3, product4;                    /* Temporary variables used to store intermediate results */
+
+    /* Intermediate product is calculated by (Id * cosVal) */
+    product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31);
+
+    /* Intermediate product is calculated by (Iq * sinVal) */
+    product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31);
+
+
+    /* Intermediate product is calculated by (Id * sinVal) */
+    product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31);
+
+    /* Intermediate product is calculated by (Iq * cosVal) */
+    product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31);
+
+    /* Calculate pIalpha by using the two intermediate products 1 and 2 */
+    *pIalpha = __QSUB(product1, product2);
+
+    /* Calculate pIbeta by using the two intermediate products 3 and 4 */
+    *pIbeta = __QADD(product4, product3);
+
+  }
+
+  /**
+   * @} end of Inverse park group
+   */
+
+
+  /**
+   * @brief  Converts the elements of the Q31 vector to floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[out]  *pDst is output pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @return none.
+   */
+  void arm_q31_to_float(
+  q31_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @ingroup groupInterpolation
+   */
+
+  /**
+   * @defgroup LinearInterpolate Linear Interpolation
+   *
+   * Linear interpolation is a method of curve fitting using linear polynomials.
+   * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line
+   *
+   * \par
+   * \image html LinearInterp.gif "Linear interpolation"
+   *
+   * \par
+   * A  Linear Interpolate function calculates an output value(y), for the input(x)
+   * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values)
+   *
+   * \par Algorithm:
+   * <pre>
+   *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
+   *       where x0, x1 are nearest values of input x
+   *             y0, y1 are nearest values to output y
+   * </pre>
+   *
+   * \par
+   * This set of functions implements Linear interpolation process
+   * for Q7, Q15, Q31, and floating-point data types.  The functions operate on a single
+   * sample of data and each call to the function returns a single processed value.
+   * <code>S</code> points to an instance of the Linear Interpolate function data structure.
+   * <code>x</code> is the input sample value. The functions returns the output value.
+   *
+   * \par
+   * if x is outside of the table boundary, Linear interpolation returns first value of the table
+   * if x is below input range and returns last value of table if x is above range.
+   */
+
+  /**
+   * @addtogroup LinearInterpolate
+   * @{
+   */
+
+  /**
+   * @brief  Process function for the floating-point Linear Interpolation Function.
+   * @param[in,out] *S is an instance of the floating-point Linear Interpolation structure
+   * @param[in] x input sample to process
+   * @return y processed output sample.
+   *
+   */
+
+  static __INLINE float32_t arm_linear_interp_f32(
+  arm_linear_interp_instance_f32 * S,
+  float32_t x)
+  {
+
+    float32_t y;
+    float32_t x0, x1;                            /* Nearest input values */
+    float32_t y0, y1;                            /* Nearest output values */
+    float32_t xSpacing = S->xSpacing;            /* spacing between input values */
+    int32_t i;                                   /* Index variable */
+    float32_t *pYData = S->pYData;               /* pointer to output table */
+
+    /* Calculation of index */
+    i = (int32_t) ((x - S->x1) / xSpacing);
+
+    if(i < 0)
+    {
+      /* Iniatilize output for below specified range as least output value of table */
+      y = pYData[0];
+    }
+    else if((uint32_t)i >= S->nValues)
+    {
+      /* Iniatilize output for above specified range as last output value of table */
+      y = pYData[S->nValues - 1];
+    }
+    else
+    {
+      /* Calculation of nearest input values */
+      x0 = S->x1 + i * xSpacing;
+      x1 = S->x1 + (i + 1) * xSpacing;
+
+      /* Read of nearest output values */
+      y0 = pYData[i];
+      y1 = pYData[i + 1];
+
+      /* Calculation of output */
+      y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0));
+
+    }
+
+    /* returns output value */
+    return (y);
+  }
+
+   /**
+   *
+   * @brief  Process function for the Q31 Linear Interpolation Function.
+   * @param[in] *pYData  pointer to Q31 Linear Interpolation table
+   * @param[in] x input sample to process
+   * @param[in] nValues number of table values
+   * @return y processed output sample.
+   *
+   * \par
+   * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+   * This function can support maximum of table size 2^12.
+   *
+   */
+
+
+  static __INLINE q31_t arm_linear_interp_q31(
+  q31_t * pYData,
+  q31_t x,
+  uint32_t nValues)
+  {
+    q31_t y;                                     /* output */
+    q31_t y0, y1;                                /* Nearest output values */
+    q31_t fract;                                 /* fractional part */
+    int32_t index;                               /* Index to read nearest output values */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    index = ((x & 0xFFF00000) >> 20);
+
+    if(index >= (int32_t)(nValues - 1))
+    {
+      return (pYData[nValues - 1]);
+    }
+    else if(index < 0)
+    {
+      return (pYData[0]);
+    }
+    else
+    {
+
+      /* 20 bits for the fractional part */
+      /* shift left by 11 to keep fract in 1.31 format */
+      fract = (x & 0x000FFFFF) << 11;
+
+      /* Read two nearest output values from the index in 1.31(q31) format */
+      y0 = pYData[index];
+      y1 = pYData[index + 1u];
+
+      /* Calculation of y0 * (1-fract) and y is in 2.30 format */
+      y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32));
+
+      /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */
+      y += ((q31_t) (((q63_t) y1 * fract) >> 32));
+
+      /* Convert y to 1.31 format */
+      return (y << 1u);
+
+    }
+
+  }
+
+  /**
+   *
+   * @brief  Process function for the Q15 Linear Interpolation Function.
+   * @param[in] *pYData  pointer to Q15 Linear Interpolation table
+   * @param[in] x input sample to process
+   * @param[in] nValues number of table values
+   * @return y processed output sample.
+   *
+   * \par
+   * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+   * This function can support maximum of table size 2^12.
+   *
+   */
+
+
+  static __INLINE q15_t arm_linear_interp_q15(
+  q15_t * pYData,
+  q31_t x,
+  uint32_t nValues)
+  {
+    q63_t y;                                     /* output */
+    q15_t y0, y1;                                /* Nearest output values */
+    q31_t fract;                                 /* fractional part */
+    int32_t index;                               /* Index to read nearest output values */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    index = ((x & 0xFFF00000) >> 20u);
+
+    if(index >= (int32_t)(nValues - 1))
+    {
+      return (pYData[nValues - 1]);
+    }
+    else if(index < 0)
+    {
+      return (pYData[0]);
+    }
+    else
+    {
+      /* 20 bits for the fractional part */
+      /* fract is in 12.20 format */
+      fract = (x & 0x000FFFFF);
+
+      /* Read two nearest output values from the index */
+      y0 = pYData[index];
+      y1 = pYData[index + 1u];
+
+      /* Calculation of y0 * (1-fract) and y is in 13.35 format */
+      y = ((q63_t) y0 * (0xFFFFF - fract));
+
+      /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */
+      y += ((q63_t) y1 * (fract));
+
+      /* convert y to 1.15 format */
+      return (y >> 20);
+    }
+
+
+  }
+
+  /**
+   *
+   * @brief  Process function for the Q7 Linear Interpolation Function.
+   * @param[in] *pYData  pointer to Q7 Linear Interpolation table
+   * @param[in] x input sample to process
+   * @param[in] nValues number of table values
+   * @return y processed output sample.
+   *
+   * \par
+   * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+   * This function can support maximum of table size 2^12.
+   */
+
+
+  static __INLINE q7_t arm_linear_interp_q7(
+  q7_t * pYData,
+  q31_t x,
+  uint32_t nValues)
+  {
+    q31_t y;                                     /* output */
+    q7_t y0, y1;                                 /* Nearest output values */
+    q31_t fract;                                 /* fractional part */
+    uint32_t index;                              /* Index to read nearest output values */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    if (x < 0)
+    {
+      return (pYData[0]);
+    }
+    index = (x >> 20) & 0xfff;
+
+
+    if(index >= (nValues - 1))
+    {
+      return (pYData[nValues - 1]);
+    }
+    else
+    {
+
+      /* 20 bits for the fractional part */
+      /* fract is in 12.20 format */
+      fract = (x & 0x000FFFFF);
+
+      /* Read two nearest output values from the index and are in 1.7(q7) format */
+      y0 = pYData[index];
+      y1 = pYData[index + 1u];
+
+      /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */
+      y = ((y0 * (0xFFFFF - fract)));
+
+      /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */
+      y += (y1 * fract);
+
+      /* convert y to 1.7(q7) format */
+      return (y >> 20u);
+
+    }
+
+  }
+  /**
+   * @} end of LinearInterpolate group
+   */
+
+  /**
+   * @brief  Fast approximation to the trigonometric sine function for floating-point data.
+   * @param[in] x input value in radians.
+   * @return  sin(x).
+   */
+
+  float32_t arm_sin_f32(
+  float32_t x);
+
+  /**
+   * @brief  Fast approximation to the trigonometric sine function for Q31 data.
+   * @param[in] x Scaled input value in radians.
+   * @return  sin(x).
+   */
+
+  q31_t arm_sin_q31(
+  q31_t x);
+
+  /**
+   * @brief  Fast approximation to the trigonometric sine function for Q15 data.
+   * @param[in] x Scaled input value in radians.
+   * @return  sin(x).
+   */
+
+  q15_t arm_sin_q15(
+  q15_t x);
+
+  /**
+   * @brief  Fast approximation to the trigonometric cosine function for floating-point data.
+   * @param[in] x input value in radians.
+   * @return  cos(x).
+   */
+
+  float32_t arm_cos_f32(
+  float32_t x);
+
+  /**
+   * @brief Fast approximation to the trigonometric cosine function for Q31 data.
+   * @param[in] x Scaled input value in radians.
+   * @return  cos(x).
+   */
+
+  q31_t arm_cos_q31(
+  q31_t x);
+
+  /**
+   * @brief  Fast approximation to the trigonometric cosine function for Q15 data.
+   * @param[in] x Scaled input value in radians.
+   * @return  cos(x).
+   */
+
+  q15_t arm_cos_q15(
+  q15_t x);
+
+
+  /**
+   * @ingroup groupFastMath
+   */
+
+
+  /**
+   * @defgroup SQRT Square Root
+   *
+   * Computes the square root of a number.
+   * There are separate functions for Q15, Q31, and floating-point data types.
+   * The square root function is computed using the Newton-Raphson algorithm.
+   * This is an iterative algorithm of the form:
+   * <pre>
+   *      x1 = x0 - f(x0)/f'(x0)
+   * </pre>
+   * where <code>x1</code> is the current estimate,
+   * <code>x0</code> is the previous estimate, and
+   * <code>f'(x0)</code> is the derivative of <code>f()</code> evaluated at <code>x0</code>.
+   * For the square root function, the algorithm reduces to:
+   * <pre>
+   *     x0 = in/2                         [initial guess]
+   *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]
+   * </pre>
+   */
+
+
+  /**
+   * @addtogroup SQRT
+   * @{
+   */
+
+  /**
+   * @brief  Floating-point square root function.
+   * @param[in]  in     input value.
+   * @param[out] *pOut  square root of input value.
+   * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+   * <code>in</code> is negative value and returns zero output for negative values.
+   */
+
+  static __INLINE arm_status arm_sqrt_f32(
+  float32_t in,
+  float32_t * pOut)
+  {
+    if(in >= 0.0f)
+    {
+
+//      #if __FPU_USED
+#if (__FPU_USED == 1) && defined ( __CC_ARM   )
+      *pOut = __sqrtf(in);
+#else
+      *pOut = sqrtf(in);
+#endif
+
+      return (ARM_MATH_SUCCESS);
+    }
+    else
+    {
+      *pOut = 0.0f;
+      return (ARM_MATH_ARGUMENT_ERROR);
+    }
+
+  }
+
+
+  /**
+   * @brief Q31 square root function.
+   * @param[in]   in    input value.  The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF.
+   * @param[out]  *pOut square root of input value.
+   * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+   * <code>in</code> is negative value and returns zero output for negative values.
+   */
+  arm_status arm_sqrt_q31(
+  q31_t in,
+  q31_t * pOut);
+
+  /**
+   * @brief  Q15 square root function.
+   * @param[in]   in     input value.  The range of the input value is [0 +1) or 0x0000 to 0x7FFF.
+   * @param[out]  *pOut  square root of input value.
+   * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+   * <code>in</code> is negative value and returns zero output for negative values.
+   */
+  arm_status arm_sqrt_q15(
+  q15_t in,
+  q15_t * pOut);
+
+  /**
+   * @} end of SQRT group
+   */
+
+
+
+
+
+
+  /**
+   * @brief floating-point Circular write function.
+   */
+
+  static __INLINE void arm_circularWrite_f32(
+  int32_t * circBuffer,
+  int32_t L,
+  uint16_t * writeOffset,
+  int32_t bufferInc,
+  const int32_t * src,
+  int32_t srcInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0u;
+    int32_t wOffset;
+
+    /* Copy the value of Index pointer that points
+     * to the current location where the input samples to be copied */
+    wOffset = *writeOffset;
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while(i > 0u)
+    {
+      /* copy the input sample to the circular buffer */
+      circBuffer[wOffset] = *src;
+
+      /* Update the input pointer */
+      src += srcInc;
+
+      /* Circularly update wOffset.  Watch out for positive and negative value */
+      wOffset += bufferInc;
+      if(wOffset >= L)
+        wOffset -= L;
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *writeOffset = wOffset;
+  }
+
+
+
+  /**
+   * @brief floating-point Circular Read function.
+   */
+  static __INLINE void arm_circularRead_f32(
+  int32_t * circBuffer,
+  int32_t L,
+  int32_t * readOffset,
+  int32_t bufferInc,
+  int32_t * dst,
+  int32_t * dst_base,
+  int32_t dst_length,
+  int32_t dstInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0u;
+    int32_t rOffset, dst_end;
+
+    /* Copy the value of Index pointer that points
+     * to the current location from where the input samples to be read */
+    rOffset = *readOffset;
+    dst_end = (int32_t) (dst_base + dst_length);
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while(i > 0u)
+    {
+      /* copy the sample from the circular buffer to the destination buffer */
+      *dst = circBuffer[rOffset];
+
+      /* Update the input pointer */
+      dst += dstInc;
+
+      if(dst == (int32_t *) dst_end)
+      {
+        dst = dst_base;
+      }
+
+      /* Circularly update rOffset.  Watch out for positive and negative value  */
+      rOffset += bufferInc;
+
+      if(rOffset >= L)
+      {
+        rOffset -= L;
+      }
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *readOffset = rOffset;
+  }
+
+  /**
+   * @brief Q15 Circular write function.
+   */
+
+  static __INLINE void arm_circularWrite_q15(
+  q15_t * circBuffer,
+  int32_t L,
+  uint16_t * writeOffset,
+  int32_t bufferInc,
+  const q15_t * src,
+  int32_t srcInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0u;
+    int32_t wOffset;
+
+    /* Copy the value of Index pointer that points
+     * to the current location where the input samples to be copied */
+    wOffset = *writeOffset;
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while(i > 0u)
+    {
+      /* copy the input sample to the circular buffer */
+      circBuffer[wOffset] = *src;
+
+      /* Update the input pointer */
+      src += srcInc;
+
+      /* Circularly update wOffset.  Watch out for positive and negative value */
+      wOffset += bufferInc;
+      if(wOffset >= L)
+        wOffset -= L;
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *writeOffset = wOffset;
+  }
+
+
+
+  /**
+   * @brief Q15 Circular Read function.
+   */
+  static __INLINE void arm_circularRead_q15(
+  q15_t * circBuffer,
+  int32_t L,
+  int32_t * readOffset,
+  int32_t bufferInc,
+  q15_t * dst,
+  q15_t * dst_base,
+  int32_t dst_length,
+  int32_t dstInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0;
+    int32_t rOffset, dst_end;
+
+    /* Copy the value of Index pointer that points
+     * to the current location from where the input samples to be read */
+    rOffset = *readOffset;
+
+    dst_end = (int32_t) (dst_base + dst_length);
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while(i > 0u)
+    {
+      /* copy the sample from the circular buffer to the destination buffer */
+      *dst = circBuffer[rOffset];
+
+      /* Update the input pointer */
+      dst += dstInc;
+
+      if(dst == (q15_t *) dst_end)
+      {
+        dst = dst_base;
+      }
+
+      /* Circularly update wOffset.  Watch out for positive and negative value */
+      rOffset += bufferInc;
+
+      if(rOffset >= L)
+      {
+        rOffset -= L;
+      }
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *readOffset = rOffset;
+  }
+
+
+  /**
+   * @brief Q7 Circular write function.
+   */
+
+  static __INLINE void arm_circularWrite_q7(
+  q7_t * circBuffer,
+  int32_t L,
+  uint16_t * writeOffset,
+  int32_t bufferInc,
+  const q7_t * src,
+  int32_t srcInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0u;
+    int32_t wOffset;
+
+    /* Copy the value of Index pointer that points
+     * to the current location where the input samples to be copied */
+    wOffset = *writeOffset;
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while(i > 0u)
+    {
+      /* copy the input sample to the circular buffer */
+      circBuffer[wOffset] = *src;
+
+      /* Update the input pointer */
+      src += srcInc;
+
+      /* Circularly update wOffset.  Watch out for positive and negative value */
+      wOffset += bufferInc;
+      if(wOffset >= L)
+        wOffset -= L;
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *writeOffset = wOffset;
+  }
+
+
+
+  /**
+   * @brief Q7 Circular Read function.
+   */
+  static __INLINE void arm_circularRead_q7(
+  q7_t * circBuffer,
+  int32_t L,
+  int32_t * readOffset,
+  int32_t bufferInc,
+  q7_t * dst,
+  q7_t * dst_base,
+  int32_t dst_length,
+  int32_t dstInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0;
+    int32_t rOffset, dst_end;
+
+    /* Copy the value of Index pointer that points
+     * to the current location from where the input samples to be read */
+    rOffset = *readOffset;
+
+    dst_end = (int32_t) (dst_base + dst_length);
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while(i > 0u)
+    {
+      /* copy the sample from the circular buffer to the destination buffer */
+      *dst = circBuffer[rOffset];
+
+      /* Update the input pointer */
+      dst += dstInc;
+
+      if(dst == (q7_t *) dst_end)
+      {
+        dst = dst_base;
+      }
+
+      /* Circularly update rOffset.  Watch out for positive and negative value */
+      rOffset += bufferInc;
+
+      if(rOffset >= L)
+      {
+        rOffset -= L;
+      }
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *readOffset = rOffset;
+  }
+
+
+  /**
+   * @brief  Sum of the squares of the elements of a Q31 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_power_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q63_t * pResult);
+
+  /**
+   * @brief  Sum of the squares of the elements of a floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_power_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult);
+
+  /**
+   * @brief  Sum of the squares of the elements of a Q15 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_power_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q63_t * pResult);
+
+  /**
+   * @brief  Sum of the squares of the elements of a Q7 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_power_q7(
+  q7_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult);
+
+  /**
+   * @brief  Mean value of a Q7 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_mean_q7(
+  q7_t * pSrc,
+  uint32_t blockSize,
+  q7_t * pResult);
+
+  /**
+   * @brief  Mean value of a Q15 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+  void arm_mean_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult);
+
+  /**
+   * @brief  Mean value of a Q31 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+  void arm_mean_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult);
+
+  /**
+   * @brief  Mean value of a floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+  void arm_mean_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult);
+
+  /**
+   * @brief  Variance of the elements of a floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_var_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult);
+
+  /**
+   * @brief  Variance of the elements of a Q31 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_var_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult);
+
+  /**
+   * @brief  Variance of the elements of a Q15 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_var_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult);
+
+  /**
+   * @brief  Root Mean Square of the elements of a floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_rms_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult);
+
+  /**
+   * @brief  Root Mean Square of the elements of a Q31 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_rms_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult);
+
+  /**
+   * @brief  Root Mean Square of the elements of a Q15 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_rms_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult);
+
+  /**
+   * @brief  Standard deviation of the elements of a floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_std_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult);
+
+  /**
+   * @brief  Standard deviation of the elements of a Q31 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_std_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult);
+
+  /**
+   * @brief  Standard deviation of the elements of a Q15 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_std_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult);
+
+  /**
+   * @brief  Floating-point complex magnitude
+   * @param[in]  *pSrc points to the complex input vector
+   * @param[out]  *pDst points to the real output vector
+   * @param[in]  numSamples number of complex samples in the input vector
+   * @return none.
+   */
+
+  void arm_cmplx_mag_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q31 complex magnitude
+   * @param[in]  *pSrc points to the complex input vector
+   * @param[out]  *pDst points to the real output vector
+   * @param[in]  numSamples number of complex samples in the input vector
+   * @return none.
+   */
+
+  void arm_cmplx_mag_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q15 complex magnitude
+   * @param[in]  *pSrc points to the complex input vector
+   * @param[out]  *pDst points to the real output vector
+   * @param[in]  numSamples number of complex samples in the input vector
+   * @return none.
+   */
+
+  void arm_cmplx_mag_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q15 complex dot product
+   * @param[in]  *pSrcA points to the first input vector
+   * @param[in]  *pSrcB points to the second input vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @param[out]  *realResult real part of the result returned here
+   * @param[out]  *imagResult imaginary part of the result returned here
+   * @return none.
+   */
+
+  void arm_cmplx_dot_prod_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  uint32_t numSamples,
+  q31_t * realResult,
+  q31_t * imagResult);
+
+  /**
+   * @brief  Q31 complex dot product
+   * @param[in]  *pSrcA points to the first input vector
+   * @param[in]  *pSrcB points to the second input vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @param[out]  *realResult real part of the result returned here
+   * @param[out]  *imagResult imaginary part of the result returned here
+   * @return none.
+   */
+
+  void arm_cmplx_dot_prod_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  uint32_t numSamples,
+  q63_t * realResult,
+  q63_t * imagResult);
+
+  /**
+   * @brief  Floating-point complex dot product
+   * @param[in]  *pSrcA points to the first input vector
+   * @param[in]  *pSrcB points to the second input vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @param[out]  *realResult real part of the result returned here
+   * @param[out]  *imagResult imaginary part of the result returned here
+   * @return none.
+   */
+
+  void arm_cmplx_dot_prod_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  uint32_t numSamples,
+  float32_t * realResult,
+  float32_t * imagResult);
+
+  /**
+   * @brief  Q15 complex-by-real multiplication
+   * @param[in]  *pSrcCmplx points to the complex input vector
+   * @param[in]  *pSrcReal points to the real input vector
+   * @param[out]  *pCmplxDst points to the complex output vector
+   * @param[in]  numSamples number of samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_mult_real_q15(
+  q15_t * pSrcCmplx,
+  q15_t * pSrcReal,
+  q15_t * pCmplxDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q31 complex-by-real multiplication
+   * @param[in]  *pSrcCmplx points to the complex input vector
+   * @param[in]  *pSrcReal points to the real input vector
+   * @param[out]  *pCmplxDst points to the complex output vector
+   * @param[in]  numSamples number of samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_mult_real_q31(
+  q31_t * pSrcCmplx,
+  q31_t * pSrcReal,
+  q31_t * pCmplxDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Floating-point complex-by-real multiplication
+   * @param[in]  *pSrcCmplx points to the complex input vector
+   * @param[in]  *pSrcReal points to the real input vector
+   * @param[out]  *pCmplxDst points to the complex output vector
+   * @param[in]  numSamples number of samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_mult_real_f32(
+  float32_t * pSrcCmplx,
+  float32_t * pSrcReal,
+  float32_t * pCmplxDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Minimum value of a Q7 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *result is output pointer
+   * @param[in]  index is the array index of the minimum value in the input buffer.
+   * @return none.
+   */
+
+  void arm_min_q7(
+  q7_t * pSrc,
+  uint32_t blockSize,
+  q7_t * result,
+  uint32_t * index);
+
+  /**
+   * @brief  Minimum value of a Q15 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output pointer
+   * @param[in]  *pIndex is the array index of the minimum value in the input buffer.
+   * @return none.
+   */
+
+  void arm_min_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult,
+  uint32_t * pIndex);
+
+  /**
+   * @brief  Minimum value of a Q31 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output pointer
+   * @param[out]  *pIndex is the array index of the minimum value in the input buffer.
+   * @return none.
+   */
+  void arm_min_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult,
+  uint32_t * pIndex);
+
+  /**
+   * @brief  Minimum value of a floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output pointer
+   * @param[out]  *pIndex is the array index of the minimum value in the input buffer.
+   * @return none.
+   */
+
+  void arm_min_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult,
+  uint32_t * pIndex);
+
+/**
+ * @brief Maximum value of a Q7 vector.
+ * @param[in]       *pSrc points to the input buffer
+ * @param[in]       blockSize length of the input vector
+ * @param[out]      *pResult maximum value returned here
+ * @param[out]      *pIndex index of maximum value returned here
+ * @return none.
+ */
+
+  void arm_max_q7(
+  q7_t * pSrc,
+  uint32_t blockSize,
+  q7_t * pResult,
+  uint32_t * pIndex);
+
+/**
+ * @brief Maximum value of a Q15 vector.
+ * @param[in]       *pSrc points to the input buffer
+ * @param[in]       blockSize length of the input vector
+ * @param[out]      *pResult maximum value returned here
+ * @param[out]      *pIndex index of maximum value returned here
+ * @return none.
+ */
+
+  void arm_max_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult,
+  uint32_t * pIndex);
+
+/**
+ * @brief Maximum value of a Q31 vector.
+ * @param[in]       *pSrc points to the input buffer
+ * @param[in]       blockSize length of the input vector
+ * @param[out]      *pResult maximum value returned here
+ * @param[out]      *pIndex index of maximum value returned here
+ * @return none.
+ */
+
+  void arm_max_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult,
+  uint32_t * pIndex);
+
+/**
+ * @brief Maximum value of a floating-point vector.
+ * @param[in]       *pSrc points to the input buffer
+ * @param[in]       blockSize length of the input vector
+ * @param[out]      *pResult maximum value returned here
+ * @param[out]      *pIndex index of maximum value returned here
+ * @return none.
+ */
+
+  void arm_max_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult,
+  uint32_t * pIndex);
+
+  /**
+   * @brief  Q15 complex-by-complex multiplication
+   * @param[in]  *pSrcA points to the first input vector
+   * @param[in]  *pSrcB points to the second input vector
+   * @param[out]  *pDst  points to the output vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_mult_cmplx_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  q15_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q31 complex-by-complex multiplication
+   * @param[in]  *pSrcA points to the first input vector
+   * @param[in]  *pSrcB points to the second input vector
+   * @param[out]  *pDst  points to the output vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_mult_cmplx_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  q31_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Floating-point complex-by-complex multiplication
+   * @param[in]  *pSrcA points to the first input vector
+   * @param[in]  *pSrcB points to the second input vector
+   * @param[out]  *pDst  points to the output vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_mult_cmplx_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  float32_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief Converts the elements of the floating-point vector to Q31 vector.
+   * @param[in]       *pSrc points to the floating-point input vector
+   * @param[out]      *pDst points to the Q31 output vector
+   * @param[in]       blockSize length of the input vector
+   * @return none.
+   */
+  void arm_float_to_q31(
+  float32_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Converts the elements of the floating-point vector to Q15 vector.
+   * @param[in]       *pSrc points to the floating-point input vector
+   * @param[out]      *pDst points to the Q15 output vector
+   * @param[in]       blockSize length of the input vector
+   * @return          none
+   */
+  void arm_float_to_q15(
+  float32_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Converts the elements of the floating-point vector to Q7 vector.
+   * @param[in]       *pSrc points to the floating-point input vector
+   * @param[out]      *pDst points to the Q7 output vector
+   * @param[in]       blockSize length of the input vector
+   * @return          none
+   */
+  void arm_float_to_q7(
+  float32_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Converts the elements of the Q31 vector to Q15 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[out]  *pDst is output pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @return none.
+   */
+  void arm_q31_to_q15(
+  q31_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Converts the elements of the Q31 vector to Q7 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[out]  *pDst is output pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @return none.
+   */
+  void arm_q31_to_q7(
+  q31_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Converts the elements of the Q15 vector to floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[out]  *pDst is output pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @return none.
+   */
+  void arm_q15_to_float(
+  q15_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Converts the elements of the Q15 vector to Q31 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[out]  *pDst is output pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @return none.
+   */
+  void arm_q15_to_q31(
+  q15_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Converts the elements of the Q15 vector to Q7 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[out]  *pDst is output pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @return none.
+   */
+  void arm_q15_to_q7(
+  q15_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @ingroup groupInterpolation
+   */
+
+  /**
+   * @defgroup BilinearInterpolate Bilinear Interpolation
+   *
+   * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid.
+   * The underlying function <code>f(x, y)</code> is sampled on a regular grid and the interpolation process
+   * determines values between the grid points.
+   * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension.
+   * Bilinear interpolation is often used in image processing to rescale images.
+   * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types.
+   *
+   * <b>Algorithm</b>
+   * \par
+   * The instance structure used by the bilinear interpolation functions describes a two dimensional data table.
+   * For floating-point, the instance structure is defined as:
+   * <pre>
+   *   typedef struct
+   *   {
+   *     uint16_t numRows;
+   *     uint16_t numCols;
+   *     float32_t *pData;
+   * } arm_bilinear_interp_instance_f32;
+   * </pre>
+   *
+   * \par
+   * where <code>numRows</code> specifies the number of rows in the table;
+   * <code>numCols</code> specifies the number of columns in the table;
+   * and <code>pData</code> points to an array of size <code>numRows*numCols</code> values.
+   * The data table <code>pTable</code> is organized in row order and the supplied data values fall on integer indexes.
+   * That is, table element (x,y) is located at <code>pTable[x + y*numCols]</code> where x and y are integers.
+   *
+   * \par
+   * Let <code>(x, y)</code> specify the desired interpolation point.  Then define:
+   * <pre>
+   *     XF = floor(x)
+   *     YF = floor(y)
+   * </pre>
+   * \par
+   * The interpolated output point is computed as:
+   * <pre>
+   *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
+   *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
+   *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
+   *           + f(XF+1, YF+1) * (x-XF)*(y-YF)
+   * </pre>
+   * Note that the coordinates (x, y) contain integer and fractional components.
+   * The integer components specify which portion of the table to use while the
+   * fractional components control the interpolation processor.
+   *
+   * \par
+   * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output.
+   */
+
+  /**
+   * @addtogroup BilinearInterpolate
+   * @{
+   */
+
+  /**
+  *
+  * @brief  Floating-point bilinear interpolation.
+  * @param[in,out] *S points to an instance of the interpolation structure.
+  * @param[in] X interpolation coordinate.
+  * @param[in] Y interpolation coordinate.
+  * @return out interpolated value.
+  */
+
+
+  static __INLINE float32_t arm_bilinear_interp_f32(
+  const arm_bilinear_interp_instance_f32 * S,
+  float32_t X,
+  float32_t Y)
+  {
+    float32_t out;
+    float32_t f00, f01, f10, f11;
+    float32_t *pData = S->pData;
+    int32_t xIndex, yIndex, index;
+    float32_t xdiff, ydiff;
+    float32_t b1, b2, b3, b4;
+
+    xIndex = (int32_t) X;
+    yIndex = (int32_t) Y;
+
+    /* Care taken for table outside boundary */
+    /* Returns zero output when values are outside table boundary */
+    if(xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0
+       || yIndex > (S->numCols - 1))
+    {
+      return (0);
+    }
+
+    /* Calculation of index for two nearest points in X-direction */
+    index = (xIndex - 1) + (yIndex - 1) * S->numCols;
+
+
+    /* Read two nearest points in X-direction */
+    f00 = pData[index];
+    f01 = pData[index + 1];
+
+    /* Calculation of index for two nearest points in Y-direction */
+    index = (xIndex - 1) + (yIndex) * S->numCols;
+
+
+    /* Read two nearest points in Y-direction */
+    f10 = pData[index];
+    f11 = pData[index + 1];
+
+    /* Calculation of intermediate values */
+    b1 = f00;
+    b2 = f01 - f00;
+    b3 = f10 - f00;
+    b4 = f00 - f01 - f10 + f11;
+
+    /* Calculation of fractional part in X */
+    xdiff = X - xIndex;
+
+    /* Calculation of fractional part in Y */
+    ydiff = Y - yIndex;
+
+    /* Calculation of bi-linear interpolated output */
+    out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff;
+
+    /* return to application */
+    return (out);
+
+  }
+
+  /**
+  *
+  * @brief  Q31 bilinear interpolation.
+  * @param[in,out] *S points to an instance of the interpolation structure.
+  * @param[in] X interpolation coordinate in 12.20 format.
+  * @param[in] Y interpolation coordinate in 12.20 format.
+  * @return out interpolated value.
+  */
+
+  static __INLINE q31_t arm_bilinear_interp_q31(
+  arm_bilinear_interp_instance_q31 * S,
+  q31_t X,
+  q31_t Y)
+  {
+    q31_t out;                                   /* Temporary output */
+    q31_t acc = 0;                               /* output */
+    q31_t xfract, yfract;                        /* X, Y fractional parts */
+    q31_t x1, x2, y1, y2;                        /* Nearest output values */
+    int32_t rI, cI;                              /* Row and column indices */
+    q31_t *pYData = S->pData;                    /* pointer to output table values */
+    uint32_t nCols = S->numCols;                 /* num of rows */
+
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    rI = ((X & 0xFFF00000) >> 20u);
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    cI = ((Y & 0xFFF00000) >> 20u);
+
+    /* Care taken for table outside boundary */
+    /* Returns zero output when values are outside table boundary */
+    if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
+    {
+      return (0);
+    }
+
+    /* 20 bits for the fractional part */
+    /* shift left xfract by 11 to keep 1.31 format */
+    xfract = (X & 0x000FFFFF) << 11u;
+
+    /* Read two nearest output values from the index */
+    x1 = pYData[(rI) + nCols * (cI)];
+    x2 = pYData[(rI) + nCols * (cI) + 1u];
+
+    /* 20 bits for the fractional part */
+    /* shift left yfract by 11 to keep 1.31 format */
+    yfract = (Y & 0x000FFFFF) << 11u;
+
+    /* Read two nearest output values from the index */
+    y1 = pYData[(rI) + nCols * (cI + 1)];
+    y2 = pYData[(rI) + nCols * (cI + 1) + 1u];
+
+    /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */
+    out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32));
+    acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32));
+
+    /* x2 * (xfract) * (1-yfract)  in 3.29(q29) and adding to acc */
+    out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32));
+    acc += ((q31_t) ((q63_t) out * (xfract) >> 32));
+
+    /* y1 * (1 - xfract) * (yfract)  in 3.29(q29) and adding to acc */
+    out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32));
+    acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
+
+    /* y2 * (xfract) * (yfract)  in 3.29(q29) and adding to acc */
+    out = ((q31_t) ((q63_t) y2 * (xfract) >> 32));
+    acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
+
+    /* Convert acc to 1.31(q31) format */
+    return (acc << 2u);
+
+  }
+
+  /**
+  * @brief  Q15 bilinear interpolation.
+  * @param[in,out] *S points to an instance of the interpolation structure.
+  * @param[in] X interpolation coordinate in 12.20 format.
+  * @param[in] Y interpolation coordinate in 12.20 format.
+  * @return out interpolated value.
+  */
+
+  static __INLINE q15_t arm_bilinear_interp_q15(
+  arm_bilinear_interp_instance_q15 * S,
+  q31_t X,
+  q31_t Y)
+  {
+    q63_t acc = 0;                               /* output */
+    q31_t out;                                   /* Temporary output */
+    q15_t x1, x2, y1, y2;                        /* Nearest output values */
+    q31_t xfract, yfract;                        /* X, Y fractional parts */
+    int32_t rI, cI;                              /* Row and column indices */
+    q15_t *pYData = S->pData;                    /* pointer to output table values */
+    uint32_t nCols = S->numCols;                 /* num of rows */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    rI = ((X & 0xFFF00000) >> 20);
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    cI = ((Y & 0xFFF00000) >> 20);
+
+    /* Care taken for table outside boundary */
+    /* Returns zero output when values are outside table boundary */
+    if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
+    {
+      return (0);
+    }
+
+    /* 20 bits for the fractional part */
+    /* xfract should be in 12.20 format */
+    xfract = (X & 0x000FFFFF);
+
+    /* Read two nearest output values from the index */
+    x1 = pYData[(rI) + nCols * (cI)];
+    x2 = pYData[(rI) + nCols * (cI) + 1u];
+
+
+    /* 20 bits for the fractional part */
+    /* yfract should be in 12.20 format */
+    yfract = (Y & 0x000FFFFF);
+
+    /* Read two nearest output values from the index */
+    y1 = pYData[(rI) + nCols * (cI + 1)];
+    y2 = pYData[(rI) + nCols * (cI + 1) + 1u];
+
+    /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */
+
+    /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */
+    /* convert 13.35 to 13.31 by right shifting  and out is in 1.31 */
+    out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4u);
+    acc = ((q63_t) out * (0xFFFFF - yfract));
+
+    /* x2 * (xfract) * (1-yfract)  in 1.51 and adding to acc */
+    out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4u);
+    acc += ((q63_t) out * (xfract));
+
+    /* y1 * (1 - xfract) * (yfract)  in 1.51 and adding to acc */
+    out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4u);
+    acc += ((q63_t) out * (yfract));
+
+    /* y2 * (xfract) * (yfract)  in 1.51 and adding to acc */
+    out = (q31_t) (((q63_t) y2 * (xfract)) >> 4u);
+    acc += ((q63_t) out * (yfract));
+
+    /* acc is in 13.51 format and down shift acc by 36 times */
+    /* Convert out to 1.15 format */
+    return (acc >> 36);
+
+  }
+
+  /**
+  * @brief  Q7 bilinear interpolation.
+  * @param[in,out] *S points to an instance of the interpolation structure.
+  * @param[in] X interpolation coordinate in 12.20 format.
+  * @param[in] Y interpolation coordinate in 12.20 format.
+  * @return out interpolated value.
+  */
+
+  static __INLINE q7_t arm_bilinear_interp_q7(
+  arm_bilinear_interp_instance_q7 * S,
+  q31_t X,
+  q31_t Y)
+  {
+    q63_t acc = 0;                               /* output */
+    q31_t out;                                   /* Temporary output */
+    q31_t xfract, yfract;                        /* X, Y fractional parts */
+    q7_t x1, x2, y1, y2;                         /* Nearest output values */
+    int32_t rI, cI;                              /* Row and column indices */
+    q7_t *pYData = S->pData;                     /* pointer to output table values */
+    uint32_t nCols = S->numCols;                 /* num of rows */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    rI = ((X & 0xFFF00000) >> 20);
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    cI = ((Y & 0xFFF00000) >> 20);
+
+    /* Care taken for table outside boundary */
+    /* Returns zero output when values are outside table boundary */
+    if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
+    {
+      return (0);
+    }
+
+    /* 20 bits for the fractional part */
+    /* xfract should be in 12.20 format */
+    xfract = (X & 0x000FFFFF);
+
+    /* Read two nearest output values from the index */
+    x1 = pYData[(rI) + nCols * (cI)];
+    x2 = pYData[(rI) + nCols * (cI) + 1u];
+
+
+    /* 20 bits for the fractional part */
+    /* yfract should be in 12.20 format */
+    yfract = (Y & 0x000FFFFF);
+
+    /* Read two nearest output values from the index */
+    y1 = pYData[(rI) + nCols * (cI + 1)];
+    y2 = pYData[(rI) + nCols * (cI + 1) + 1u];
+
+    /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */
+    out = ((x1 * (0xFFFFF - xfract)));
+    acc = (((q63_t) out * (0xFFFFF - yfract)));
+
+    /* x2 * (xfract) * (1-yfract)  in 2.22 and adding to acc */
+    out = ((x2 * (0xFFFFF - yfract)));
+    acc += (((q63_t) out * (xfract)));
+
+    /* y1 * (1 - xfract) * (yfract)  in 2.22 and adding to acc */
+    out = ((y1 * (0xFFFFF - xfract)));
+    acc += (((q63_t) out * (yfract)));
+
+    /* y2 * (xfract) * (yfract)  in 2.22 and adding to acc */
+    out = ((y2 * (yfract)));
+    acc += (((q63_t) out * (xfract)));
+
+    /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */
+    return (acc >> 40);
+
+  }
+
+  /**
+   * @} end of BilinearInterpolate group
+   */
+   
+
+//SMMLAR
+#define multAcc_32x32_keep32_R(a, x, y) \
+    a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32)
+
+//SMMLSR
+#define multSub_32x32_keep32_R(a, x, y) \
+    a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32)
+
+//SMMULR
+#define mult_32x32_keep32_R(a, x, y) \
+    a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32)
+
+//SMMLA
+#define multAcc_32x32_keep32(a, x, y) \
+    a += (q31_t) (((q63_t) x * y) >> 32)
+
+//SMMLS
+#define multSub_32x32_keep32(a, x, y) \
+    a -= (q31_t) (((q63_t) x * y) >> 32)
+
+//SMMUL
+#define mult_32x32_keep32(a, x, y) \
+    a = (q31_t) (((q63_t) x * y ) >> 32)
+
+
+#if defined ( __CC_ARM ) //Keil
+
+//Enter low optimization region - place directly above function definition
+    #ifdef ARM_MATH_CM4
+      #define LOW_OPTIMIZATION_ENTER \
+         _Pragma ("push")         \
+         _Pragma ("O1")
+    #else
+      #define LOW_OPTIMIZATION_ENTER 
+    #endif
+
+//Exit low optimization region - place directly after end of function definition
+    #ifdef ARM_MATH_CM4
+      #define LOW_OPTIMIZATION_EXIT \
+         _Pragma ("pop")
+    #else
+      #define LOW_OPTIMIZATION_EXIT  
+    #endif
+
+//Enter low optimization region - place directly above function definition
+  #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+
+//Exit low optimization region - place directly after end of function definition
+  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined(__ICCARM__) //IAR
+
+//Enter low optimization region - place directly above function definition
+    #ifdef ARM_MATH_CM4
+      #define LOW_OPTIMIZATION_ENTER \
+         _Pragma ("optimize=low")
+    #else
+      #define LOW_OPTIMIZATION_ENTER   
+    #endif
+
+//Exit low optimization region - place directly after end of function definition
+  #define LOW_OPTIMIZATION_EXIT
+
+//Enter low optimization region - place directly above function definition
+    #ifdef ARM_MATH_CM4
+      #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \
+         _Pragma ("optimize=low")
+    #else
+      #define IAR_ONLY_LOW_OPTIMIZATION_ENTER   
+    #endif
+
+//Exit low optimization region - place directly after end of function definition
+  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined(__GNUC__)
+
+  #define LOW_OPTIMIZATION_ENTER __attribute__(( optimize("-O1") ))
+
+  #define LOW_OPTIMIZATION_EXIT
+
+  #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+
+  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined(__CSMC__)		// Cosmic
+
+#define LOW_OPTIMIZATION_ENTER
+#define LOW_OPTIMIZATION_EXIT
+#define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+#define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined(__TASKING__)		// TASKING
+
+#define LOW_OPTIMIZATION_ENTER
+#define LOW_OPTIMIZATION_EXIT
+#define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+#define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#endif
+
+
+#ifdef	__cplusplus
+}
+#endif
+
+
+#endif /* _ARM_MATH_H */
+
+/**
+ *
+ * End of file.
+ */
diff --git a/ext/TARGET_LPC1768/cmsis.h b/ext/TARGET_LPC1768/cmsis.h
new file mode 100644
index 0000000..dc231a4
--- /dev/null
+++ b/ext/TARGET_LPC1768/cmsis.h
@@ -0,0 +1,13 @@
+/* mbed Microcontroller Library - CMSIS

+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.

+ * 

+ * A generic CMSIS include header, pulling in LPC1768 specifics

+ */

+

+#ifndef MBED_CMSIS_H

+#define MBED_CMSIS_H

+

+#include "LPC17xx.h"

+#include "cmsis_nvic.h"

+

+#endif

diff --git a/ext/TARGET_LPC1768/cmsis_nvic.h b/ext/TARGET_LPC1768/cmsis_nvic.h
new file mode 100644
index 0000000..00a4e8e
--- /dev/null
+++ b/ext/TARGET_LPC1768/cmsis_nvic.h
@@ -0,0 +1,51 @@
+/* mbed Microcontroller Library

+ * CMSIS-style functionality to support dynamic vectors

+ *******************************************************************************

+ * Copyright (c) 2011 ARM Limited. All rights reserved.

+ * All rights reserved.

+ *

+ * Redistribution and use in source and binary forms, with or without

+ * modification, are permitted provided that the following conditions are met:

+ *

+ * 1. Redistributions of source code must retain the above copyright notice,

+ *    this list of conditions and the following disclaimer.

+ * 2. Redistributions in binary form must reproduce the above copyright notice,

+ *    this list of conditions and the following disclaimer in the documentation

+ *    and/or other materials provided with the distribution.

+ * 3. Neither the name of ARM Limited nor the names of its contributors

+ *    may be used to endorse or promote products derived from this software

+ *    without specific prior written permission.

+ *

+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"

+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE

+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE

+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE

+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL

+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR

+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER

+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,

+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE

+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

+ *******************************************************************************

+ */

+

+#ifndef MBED_CMSIS_NVIC_H

+#define MBED_CMSIS_NVIC_H

+

+#include "cmsis.h"

+

+#define NVIC_NUM_VECTORS      (16 + 33)

+#define NVIC_USER_IRQ_OFFSET  16

+

+#ifdef __cplusplus

+extern "C" {

+#endif

+

+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);

+uint32_t NVIC_GetVector(IRQn_Type IRQn);

+

+#ifdef __cplusplus

+}

+#endif

+

+#endif

diff --git a/ext/TARGET_LPC1768/core_ca9.h b/ext/TARGET_LPC1768/core_ca9.h
new file mode 100644
index 0000000..98b2b0a
--- /dev/null
+++ b/ext/TARGET_LPC1768/core_ca9.h
@@ -0,0 +1,276 @@
+/**************************************************************************//**

+ * @file     core_ca9.h

+ * @brief    CMSIS Cortex-A9 Core Peripheral Access Layer Header File

+ * @version

+ * @date     25 March 2013

+ *

+ * @note

+ *

+ ******************************************************************************/

+/* Copyright (c) 2009 - 2012 ARM LIMITED

+

+   All rights reserved.

+   Redistribution and use in source and binary forms, with or without

+   modification, are permitted provided that the following conditions are met:

+   - Redistributions of source code must retain the above copyright

+     notice, this list of conditions and the following disclaimer.

+   - Redistributions in binary form must reproduce the above copyright

+     notice, this list of conditions and the following disclaimer in the

+     documentation and/or other materials provided with the distribution.

+   - Neither the name of ARM nor the names of its contributors may be used

+     to endorse or promote products derived from this software without

+     specific prior written permission.

+   *

+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"

+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE

+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE

+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE

+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR

+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF

+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS

+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN

+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)

+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE

+   POSSIBILITY OF SUCH DAMAGE.

+   ---------------------------------------------------------------------------*/

+

+

+#if defined ( __ICCARM__ )

+ #pragma system_include  /* treat file as system include file for MISRA check */

+#endif

+

+#ifdef __cplusplus

+ extern "C" {

+#endif

+

+#ifndef __CORE_CA9_H_GENERIC

+#define __CORE_CA9_H_GENERIC

+

+

+/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions

+  CMSIS violates the following MISRA-C:2004 rules:

+

+   \li Required Rule 8.5, object/function definition in header file.<br>

+     Function definitions in header files are used to allow 'inlining'.

+

+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>

+     Unions are used for effective representation of core registers.

+

+   \li Advisory Rule 19.7, Function-like macro defined.<br>

+     Function-like macros are used to allow more efficient code.

+ */

+

+

+/*******************************************************************************

+ *                 CMSIS definitions

+ ******************************************************************************/

+/** \ingroup Cortex_A9

+  @{

+ */

+

+/*  CMSIS CA9 definitions */

+#define __CA9_CMSIS_VERSION_MAIN  (0x03)                                   /*!< [31:16] CMSIS HAL main version   */

+#define __CA9_CMSIS_VERSION_SUB   (0x10)                                   /*!< [15:0]  CMSIS HAL sub version    */

+#define __CA9_CMSIS_VERSION       ((__CA9_CMSIS_VERSION_MAIN << 16) | \

+                                    __CA9_CMSIS_VERSION_SUB          )     /*!< CMSIS HAL version number         */

+

+#define __CORTEX_A                (0x09)                                   /*!< Cortex-A Core                    */

+

+

+#if   defined ( __CC_ARM )

+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */

+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */

+  #define __STATIC_INLINE  static __inline

+  #define __STATIC_ASM     static __asm

+

+#elif defined ( __ICCARM__ )

+  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */

+  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */

+  #define __STATIC_INLINE  static inline

+  #define __STATIC_ASM     static __asm

+

+#include <stdint.h>

+inline uint32_t __get_PSR(void) {

+	__ASM("mrs r0, cpsr");

+}

+

+#elif defined ( __TMS470__ )

+  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler       */

+  #define __STATIC_INLINE  static inline

+  #define __STATIC_ASM     static __asm

+

+#elif defined ( __GNUC__ )

+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */

+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */

+  #define __STATIC_INLINE  static inline

+  #define __STATIC_ASM     static __asm

+

+#elif defined ( __TASKING__ )

+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */

+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */

+  #define __STATIC_INLINE  static inline

+  #define __STATIC_ASM     static __asm

+

+#endif

+

+/** __FPU_USED indicates whether an FPU is used or not. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.

+*/

+#if defined ( __CC_ARM )

+  #if defined __TARGET_FPU_VFP

+    #if (__FPU_PRESENT == 1)

+      #define __FPU_USED       1

+    #else

+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"

+      #define __FPU_USED       0

+    #endif

+  #else

+    #define __FPU_USED         0

+  #endif

+

+#elif defined ( __ICCARM__ )

+  #if defined __ARMVFP__

+    #if (__FPU_PRESENT == 1)

+      #define __FPU_USED       1

+    #else

+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"

+      #define __FPU_USED       0

+    #endif

+  #else

+    #define __FPU_USED         0

+  #endif

+

+#elif defined ( __TMS470__ )

+  #if defined __TI_VFP_SUPPORT__

+    #if (__FPU_PRESENT == 1)

+      #define __FPU_USED       1

+    #else

+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"

+      #define __FPU_USED       0

+    #endif

+  #else

+    #define __FPU_USED         0

+  #endif

+

+#elif defined ( __GNUC__ )

+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)

+    #if (__FPU_PRESENT == 1)

+      #define __FPU_USED       1

+    #else

+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"

+      #define __FPU_USED       0

+    #endif

+  #else

+    #define __FPU_USED         0

+  #endif

+

+#elif defined ( __TASKING__ )

+  #if defined __FPU_VFP__

+    #if (__FPU_PRESENT == 1)

+      #define __FPU_USED       1

+    #else

+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"

+      #define __FPU_USED       0

+    #endif

+  #else

+    #define __FPU_USED         0

+  #endif

+#endif

+

+#include <stdint.h>                      /*!< standard types definitions                      */

+#include "core_caInstr.h"                /*!< Core Instruction Access                         */

+#include "core_caFunc.h"                 /*!< Core Function Access                            */

+#include "core_cm4_simd.h"               /*!< Compiler specific SIMD Intrinsics               */

+

+#endif /* __CORE_CA9_H_GENERIC */

+

+#ifndef __CMSIS_GENERIC

+

+#ifndef __CORE_CA9_H_DEPENDANT

+#define __CORE_CA9_H_DEPENDANT

+

+/* check device defines and use defaults */

+#if defined __CHECK_DEVICE_DEFINES

+  #ifndef __CA9_REV

+    #define __CA9_REV               0x0000

+    #warning "__CA9_REV not defined in device header file; using default!"

+  #endif

+

+  #ifndef __FPU_PRESENT

+    #define __FPU_PRESENT             1

+    #warning "__FPU_PRESENT not defined in device header file; using default!"

+  #endif

+

+  #ifndef __Vendor_SysTickConfig

+    #define __Vendor_SysTickConfig    1

+  #endif

+

+  #if __Vendor_SysTickConfig == 0

+    #error "__Vendor_SysTickConfig set to 0, but vendor systick timer must be supplied for Cortex-A9"

+  #endif

+#endif

+

+/* IO definitions (access restrictions to peripheral registers) */

+/**

+    \defgroup CMSIS_glob_defs CMSIS Global Defines

+

+    <strong>IO Type Qualifiers</strong> are used

+    \li to specify the access to peripheral variables.

+    \li for automatic generation of peripheral register debug information.

+*/

+#ifdef __cplusplus

+  #define   __I     volatile             /*!< Defines 'read only' permissions                 */

+#else

+  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */

+#endif

+#define     __O     volatile             /*!< Defines 'write only' permissions                */

+#define     __IO    volatile             /*!< Defines 'read / write' permissions              */

+

+/*@} end of group Cortex_A9 */

+

+

+/*******************************************************************************

+ *                 Register Abstraction

+ ******************************************************************************/

+/** \defgroup CMSIS_core_register Defines and Type Definitions

+    \brief Type definitions and defines for Cortex-A processor based devices.

+*/

+

+/** \ingroup    CMSIS_core_register

+    \defgroup   CMSIS_CORE  Status and Control Registers

+    \brief  Core Register type definitions.

+  @{

+ */

+

+/** \brief  Union type to access the Application Program Status Register (APSR).

+ */

+typedef union

+{

+  struct

+  {

+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */

+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */

+    uint32_t reserved1:7;                /*!< bit: 20..23  Reserved                           */

+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */

+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */

+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */

+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */

+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */

+  } b;                                   /*!< Structure used for bit  access                  */

+  uint32_t w;                            /*!< Type      used for word access                  */ 

+} APSR_Type;

+

+

+/*@} end of group CMSIS_CORE */

+

+/*@} end of CMSIS_Core_FPUFunctions */

+

+

+#endif /* __CORE_CA9_H_GENERIC */

+

+#endif /* __CMSIS_GENERIC */

+

+#ifdef __cplusplus

+}

+

+

+#endif

diff --git a/ext/TARGET_LPC1768/core_caFunc.h b/ext/TARGET_LPC1768/core_caFunc.h
new file mode 100644
index 0000000..a25e6d7
--- /dev/null
+++ b/ext/TARGET_LPC1768/core_caFunc.h
@@ -0,0 +1,1418 @@
+/**************************************************************************//**

+ * @file     core_caFunc.h

+ * @brief    CMSIS Cortex-A Core Function Access Header File

+ * @version  V3.10

+ * @date     30 Oct 2013

+ *

+ * @note

+ *

+ ******************************************************************************/

+/* Copyright (c) 2009 - 2013 ARM LIMITED

+

+   All rights reserved.

+   Redistribution and use in source and binary forms, with or without

+   modification, are permitted provided that the following conditions are met:

+   - Redistributions of source code must retain the above copyright

+     notice, this list of conditions and the following disclaimer.

+   - Redistributions in binary form must reproduce the above copyright

+     notice, this list of conditions and the following disclaimer in the

+     documentation and/or other materials provided with the distribution.

+   - Neither the name of ARM nor the names of its contributors may be used

+     to endorse or promote products derived from this software without

+     specific prior written permission.

+   *

+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"

+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE

+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE

+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE

+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR

+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF

+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS

+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN

+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)

+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE

+   POSSIBILITY OF SUCH DAMAGE.

+   ---------------------------------------------------------------------------*/

+

+

+#ifndef __CORE_CAFUNC_H__

+#define __CORE_CAFUNC_H__

+

+

+/* ###########################  Core Function Access  ########################### */

+/** \ingroup  CMSIS_Core_FunctionInterface

+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions

+  @{

+ */

+

+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/

+/* ARM armcc specific functions */

+

+#if (__ARMCC_VERSION < 400677)

+  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"

+#endif

+

+#define MODE_USR 0x10

+#define MODE_FIQ 0x11

+#define MODE_IRQ 0x12

+#define MODE_SVC 0x13

+#define MODE_MON 0x16

+#define MODE_ABT 0x17

+#define MODE_HYP 0x1A

+#define MODE_UND 0x1B

+#define MODE_SYS 0x1F

+

+/** \brief  Get APSR Register

+

+    This function returns the content of the APSR Register.

+

+    \return               APSR Register value

+ */

+__STATIC_INLINE uint32_t __get_APSR(void)

+{

+  register uint32_t __regAPSR          __ASM("apsr");

+  return(__regAPSR);

+}

+

+

+/** \brief  Get CPSR Register

+

+    This function returns the content of the CPSR Register.

+

+    \return               CPSR Register value

+ */

+__STATIC_INLINE uint32_t __get_CPSR(void)

+{

+  register uint32_t __regCPSR          __ASM("cpsr");

+  return(__regCPSR);

+}

+

+/** \brief  Set Stack Pointer

+

+    This function assigns the given value to the current stack pointer.

+

+    \param [in]    topOfStack  Stack Pointer value to set

+ */

+register uint32_t __regSP              __ASM("sp");

+__STATIC_INLINE void __set_SP(uint32_t topOfStack)

+{

+    __regSP = topOfStack;

+}

+

+

+/** \brief  Get link register

+

+    This function returns the value of the link register

+

+    \return    Value of link register

+ */

+register uint32_t __reglr         __ASM("lr");

+__STATIC_INLINE uint32_t __get_LR(void)

+{

+  return(__reglr);

+}

+

+/** \brief  Set link register

+

+    This function sets the value of the link register

+

+    \param [in]    lr  LR value to set

+ */

+__STATIC_INLINE void __set_LR(uint32_t lr)

+{

+  __reglr = lr;

+}

+

+/** \brief  Set Process Stack Pointer

+

+    This function assigns the given value to the USR/SYS Stack Pointer (PSP).

+

+    \param [in]    topOfProcStack  USR/SYS Stack Pointer value to set

+ */

+__STATIC_ASM void __set_PSP(uint32_t topOfProcStack)

+{

+    ARM

+    PRESERVE8

+

+    BIC     R0, R0, #7  ;ensure stack is 8-byte aligned

+    MRS     R1, CPSR

+    CPS     #MODE_SYS   ;no effect in USR mode

+    MOV     SP, R0

+    MSR     CPSR_c, R1  ;no effect in USR mode

+    ISB

+    BX      LR

+

+}

+

+/** \brief  Set User Mode

+

+    This function changes the processor state to User Mode

+ */

+__STATIC_ASM void __set_CPS_USR(void)

+{

+    ARM 

+

+    CPS  #MODE_USR  

+    BX   LR

+}

+

+

+/** \brief  Enable FIQ

+

+    This function enables FIQ interrupts by clearing the F-bit in the CPSR.

+    Can only be executed in Privileged modes.

+ */

+#define __enable_fault_irq                __enable_fiq

+

+

+/** \brief  Disable FIQ

+

+    This function disables FIQ interrupts by setting the F-bit in the CPSR.

+    Can only be executed in Privileged modes.

+ */

+#define __disable_fault_irq               __disable_fiq

+

+

+/** \brief  Get FPSCR

+

+    This function returns the current value of the Floating Point Status/Control register.

+

+    \return               Floating Point Status/Control register value

+ */

+__STATIC_INLINE uint32_t __get_FPSCR(void)

+{

+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)

+  register uint32_t __regfpscr         __ASM("fpscr");

+  return(__regfpscr);

+#else

+   return(0);

+#endif

+}

+

+

+/** \brief  Set FPSCR

+

+    This function assigns the given value to the Floating Point Status/Control register.

+

+    \param [in]    fpscr  Floating Point Status/Control value to set

+ */

+__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)

+{

+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)

+  register uint32_t __regfpscr         __ASM("fpscr");

+  __regfpscr = (fpscr);

+#endif

+}

+

+/** \brief  Get FPEXC

+

+    This function returns the current value of the Floating Point Exception Control register.

+

+    \return               Floating Point Exception Control register value

+ */

+__STATIC_INLINE uint32_t __get_FPEXC(void)

+{

+#if (__FPU_PRESENT == 1)

+  register uint32_t __regfpexc         __ASM("fpexc");

+  return(__regfpexc);

+#else

+   return(0);

+#endif

+}

+

+

+/** \brief  Set FPEXC

+

+    This function assigns the given value to the Floating Point Exception Control register.

+

+    \param [in]    fpscr  Floating Point Exception Control value to set

+ */

+__STATIC_INLINE void __set_FPEXC(uint32_t fpexc)

+{

+#if (__FPU_PRESENT == 1)

+  register uint32_t __regfpexc         __ASM("fpexc");

+  __regfpexc = (fpexc);

+#endif

+}

+

+/** \brief  Get CPACR

+

+    This function returns the current value of the Coprocessor Access Control register.

+

+    \return               Coprocessor Access Control register value

+ */

+__STATIC_INLINE uint32_t __get_CPACR(void)

+{

+    register uint32_t __regCPACR         __ASM("cp15:0:c1:c0:2");

+    return __regCPACR;

+}

+

+/** \brief  Set CPACR

+

+    This function assigns the given value to the Coprocessor Access Control register.

+

+    \param [in]    cpacr  Coprocessor Acccess Control value to set

+ */

+__STATIC_INLINE void __set_CPACR(uint32_t cpacr)

+{

+    register uint32_t __regCPACR         __ASM("cp15:0:c1:c0:2");

+    __regCPACR = cpacr;

+    __ISB();

+}

+

+/** \brief  Get CBAR

+

+    This function returns the value of the Configuration Base Address register.

+

+    \return               Configuration Base Address register value

+ */

+__STATIC_INLINE uint32_t __get_CBAR() {

+    register uint32_t __regCBAR         __ASM("cp15:4:c15:c0:0");

+    return(__regCBAR);

+}

+

+/** \brief  Get TTBR0

+

+    This function returns the value of the Translation Table Base Register 0.

+

+    \return               Translation Table Base Register 0 value

+ */

+__STATIC_INLINE uint32_t __get_TTBR0() {

+    register uint32_t __regTTBR0        __ASM("cp15:0:c2:c0:0");

+    return(__regTTBR0);

+}

+

+/** \brief  Set TTBR0

+

+    This function assigns the given value to the Translation Table Base Register 0.

+

+    \param [in]    ttbr0  Translation Table Base Register 0 value to set

+ */

+__STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {

+    register uint32_t __regTTBR0        __ASM("cp15:0:c2:c0:0");

+    __regTTBR0 = ttbr0;

+    __ISB();

+}

+

+/** \brief  Get DACR

+

+    This function returns the value of the Domain Access Control Register.

+

+    \return               Domain Access Control Register value

+ */

+__STATIC_INLINE uint32_t __get_DACR() {

+    register uint32_t __regDACR         __ASM("cp15:0:c3:c0:0");

+    return(__regDACR);

+}

+

+/** \brief  Set DACR

+

+    This function assigns the given value to the Domain Access Control Register.

+

+    \param [in]    dacr   Domain Access Control Register value to set

+ */

+__STATIC_INLINE void __set_DACR(uint32_t dacr) {

+    register uint32_t __regDACR         __ASM("cp15:0:c3:c0:0");

+    __regDACR = dacr;

+    __ISB();

+}

+

+/******************************** Cache and BTAC enable  ****************************************************/

+

+/** \brief  Set SCTLR

+

+    This function assigns the given value to the System Control Register.

+

+    \param [in]    sctlr  System Control Register value to set

+ */

+__STATIC_INLINE void __set_SCTLR(uint32_t sctlr)

+{

+    register uint32_t __regSCTLR         __ASM("cp15:0:c1:c0:0");

+    __regSCTLR = sctlr;

+}

+

+/** \brief  Get SCTLR

+

+    This function returns the value of the System Control Register.

+

+    \return               System Control Register value

+ */

+__STATIC_INLINE uint32_t __get_SCTLR() {

+    register uint32_t __regSCTLR         __ASM("cp15:0:c1:c0:0");

+    return(__regSCTLR);

+}

+

+/** \brief  Enable Caches

+

+    Enable Caches

+ */

+__STATIC_INLINE void __enable_caches(void) {

+    // Set I bit 12 to enable I Cache

+    // Set C bit  2 to enable D Cache

+    __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));

+}

+

+/** \brief  Disable Caches

+

+    Disable Caches

+ */

+__STATIC_INLINE void __disable_caches(void) {

+    // Clear I bit 12 to disable I Cache

+    // Clear C bit  2 to disable D Cache

+    __set_SCTLR( __get_SCTLR() & ~(1 << 12) & ~(1 << 2));

+    __ISB();

+}

+

+/** \brief  Enable BTAC

+

+    Enable BTAC

+ */

+__STATIC_INLINE void __enable_btac(void) {

+    // Set Z bit 11 to enable branch prediction

+    __set_SCTLR( __get_SCTLR() | (1 << 11));

+    __ISB();

+}

+

+/** \brief  Disable BTAC

+

+    Disable BTAC

+ */

+__STATIC_INLINE void __disable_btac(void) {

+    // Clear Z bit 11 to disable branch prediction

+    __set_SCTLR( __get_SCTLR() & ~(1 << 11));

+}

+

+

+/** \brief  Enable MMU

+

+    Enable MMU

+ */

+__STATIC_INLINE void __enable_mmu(void) {

+    // Set M bit 0 to enable the MMU

+    // Set AFE bit to enable simplified access permissions model

+    // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking

+    __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));

+    __ISB();

+}

+

+/** \brief  Disable MMU

+

+    Disable MMU

+ */

+__STATIC_INLINE void __disable_mmu(void) {

+    // Clear M bit 0 to disable the MMU

+    __set_SCTLR( __get_SCTLR() & ~1);

+    __ISB();

+}

+

+/******************************** TLB maintenance operations ************************************************/

+/** \brief  Invalidate the whole tlb

+

+    TLBIALL. Invalidate the whole tlb

+ */

+

+__STATIC_INLINE void __ca9u_inv_tlb_all(void) {

+    register uint32_t __TLBIALL         __ASM("cp15:0:c8:c7:0");

+    __TLBIALL = 0;

+    __DSB();

+    __ISB();

+}

+

+/******************************** BTB maintenance operations ************************************************/

+/** \brief  Invalidate entire branch predictor array

+

+    BPIALL. Branch Predictor Invalidate All.

+ */

+

+__STATIC_INLINE void __v7_inv_btac(void) {

+    register uint32_t __BPIALL          __ASM("cp15:0:c7:c5:6");

+    __BPIALL  = 0;

+    __DSB();     //ensure completion of the invalidation

+    __ISB();     //ensure instruction fetch path sees new state

+}

+

+

+/******************************** L1 cache operations ******************************************************/

+

+/** \brief  Invalidate the whole I$

+

+    ICIALLU. Instruction Cache Invalidate All to PoU

+ */

+__STATIC_INLINE void __v7_inv_icache_all(void) {

+    register uint32_t __ICIALLU         __ASM("cp15:0:c7:c5:0");

+    __ICIALLU = 0;

+    __DSB();     //ensure completion of the invalidation

+    __ISB();     //ensure instruction fetch path sees new I cache state

+}

+

+/** \brief  Clean D$ by MVA

+

+    DCCMVAC. Data cache clean by MVA to PoC

+ */

+__STATIC_INLINE void __v7_clean_dcache_mva(void *va) {

+    register uint32_t __DCCMVAC         __ASM("cp15:0:c7:c10:1");

+    __DCCMVAC = (uint32_t)va;

+    __DMB();     //ensure the ordering of data cache maintenance operations and their effects

+}

+

+/** \brief  Invalidate D$ by MVA

+

+    DCIMVAC. Data cache invalidate by MVA to PoC

+ */

+__STATIC_INLINE void __v7_inv_dcache_mva(void *va) {

+    register uint32_t __DCIMVAC         __ASM("cp15:0:c7:c6:1");

+    __DCIMVAC = (uint32_t)va;

+    __DMB();     //ensure the ordering of data cache maintenance operations and their effects

+}

+

+/** \brief  Clean and Invalidate D$ by MVA

+

+    DCCIMVAC. Data cache clean and invalidate by MVA to PoC

+ */

+__STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {

+    register uint32_t __DCCIMVAC        __ASM("cp15:0:c7:c14:1");

+    __DCCIMVAC = (uint32_t)va;

+    __DMB();     //ensure the ordering of data cache maintenance operations and their effects

+}

+

+/** \brief  Clean and Invalidate the entire data or unified cache

+

+    Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency.

+ */

+#pragma push

+#pragma arm

+__STATIC_ASM void __v7_all_cache(uint32_t op) {

+        ARM 

+

+        PUSH    {R4-R11}

+

+        MRC     p15, 1, R6, c0, c0, 1      // Read CLIDR

+        ANDS    R3, R6, #0x07000000        // Extract coherency level

+        MOV     R3, R3, LSR #23            // Total cache levels << 1

+        BEQ     Finished                   // If 0, no need to clean

+

+        MOV     R10, #0                    // R10 holds current cache level << 1

+Loop1   ADD     R2, R10, R10, LSR #1       // R2 holds cache "Set" position

+        MOV     R1, R6, LSR R2             // Bottom 3 bits are the Cache-type for this level

+        AND     R1, R1, #7                 // Isolate those lower 3 bits

+        CMP     R1, #2

+        BLT     Skip                       // No cache or only instruction cache at this level

+

+        MCR     p15, 2, R10, c0, c0, 0     // Write the Cache Size selection register

+        ISB                                // ISB to sync the change to the CacheSizeID reg

+        MRC     p15, 1, R1, c0, c0, 0      // Reads current Cache Size ID register

+        AND     R2, R1, #7                 // Extract the line length field

+        ADD     R2, R2, #4                 // Add 4 for the line length offset (log2 16 bytes)

+        LDR     R4, =0x3FF

+        ANDS    R4, R4, R1, LSR #3         // R4 is the max number on the way size (right aligned)

+        CLZ     R5, R4                     // R5 is the bit position of the way size increment

+        LDR     R7, =0x7FFF

+        ANDS    R7, R7, R1, LSR #13        // R7 is the max number of the index size (right aligned)

+

+Loop2   MOV     R9, R4                     // R9 working copy of the max way size (right aligned)

+

+Loop3   ORR     R11, R10, R9, LSL R5       // Factor in the Way number and cache number into R11

+        ORR     R11, R11, R7, LSL R2       // Factor in the Set number

+        CMP     R0, #0

+        BNE     Dccsw

+        MCR     p15, 0, R11, c7, c6, 2     // DCISW. Invalidate by Set/Way

+        B       cont

+Dccsw   CMP     R0, #1

+        BNE     Dccisw

+        MCR     p15, 0, R11, c7, c10, 2    // DCCSW. Clean by Set/Way

+        B       cont

+Dccisw  MCR     p15, 0, R11, c7, c14, 2    // DCCISW. Clean and Invalidate by Set/Way

+cont    SUBS    R9, R9, #1                 // Decrement the Way number

+        BGE     Loop3

+        SUBS    R7, R7, #1                 // Decrement the Set number

+        BGE     Loop2

+Skip    ADD     R10, R10, #2               // Increment the cache number

+        CMP     R3, R10

+        BGT     Loop1

+

+Finished

+        DSB

+        POP    {R4-R11}

+        BX     lr

+

+}

+#pragma pop

+

+

+/** \brief  Invalidate the whole D$

+

+    DCISW. Invalidate by Set/Way

+ */

+

+__STATIC_INLINE void __v7_inv_dcache_all(void) {

+    __v7_all_cache(0);

+}

+

+/** \brief  Clean the whole D$

+

+    DCCSW. Clean by Set/Way

+ */

+

+__STATIC_INLINE void __v7_clean_dcache_all(void) {

+    __v7_all_cache(1);

+}

+

+/** \brief  Clean and invalidate the whole D$

+

+    DCCISW. Clean and Invalidate by Set/Way

+ */

+

+__STATIC_INLINE void __v7_clean_inv_dcache_all(void) {

+    __v7_all_cache(2);

+}

+

+#include "core_ca_mmu.h"

+

+#elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/

+

+#define __inline inline

+

+inline static uint32_t __disable_irq_iar() {

+  int irq_dis = __get_CPSR() & 0x80;      // 7bit CPSR.I

+  __disable_irq();

+  return irq_dis;

+}

+

+#define MODE_USR 0x10

+#define MODE_FIQ 0x11

+#define MODE_IRQ 0x12

+#define MODE_SVC 0x13

+#define MODE_MON 0x16

+#define MODE_ABT 0x17

+#define MODE_HYP 0x1A

+#define MODE_UND 0x1B

+#define MODE_SYS 0x1F

+

+/** \brief  Set Process Stack Pointer

+

+    This function assigns the given value to the USR/SYS Stack Pointer (PSP).

+

+    \param [in]    topOfProcStack  USR/SYS Stack Pointer value to set

+ */

+// from rt_CMSIS.c

+__arm static inline void __set_PSP(uint32_t topOfProcStack) {

+__asm(

+  "    ARM\n"

+//  "    PRESERVE8\n"

+

+  "    BIC     R0, R0, #7  ;ensure stack is 8-byte aligned \n"

+  "    MRS     R1, CPSR \n"

+  "    CPS     #0x1F   ;no effect in USR mode \n"        // MODE_SYS

+  "    MOV     SP, R0 \n"

+  "    MSR     CPSR_c, R1  ;no effect in USR mode \n"

+  "    ISB \n"

+  "    BX      LR \n");

+}

+

+/** \brief  Set User Mode

+

+    This function changes the processor state to User Mode

+ */

+// from rt_CMSIS.c

+__arm static inline void __set_CPS_USR(void) {

+__asm(

+  "    ARM \n"

+

+  "    CPS  #0x10  \n"                  // MODE_USR

+  "    BX   LR\n");

+}

+

+/** \brief  Set TTBR0

+

+    This function assigns the given value to the Translation Table Base Register 0.

+

+    \param [in]    ttbr0  Translation Table Base Register 0 value to set

+ */

+// from mmu_Renesas_RZ_A1.c

+__STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {

+    __MCR(15, 0, ttbr0, 2, 0, 0);      // reg to cp15

+    __ISB();

+}

+

+/** \brief  Set DACR

+

+    This function assigns the given value to the Domain Access Control Register.

+

+    \param [in]    dacr   Domain Access Control Register value to set

+ */

+// from mmu_Renesas_RZ_A1.c

+__STATIC_INLINE void __set_DACR(uint32_t dacr) {

+    __MCR(15, 0, dacr, 3, 0, 0);      // reg to cp15

+    __ISB();

+}

+

+

+/******************************** Cache and BTAC enable  ****************************************************/

+/** \brief  Set SCTLR

+

+    This function assigns the given value to the System Control Register.

+

+    \param [in]    sctlr  System Control Register value to set

+ */

+// from __enable_mmu()

+__STATIC_INLINE void __set_SCTLR(uint32_t sctlr) {

+    __MCR(15, 0, sctlr, 1, 0, 0);      // reg to cp15

+}

+

+/** \brief  Get SCTLR

+

+    This function returns the value of the System Control Register.

+

+    \return               System Control Register value

+ */

+// from __enable_mmu()

+__STATIC_INLINE uint32_t __get_SCTLR() {

+	uint32_t __regSCTLR = __MRC(15, 0, 1, 0, 0);

+	return __regSCTLR;

+}

+

+/** \brief  Enable Caches

+

+    Enable Caches

+ */

+// from system_Renesas_RZ_A1.c

+__STATIC_INLINE void __enable_caches(void) {

+    __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));

+}

+

+/** \brief  Enable BTAC

+

+    Enable BTAC

+ */

+// from system_Renesas_RZ_A1.c

+__STATIC_INLINE void __enable_btac(void) {

+    __set_SCTLR( __get_SCTLR() | (1 << 11));

+    __ISB();

+}

+

+/** \brief  Enable MMU

+

+    Enable MMU

+ */

+// from system_Renesas_RZ_A1.c

+__STATIC_INLINE void __enable_mmu(void) {

+    // Set M bit 0 to enable the MMU

+    // Set AFE bit to enable simplified access permissions model

+    // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking

+    __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));

+    __ISB();

+}

+

+/******************************** TLB maintenance operations ************************************************/

+/** \brief  Invalidate the whole tlb

+

+    TLBIALL. Invalidate the whole tlb

+ */

+// from system_Renesas_RZ_A1.c

+__STATIC_INLINE void __ca9u_inv_tlb_all(void) {

+	uint32_t val = 0;

+    __MCR(15, 0, val, 8, 7, 0);      // reg to cp15

+    __MCR(15, 0, val, 8, 6, 0);      // reg to cp15

+    __MCR(15, 0, val, 8, 5, 0);      // reg to cp15

+    __DSB();

+    __ISB();

+}

+

+/******************************** BTB maintenance operations ************************************************/

+/** \brief  Invalidate entire branch predictor array

+

+    BPIALL. Branch Predictor Invalidate All.

+ */

+// from system_Renesas_RZ_A1.c

+__STATIC_INLINE void __v7_inv_btac(void) {

+	uint32_t val = 0;

+    __MCR(15, 0, val, 7, 5, 6);      // reg to cp15

+    __DSB();     //ensure completion of the invalidation

+    __ISB();     //ensure instruction fetch path sees new state

+}

+

+

+/******************************** L1 cache operations ******************************************************/

+

+/** \brief  Invalidate the whole I$

+

+    ICIALLU. Instruction Cache Invalidate All to PoU

+ */

+// from system_Renesas_RZ_A1.c

+__STATIC_INLINE void __v7_inv_icache_all(void) {

+	uint32_t val = 0;

+    __MCR(15, 0, val, 7, 5, 0);      // reg to cp15

+    __DSB();     //ensure completion of the invalidation

+    __ISB();     //ensure instruction fetch path sees new I cache state

+}

+

+// from __v7_inv_dcache_all()

+__arm static inline void __v7_all_cache(uint32_t op) {

+__asm(

+	"        ARM \n"

+

+	"        PUSH    {R4-R11} \n"

+

+	"        MRC     p15, 1, R6, c0, c0, 1\n"      // Read CLIDR

+	"        ANDS    R3, R6, #0x07000000\n"        // Extract coherency level

+	"        MOV     R3, R3, LSR #23\n"            // Total cache levels << 1

+	"        BEQ     Finished\n"                   // If 0, no need to clean

+

+	"        MOV     R10, #0\n"                    // R10 holds current cache level << 1

+    "Loop1:   ADD     R2, R10, R10, LSR #1\n"       // R2 holds cache "Set" position

+	"        MOV     R1, R6, LSR R2 \n"            // Bottom 3 bits are the Cache-type for this level

+	"        AND     R1, R1, #7 \n"                // Isolate those lower 3 bits

+	"        CMP     R1, #2 \n"

+	"        BLT     Skip \n"                      // No cache or only instruction cache at this level

+

+	"        MCR     p15, 2, R10, c0, c0, 0 \n"    // Write the Cache Size selection register

+	"        ISB \n"                               // ISB to sync the change to the CacheSizeID reg

+	"        MRC     p15, 1, R1, c0, c0, 0 \n"     // Reads current Cache Size ID register

+	"        AND     R2, R1, #7 \n"                // Extract the line length field

+	"        ADD     R2, R2, #4 \n"                // Add 4 for the line length offset (log2 16 bytes)

+	"        movw    R4, #0x3FF \n"

+	"        ANDS    R4, R4, R1, LSR #3 \n"        // R4 is the max number on the way size (right aligned)

+	"        CLZ     R5, R4 \n"                    // R5 is the bit position of the way size increment

+	"        movw    R7, #0x7FFF \n"

+	"        ANDS    R7, R7, R1, LSR #13 \n"       // R7 is the max number of the index size (right aligned)

+

+	"Loop2:   MOV     R9, R4 \n"                    // R9 working copy of the max way size (right aligned)

+

+	"Loop3:   ORR     R11, R10, R9, LSL R5 \n"      // Factor in the Way number and cache number into R11

+	"        ORR     R11, R11, R7, LSL R2 \n"      // Factor in the Set number

+	"        CMP     R0, #0 \n"

+	"        BNE     Dccsw \n"

+	"        MCR     p15, 0, R11, c7, c6, 2 \n"    // DCISW. Invalidate by Set/Way

+	"        B       cont \n"

+	"Dccsw:   CMP     R0, #1 \n"

+	"        BNE     Dccisw \n"

+	"        MCR     p15, 0, R11, c7, c10, 2 \n"   // DCCSW. Clean by Set/Way

+	"        B       cont \n"

+	"Dccisw:  MCR     p15, 0, R11, c7, c14, 2 \n"   // DCCISW, Clean and Invalidate by Set/Way

+	"cont:    SUBS    R9, R9, #1 \n"                // Decrement the Way number

+	"        BGE     Loop3 \n"

+	"        SUBS    R7, R7, #1 \n"                // Decrement the Set number

+	"        BGE     Loop2 \n"

+	"Skip:    ADD     R10, R10, #2 \n"              // increment the cache number

+	"        CMP     R3, R10 \n"

+	"        BGT     Loop1 \n"

+

+	"Finished: \n"

+	"        DSB \n"

+	"        POP    {R4-R11} \n"

+	"        BX     lr \n" );

+}

+

+/** \brief  Invalidate the whole D$

+

+    DCISW. Invalidate by Set/Way

+ */

+// from system_Renesas_RZ_A1.c

+__STATIC_INLINE void __v7_inv_dcache_all(void) {

+    __v7_all_cache(0);

+}

+#include "core_ca_mmu.h"

+

+#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/

+/* GNU gcc specific functions */

+

+#define MODE_USR 0x10

+#define MODE_FIQ 0x11

+#define MODE_IRQ 0x12

+#define MODE_SVC 0x13

+#define MODE_MON 0x16

+#define MODE_ABT 0x17

+#define MODE_HYP 0x1A

+#define MODE_UND 0x1B

+#define MODE_SYS 0x1F

+

+

+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)

+{

+    __ASM volatile ("cpsie i");

+}

+

+/** \brief  Disable IRQ Interrupts

+

+  This function disables IRQ interrupts by setting the I-bit in the CPSR.

+  Can only be executed in Privileged modes.

+ */

+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __disable_irq(void)

+{

+    uint32_t result;

+

+    __ASM volatile ("mrs %0, cpsr" : "=r" (result));

+    __ASM volatile ("cpsid i");

+    return(result & 0x80);

+}

+

+

+/** \brief  Get APSR Register

+

+    This function returns the content of the APSR Register.

+

+    \return               APSR Register value

+ */

+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)

+{

+#if 1

+  register uint32_t __regAPSR;

+  __ASM volatile ("mrs %0, apsr" : "=r" (__regAPSR) );

+#else

+  register uint32_t __regAPSR          __ASM("apsr");

+#endif

+  return(__regAPSR);

+}

+

+

+/** \brief  Get CPSR Register

+

+    This function returns the content of the CPSR Register.

+

+    \return               CPSR Register value

+ */

+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CPSR(void)

+{

+#if 1

+  register uint32_t __regCPSR;

+  __ASM volatile ("mrs %0, cpsr" : "=r" (__regCPSR));

+#else

+  register uint32_t __regCPSR          __ASM("cpsr");

+#endif

+  return(__regCPSR);

+}

+

+#if 0

+/** \brief  Set Stack Pointer

+

+    This function assigns the given value to the current stack pointer.

+

+    \param [in]    topOfStack  Stack Pointer value to set

+ */

+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_SP(uint32_t topOfStack)

+{

+    register uint32_t __regSP       __ASM("sp");

+    __regSP = topOfStack;

+}

+#endif

+

+/** \brief  Get link register

+

+    This function returns the value of the link register

+

+    \return    Value of link register

+ */

+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_LR(void)

+{

+  register uint32_t __reglr         __ASM("lr");

+  return(__reglr);

+}

+

+#if 0

+/** \brief  Set link register

+

+    This function sets the value of the link register

+

+    \param [in]    lr  LR value to set

+ */

+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_LR(uint32_t lr)

+{

+  register uint32_t __reglr         __ASM("lr");

+  __reglr = lr;

+}

+#endif

+

+/** \brief  Set Process Stack Pointer

+

+    This function assigns the given value to the USR/SYS Stack Pointer (PSP).

+

+    \param [in]    topOfProcStack  USR/SYS Stack Pointer value to set

+ */

+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)

+{

+    __asm__ volatile (

+    ".ARM;"

+    ".eabi_attribute Tag_ABI_align8_preserved,1;"

+

+    "BIC     R0, R0, #7;" /* ;ensure stack is 8-byte aligned */

+    "MRS     R1, CPSR;"

+    "CPS     %0;"         /* ;no effect in USR mode */

+    "MOV     SP, R0;"

+    "MSR     CPSR_c, R1;" /* ;no effect in USR mode */

+    "ISB;"

+    //"BX      LR;"

+    :

+    : "i"(MODE_SYS)

+    : "r0", "r1");

+    return;

+}

+

+/** \brief  Set User Mode

+

+    This function changes the processor state to User Mode

+ */

+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CPS_USR(void)

+{

+    __asm__ volatile (

+    ".ARM;"

+

+    "CPS  %0;"

+    //"BX   LR;"

+    :

+    : "i"(MODE_USR)

+    : );

+    return;

+}

+

+

+/** \brief  Enable FIQ

+

+    This function enables FIQ interrupts by clearing the F-bit in the CPSR.

+    Can only be executed in Privileged modes.

+ */

+#define __enable_fault_irq()                __asm__ volatile ("cpsie f")

+

+

+/** \brief  Disable FIQ

+

+    This function disables FIQ interrupts by setting the F-bit in the CPSR.

+    Can only be executed in Privileged modes.

+ */

+#define __disable_fault_irq()               __asm__ volatile ("cpsid f")

+

+

+/** \brief  Get FPSCR

+

+    This function returns the current value of the Floating Point Status/Control register.

+

+    \return               Floating Point Status/Control register value

+ */

+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)

+{

+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)

+#if 1

+    uint32_t result;

+

+    __ASM volatile ("vmrs %0, fpscr" : "=r" (result) );

+    return (result);

+#else

+  register uint32_t __regfpscr         __ASM("fpscr");

+  return(__regfpscr);

+#endif

+#else

+   return(0);

+#endif

+}

+

+

+/** \brief  Set FPSCR

+

+    This function assigns the given value to the Floating Point Status/Control register.

+

+    \param [in]    fpscr  Floating Point Status/Control value to set

+ */

+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)

+{

+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)

+#if 1

+    __ASM volatile ("vmsr fpscr, %0" : : "r" (fpscr) );

+#else

+  register uint32_t __regfpscr         __ASM("fpscr");

+  __regfpscr = (fpscr);

+#endif

+#endif

+}

+

+/** \brief  Get FPEXC

+

+    This function returns the current value of the Floating Point Exception Control register.

+

+    \return               Floating Point Exception Control register value

+ */

+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPEXC(void)

+{

+#if (__FPU_PRESENT == 1)

+#if 1

+    uint32_t result;

+

+    __ASM volatile ("vmrs %0, fpexc" : "=r" (result));

+    return (result);

+#else

+  register uint32_t __regfpexc         __ASM("fpexc");

+  return(__regfpexc);

+#endif

+#else

+   return(0);

+#endif

+}

+

+

+/** \brief  Set FPEXC

+

+    This function assigns the given value to the Floating Point Exception Control register.

+

+    \param [in]    fpscr  Floating Point Exception Control value to set

+ */

+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPEXC(uint32_t fpexc)

+{

+#if (__FPU_PRESENT == 1)

+#if 1

+    __ASM volatile ("vmsr fpexc, %0" : : "r" (fpexc));

+#else

+  register uint32_t __regfpexc         __ASM("fpexc");

+  __regfpexc = (fpexc);

+#endif

+#endif

+}

+

+/** \brief  Get CPACR

+

+    This function returns the current value of the Coprocessor Access Control register.

+

+    \return               Coprocessor Access Control register value

+ */

+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CPACR(void)

+{

+#if 1

+    register uint32_t __regCPACR;

+    __ASM volatile ("mrc p15, 0, %0, c1, c0, 2" : "=r" (__regCPACR));

+#else

+    register uint32_t __regCPACR         __ASM("cp15:0:c1:c0:2");

+#endif

+    return __regCPACR;

+}

+

+/** \brief  Set CPACR

+

+    This function assigns the given value to the Coprocessor Access Control register.

+

+    \param [in]    cpacr  Coprocessor Acccess Control value to set

+ */

+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CPACR(uint32_t cpacr)

+{

+#if 1

+    __ASM volatile ("mcr p15, 0, %0, c1, c0, 2" : : "r" (cpacr));

+#else

+    register uint32_t __regCPACR         __ASM("cp15:0:c1:c0:2");

+    __regCPACR = cpacr;

+#endif

+    __ISB();

+}

+

+/** \brief  Get CBAR

+

+    This function returns the value of the Configuration Base Address register.

+

+    \return               Configuration Base Address register value

+ */

+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CBAR() {

+#if 1

+    register uint32_t __regCBAR;

+    __ASM volatile ("mrc p15, 4, %0, c15, c0, 0" : "=r" (__regCBAR));

+#else

+    register uint32_t __regCBAR         __ASM("cp15:4:c15:c0:0");

+#endif

+    return(__regCBAR);

+}

+

+/** \brief  Get TTBR0

+

+    This function returns the value of the Translation Table Base Register 0.

+

+    \return               Translation Table Base Register 0 value

+ */

+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_TTBR0() {

+#if 1

+    register uint32_t __regTTBR0;

+    __ASM volatile ("mrc p15, 0, %0, c2, c0, 0" : "=r" (__regTTBR0));

+#else

+    register uint32_t __regTTBR0        __ASM("cp15:0:c2:c0:0");

+#endif

+    return(__regTTBR0);

+}

+

+/** \brief  Set TTBR0

+

+    This function assigns the given value to the Translation Table Base Register 0.

+

+    \param [in]    ttbr0  Translation Table Base Register 0 value to set

+ */

+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {

+#if 1

+	__ASM volatile ("mcr p15, 0, %0, c2, c0, 0" : : "r" (ttbr0));

+#else

+    register uint32_t __regTTBR0        __ASM("cp15:0:c2:c0:0");

+    __regTTBR0 = ttbr0;

+#endif

+    __ISB();

+}

+

+/** \brief  Get DACR

+

+    This function returns the value of the Domain Access Control Register.

+

+    \return               Domain Access Control Register value

+ */

+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_DACR() {

+#if 1

+    register uint32_t __regDACR;

+    __ASM volatile ("mrc p15, 0, %0, c3, c0, 0" : "=r" (__regDACR));

+#else

+    register uint32_t __regDACR         __ASM("cp15:0:c3:c0:0");

+#endif

+    return(__regDACR);

+}

+

+/** \brief  Set DACR

+

+    This function assigns the given value to the Domain Access Control Register.

+

+    \param [in]    dacr   Domain Access Control Register value to set

+ */

+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_DACR(uint32_t dacr) {

+#if 1

+	__ASM volatile ("mcr p15, 0, %0, c3, c0, 0" : : "r" (dacr));

+#else

+    register uint32_t __regDACR         __ASM("cp15:0:c3:c0:0");

+    __regDACR = dacr;

+#endif

+    __ISB();

+}

+

+/******************************** Cache and BTAC enable  ****************************************************/

+

+/** \brief  Set SCTLR

+

+    This function assigns the given value to the System Control Register.

+

+    \param [in]    sctlr  System Control Register value to set

+ */

+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_SCTLR(uint32_t sctlr)

+{

+#if 1

+	__ASM volatile ("mcr p15, 0, %0, c1, c0, 0" : : "r" (sctlr));

+#else

+    register uint32_t __regSCTLR         __ASM("cp15:0:c1:c0:0");

+    __regSCTLR = sctlr;

+#endif

+}

+

+/** \brief  Get SCTLR

+

+    This function returns the value of the System Control Register.

+

+    \return               System Control Register value

+ */

+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_SCTLR() {

+#if 1

+	register uint32_t __regSCTLR;

+	__ASM volatile ("mrc p15, 0, %0, c1, c0, 0" : "=r" (__regSCTLR));

+#else

+    register uint32_t __regSCTLR         __ASM("cp15:0:c1:c0:0");

+#endif

+    return(__regSCTLR);

+}

+

+/** \brief  Enable Caches

+

+    Enable Caches

+ */

+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_caches(void) {

+    // Set I bit 12 to enable I Cache

+    // Set C bit  2 to enable D Cache

+    __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));

+}

+

+/** \brief  Disable Caches

+

+    Disable Caches

+ */

+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_caches(void) {

+    // Clear I bit 12 to disable I Cache

+    // Clear C bit  2 to disable D Cache

+    __set_SCTLR( __get_SCTLR() & ~(1 << 12) & ~(1 << 2));

+    __ISB();

+}

+

+/** \brief  Enable BTAC

+

+    Enable BTAC

+ */

+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_btac(void) {

+    // Set Z bit 11 to enable branch prediction

+    __set_SCTLR( __get_SCTLR() | (1 << 11));

+    __ISB();

+}

+

+/** \brief  Disable BTAC

+

+    Disable BTAC

+ */

+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_btac(void) {

+    // Clear Z bit 11 to disable branch prediction

+    __set_SCTLR( __get_SCTLR() & ~(1 << 11));

+}

+

+

+/** \brief  Enable MMU

+

+    Enable MMU

+ */

+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_mmu(void) {

+    // Set M bit 0 to enable the MMU

+    // Set AFE bit to enable simplified access permissions model

+    // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking

+    __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));

+    __ISB();

+}

+

+/** \brief  Disable MMU

+

+    Disable MMU

+ */

+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_mmu(void) {

+    // Clear M bit 0 to disable the MMU

+    __set_SCTLR( __get_SCTLR() & ~1);

+    __ISB();

+}

+

+/******************************** TLB maintenance operations ************************************************/

+/** \brief  Invalidate the whole tlb

+

+    TLBIALL. Invalidate the whole tlb

+ */

+

+__attribute__( ( always_inline ) ) __STATIC_INLINE void __ca9u_inv_tlb_all(void) {

+#if 1

+	__ASM volatile ("mcr p15, 0, %0, c8, c7, 0" : : "r" (0));

+#else

+    register uint32_t __TLBIALL         __ASM("cp15:0:c8:c7:0");

+    __TLBIALL = 0;

+#endif

+    __DSB();

+    __ISB();

+}

+

+/******************************** BTB maintenance operations ************************************************/

+/** \brief  Invalidate entire branch predictor array

+

+    BPIALL. Branch Predictor Invalidate All.

+ */

+

+__attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_btac(void) {

+#if 1

+	__ASM volatile ("mcr p15, 0, %0, c7, c5, 6" : : "r" (0));

+#else

+    register uint32_t __BPIALL          __ASM("cp15:0:c7:c5:6");

+    __BPIALL  = 0;

+#endif

+    __DSB();     //ensure completion of the invalidation

+    __ISB();     //ensure instruction fetch path sees new state

+}

+

+

+/******************************** L1 cache operations ******************************************************/

+

+/** \brief  Invalidate the whole I$

+

+    ICIALLU. Instruction Cache Invalidate All to PoU

+ */

+__attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_icache_all(void) {

+#if 1

+	__ASM volatile ("mcr p15, 0, %0, c7, c5, 0" : : "r" (0));

+#else

+    register uint32_t __ICIALLU         __ASM("cp15:0:c7:c5:0");

+    __ICIALLU = 0;

+#endif

+    __DSB();     //ensure completion of the invalidation

+    __ISB();     //ensure instruction fetch path sees new I cache state

+}

+

+/** \brief  Clean D$ by MVA

+

+    DCCMVAC. Data cache clean by MVA to PoC

+ */

+__attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_dcache_mva(void *va) {

+#if 1

+    __ASM volatile ("mcr p15, 0, %0, c7, c10, 1" : : "r" ((uint32_t)va));

+#else

+    register uint32_t __DCCMVAC         __ASM("cp15:0:c7:c10:1");

+    __DCCMVAC = (uint32_t)va;

+#endif

+    __DMB();     //ensure the ordering of data cache maintenance operations and their effects

+}

+

+/** \brief  Invalidate D$ by MVA

+

+    DCIMVAC. Data cache invalidate by MVA to PoC

+ */

+__attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_dcache_mva(void *va) {

+#if 1

+    __ASM volatile ("mcr p15, 0, %0, c7, c6, 1" : : "r" ((uint32_t)va));

+#else

+    register uint32_t __DCIMVAC         __ASM("cp15:0:c7:c6:1");

+    __DCIMVAC = (uint32_t)va;

+#endif

+    __DMB();     //ensure the ordering of data cache maintenance operations and their effects

+}

+

+/** \brief  Clean and Invalidate D$ by MVA

+

+    DCCIMVAC. Data cache clean and invalidate by MVA to PoC

+ */

+__attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {

+#if 1

+    __ASM volatile ("mcr p15, 0, %0, c7, c14, 1" : : "r" ((uint32_t)va));

+#else

+    register uint32_t __DCCIMVAC        __ASM("cp15:0:c7:c14:1");

+    __DCCIMVAC = (uint32_t)va;

+#endif

+    __DMB();     //ensure the ordering of data cache maintenance operations and their effects

+}

+

+/** \brief  Clean and Invalidate the entire data or unified cache

+

+    Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency.

+ */

+extern void __v7_all_cache(uint32_t op);

+

+

+/** \brief  Invalidate the whole D$

+

+    DCISW. Invalidate by Set/Way

+ */

+

+__attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_dcache_all(void) {

+    __v7_all_cache(0);

+}

+

+/** \brief  Clean the whole D$

+

+    DCCSW. Clean by Set/Way

+ */

+

+__attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_dcache_all(void) {

+    __v7_all_cache(1);

+}

+

+/** \brief  Clean and invalidate the whole D$

+

+    DCCISW. Clean and Invalidate by Set/Way

+ */

+

+__attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_inv_dcache_all(void) {

+    __v7_all_cache(2);

+}

+

+#include "core_ca_mmu.h"

+

+#elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/

+

+#error TASKING Compiler support not implemented for Cortex-A

+

+#endif

+

+/*@} end of CMSIS_Core_RegAccFunctions */

+

+

+#endif /* __CORE_CAFUNC_H__ */

diff --git a/ext/TARGET_LPC1768/core_caInstr.h b/ext/TARGET_LPC1768/core_caInstr.h
new file mode 100644
index 0000000..82809b5
--- /dev/null
+++ b/ext/TARGET_LPC1768/core_caInstr.h
@@ -0,0 +1,45 @@
+/**************************************************************************//**

+ * @file     core_caInstr.h

+ * @brief    CMSIS Cortex-A9 Core Peripheral Access Layer Header File

+ * @version

+ * @date     04. December 2012

+ *

+ * @note

+ *

+ ******************************************************************************/

+/* Copyright (c) 2009 - 2012 ARM LIMITED

+

+   All rights reserved.

+   Redistribution and use in source and binary forms, with or without

+   modification, are permitted provided that the following conditions are met:

+   - Redistributions of source code must retain the above copyright

+     notice, this list of conditions and the following disclaimer.

+   - Redistributions in binary form must reproduce the above copyright

+     notice, this list of conditions and the following disclaimer in the

+     documentation and/or other materials provided with the distribution.

+   - Neither the name of ARM nor the names of its contributors may be used

+     to endorse or promote products derived from this software without

+     specific prior written permission.

+   *

+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"

+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE

+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE

+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE

+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR

+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF

+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS

+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN

+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)

+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE

+   POSSIBILITY OF SUCH DAMAGE.

+   ---------------------------------------------------------------------------*/

+

+#ifndef __CORE_CAINSTR_H__

+#define __CORE_CAINSTR_H__

+

+#define __CORTEX_M 0x3

+#include "core_cmInstr.h"

+#undef  __CORTEX_M

+

+#endif

+

diff --git a/ext/TARGET_LPC1768/core_ca_mmu.h b/ext/TARGET_LPC1768/core_ca_mmu.h
new file mode 100644
index 0000000..3ce170d
--- /dev/null
+++ b/ext/TARGET_LPC1768/core_ca_mmu.h
@@ -0,0 +1,847 @@
+;/**************************************************************************//**

+; * @file     core_ca_mmu.h

+; * @brief    MMU Startup File for A9_MP Device Series

+; * @version  V1.01

+; * @date     10 Sept 2014

+; *

+; * @note

+; *

+; ******************************************************************************/

+;/* Copyright (c) 2012-2014 ARM LIMITED

+;

+;   All rights reserved.

+;   Redistribution and use in source and binary forms, with or without

+;   modification, are permitted provided that the following conditions are met:

+;   - Redistributions of source code must retain the above copyright

+;     notice, this list of conditions and the following disclaimer.

+;   - Redistributions in binary form must reproduce the above copyright

+;     notice, this list of conditions and the following disclaimer in the

+;     documentation and/or other materials provided with the distribution.

+;   - Neither the name of ARM nor the names of its contributors may be used

+;     to endorse or promote products derived from this software without

+;     specific prior written permission.

+;   *

+;   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"

+;   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE

+;   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE

+;   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE

+;   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR

+;   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF

+;   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS

+;   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN

+;   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)

+;   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE

+;   POSSIBILITY OF SUCH DAMAGE.

+;   ---------------------------------------------------------------------------*/

+

+#ifdef __cplusplus

+ extern "C" {

+#endif

+

+#ifndef _MMU_FUNC_H

+#define _MMU_FUNC_H

+

+#define SECTION_DESCRIPTOR      (0x2)

+#define SECTION_MASK            (0xFFFFFFFC)

+

+#define SECTION_TEXCB_MASK      (0xFFFF8FF3)

+#define SECTION_B_SHIFT         (2)

+#define SECTION_C_SHIFT         (3)

+#define SECTION_TEX0_SHIFT      (12)

+#define SECTION_TEX1_SHIFT      (13)

+#define SECTION_TEX2_SHIFT      (14)

+

+#define SECTION_XN_MASK         (0xFFFFFFEF)

+#define SECTION_XN_SHIFT        (4)

+

+#define SECTION_DOMAIN_MASK     (0xFFFFFE1F)

+#define SECTION_DOMAIN_SHIFT    (5)

+

+#define SECTION_P_MASK          (0xFFFFFDFF)

+#define SECTION_P_SHIFT         (9)

+

+#define SECTION_AP_MASK         (0xFFFF73FF)

+#define SECTION_AP_SHIFT        (10)

+#define SECTION_AP2_SHIFT       (15)

+

+#define SECTION_S_MASK          (0xFFFEFFFF)

+#define SECTION_S_SHIFT         (16)

+

+#define SECTION_NG_MASK         (0xFFFDFFFF)

+#define SECTION_NG_SHIFT        (17)

+

+#define SECTION_NS_MASK         (0xFFF7FFFF)

+#define SECTION_NS_SHIFT        (19)

+

+

+#define PAGE_L1_DESCRIPTOR      (0x1)

+#define PAGE_L1_MASK            (0xFFFFFFFC)

+

+#define PAGE_L2_4K_DESC         (0x2)

+#define PAGE_L2_4K_MASK         (0xFFFFFFFD)

+

+#define PAGE_L2_64K_DESC        (0x1)

+#define PAGE_L2_64K_MASK        (0xFFFFFFFC)

+

+#define PAGE_4K_TEXCB_MASK      (0xFFFFFE33)

+#define PAGE_4K_B_SHIFT         (2)

+#define PAGE_4K_C_SHIFT         (3)

+#define PAGE_4K_TEX0_SHIFT      (6)

+#define PAGE_4K_TEX1_SHIFT      (7)

+#define PAGE_4K_TEX2_SHIFT      (8)

+

+#define PAGE_64K_TEXCB_MASK     (0xFFFF8FF3)

+#define PAGE_64K_B_SHIFT        (2)

+#define PAGE_64K_C_SHIFT        (3)

+#define PAGE_64K_TEX0_SHIFT     (12)

+#define PAGE_64K_TEX1_SHIFT     (13)

+#define PAGE_64K_TEX2_SHIFT     (14)

+

+#define PAGE_TEXCB_MASK         (0xFFFF8FF3)

+#define PAGE_B_SHIFT            (2)

+#define PAGE_C_SHIFT            (3)

+#define PAGE_TEX_SHIFT          (12)

+

+#define PAGE_XN_4K_MASK         (0xFFFFFFFE)

+#define PAGE_XN_4K_SHIFT        (0)

+#define PAGE_XN_64K_MASK        (0xFFFF7FFF)

+#define PAGE_XN_64K_SHIFT       (15)

+

+

+#define PAGE_DOMAIN_MASK        (0xFFFFFE1F)

+#define PAGE_DOMAIN_SHIFT       (5)

+

+#define PAGE_P_MASK             (0xFFFFFDFF)

+#define PAGE_P_SHIFT            (9)

+

+#define PAGE_AP_MASK            (0xFFFFFDCF)

+#define PAGE_AP_SHIFT           (4)

+#define PAGE_AP2_SHIFT          (9)

+

+#define PAGE_S_MASK             (0xFFFFFBFF)

+#define PAGE_S_SHIFT            (10)

+

+#define PAGE_NG_MASK            (0xFFFFF7FF)

+#define PAGE_NG_SHIFT           (11)

+

+#define PAGE_NS_MASK            (0xFFFFFFF7)

+#define PAGE_NS_SHIFT           (3)

+

+#define OFFSET_1M               (0x00100000)

+#define OFFSET_64K              (0x00010000)

+#define OFFSET_4K               (0x00001000)

+

+#define DESCRIPTOR_FAULT        (0x00000000)

+

+/* ###########################  MMU Function Access  ########################### */

+/** \ingroup  MMU_FunctionInterface

+    \defgroup MMU_Functions MMU Functions Interface

+  @{

+ */

+

+/* Attributes enumerations */

+

+/* Region size attributes */

+typedef enum

+{

+   SECTION,

+   PAGE_4k,

+   PAGE_64k,

+} mmu_region_size_Type;

+

+/* Region type attributes */

+typedef enum

+{

+   NORMAL,

+   DEVICE,

+   SHARED_DEVICE,

+   NON_SHARED_DEVICE,

+   STRONGLY_ORDERED

+} mmu_memory_Type;

+

+/* Region cacheability attributes */

+typedef enum

+{

+   NON_CACHEABLE,

+   WB_WA,

+   WT,

+   WB_NO_WA,

+} mmu_cacheability_Type;

+

+/* Region parity check attributes */

+typedef enum

+{

+   ECC_DISABLED,

+   ECC_ENABLED,

+} mmu_ecc_check_Type;

+

+/* Region execution attributes */

+typedef enum

+{

+   EXECUTE,

+   NON_EXECUTE,

+} mmu_execute_Type;

+

+/* Region global attributes */

+typedef enum

+{

+   GLOBAL,

+   NON_GLOBAL,

+} mmu_global_Type;

+

+/* Region shareability attributes */

+typedef enum

+{

+   NON_SHARED,

+   SHARED,

+} mmu_shared_Type;

+

+/* Region security attributes */

+typedef enum

+{

+   SECURE,

+   NON_SECURE,

+} mmu_secure_Type;

+

+/* Region access attributes */

+typedef enum

+{

+   NO_ACCESS,

+   RW,

+   READ,

+} mmu_access_Type;

+

+/* Memory Region definition */

+typedef struct RegionStruct {

+    mmu_region_size_Type rg_t;

+    mmu_memory_Type mem_t;

+    uint8_t domain;

+    mmu_cacheability_Type inner_norm_t;

+    mmu_cacheability_Type outer_norm_t;

+    mmu_ecc_check_Type e_t;

+    mmu_execute_Type xn_t;

+    mmu_global_Type g_t;

+    mmu_secure_Type sec_t;

+    mmu_access_Type priv_t;

+    mmu_access_Type user_t;

+    mmu_shared_Type sh_t;

+

+} mmu_region_attributes_Type;

+

+/** \brief  Set section execution-never attribute

+

+    The function sets section execution-never attribute

+

+    \param [out]    descriptor_l1  L1 descriptor.

+    \param [in]                xn  Section execution-never attribute : EXECUTE , NON_EXECUTE.

+

+    \return          0  

+ */

+__STATIC_INLINE int __xn_section(uint32_t *descriptor_l1, mmu_execute_Type xn)

+{

+    *descriptor_l1 &= SECTION_XN_MASK;

+    *descriptor_l1 |= ((xn & 0x1) << SECTION_XN_SHIFT);

+    return 0;

+}

+

+/** \brief  Set section domain

+

+    The function sets section domain

+

+    \param [out]    descriptor_l1  L1 descriptor.

+    \param [in]            domain  Section domain

+

+    \return          0  

+ */

+__STATIC_INLINE int __domain_section(uint32_t *descriptor_l1, uint8_t domain)

+{

+    *descriptor_l1 &= SECTION_DOMAIN_MASK;

+    *descriptor_l1 |= ((domain & 0xF) << SECTION_DOMAIN_SHIFT);

+    return 0;

+}

+

+/** \brief  Set section parity check

+

+    The function sets section parity check

+

+    \param [out]    descriptor_l1  L1 descriptor.

+    \param [in]              p_bit Parity check: ECC_DISABLED, ECC_ENABLED

+

+    \return          0  

+ */

+__STATIC_INLINE int __p_section(uint32_t *descriptor_l1, mmu_ecc_check_Type p_bit)

+{

+    *descriptor_l1 &= SECTION_P_MASK;

+    *descriptor_l1 |= ((p_bit & 0x1) << SECTION_P_SHIFT);

+    return 0;

+}

+

+/** \brief  Set section access privileges

+

+    The function sets section access privileges

+

+    \param [out]    descriptor_l1  L1 descriptor.

+    \param [in]              user  User Level Access: NO_ACCESS, RW, READ

+    \param [in]              priv  Privilege Level Access: NO_ACCESS, RW, READ

+    \param [in]               afe  Access flag enable

+

+    \return          0  

+ */

+__STATIC_INLINE int __ap_section(uint32_t *descriptor_l1, mmu_access_Type user, mmu_access_Type priv,  uint32_t afe)

+{

+    uint32_t ap = 0;

+

+    if (afe == 0) { //full access

+        if ((priv == NO_ACCESS) && (user == NO_ACCESS)) { ap = 0x0; }

+        else if ((priv == RW) && (user == NO_ACCESS))   { ap = 0x1; }

+        else if ((priv == RW) && (user == READ))        { ap = 0x2; }

+        else if ((priv == RW) && (user == RW))          { ap = 0x3; }

+        else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }

+        else if ((priv == READ) && (user == READ))      { ap = 0x7; }

+    }

+

+    else { //Simplified access

+        if ((priv == RW) && (user == NO_ACCESS))        { ap = 0x1; }

+        else if ((priv == RW) && (user == RW))          { ap = 0x3; }

+        else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }

+        else if ((priv == READ) && (user == READ))      { ap = 0x7; }

+    }

+

+    *descriptor_l1 &= SECTION_AP_MASK;

+    *descriptor_l1 |= (ap & 0x3) << SECTION_AP_SHIFT;

+    *descriptor_l1 |= ((ap & 0x4)>>2) << SECTION_AP2_SHIFT;

+

+    return 0;

+}

+

+/** \brief  Set section shareability

+

+    The function sets section shareability

+

+    \param [out]    descriptor_l1  L1 descriptor.

+    \param [in]             s_bit  Section shareability: NON_SHARED, SHARED

+

+    \return          0  

+ */

+__STATIC_INLINE int __shared_section(uint32_t *descriptor_l1, mmu_shared_Type s_bit)

+{

+    *descriptor_l1 &= SECTION_S_MASK;

+    *descriptor_l1 |= ((s_bit & 0x1) << SECTION_S_SHIFT);

+    return 0;

+}

+

+/** \brief  Set section Global attribute

+

+    The function sets section Global attribute

+

+    \param [out]    descriptor_l1  L1 descriptor.

+    \param [in]             g_bit  Section attribute: GLOBAL, NON_GLOBAL

+

+    \return          0  

+ */

+__STATIC_INLINE int __global_section(uint32_t *descriptor_l1, mmu_global_Type g_bit)

+{

+    *descriptor_l1 &= SECTION_NG_MASK;

+    *descriptor_l1 |= ((g_bit & 0x1) << SECTION_NG_SHIFT);

+    return 0;

+}

+

+/** \brief  Set section Security attribute

+

+    The function sets section Global attribute

+

+    \param [out]    descriptor_l1  L1 descriptor.

+    \param [in]             s_bit  Section Security attribute: SECURE, NON_SECURE

+

+    \return          0  

+ */

+__STATIC_INLINE int __secure_section(uint32_t *descriptor_l1, mmu_secure_Type s_bit)

+{

+    *descriptor_l1 &= SECTION_NS_MASK;

+    *descriptor_l1 |= ((s_bit & 0x1) << SECTION_NS_SHIFT);

+    return 0;

+}

+

+/* Page 4k or 64k */

+/** \brief  Set 4k/64k page execution-never attribute

+

+    The function sets 4k/64k page execution-never attribute

+

+    \param [out]    descriptor_l2  L2 descriptor.

+    \param [in]                xn  Page execution-never attribute : EXECUTE , NON_EXECUTE.

+    \param [in]              page  Page size: PAGE_4k, PAGE_64k,

+   

+    \return          0  

+ */

+__STATIC_INLINE int __xn_page(uint32_t *descriptor_l2, mmu_execute_Type xn, mmu_region_size_Type page)

+{

+    if (page == PAGE_4k)

+    {

+        *descriptor_l2 &= PAGE_XN_4K_MASK;

+        *descriptor_l2 |= ((xn & 0x1) << PAGE_XN_4K_SHIFT);

+    }

+    else

+    {

+        *descriptor_l2 &= PAGE_XN_64K_MASK;

+        *descriptor_l2 |= ((xn & 0x1) << PAGE_XN_64K_SHIFT);

+    }

+    return 0;

+}

+

+/** \brief  Set 4k/64k page domain

+

+    The function sets 4k/64k page domain

+

+    \param [out]    descriptor_l1  L1 descriptor.

+    \param [in]            domain  Page domain

+

+    \return          0  

+ */

+__STATIC_INLINE int __domain_page(uint32_t *descriptor_l1, uint8_t domain)

+{

+    *descriptor_l1 &= PAGE_DOMAIN_MASK;

+    *descriptor_l1 |= ((domain & 0xf) << PAGE_DOMAIN_SHIFT);

+    return 0;

+}

+

+/** \brief  Set 4k/64k page parity check

+

+    The function sets 4k/64k page parity check

+

+    \param [out]    descriptor_l1  L1 descriptor.

+    \param [in]              p_bit Parity check: ECC_DISABLED, ECC_ENABLED

+

+    \return          0  

+ */

+__STATIC_INLINE int __p_page(uint32_t *descriptor_l1, mmu_ecc_check_Type p_bit)

+{

+    *descriptor_l1 &= SECTION_P_MASK;

+    *descriptor_l1 |= ((p_bit & 0x1) << SECTION_P_SHIFT);

+    return 0;

+}

+

+/** \brief  Set 4k/64k page access privileges

+

+    The function sets 4k/64k page access privileges

+

+    \param [out]    descriptor_l2  L2 descriptor.

+    \param [in]              user  User Level Access: NO_ACCESS, RW, READ

+    \param [in]              priv  Privilege Level Access: NO_ACCESS, RW, READ

+    \param [in]               afe  Access flag enable

+

+    \return          0  

+ */

+__STATIC_INLINE int __ap_page(uint32_t *descriptor_l2, mmu_access_Type user, mmu_access_Type priv,  uint32_t afe)

+{

+    uint32_t ap = 0;

+

+    if (afe == 0) { //full access

+        if ((priv == NO_ACCESS) && (user == NO_ACCESS)) { ap = 0x0; }

+        else if ((priv == RW) && (user == NO_ACCESS))   { ap = 0x1; }

+        else if ((priv == RW) && (user == READ))        { ap = 0x2; }

+        else if ((priv == RW) && (user == RW))          { ap = 0x3; }

+        else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }

+        else if ((priv == READ) && (user == READ))      { ap = 0x6; }

+    }

+

+    else { //Simplified access

+        if ((priv == RW) && (user == NO_ACCESS))        { ap = 0x1; }

+        else if ((priv == RW) && (user == RW))          { ap = 0x3; }

+        else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }

+        else if ((priv == READ) && (user == READ))      { ap = 0x7; }

+    }

+

+    *descriptor_l2 &= PAGE_AP_MASK;

+    *descriptor_l2 |= (ap & 0x3) << PAGE_AP_SHIFT;

+    *descriptor_l2 |= ((ap & 0x4)>>2) << PAGE_AP2_SHIFT;

+

+    return 0;

+}

+

+/** \brief  Set 4k/64k page shareability

+

+    The function sets 4k/64k page shareability

+

+    \param [out]    descriptor_l2  L2 descriptor.

+    \param [in]             s_bit  4k/64k page shareability: NON_SHARED, SHARED

+

+    \return          0  

+ */

+__STATIC_INLINE int __shared_page(uint32_t *descriptor_l2, mmu_shared_Type s_bit)

+{

+    *descriptor_l2 &= PAGE_S_MASK;

+    *descriptor_l2 |= ((s_bit & 0x1) << PAGE_S_SHIFT);

+    return 0;

+}

+

+/** \brief  Set 4k/64k page Global attribute

+

+    The function sets 4k/64k page Global attribute

+

+    \param [out]    descriptor_l2  L2 descriptor.

+    \param [in]             g_bit  4k/64k page attribute: GLOBAL, NON_GLOBAL

+

+    \return          0  

+ */

+__STATIC_INLINE int __global_page(uint32_t *descriptor_l2, mmu_global_Type g_bit)

+{

+    *descriptor_l2 &= PAGE_NG_MASK;

+    *descriptor_l2 |= ((g_bit & 0x1) << PAGE_NG_SHIFT);

+    return 0;

+}

+

+/** \brief  Set 4k/64k page Security attribute

+

+    The function sets 4k/64k page Global attribute

+

+    \param [out]    descriptor_l1  L1 descriptor.

+    \param [in]             s_bit  4k/64k page Security attribute: SECURE, NON_SECURE

+

+    \return          0  

+ */

+__STATIC_INLINE int __secure_page(uint32_t *descriptor_l1, mmu_secure_Type s_bit)

+{

+    *descriptor_l1 &= PAGE_NS_MASK;

+    *descriptor_l1 |= ((s_bit & 0x1) << PAGE_NS_SHIFT);

+    return 0;

+}

+

+

+/** \brief  Set Section memory attributes

+

+    The function sets section memory attributes

+

+    \param [out]    descriptor_l1  L1 descriptor.

+    \param [in]               mem  Section memory type: NORMAL, DEVICE, SHARED_DEVICE, NON_SHARED_DEVICE, STRONGLY_ORDERED

+    \param [in]             outer  Outer cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,

+    \param [in]             inner  Inner cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,

+

+    \return          0  

+ */

+__STATIC_INLINE int __memory_section(uint32_t *descriptor_l1, mmu_memory_Type mem, mmu_cacheability_Type outer, mmu_cacheability_Type inner)

+{

+    *descriptor_l1 &= SECTION_TEXCB_MASK;

+

+    if (STRONGLY_ORDERED == mem)

+    {

+        return 0;

+    }

+    else if (SHARED_DEVICE == mem)

+    {

+        *descriptor_l1 |= (1 << SECTION_B_SHIFT);

+    }

+    else if (NON_SHARED_DEVICE == mem)

+    {

+        *descriptor_l1 |= (1 << SECTION_TEX1_SHIFT);

+    }

+    else if (NORMAL == mem)

+    {

+           *descriptor_l1 |= 1 << SECTION_TEX2_SHIFT;

+           switch(inner)

+           {

+            case NON_CACHEABLE:

+            break;

+            case WB_WA:

+                *descriptor_l1 |= (1 << SECTION_B_SHIFT);

+                break;

+            case WT:

+                *descriptor_l1 |= 1 << SECTION_C_SHIFT;

+                break;

+            case WB_NO_WA:

+                *descriptor_l1 |= (1 << SECTION_B_SHIFT) | (1 << SECTION_C_SHIFT);

+                break;

+        }

+        switch(outer)

+        {

+            case NON_CACHEABLE:

+             break;

+            case WB_WA:

+                *descriptor_l1 |= (1 << SECTION_TEX0_SHIFT);

+                break;

+            case WT:

+                *descriptor_l1 |= 1 << SECTION_TEX1_SHIFT;

+                break;

+            case WB_NO_WA:

+                *descriptor_l1 |= (1 << SECTION_TEX0_SHIFT) | (1 << SECTION_TEX0_SHIFT);

+                break;

+        }

+    }

+

+    return 0;

+}

+

+/** \brief  Set 4k/64k page memory attributes

+

+    The function sets 4k/64k page memory attributes

+

+    \param [out]    descriptor_l2  L2 descriptor.

+    \param [in]               mem  4k/64k page memory type: NORMAL, DEVICE, SHARED_DEVICE, NON_SHARED_DEVICE, STRONGLY_ORDERED

+    \param [in]             outer  Outer cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,

+    \param [in]             inner  Inner cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,

+

+    \return          0  

+ */

+__STATIC_INLINE int __memory_page(uint32_t *descriptor_l2, mmu_memory_Type mem, mmu_cacheability_Type outer, mmu_cacheability_Type inner, mmu_region_size_Type page)

+{

+    *descriptor_l2 &= PAGE_4K_TEXCB_MASK;

+

+    if (page == PAGE_64k)

+    {

+        //same as section

+        __memory_section(descriptor_l2, mem, outer, inner);

+    }

+    else

+    {

+        if (STRONGLY_ORDERED == mem)

+        {

+            return 0;

+        }

+        else if (SHARED_DEVICE == mem)

+        {

+            *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT);

+        }

+        else if (NON_SHARED_DEVICE == mem)

+        {

+             *descriptor_l2 |= (1 << PAGE_4K_TEX1_SHIFT);

+        }

+        else if (NORMAL == mem)

+        {

+            *descriptor_l2 |= 1 << PAGE_4K_TEX2_SHIFT;

+            switch(inner)

+            {

+                case NON_CACHEABLE:

+                break;

+                case WB_WA:

+                     *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT);

+                     break;

+                case WT:

+                    *descriptor_l2 |= 1 << PAGE_4K_C_SHIFT;

+                     break;

+                case WB_NO_WA:

+                    *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT) | (1 << PAGE_4K_C_SHIFT);

+                    break;

+            }

+            switch(outer)

+            {

+                case NON_CACHEABLE:

+                break;

+                case WB_WA:

+                      *descriptor_l2 |= (1 << PAGE_4K_TEX0_SHIFT);

+                    break;

+                case WT:

+                     *descriptor_l2 |= 1 << PAGE_4K_TEX1_SHIFT;

+                    break;

+                case WB_NO_WA:

+                    *descriptor_l2 |= (1 << PAGE_4K_TEX0_SHIFT) | (1 << PAGE_4K_TEX0_SHIFT);

+                    break;

+            }

+        }

+    }

+

+    return 0;

+}

+

+/** \brief  Create a L1 section descriptor

+

+    The function creates a section descriptor.

+    

+    Assumptions:

+    - 16MB super sections not supported

+    - TEX remap disabled, so memory type and attributes are described directly by bits in the descriptor

+    - Functions always return 0

+

+    \param [out]       descriptor  L1 descriptor

+    \param [out]      descriptor2  L2 descriptor

+    \param [in]               reg  Section attributes

+

+    \return          0  

+ */

+__STATIC_INLINE int __get_section_descriptor(uint32_t *descriptor, mmu_region_attributes_Type reg)

+{

+    *descriptor  = 0;

+

+   __memory_section(descriptor, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t);

+   __xn_section(descriptor,reg.xn_t);

+   __domain_section(descriptor, reg.domain);

+   __p_section(descriptor, reg.e_t);

+   __ap_section(descriptor, reg.priv_t, reg.user_t, 1);

+   __shared_section(descriptor,reg.sh_t);

+   __global_section(descriptor,reg.g_t);

+   __secure_section(descriptor,reg.sec_t);

+   *descriptor &= SECTION_MASK;

+   *descriptor |= SECTION_DESCRIPTOR;

+

+   return 0;

+

+}

+

+

+/** \brief  Create a L1 and L2 4k/64k page descriptor

+

+    The function creates a 4k/64k page descriptor.

+    Assumptions:

+    - TEX remap disabled, so memory type and attributes are described directly by bits in the descriptor

+    - Functions always return 0

+

+    \param [out]       descriptor  L1 descriptor

+    \param [out]      descriptor2  L2 descriptor

+    \param [in]               reg  4k/64k page attributes

+

+    \return          0  

+ */

+__STATIC_INLINE int __get_page_descriptor(uint32_t *descriptor, uint32_t *descriptor2, mmu_region_attributes_Type reg)

+{

+    *descriptor  = 0;

+    *descriptor2 = 0;

+

+    switch (reg.rg_t)

+    {

+        case PAGE_4k:

+            __memory_page(descriptor2, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t, PAGE_4k);

+            __xn_page(descriptor2, reg.xn_t, PAGE_4k);

+            __domain_page(descriptor, reg.domain);

+            __p_page(descriptor, reg.e_t);

+            __ap_page(descriptor2, reg.priv_t, reg.user_t, 1);

+            __shared_page(descriptor2,reg.sh_t);

+            __global_page(descriptor2,reg.g_t);

+            __secure_page(descriptor,reg.sec_t);

+            *descriptor &= PAGE_L1_MASK;

+            *descriptor |= PAGE_L1_DESCRIPTOR;

+            *descriptor2 &= PAGE_L2_4K_MASK;

+            *descriptor2 |= PAGE_L2_4K_DESC;

+            break;

+

+        case PAGE_64k:

+            __memory_page(descriptor2, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t, PAGE_64k);

+            __xn_page(descriptor2, reg.xn_t, PAGE_64k);

+            __domain_page(descriptor, reg.domain);

+            __p_page(descriptor, reg.e_t);

+            __ap_page(descriptor2, reg.priv_t, reg.user_t, 1);

+            __shared_page(descriptor2,reg.sh_t);

+            __global_page(descriptor2,reg.g_t);

+            __secure_page(descriptor,reg.sec_t);

+            *descriptor &= PAGE_L1_MASK;

+            *descriptor |= PAGE_L1_DESCRIPTOR;

+            *descriptor2 &= PAGE_L2_64K_MASK;

+            *descriptor2 |= PAGE_L2_64K_DESC;

+            break;

+

+        case SECTION:

+            //error

+            break;    

+

+    }

+

+   return 0;

+

+}

+

+/** \brief  Create a 1MB Section

+

+    \param [in]               ttb  Translation table base address

+    \param [in]      base_address  Section base address

+    \param [in]             count  Number of sections to create

+    \param [in]     descriptor_l1  L1 descriptor (region attributes) 

+

+ */

+__STATIC_INLINE void __TTSection(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1)

+{

+    uint32_t offset;

+    uint32_t entry;

+    uint32_t i;

+

+    offset = base_address >> 20;

+    entry  = (base_address & 0xFFF00000) | descriptor_l1;

+

+    //4 bytes aligned

+    ttb = ttb + offset;

+

+    for (i = 0; i < count; i++ )

+    {

+        //4 bytes aligned

+       *ttb++ = entry;

+       entry += OFFSET_1M;

+    }

+}

+

+/** \brief  Create a 4k page entry

+

+    \param [in]               ttb  L1 table base address

+    \param [in]      base_address  4k base address

+    \param [in]             count  Number of 4k pages to create

+    \param [in]     descriptor_l1  L1 descriptor (region attributes) 

+    \param [in]            ttb_l2  L2 table base address

+    \param [in]     descriptor_l2  L2 descriptor (region attributes) 

+

+ */

+__STATIC_INLINE void __TTPage_4k(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1, uint32_t *ttb_l2, uint32_t descriptor_l2 )

+{

+

+    uint32_t offset, offset2;

+    uint32_t entry, entry2;

+    uint32_t i;

+

+

+    offset = base_address >> 20;

+    entry  = ((int)ttb_l2 & 0xFFFFFC00) | descriptor_l1;

+

+    //4 bytes aligned

+    ttb += offset;

+    //create l1_entry

+    *ttb = entry;

+

+    offset2 = (base_address & 0xff000) >> 12;

+    ttb_l2 += offset2;

+    entry2 = (base_address & 0xFFFFF000) | descriptor_l2;

+    for (i = 0; i < count; i++ )

+    {

+        //4 bytes aligned

+       *ttb_l2++ = entry2;

+       entry2 += OFFSET_4K;

+    }

+}

+

+/** \brief  Create a 64k page entry

+

+    \param [in]               ttb  L1 table base address

+    \param [in]      base_address  64k base address

+    \param [in]             count  Number of 64k pages to create

+    \param [in]     descriptor_l1  L1 descriptor (region attributes) 

+    \param [in]            ttb_l2  L2 table base address

+    \param [in]     descriptor_l2  L2 descriptor (region attributes) 

+

+ */

+__STATIC_INLINE void __TTPage_64k(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1, uint32_t *ttb_l2, uint32_t descriptor_l2 )

+{

+    uint32_t offset, offset2;

+    uint32_t entry, entry2;

+    uint32_t i,j;

+

+

+    offset = base_address >> 20;

+    entry  = ((int)ttb_l2 & 0xFFFFFC00) | descriptor_l1;

+

+    //4 bytes aligned

+    ttb += offset;

+    //create l1_entry

+    *ttb = entry;

+

+    offset2 = (base_address & 0xff000) >> 12;

+    ttb_l2 += offset2;

+    entry2 = (base_address & 0xFFFF0000) | descriptor_l2;

+    for (i = 0; i < count; i++ )

+    {

+        //create 16 entries

+        for (j = 0; j < 16; j++)

+            //4 bytes aligned

+            *ttb_l2++ = entry2;

+        entry2 += OFFSET_64K;

+    }

+}

+

+/*@} end of MMU_Functions */

+#endif

+

+#ifdef __cplusplus

+}

+#endif

diff --git a/ext/TARGET_LPC1768/core_cm0.h b/ext/TARGET_LPC1768/core_cm0.h
new file mode 100644
index 0000000..1110d17
--- /dev/null
+++ b/ext/TARGET_LPC1768/core_cm0.h
@@ -0,0 +1,740 @@
+/**************************************************************************//**

+ * @file     core_cm0.h

+ * @brief    CMSIS Cortex-M0 Core Peripheral Access Layer Header File

+ * @version  V4.10

+ * @date     18. March 2015

+ *

+ * @note

+ *

+ ******************************************************************************/

+/* Copyright (c) 2009 - 2015 ARM LIMITED

+

+   All rights reserved.

+   Redistribution and use in source and binary forms, with or without

+   modification, are permitted provided that the following conditions are met:

+   - Redistributions of source code must retain the above copyright

+     notice, this list of conditions and the following disclaimer.

+   - Redistributions in binary form must reproduce the above copyright

+     notice, this list of conditions and the following disclaimer in the

+     documentation and/or other materials provided with the distribution.

+   - Neither the name of ARM nor the names of its contributors may be used

+     to endorse or promote products derived from this software without

+     specific prior written permission.

+   *

+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"

+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE

+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE

+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE

+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR

+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF

+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS

+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN

+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)

+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE

+   POSSIBILITY OF SUCH DAMAGE.

+   ---------------------------------------------------------------------------*/

+

+

+#if defined ( __ICCARM__ )

+ #pragma system_include  /* treat file as system include file for MISRA check */

+#endif

+

+#ifndef __CORE_CM0_H_GENERIC

+#define __CORE_CM0_H_GENERIC

+

+#ifdef __cplusplus

+ extern "C" {

+#endif

+

+/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions

+  CMSIS violates the following MISRA-C:2004 rules:

+

+   \li Required Rule 8.5, object/function definition in header file.<br>

+     Function definitions in header files are used to allow 'inlining'.

+

+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>

+     Unions are used for effective representation of core registers.

+

+   \li Advisory Rule 19.7, Function-like macro defined.<br>

+     Function-like macros are used to allow more efficient code.

+ */

+

+

+/*******************************************************************************

+ *                 CMSIS definitions

+ ******************************************************************************/

+/** \ingroup Cortex_M0

+  @{

+ */

+

+/*  CMSIS CM0 definitions */

+#define __CM0_CMSIS_VERSION_MAIN  (0x04)                                   /*!< [31:16] CMSIS HAL main version   */

+#define __CM0_CMSIS_VERSION_SUB   (0x00)                                   /*!< [15:0]  CMSIS HAL sub version    */

+#define __CM0_CMSIS_VERSION       ((__CM0_CMSIS_VERSION_MAIN << 16) | \

+                                    __CM0_CMSIS_VERSION_SUB          )     /*!< CMSIS HAL version number         */

+

+#define __CORTEX_M                (0x00)                                   /*!< Cortex-M Core                    */

+

+

+#if   defined ( __CC_ARM )

+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */

+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */

+  #define __STATIC_INLINE  static __inline

+

+#elif defined ( __GNUC__ )

+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */

+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */

+  #define __STATIC_INLINE  static inline

+

+#elif defined ( __ICCARM__ )

+  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */

+  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */

+  #define __STATIC_INLINE  static inline

+

+#elif defined ( __TMS470__ )

+  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler       */

+  #define __STATIC_INLINE  static inline

+

+#elif defined ( __TASKING__ )

+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */

+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */

+  #define __STATIC_INLINE  static inline

+

+#elif defined ( __CSMC__ )

+  #define __packed

+  #define __ASM            _asm                                      /*!< asm keyword for COSMIC Compiler      */

+  #define __INLINE         inline                                    /*use -pc99 on compile line !< inline keyword for COSMIC Compiler   */

+  #define __STATIC_INLINE  static inline

+

+#endif

+

+/** __FPU_USED indicates whether an FPU is used or not.

+    This core does not support an FPU at all

+*/

+#define __FPU_USED       0

+

+#if defined ( __CC_ARM )

+  #if defined __TARGET_FPU_VFP

+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"

+  #endif

+

+#elif defined ( __GNUC__ )

+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)

+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"

+  #endif

+

+#elif defined ( __ICCARM__ )

+  #if defined __ARMVFP__

+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"

+  #endif

+

+#elif defined ( __TMS470__ )

+  #if defined __TI__VFP_SUPPORT____

+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"

+  #endif

+

+#elif defined ( __TASKING__ )

+  #if defined __FPU_VFP__

+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"

+  #endif

+

+#elif defined ( __CSMC__ )		/* Cosmic */

+  #if ( __CSMC__ & 0x400)		// FPU present for parser

+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"

+  #endif

+#endif

+

+#include <stdint.h>                      /* standard types definitions                      */

+#include <core_cmInstr.h>                /* Core Instruction Access                         */

+#include <core_cmFunc.h>                 /* Core Function Access                            */

+

+#ifdef __cplusplus

+}

+#endif

+

+#endif /* __CORE_CM0_H_GENERIC */

+

+#ifndef __CMSIS_GENERIC

+

+#ifndef __CORE_CM0_H_DEPENDANT

+#define __CORE_CM0_H_DEPENDANT

+

+#ifdef __cplusplus

+ extern "C" {

+#endif

+

+/* check device defines and use defaults */

+#if defined __CHECK_DEVICE_DEFINES

+  #ifndef __CM0_REV

+    #define __CM0_REV               0x0000

+    #warning "__CM0_REV not defined in device header file; using default!"

+  #endif

+

+  #ifndef __NVIC_PRIO_BITS

+    #define __NVIC_PRIO_BITS          2

+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"

+  #endif

+

+  #ifndef __Vendor_SysTickConfig

+    #define __Vendor_SysTickConfig    0

+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"

+  #endif

+#endif

+

+/* IO definitions (access restrictions to peripheral registers) */

+/**

+    \defgroup CMSIS_glob_defs CMSIS Global Defines

+

+    <strong>IO Type Qualifiers</strong> are used

+    \li to specify the access to peripheral variables.

+    \li for automatic generation of peripheral register debug information.

+*/

+#ifdef __cplusplus

+  #define   __I     volatile             /*!< Defines 'read only' permissions                 */

+#else

+  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */

+#endif

+#define     __O     volatile             /*!< Defines 'write only' permissions                */

+#define     __IO    volatile             /*!< Defines 'read / write' permissions              */

+

+/*@} end of group Cortex_M0 */

+

+

+

+/*******************************************************************************

+ *                 Register Abstraction

+  Core Register contain:

+  - Core Register

+  - Core NVIC Register

+  - Core SCB Register

+  - Core SysTick Register

+ ******************************************************************************/

+/** \defgroup CMSIS_core_register Defines and Type Definitions

+    \brief Type definitions and defines for Cortex-M processor based devices.

+*/

+

+/** \ingroup    CMSIS_core_register

+    \defgroup   CMSIS_CORE  Status and Control Registers

+    \brief  Core Register type definitions.

+  @{

+ */

+

+/** \brief  Union type to access the Application Program Status Register (APSR).

+ */

+typedef union

+{

+  struct

+  {

+    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved                           */

+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */

+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */

+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */

+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */

+  } b;                                   /*!< Structure used for bit  access                  */

+  uint32_t w;                            /*!< Type      used for word access                  */

+} APSR_Type;

+

+/* APSR Register Definitions */

+#define APSR_N_Pos                         31                                             /*!< APSR: N Position */

+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */

+

+#define APSR_Z_Pos                         30                                             /*!< APSR: Z Position */

+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */

+

+#define APSR_C_Pos                         29                                             /*!< APSR: C Position */

+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */

+

+#define APSR_V_Pos                         28                                             /*!< APSR: V Position */

+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */

+

+

+/** \brief  Union type to access the Interrupt Program Status Register (IPSR).

+ */

+typedef union

+{

+  struct

+  {

+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */

+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */

+  } b;                                   /*!< Structure used for bit  access                  */

+  uint32_t w;                            /*!< Type      used for word access                  */

+} IPSR_Type;

+

+/* IPSR Register Definitions */

+#define IPSR_ISR_Pos                        0                                             /*!< IPSR: ISR Position */

+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */

+

+

+/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).

+ */

+typedef union

+{

+  struct

+  {

+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */

+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */

+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */

+    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved                           */

+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */

+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */

+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */

+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */

+  } b;                                   /*!< Structure used for bit  access                  */

+  uint32_t w;                            /*!< Type      used for word access                  */

+} xPSR_Type;

+

+/* xPSR Register Definitions */

+#define xPSR_N_Pos                         31                                             /*!< xPSR: N Position */

+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */

+

+#define xPSR_Z_Pos                         30                                             /*!< xPSR: Z Position */

+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */

+

+#define xPSR_C_Pos                         29                                             /*!< xPSR: C Position */

+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */

+

+#define xPSR_V_Pos                         28                                             /*!< xPSR: V Position */

+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */

+

+#define xPSR_T_Pos                         24                                             /*!< xPSR: T Position */

+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */

+

+#define xPSR_ISR_Pos                        0                                             /*!< xPSR: ISR Position */

+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */

+

+

+/** \brief  Union type to access the Control Registers (CONTROL).

+ */

+typedef union

+{

+  struct

+  {

+    uint32_t _reserved0:1;               /*!< bit:      0  Reserved                           */

+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */

+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved                           */

+  } b;                                   /*!< Structure used for bit  access                  */

+  uint32_t w;                            /*!< Type      used for word access                  */

+} CONTROL_Type;

+

+/* CONTROL Register Definitions */

+#define CONTROL_SPSEL_Pos                   1                                             /*!< CONTROL: SPSEL Position */

+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */

+

+/*@} end of group CMSIS_CORE */

+

+

+/** \ingroup    CMSIS_core_register

+    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)

+    \brief      Type definitions for the NVIC Registers

+  @{

+ */

+

+/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).

+ */

+typedef struct

+{

+  __IO uint32_t ISER[1];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */

+       uint32_t RESERVED0[31];

+  __IO uint32_t ICER[1];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register          */

+       uint32_t RSERVED1[31];

+  __IO uint32_t ISPR[1];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register           */

+       uint32_t RESERVED2[31];

+  __IO uint32_t ICPR[1];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register         */

+       uint32_t RESERVED3[31];

+       uint32_t RESERVED4[64];

+  __IO uint32_t IP[8];                   /*!< Offset: 0x300 (R/W)  Interrupt Priority Register              */

+}  NVIC_Type;

+

+/*@} end of group CMSIS_NVIC */

+

+

+/** \ingroup  CMSIS_core_register

+    \defgroup CMSIS_SCB     System Control Block (SCB)

+    \brief      Type definitions for the System Control Block Registers

+  @{

+ */

+

+/** \brief  Structure type to access the System Control Block (SCB).

+ */

+typedef struct

+{

+  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */

+  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */

+       uint32_t RESERVED0;

+  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */

+  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */

+  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */

+       uint32_t RESERVED1;

+  __IO uint32_t SHP[2];                  /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED   */

+  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */

+} SCB_Type;

+

+/* SCB CPUID Register Definitions */

+#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */

+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */

+

+#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */

+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */

+

+#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */

+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */

+

+#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */

+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */

+

+#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */

+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */

+

+/* SCB Interrupt Control State Register Definitions */

+#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */

+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */

+

+#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */

+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */

+

+#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */

+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */

+

+#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */

+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */

+

+#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */

+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */

+

+#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */

+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */

+

+#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */

+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */

+

+#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */

+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */

+

+#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */

+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */

+

+/* SCB Application Interrupt and Reset Control Register Definitions */

+#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */

+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */

+

+#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */

+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */

+

+#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */

+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */

+

+#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */

+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */

+

+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */

+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */

+

+/* SCB System Control Register Definitions */

+#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */

+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */

+

+#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */

+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */

+

+#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */

+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */

+

+/* SCB Configuration Control Register Definitions */

+#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */

+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */

+

+#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */

+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */

+

+/* SCB System Handler Control and State Register Definitions */

+#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */

+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */

+

+/*@} end of group CMSIS_SCB */

+

+

+/** \ingroup  CMSIS_core_register

+    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)

+    \brief      Type definitions for the System Timer Registers.

+  @{

+ */

+

+/** \brief  Structure type to access the System Timer (SysTick).

+ */

+typedef struct

+{

+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */

+  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */

+  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */

+  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */

+} SysTick_Type;

+

+/* SysTick Control / Status Register Definitions */

+#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */

+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */

+

+#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */

+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */

+

+#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */

+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */

+

+#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */

+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */

+

+/* SysTick Reload Register Definitions */

+#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */

+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */

+

+/* SysTick Current Register Definitions */

+#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */

+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */

+

+/* SysTick Calibration Register Definitions */

+#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */

+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */

+

+#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */

+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */

+

+#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */

+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */

+

+/*@} end of group CMSIS_SysTick */

+

+

+/** \ingroup  CMSIS_core_register

+    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)

+    \brief      Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR)

+                are only accessible over DAP and not via processor. Therefore

+                they are not covered by the Cortex-M0 header file.

+  @{

+ */

+/*@} end of group CMSIS_CoreDebug */

+

+

+/** \ingroup    CMSIS_core_register

+    \defgroup   CMSIS_core_base     Core Definitions

+    \brief      Definitions for base addresses, unions, and structures.

+  @{

+ */

+

+/* Memory mapping of Cortex-M0 Hardware */

+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */

+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address              */

+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                 */

+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */

+

+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */

+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */

+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */

+

+

+/*@} */

+

+

+

+/*******************************************************************************

+ *                Hardware Abstraction Layer

+  Core Function Interface contains:

+  - Core NVIC Functions

+  - Core SysTick Functions

+  - Core Register Access Functions

+ ******************************************************************************/

+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference

+*/

+

+

+

+/* ##########################   NVIC functions  #################################### */

+/** \ingroup  CMSIS_Core_FunctionInterface

+    \defgroup CMSIS_Core_NVICFunctions NVIC Functions

+    \brief      Functions that manage interrupts and exceptions via the NVIC.

+    @{

+ */

+

+/* Interrupt Priorities are WORD accessible only under ARMv6M                   */

+/* The following MACROS handle generation of the register offset and byte masks */

+#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)

+#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )

+#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )

+

+

+/** \brief  Enable External Interrupt

+

+    The function enables a device-specific interrupt in the NVIC interrupt controller.

+

+    \param [in]      IRQn  External interrupt number. Value cannot be negative.

+ */

+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)

+{

+  NVIC->ISER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));

+}

+

+

+/** \brief  Disable External Interrupt

+

+    The function disables a device-specific interrupt in the NVIC interrupt controller.

+

+    \param [in]      IRQn  External interrupt number. Value cannot be negative.

+ */

+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)

+{

+  NVIC->ICER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));

+}

+

+

+/** \brief  Get Pending Interrupt

+

+    The function reads the pending register in the NVIC and returns the pending bit

+    for the specified interrupt.

+

+    \param [in]      IRQn  Interrupt number.

+

+    \return             0  Interrupt status is not pending.

+    \return             1  Interrupt status is pending.

+ */

+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)

+{

+  return((uint32_t)(((NVIC->ISPR[0] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));

+}

+

+

+/** \brief  Set Pending Interrupt

+

+    The function sets the pending bit of an external interrupt.

+

+    \param [in]      IRQn  Interrupt number. Value cannot be negative.

+ */

+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)

+{

+  NVIC->ISPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));

+}

+

+

+/** \brief  Clear Pending Interrupt

+

+    The function clears the pending bit of an external interrupt.

+

+    \param [in]      IRQn  External interrupt number. Value cannot be negative.

+ */

+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)

+{

+  NVIC->ICPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));

+}

+

+

+/** \brief  Set Interrupt Priority

+

+    The function sets the priority of an interrupt.

+

+    \note The priority cannot be set for every core interrupt.

+

+    \param [in]      IRQn  Interrupt number.

+    \param [in]  priority  Priority to set.

+ */

+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)

+{

+  if((int32_t)(IRQn) < 0) {

+    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |

+       (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));

+  }

+  else {

+    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |

+       (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));

+  }

+}

+

+

+/** \brief  Get Interrupt Priority

+

+    The function reads the priority of an interrupt. The interrupt

+    number can be positive to specify an external (device specific)

+    interrupt, or negative to specify an internal (core) interrupt.

+

+

+    \param [in]   IRQn  Interrupt number.

+    \return             Interrupt Priority. Value is aligned automatically to the implemented

+                        priority bits of the microcontroller.

+ */

+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)

+{

+

+  if((int32_t)(IRQn) < 0) {

+    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));

+  }

+  else {

+    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));

+  }

+}

+

+

+/** \brief  System Reset

+

+    The function initiates a system reset request to reset the MCU.

+ */

+__STATIC_INLINE void NVIC_SystemReset(void)

+{

+  __DSB();                                                     /* Ensure all outstanding memory accesses included

+                                                                  buffered write are completed before reset */

+  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |

+                 SCB_AIRCR_SYSRESETREQ_Msk);

+  __DSB();                                                     /* Ensure completion of memory access */

+  while(1) { __NOP(); }                                        /* wait until reset */

+}

+

+/*@} end of CMSIS_Core_NVICFunctions */

+

+

+

+/* ##################################    SysTick function  ############################################ */

+/** \ingroup  CMSIS_Core_FunctionInterface

+    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions

+    \brief      Functions that configure the System.

+  @{

+ */

+

+#if (__Vendor_SysTickConfig == 0)

+

+/** \brief  System Tick Configuration

+

+    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.

+    Counter is in free running mode to generate periodic interrupts.

+

+    \param [in]  ticks  Number of ticks between two interrupts.

+

+    \return          0  Function succeeded.

+    \return          1  Function failed.

+

+    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the

+    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>

+    must contain a vendor-specific implementation of this function.

+

+ */

+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)

+{

+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); }    /* Reload value impossible */

+

+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */

+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */

+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */

+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |

+                   SysTick_CTRL_TICKINT_Msk   |

+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */

+  return (0UL);                                                     /* Function successful */

+}

+

+#endif

+

+/*@} end of CMSIS_Core_SysTickFunctions */

+

+

+

+

+#ifdef __cplusplus

+}

+#endif

+

+#endif /* __CORE_CM0_H_DEPENDANT */

+

+#endif /* __CMSIS_GENERIC */

diff --git a/ext/TARGET_LPC1768/core_cm0plus.h b/ext/TARGET_LPC1768/core_cm0plus.h
new file mode 100644
index 0000000..62e914b
--- /dev/null
+++ b/ext/TARGET_LPC1768/core_cm0plus.h
@@ -0,0 +1,854 @@
+/**************************************************************************//**

+ * @file     core_cm0plus.h

+ * @brief    CMSIS Cortex-M0+ Core Peripheral Access Layer Header File

+ * @version  V4.10

+ * @date     18. March 2015

+ *

+ * @note

+ *

+ ******************************************************************************/

+/* Copyright (c) 2009 - 2015 ARM LIMITED

+

+   All rights reserved.

+   Redistribution and use in source and binary forms, with or without

+   modification, are permitted provided that the following conditions are met:

+   - Redistributions of source code must retain the above copyright

+     notice, this list of conditions and the following disclaimer.

+   - Redistributions in binary form must reproduce the above copyright

+     notice, this list of conditions and the following disclaimer in the

+     documentation and/or other materials provided with the distribution.

+   - Neither the name of ARM nor the names of its contributors may be used

+     to endorse or promote products derived from this software without

+     specific prior written permission.

+   *

+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"

+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE

+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE

+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE

+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR

+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF

+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS

+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN

+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)

+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE

+   POSSIBILITY OF SUCH DAMAGE.

+   ---------------------------------------------------------------------------*/

+

+

+#if defined ( __ICCARM__ )

+ #pragma system_include  /* treat file as system include file for MISRA check */

+#endif

+

+#ifndef __CORE_CM0PLUS_H_GENERIC

+#define __CORE_CM0PLUS_H_GENERIC

+

+#ifdef __cplusplus

+ extern "C" {

+#endif

+

+/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions

+  CMSIS violates the following MISRA-C:2004 rules:

+

+   \li Required Rule 8.5, object/function definition in header file.<br>

+     Function definitions in header files are used to allow 'inlining'.

+

+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>

+     Unions are used for effective representation of core registers.

+

+   \li Advisory Rule 19.7, Function-like macro defined.<br>

+     Function-like macros are used to allow more efficient code.

+ */

+

+

+/*******************************************************************************

+ *                 CMSIS definitions

+ ******************************************************************************/

+/** \ingroup Cortex-M0+

+  @{

+ */

+

+/*  CMSIS CM0P definitions */

+#define __CM0PLUS_CMSIS_VERSION_MAIN (0x04)                                /*!< [31:16] CMSIS HAL main version   */

+#define __CM0PLUS_CMSIS_VERSION_SUB  (0x00)                                /*!< [15:0]  CMSIS HAL sub version    */

+#define __CM0PLUS_CMSIS_VERSION      ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \

+                                       __CM0PLUS_CMSIS_VERSION_SUB)        /*!< CMSIS HAL version number         */

+

+#define __CORTEX_M                (0x00)                                   /*!< Cortex-M Core                    */

+

+

+#if   defined ( __CC_ARM )

+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */

+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */

+  #define __STATIC_INLINE  static __inline

+

+#elif defined ( __GNUC__ )

+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */

+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */

+  #define __STATIC_INLINE  static inline

+

+#elif defined ( __ICCARM__ )

+  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */

+  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */

+  #define __STATIC_INLINE  static inline

+

+#elif defined ( __TMS470__ )

+  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler       */

+  #define __STATIC_INLINE  static inline

+

+#elif defined ( __TASKING__ )

+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */

+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */

+  #define __STATIC_INLINE  static inline

+

+#elif defined ( __CSMC__ )

+  #define __packed

+  #define __ASM            _asm                                      /*!< asm keyword for COSMIC Compiler      */

+  #define __INLINE         inline                                    /*use -pc99 on compile line !< inline keyword for COSMIC Compiler   */

+  #define __STATIC_INLINE  static inline

+

+#endif

+

+/** __FPU_USED indicates whether an FPU is used or not.

+    This core does not support an FPU at all

+*/

+#define __FPU_USED       0

+

+#if defined ( __CC_ARM )

+  #if defined __TARGET_FPU_VFP

+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"

+  #endif

+

+#elif defined ( __GNUC__ )

+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)

+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"

+  #endif

+

+#elif defined ( __ICCARM__ )

+  #if defined __ARMVFP__

+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"

+  #endif

+

+#elif defined ( __TMS470__ )

+  #if defined __TI__VFP_SUPPORT____

+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"

+  #endif

+

+#elif defined ( __TASKING__ )

+  #if defined __FPU_VFP__

+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"

+  #endif

+

+#elif defined ( __CSMC__ )		/* Cosmic */

+  #if ( __CSMC__ & 0x400)		// FPU present for parser

+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"

+  #endif

+#endif

+

+#include <stdint.h>                      /* standard types definitions                      */

+#include <core_cmInstr.h>                /* Core Instruction Access                         */

+#include <core_cmFunc.h>                 /* Core Function Access                            */

+

+#ifdef __cplusplus

+}

+#endif

+

+#endif /* __CORE_CM0PLUS_H_GENERIC */

+

+#ifndef __CMSIS_GENERIC

+

+#ifndef __CORE_CM0PLUS_H_DEPENDANT

+#define __CORE_CM0PLUS_H_DEPENDANT

+

+#ifdef __cplusplus

+ extern "C" {

+#endif

+

+/* check device defines and use defaults */

+#if defined __CHECK_DEVICE_DEFINES

+  #ifndef __CM0PLUS_REV

+    #define __CM0PLUS_REV             0x0000

+    #warning "__CM0PLUS_REV not defined in device header file; using default!"

+  #endif

+

+  #ifndef __MPU_PRESENT

+    #define __MPU_PRESENT             0

+    #warning "__MPU_PRESENT not defined in device header file; using default!"

+  #endif

+

+  #ifndef __VTOR_PRESENT

+    #define __VTOR_PRESENT            0

+    #warning "__VTOR_PRESENT not defined in device header file; using default!"

+  #endif

+

+  #ifndef __NVIC_PRIO_BITS

+    #define __NVIC_PRIO_BITS          2

+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"

+  #endif

+

+  #ifndef __Vendor_SysTickConfig

+    #define __Vendor_SysTickConfig    0

+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"

+  #endif

+#endif

+

+/* IO definitions (access restrictions to peripheral registers) */

+/**

+    \defgroup CMSIS_glob_defs CMSIS Global Defines

+

+    <strong>IO Type Qualifiers</strong> are used

+    \li to specify the access to peripheral variables.

+    \li for automatic generation of peripheral register debug information.

+*/

+#ifdef __cplusplus

+  #define   __I     volatile             /*!< Defines 'read only' permissions                 */

+#else

+  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */

+#endif

+#define     __O     volatile             /*!< Defines 'write only' permissions                */

+#define     __IO    volatile             /*!< Defines 'read / write' permissions              */

+

+/*@} end of group Cortex-M0+ */

+

+

+

+/*******************************************************************************

+ *                 Register Abstraction

+  Core Register contain:

+  - Core Register

+  - Core NVIC Register

+  - Core SCB Register

+  - Core SysTick Register

+  - Core MPU Register

+ ******************************************************************************/

+/** \defgroup CMSIS_core_register Defines and Type Definitions

+    \brief Type definitions and defines for Cortex-M processor based devices.

+*/

+

+/** \ingroup    CMSIS_core_register

+    \defgroup   CMSIS_CORE  Status and Control Registers

+    \brief  Core Register type definitions.

+  @{

+ */

+

+/** \brief  Union type to access the Application Program Status Register (APSR).

+ */

+typedef union

+{

+  struct

+  {

+    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved                           */

+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */

+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */

+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */

+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */

+  } b;                                   /*!< Structure used for bit  access                  */

+  uint32_t w;                            /*!< Type      used for word access                  */

+} APSR_Type;

+

+/* APSR Register Definitions */

+#define APSR_N_Pos                         31                                             /*!< APSR: N Position */

+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */

+

+#define APSR_Z_Pos                         30                                             /*!< APSR: Z Position */

+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */

+

+#define APSR_C_Pos                         29                                             /*!< APSR: C Position */

+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */

+

+#define APSR_V_Pos                         28                                             /*!< APSR: V Position */

+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */

+

+

+/** \brief  Union type to access the Interrupt Program Status Register (IPSR).

+ */

+typedef union

+{

+  struct

+  {

+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */

+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */

+  } b;                                   /*!< Structure used for bit  access                  */

+  uint32_t w;                            /*!< Type      used for word access                  */

+} IPSR_Type;

+

+/* IPSR Register Definitions */

+#define IPSR_ISR_Pos                        0                                             /*!< IPSR: ISR Position */

+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */

+

+

+/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).

+ */

+typedef union

+{

+  struct

+  {

+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */

+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */

+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */

+    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved                           */

+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */

+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */

+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */

+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */

+  } b;                                   /*!< Structure used for bit  access                  */

+  uint32_t w;                            /*!< Type      used for word access                  */

+} xPSR_Type;

+

+/* xPSR Register Definitions */

+#define xPSR_N_Pos                         31                                             /*!< xPSR: N Position */

+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */

+

+#define xPSR_Z_Pos                         30                                             /*!< xPSR: Z Position */

+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */

+

+#define xPSR_C_Pos                         29                                             /*!< xPSR: C Position */

+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */

+

+#define xPSR_V_Pos                         28                                             /*!< xPSR: V Position */

+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */

+

+#define xPSR_T_Pos                         24                                             /*!< xPSR: T Position */

+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */

+

+#define xPSR_ISR_Pos                        0                                             /*!< xPSR: ISR Position */

+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */

+

+

+/** \brief  Union type to access the Control Registers (CONTROL).

+ */

+typedef union

+{

+  struct

+  {

+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */

+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */

+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved                           */

+  } b;                                   /*!< Structure used for bit  access                  */

+  uint32_t w;                            /*!< Type      used for word access                  */

+} CONTROL_Type;

+

+/* CONTROL Register Definitions */

+#define CONTROL_SPSEL_Pos                   1                                             /*!< CONTROL: SPSEL Position */

+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */

+

+#define CONTROL_nPRIV_Pos                   0                                             /*!< CONTROL: nPRIV Position */

+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */

+

+/*@} end of group CMSIS_CORE */

+

+

+/** \ingroup    CMSIS_core_register

+    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)

+    \brief      Type definitions for the NVIC Registers

+  @{

+ */

+

+/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).

+ */

+typedef struct

+{

+  __IO uint32_t ISER[1];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */

+       uint32_t RESERVED0[31];

+  __IO uint32_t ICER[1];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register          */

+       uint32_t RSERVED1[31];

+  __IO uint32_t ISPR[1];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register           */

+       uint32_t RESERVED2[31];

+  __IO uint32_t ICPR[1];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register         */

+       uint32_t RESERVED3[31];

+       uint32_t RESERVED4[64];

+  __IO uint32_t IP[8];                   /*!< Offset: 0x300 (R/W)  Interrupt Priority Register              */

+}  NVIC_Type;

+

+/*@} end of group CMSIS_NVIC */

+

+

+/** \ingroup  CMSIS_core_register

+    \defgroup CMSIS_SCB     System Control Block (SCB)

+    \brief      Type definitions for the System Control Block Registers

+  @{

+ */

+

+/** \brief  Structure type to access the System Control Block (SCB).

+ */

+typedef struct

+{

+  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */

+  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */

+#if (__VTOR_PRESENT == 1)

+  __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */

+#else

+       uint32_t RESERVED0;

+#endif

+  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */

+  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */

+  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */

+       uint32_t RESERVED1;

+  __IO uint32_t SHP[2];                  /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED   */

+  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */

+} SCB_Type;

+

+/* SCB CPUID Register Definitions */

+#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */

+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */

+

+#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */

+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */

+

+#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */

+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */

+

+#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */

+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */

+

+#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */

+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */

+

+/* SCB Interrupt Control State Register Definitions */

+#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */

+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */

+

+#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */

+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */

+

+#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */

+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */

+

+#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */

+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */

+

+#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */

+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */

+

+#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */

+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */

+

+#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */

+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */

+

+#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */

+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */

+

+#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */

+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */

+

+#if (__VTOR_PRESENT == 1)

+/* SCB Interrupt Control State Register Definitions */

+#define SCB_VTOR_TBLOFF_Pos                 8                                             /*!< SCB VTOR: TBLOFF Position */

+#define SCB_VTOR_TBLOFF_Msk                (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */

+#endif

+

+/* SCB Application Interrupt and Reset Control Register Definitions */

+#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */

+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */

+

+#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */

+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */

+

+#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */

+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */

+

+#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */

+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */

+

+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */

+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */

+

+/* SCB System Control Register Definitions */

+#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */

+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */

+

+#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */

+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */

+

+#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */

+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */

+

+/* SCB Configuration Control Register Definitions */

+#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */

+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */

+

+#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */

+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */

+

+/* SCB System Handler Control and State Register Definitions */

+#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */

+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */

+

+/*@} end of group CMSIS_SCB */

+

+

+/** \ingroup  CMSIS_core_register

+    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)

+    \brief      Type definitions for the System Timer Registers.

+  @{

+ */

+

+/** \brief  Structure type to access the System Timer (SysTick).

+ */

+typedef struct

+{

+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */

+  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */

+  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */

+  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */

+} SysTick_Type;

+

+/* SysTick Control / Status Register Definitions */

+#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */

+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */

+

+#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */

+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */

+

+#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */

+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */

+

+#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */

+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */

+

+/* SysTick Reload Register Definitions */

+#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */

+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */

+

+/* SysTick Current Register Definitions */

+#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */

+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */

+

+/* SysTick Calibration Register Definitions */

+#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */

+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */

+

+#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */

+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */

+

+#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */

+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */

+

+/*@} end of group CMSIS_SysTick */

+

+#if (__MPU_PRESENT == 1)

+/** \ingroup  CMSIS_core_register

+    \defgroup CMSIS_MPU     Memory Protection Unit (MPU)

+    \brief      Type definitions for the Memory Protection Unit (MPU)

+  @{

+ */

+

+/** \brief  Structure type to access the Memory Protection Unit (MPU).

+ */

+typedef struct

+{

+  __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */

+  __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */

+  __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */

+  __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */

+  __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */

+} MPU_Type;

+

+/* MPU Type Register */

+#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */

+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */

+

+#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */

+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */

+

+#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */

+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */

+

+/* MPU Control Register */

+#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */

+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */

+

+#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */

+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */

+

+#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */

+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */

+

+/* MPU Region Number Register */

+#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */

+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */

+

+/* MPU Region Base Address Register */

+#define MPU_RBAR_ADDR_Pos                   8                                             /*!< MPU RBAR: ADDR Position */

+#define MPU_RBAR_ADDR_Msk                  (0xFFFFFFUL << MPU_RBAR_ADDR_Pos)              /*!< MPU RBAR: ADDR Mask */

+

+#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */

+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */

+

+#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */

+#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */

+

+/* MPU Region Attribute and Size Register */

+#define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */

+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */

+

+#define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: ATTRS.XN Position */

+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */

+

+#define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: ATTRS.AP Position */

+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */

+

+#define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: ATTRS.TEX Position */

+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */

+

+#define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: ATTRS.S Position */

+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */

+

+#define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: ATTRS.C Position */

+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */

+

+#define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: ATTRS.B Position */

+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */

+

+#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */

+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */

+

+#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */

+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */

+

+#define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */

+#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */

+

+/*@} end of group CMSIS_MPU */

+#endif

+

+

+/** \ingroup  CMSIS_core_register

+    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)

+    \brief      Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR)

+                are only accessible over DAP and not via processor. Therefore

+                they are not covered by the Cortex-M0 header file.

+  @{

+ */

+/*@} end of group CMSIS_CoreDebug */

+

+

+/** \ingroup    CMSIS_core_register

+    \defgroup   CMSIS_core_base     Core Definitions

+    \brief      Definitions for base addresses, unions, and structures.

+  @{

+ */

+

+/* Memory mapping of Cortex-M0+ Hardware */

+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */

+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address              */

+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                 */

+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */

+

+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */

+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */

+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */

+

+#if (__MPU_PRESENT == 1)

+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */

+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */

+#endif

+

+/*@} */

+

+

+

+/*******************************************************************************

+ *                Hardware Abstraction Layer

+  Core Function Interface contains:

+  - Core NVIC Functions

+  - Core SysTick Functions

+  - Core Register Access Functions

+ ******************************************************************************/

+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference

+*/

+

+

+

+/* ##########################   NVIC functions  #################################### */

+/** \ingroup  CMSIS_Core_FunctionInterface

+    \defgroup CMSIS_Core_NVICFunctions NVIC Functions

+    \brief      Functions that manage interrupts and exceptions via the NVIC.

+    @{

+ */

+

+/* Interrupt Priorities are WORD accessible only under ARMv6M                   */

+/* The following MACROS handle generation of the register offset and byte masks */

+#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)

+#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )

+#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )

+

+

+/** \brief  Enable External Interrupt

+

+    The function enables a device-specific interrupt in the NVIC interrupt controller.

+

+    \param [in]      IRQn  External interrupt number. Value cannot be negative.

+ */

+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)

+{

+  NVIC->ISER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));

+}

+

+

+/** \brief  Disable External Interrupt

+

+    The function disables a device-specific interrupt in the NVIC interrupt controller.

+

+    \param [in]      IRQn  External interrupt number. Value cannot be negative.

+ */

+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)

+{

+  NVIC->ICER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));

+}

+

+

+/** \brief  Get Pending Interrupt

+

+    The function reads the pending register in the NVIC and returns the pending bit

+    for the specified interrupt.

+

+    \param [in]      IRQn  Interrupt number.

+

+    \return             0  Interrupt status is not pending.

+    \return             1  Interrupt status is pending.

+ */

+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)

+{

+  return((uint32_t)(((NVIC->ISPR[0] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));

+}

+

+

+/** \brief  Set Pending Interrupt

+

+    The function sets the pending bit of an external interrupt.

+

+    \param [in]      IRQn  Interrupt number. Value cannot be negative.

+ */

+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)

+{

+  NVIC->ISPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));

+}

+

+

+/** \brief  Clear Pending Interrupt

+

+    The function clears the pending bit of an external interrupt.

+

+    \param [in]      IRQn  External interrupt number. Value cannot be negative.

+ */

+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)

+{

+  NVIC->ICPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));

+}

+

+

+/** \brief  Set Interrupt Priority

+

+    The function sets the priority of an interrupt.

+

+    \note The priority cannot be set for every core interrupt.

+

+    \param [in]      IRQn  Interrupt number.

+    \param [in]  priority  Priority to set.

+ */

+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)

+{

+  if((int32_t)(IRQn) < 0) {

+    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |

+       (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));

+  }

+  else {

+    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |

+       (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));

+  }

+}

+

+

+/** \brief  Get Interrupt Priority

+

+    The function reads the priority of an interrupt. The interrupt

+    number can be positive to specify an external (device specific)

+    interrupt, or negative to specify an internal (core) interrupt.

+

+

+    \param [in]   IRQn  Interrupt number.

+    \return             Interrupt Priority. Value is aligned automatically to the implemented

+                        priority bits of the microcontroller.

+ */

+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)

+{

+

+  if((int32_t)(IRQn) < 0) {

+    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));

+  }

+  else {

+    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));

+  }

+}

+

+

+/** \brief  System Reset

+

+    The function initiates a system reset request to reset the MCU.

+ */

+__STATIC_INLINE void NVIC_SystemReset(void)

+{

+  __DSB();                                                     /* Ensure all outstanding memory accesses included

+                                                                  buffered write are completed before reset */

+  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |

+                 SCB_AIRCR_SYSRESETREQ_Msk);

+  __DSB();                                                     /* Ensure completion of memory access */

+  while(1) { __NOP(); }                                        /* wait until reset */

+}

+

+/*@} end of CMSIS_Core_NVICFunctions */

+

+

+

+/* ##################################    SysTick function  ############################################ */

+/** \ingroup  CMSIS_Core_FunctionInterface

+    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions

+    \brief      Functions that configure the System.

+  @{

+ */

+

+#if (__Vendor_SysTickConfig == 0)

+

+/** \brief  System Tick Configuration

+

+    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.

+    Counter is in free running mode to generate periodic interrupts.

+

+    \param [in]  ticks  Number of ticks between two interrupts.

+

+    \return          0  Function succeeded.

+    \return          1  Function failed.

+

+    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the

+    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>

+    must contain a vendor-specific implementation of this function.

+

+ */

+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)

+{

+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {return (1UL);}      /* Reload value impossible */

+

+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */

+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */

+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */

+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |

+                   SysTick_CTRL_TICKINT_Msk   |

+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */

+  return (0UL);                                                     /* Function successful */

+}

+

+#endif

+

+/*@} end of CMSIS_Core_SysTickFunctions */

+

+

+

+

+#ifdef __cplusplus

+}

+#endif

+

+#endif /* __CORE_CM0PLUS_H_DEPENDANT */

+

+#endif /* __CMSIS_GENERIC */

diff --git a/ext/TARGET_LPC1768/core_cm3.h b/ext/TARGET_LPC1768/core_cm3.h
new file mode 100644
index 0000000..d324f9b
--- /dev/null
+++ b/ext/TARGET_LPC1768/core_cm3.h
@@ -0,0 +1,1693 @@
+/**************************************************************************//**

+ * @file     core_cm3.h

+ * @brief    CMSIS Cortex-M3 Core Peripheral Access Layer Header File

+ * @version  V4.10

+ * @date     18. March 2015

+ *

+ * @note

+ *

+ ******************************************************************************/

+/* Copyright (c) 2009 - 2015 ARM LIMITED

+

+   All rights reserved.

+   Redistribution and use in source and binary forms, with or without

+   modification, are permitted provided that the following conditions are met:

+   - Redistributions of source code must retain the above copyright

+     notice, this list of conditions and the following disclaimer.

+   - Redistributions in binary form must reproduce the above copyright

+     notice, this list of conditions and the following disclaimer in the

+     documentation and/or other materials provided with the distribution.

+   - Neither the name of ARM nor the names of its contributors may be used

+     to endorse or promote products derived from this software without

+     specific prior written permission.

+   *

+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"

+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE

+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE

+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE

+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR

+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF

+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS

+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN

+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)

+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE

+   POSSIBILITY OF SUCH DAMAGE.

+   ---------------------------------------------------------------------------*/

+

+

+#if defined ( __ICCARM__ )

+ #pragma system_include  /* treat file as system include file for MISRA check */

+#endif

+

+#ifndef __CORE_CM3_H_GENERIC

+#define __CORE_CM3_H_GENERIC

+

+#ifdef __cplusplus

+ extern "C" {

+#endif

+

+/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions

+  CMSIS violates the following MISRA-C:2004 rules:

+

+   \li Required Rule 8.5, object/function definition in header file.<br>

+     Function definitions in header files are used to allow 'inlining'.

+

+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>

+     Unions are used for effective representation of core registers.

+

+   \li Advisory Rule 19.7, Function-like macro defined.<br>

+     Function-like macros are used to allow more efficient code.

+ */

+

+

+/*******************************************************************************

+ *                 CMSIS definitions

+ ******************************************************************************/

+/** \ingroup Cortex_M3

+  @{

+ */

+

+/*  CMSIS CM3 definitions */

+#define __CM3_CMSIS_VERSION_MAIN  (0x04)                                   /*!< [31:16] CMSIS HAL main version   */

+#define __CM3_CMSIS_VERSION_SUB   (0x00)                                   /*!< [15:0]  CMSIS HAL sub version    */

+#define __CM3_CMSIS_VERSION       ((__CM3_CMSIS_VERSION_MAIN << 16) | \

+                                    __CM3_CMSIS_VERSION_SUB          )     /*!< CMSIS HAL version number         */

+

+#define __CORTEX_M                (0x03)                                   /*!< Cortex-M Core                    */

+

+

+#if   defined ( __CC_ARM )

+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */

+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */

+  #define __STATIC_INLINE  static __inline

+

+#elif defined ( __GNUC__ )

+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */

+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */

+  #define __STATIC_INLINE  static inline

+

+#elif defined ( __ICCARM__ )

+  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */

+  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */

+  #define __STATIC_INLINE  static inline

+

+#elif defined ( __TMS470__ )

+  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler       */

+  #define __STATIC_INLINE  static inline

+

+#elif defined ( __TASKING__ )

+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */

+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */

+  #define __STATIC_INLINE  static inline

+

+#elif defined ( __CSMC__ )

+  #define __packed

+  #define __ASM            _asm                                      /*!< asm keyword for COSMIC Compiler      */

+  #define __INLINE         inline                                    /*use -pc99 on compile line !< inline keyword for COSMIC Compiler   */

+  #define __STATIC_INLINE  static inline

+

+#endif

+

+/** __FPU_USED indicates whether an FPU is used or not.

+    This core does not support an FPU at all

+*/

+#define __FPU_USED       0

+

+#if defined ( __CC_ARM )

+  #if defined __TARGET_FPU_VFP

+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"

+  #endif

+

+#elif defined ( __GNUC__ )

+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)

+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"

+  #endif

+

+#elif defined ( __ICCARM__ )

+  #if defined __ARMVFP__

+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"

+  #endif

+

+#elif defined ( __TMS470__ )

+  #if defined __TI__VFP_SUPPORT____

+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"

+  #endif

+

+#elif defined ( __TASKING__ )

+  #if defined __FPU_VFP__

+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"

+  #endif

+

+#elif defined ( __CSMC__ )		/* Cosmic */

+  #if ( __CSMC__ & 0x400)		// FPU present for parser

+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"

+  #endif

+#endif

+

+#include <stdint.h>                      /* standard types definitions                      */

+#include <core_cmInstr.h>                /* Core Instruction Access                         */

+#include <core_cmFunc.h>                 /* Core Function Access                            */

+

+#ifdef __cplusplus

+}

+#endif

+

+#endif /* __CORE_CM3_H_GENERIC */

+

+#ifndef __CMSIS_GENERIC

+

+#ifndef __CORE_CM3_H_DEPENDANT

+#define __CORE_CM3_H_DEPENDANT

+

+#ifdef __cplusplus

+ extern "C" {

+#endif

+

+/* check device defines and use defaults */

+#if defined __CHECK_DEVICE_DEFINES

+  #ifndef __CM3_REV

+    #define __CM3_REV               0x0200

+    #warning "__CM3_REV not defined in device header file; using default!"

+  #endif

+

+  #ifndef __MPU_PRESENT

+    #define __MPU_PRESENT             0

+    #warning "__MPU_PRESENT not defined in device header file; using default!"

+  #endif

+

+  #ifndef __NVIC_PRIO_BITS

+    #define __NVIC_PRIO_BITS          4

+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"

+  #endif

+

+  #ifndef __Vendor_SysTickConfig

+    #define __Vendor_SysTickConfig    0

+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"

+  #endif

+#endif

+

+/* IO definitions (access restrictions to peripheral registers) */

+/**

+    \defgroup CMSIS_glob_defs CMSIS Global Defines

+

+    <strong>IO Type Qualifiers</strong> are used

+    \li to specify the access to peripheral variables.

+    \li for automatic generation of peripheral register debug information.

+*/

+#ifdef __cplusplus

+  #define   __I     volatile             /*!< Defines 'read only' permissions                 */

+#else

+  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */

+#endif

+#define     __O     volatile             /*!< Defines 'write only' permissions                */

+#define     __IO    volatile             /*!< Defines 'read / write' permissions              */

+

+/*@} end of group Cortex_M3 */

+

+

+

+/*******************************************************************************

+ *                 Register Abstraction

+  Core Register contain:

+  - Core Register

+  - Core NVIC Register

+  - Core SCB Register

+  - Core SysTick Register

+  - Core Debug Register

+  - Core MPU Register

+ ******************************************************************************/

+/** \defgroup CMSIS_core_register Defines and Type Definitions

+    \brief Type definitions and defines for Cortex-M processor based devices.

+*/

+

+/** \ingroup    CMSIS_core_register

+    \defgroup   CMSIS_CORE  Status and Control Registers

+    \brief  Core Register type definitions.

+  @{

+ */

+

+/** \brief  Union type to access the Application Program Status Register (APSR).

+ */

+typedef union

+{

+  struct

+  {

+    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */

+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */

+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */

+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */

+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */

+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */

+  } b;                                   /*!< Structure used for bit  access                  */

+  uint32_t w;                            /*!< Type      used for word access                  */

+} APSR_Type;

+

+/* APSR Register Definitions */

+#define APSR_N_Pos                         31                                             /*!< APSR: N Position */

+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */

+

+#define APSR_Z_Pos                         30                                             /*!< APSR: Z Position */

+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */

+

+#define APSR_C_Pos                         29                                             /*!< APSR: C Position */

+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */

+

+#define APSR_V_Pos                         28                                             /*!< APSR: V Position */

+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */

+

+#define APSR_Q_Pos                         27                                             /*!< APSR: Q Position */

+#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */

+

+

+/** \brief  Union type to access the Interrupt Program Status Register (IPSR).

+ */

+typedef union

+{

+  struct

+  {

+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */

+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */

+  } b;                                   /*!< Structure used for bit  access                  */

+  uint32_t w;                            /*!< Type      used for word access                  */

+} IPSR_Type;

+

+/* IPSR Register Definitions */

+#define IPSR_ISR_Pos                        0                                             /*!< IPSR: ISR Position */

+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */

+

+

+/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).

+ */

+typedef union

+{

+  struct

+  {

+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */

+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */

+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */

+    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */

+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */

+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */

+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */

+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */

+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */

+  } b;                                   /*!< Structure used for bit  access                  */

+  uint32_t w;                            /*!< Type      used for word access                  */

+} xPSR_Type;

+

+/* xPSR Register Definitions */

+#define xPSR_N_Pos                         31                                             /*!< xPSR: N Position */

+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */

+

+#define xPSR_Z_Pos                         30                                             /*!< xPSR: Z Position */

+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */

+

+#define xPSR_C_Pos                         29                                             /*!< xPSR: C Position */

+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */

+

+#define xPSR_V_Pos                         28                                             /*!< xPSR: V Position */

+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */

+

+#define xPSR_Q_Pos                         27                                             /*!< xPSR: Q Position */

+#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */

+

+#define xPSR_IT_Pos                        25                                             /*!< xPSR: IT Position */

+#define xPSR_IT_Msk                        (3UL << xPSR_IT_Pos)                           /*!< xPSR: IT Mask */

+

+#define xPSR_T_Pos                         24                                             /*!< xPSR: T Position */

+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */

+

+#define xPSR_ISR_Pos                        0                                             /*!< xPSR: ISR Position */

+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */

+

+

+/** \brief  Union type to access the Control Registers (CONTROL).

+ */

+typedef union

+{

+  struct

+  {

+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */

+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */

+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved                           */

+  } b;                                   /*!< Structure used for bit  access                  */

+  uint32_t w;                            /*!< Type      used for word access                  */

+} CONTROL_Type;

+

+/* CONTROL Register Definitions */

+#define CONTROL_SPSEL_Pos                   1                                             /*!< CONTROL: SPSEL Position */

+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */

+

+#define CONTROL_nPRIV_Pos                   0                                             /*!< CONTROL: nPRIV Position */

+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */

+

+/*@} end of group CMSIS_CORE */

+

+

+/** \ingroup    CMSIS_core_register

+    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)

+    \brief      Type definitions for the NVIC Registers

+  @{

+ */

+

+/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).

+ */

+typedef struct

+{

+  __IO uint32_t ISER[8];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */

+       uint32_t RESERVED0[24];

+  __IO uint32_t ICER[8];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register         */

+       uint32_t RSERVED1[24];

+  __IO uint32_t ISPR[8];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register          */

+       uint32_t RESERVED2[24];

+  __IO uint32_t ICPR[8];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register        */

+       uint32_t RESERVED3[24];

+  __IO uint32_t IABR[8];                 /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register           */

+       uint32_t RESERVED4[56];

+  __IO uint8_t  IP[240];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */

+       uint32_t RESERVED5[644];

+  __O  uint32_t STIR;                    /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register     */

+}  NVIC_Type;

+

+/* Software Triggered Interrupt Register Definitions */

+#define NVIC_STIR_INTID_Pos                 0                                          /*!< STIR: INTLINESNUM Position */

+#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */

+

+/*@} end of group CMSIS_NVIC */

+

+

+/** \ingroup  CMSIS_core_register

+    \defgroup CMSIS_SCB     System Control Block (SCB)

+    \brief      Type definitions for the System Control Block Registers

+  @{

+ */

+

+/** \brief  Structure type to access the System Control Block (SCB).

+ */

+typedef struct

+{

+  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */

+  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */

+  __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */

+  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */

+  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */

+  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */

+  __IO uint8_t  SHP[12];                 /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */

+  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */

+  __IO uint32_t CFSR;                    /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register                    */

+  __IO uint32_t HFSR;                    /*!< Offset: 0x02C (R/W)  HardFault Status Register                             */

+  __IO uint32_t DFSR;                    /*!< Offset: 0x030 (R/W)  Debug Fault Status Register                           */

+  __IO uint32_t MMFAR;                   /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register                      */

+  __IO uint32_t BFAR;                    /*!< Offset: 0x038 (R/W)  BusFault Address Register                             */

+  __IO uint32_t AFSR;                    /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register                       */

+  __I  uint32_t PFR[2];                  /*!< Offset: 0x040 (R/ )  Processor Feature Register                            */

+  __I  uint32_t DFR;                     /*!< Offset: 0x048 (R/ )  Debug Feature Register                                */

+  __I  uint32_t ADR;                     /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register                            */

+  __I  uint32_t MMFR[4];                 /*!< Offset: 0x050 (R/ )  Memory Model Feature Register                         */

+  __I  uint32_t ISAR[5];                 /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register                   */

+       uint32_t RESERVED0[5];

+  __IO uint32_t CPACR;                   /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register                   */

+} SCB_Type;

+

+/* SCB CPUID Register Definitions */

+#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */

+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */

+

+#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */

+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */

+

+#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */

+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */

+

+#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */

+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */

+

+#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */

+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */

+

+/* SCB Interrupt Control State Register Definitions */

+#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */

+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */

+

+#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */

+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */

+

+#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */

+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */

+

+#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */

+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */

+

+#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */

+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */

+

+#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */

+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */

+

+#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */

+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */

+

+#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */

+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */

+

+#define SCB_ICSR_RETTOBASE_Pos             11                                             /*!< SCB ICSR: RETTOBASE Position */

+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */

+

+#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */

+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */

+

+/* SCB Vector Table Offset Register Definitions */

+#if (__CM3_REV < 0x0201)                   /* core r2p1 */

+#define SCB_VTOR_TBLBASE_Pos               29                                             /*!< SCB VTOR: TBLBASE Position */

+#define SCB_VTOR_TBLBASE_Msk               (1UL << SCB_VTOR_TBLBASE_Pos)                  /*!< SCB VTOR: TBLBASE Mask */

+

+#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */

+#define SCB_VTOR_TBLOFF_Msk                (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */

+#else

+#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */

+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */

+#endif

+

+/* SCB Application Interrupt and Reset Control Register Definitions */

+#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */

+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */

+

+#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */

+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */

+

+#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */

+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */

+

+#define SCB_AIRCR_PRIGROUP_Pos              8                                             /*!< SCB AIRCR: PRIGROUP Position */

+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */

+

+#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */

+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */

+

+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */

+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */

+

+#define SCB_AIRCR_VECTRESET_Pos             0                                             /*!< SCB AIRCR: VECTRESET Position */

+#define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */

+

+/* SCB System Control Register Definitions */

+#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */

+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */

+

+#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */

+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */

+

+#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */

+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */

+

+/* SCB Configuration Control Register Definitions */

+#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */

+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */

+

+#define SCB_CCR_BFHFNMIGN_Pos               8                                             /*!< SCB CCR: BFHFNMIGN Position */

+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */

+

+#define SCB_CCR_DIV_0_TRP_Pos               4                                             /*!< SCB CCR: DIV_0_TRP Position */

+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */

+

+#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */

+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */

+

+#define SCB_CCR_USERSETMPEND_Pos            1                                             /*!< SCB CCR: USERSETMPEND Position */

+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */

+

+#define SCB_CCR_NONBASETHRDENA_Pos          0                                             /*!< SCB CCR: NONBASETHRDENA Position */

+#define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */

+

+/* SCB System Handler Control and State Register Definitions */

+#define SCB_SHCSR_USGFAULTENA_Pos          18                                             /*!< SCB SHCSR: USGFAULTENA Position */

+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */

+

+#define SCB_SHCSR_BUSFAULTENA_Pos          17                                             /*!< SCB SHCSR: BUSFAULTENA Position */

+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */

+

+#define SCB_SHCSR_MEMFAULTENA_Pos          16                                             /*!< SCB SHCSR: MEMFAULTENA Position */

+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */

+

+#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */

+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */

+

+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14                                             /*!< SCB SHCSR: BUSFAULTPENDED Position */

+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */

+

+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13                                             /*!< SCB SHCSR: MEMFAULTPENDED Position */

+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */

+

+#define SCB_SHCSR_USGFAULTPENDED_Pos       12                                             /*!< SCB SHCSR: USGFAULTPENDED Position */

+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */

+

+#define SCB_SHCSR_SYSTICKACT_Pos           11                                             /*!< SCB SHCSR: SYSTICKACT Position */

+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */

+

+#define SCB_SHCSR_PENDSVACT_Pos            10                                             /*!< SCB SHCSR: PENDSVACT Position */

+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */

+

+#define SCB_SHCSR_MONITORACT_Pos            8                                             /*!< SCB SHCSR: MONITORACT Position */

+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */

+

+#define SCB_SHCSR_SVCALLACT_Pos             7                                             /*!< SCB SHCSR: SVCALLACT Position */

+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */

+

+#define SCB_SHCSR_USGFAULTACT_Pos           3                                             /*!< SCB SHCSR: USGFAULTACT Position */

+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */

+

+#define SCB_SHCSR_BUSFAULTACT_Pos           1                                             /*!< SCB SHCSR: BUSFAULTACT Position */

+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */

+

+#define SCB_SHCSR_MEMFAULTACT_Pos           0                                             /*!< SCB SHCSR: MEMFAULTACT Position */

+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */

+

+/* SCB Configurable Fault Status Registers Definitions */

+#define SCB_CFSR_USGFAULTSR_Pos            16                                             /*!< SCB CFSR: Usage Fault Status Register Position */

+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */

+

+#define SCB_CFSR_BUSFAULTSR_Pos             8                                             /*!< SCB CFSR: Bus Fault Status Register Position */

+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */

+

+#define SCB_CFSR_MEMFAULTSR_Pos             0                                             /*!< SCB CFSR: Memory Manage Fault Status Register Position */

+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */

+

+/* SCB Hard Fault Status Registers Definitions */

+#define SCB_HFSR_DEBUGEVT_Pos              31                                             /*!< SCB HFSR: DEBUGEVT Position */

+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */

+

+#define SCB_HFSR_FORCED_Pos                30                                             /*!< SCB HFSR: FORCED Position */

+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */

+

+#define SCB_HFSR_VECTTBL_Pos                1                                             /*!< SCB HFSR: VECTTBL Position */

+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */

+

+/* SCB Debug Fault Status Register Definitions */

+#define SCB_DFSR_EXTERNAL_Pos               4                                             /*!< SCB DFSR: EXTERNAL Position */

+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */

+

+#define SCB_DFSR_VCATCH_Pos                 3                                             /*!< SCB DFSR: VCATCH Position */

+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */

+

+#define SCB_DFSR_DWTTRAP_Pos                2                                             /*!< SCB DFSR: DWTTRAP Position */

+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */

+

+#define SCB_DFSR_BKPT_Pos                   1                                             /*!< SCB DFSR: BKPT Position */

+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */

+

+#define SCB_DFSR_HALTED_Pos                 0                                             /*!< SCB DFSR: HALTED Position */

+#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */

+

+/*@} end of group CMSIS_SCB */

+

+

+/** \ingroup  CMSIS_core_register

+    \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)

+    \brief      Type definitions for the System Control and ID Register not in the SCB

+  @{

+ */

+

+/** \brief  Structure type to access the System Control and ID Register not in the SCB.

+ */

+typedef struct

+{

+       uint32_t RESERVED0[1];

+  __I  uint32_t ICTR;                    /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register      */

+#if ((defined __CM3_REV) && (__CM3_REV >= 0x200))

+  __IO uint32_t ACTLR;                   /*!< Offset: 0x008 (R/W)  Auxiliary Control Register      */

+#else

+       uint32_t RESERVED1[1];

+#endif

+} SCnSCB_Type;

+

+/* Interrupt Controller Type Register Definitions */

+#define SCnSCB_ICTR_INTLINESNUM_Pos         0                                          /*!< ICTR: INTLINESNUM Position */

+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */

+

+/* Auxiliary Control Register Definitions */

+

+#define SCnSCB_ACTLR_DISFOLD_Pos            2                                          /*!< ACTLR: DISFOLD Position */

+#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */

+

+#define SCnSCB_ACTLR_DISDEFWBUF_Pos         1                                          /*!< ACTLR: DISDEFWBUF Position */

+#define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */

+

+#define SCnSCB_ACTLR_DISMCYCINT_Pos         0                                          /*!< ACTLR: DISMCYCINT Position */

+#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */

+

+/*@} end of group CMSIS_SCnotSCB */

+

+

+/** \ingroup  CMSIS_core_register

+    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)

+    \brief      Type definitions for the System Timer Registers.

+  @{

+ */

+

+/** \brief  Structure type to access the System Timer (SysTick).

+ */

+typedef struct

+{

+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */

+  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */

+  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */

+  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */

+} SysTick_Type;

+

+/* SysTick Control / Status Register Definitions */

+#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */

+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */

+

+#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */

+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */

+

+#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */

+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */

+

+#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */

+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */

+

+/* SysTick Reload Register Definitions */

+#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */

+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */

+

+/* SysTick Current Register Definitions */

+#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */

+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */

+

+/* SysTick Calibration Register Definitions */

+#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */

+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */

+

+#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */

+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */

+

+#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */

+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */

+

+/*@} end of group CMSIS_SysTick */

+

+

+/** \ingroup  CMSIS_core_register

+    \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)

+    \brief      Type definitions for the Instrumentation Trace Macrocell (ITM)

+  @{

+ */

+

+/** \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).

+ */

+typedef struct

+{

+  __O  union

+  {

+    __O  uint8_t    u8;                  /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit                   */

+    __O  uint16_t   u16;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit                  */

+    __O  uint32_t   u32;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit                  */

+  }  PORT [32];                          /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers               */

+       uint32_t RESERVED0[864];

+  __IO uint32_t TER;                     /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register                 */

+       uint32_t RESERVED1[15];

+  __IO uint32_t TPR;                     /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register              */

+       uint32_t RESERVED2[15];

+  __IO uint32_t TCR;                     /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register                */

+       uint32_t RESERVED3[29];

+  __O  uint32_t IWR;                     /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register            */

+  __I  uint32_t IRR;                     /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register             */

+  __IO uint32_t IMCR;                    /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register     */

+       uint32_t RESERVED4[43];

+  __O  uint32_t LAR;                     /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register                  */

+  __I  uint32_t LSR;                     /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register                  */

+       uint32_t RESERVED5[6];

+  __I  uint32_t PID4;                    /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */

+  __I  uint32_t PID5;                    /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */

+  __I  uint32_t PID6;                    /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */

+  __I  uint32_t PID7;                    /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */

+  __I  uint32_t PID0;                    /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */

+  __I  uint32_t PID1;                    /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */

+  __I  uint32_t PID2;                    /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */

+  __I  uint32_t PID3;                    /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */

+  __I  uint32_t CID0;                    /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */

+  __I  uint32_t CID1;                    /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */

+  __I  uint32_t CID2;                    /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */

+  __I  uint32_t CID3;                    /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */

+} ITM_Type;

+

+/* ITM Trace Privilege Register Definitions */

+#define ITM_TPR_PRIVMASK_Pos                0                                             /*!< ITM TPR: PRIVMASK Position */

+#define ITM_TPR_PRIVMASK_Msk               (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)            /*!< ITM TPR: PRIVMASK Mask */

+

+/* ITM Trace Control Register Definitions */

+#define ITM_TCR_BUSY_Pos                   23                                             /*!< ITM TCR: BUSY Position */

+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */

+

+#define ITM_TCR_TraceBusID_Pos             16                                             /*!< ITM TCR: ATBID Position */

+#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */

+

+#define ITM_TCR_GTSFREQ_Pos                10                                             /*!< ITM TCR: Global timestamp frequency Position */

+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */

+

+#define ITM_TCR_TSPrescale_Pos              8                                             /*!< ITM TCR: TSPrescale Position */

+#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */

+

+#define ITM_TCR_SWOENA_Pos                  4                                             /*!< ITM TCR: SWOENA Position */

+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */

+

+#define ITM_TCR_DWTENA_Pos                  3                                             /*!< ITM TCR: DWTENA Position */

+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */

+

+#define ITM_TCR_SYNCENA_Pos                 2                                             /*!< ITM TCR: SYNCENA Position */

+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */

+

+#define ITM_TCR_TSENA_Pos                   1                                             /*!< ITM TCR: TSENA Position */

+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */

+

+#define ITM_TCR_ITMENA_Pos                  0                                             /*!< ITM TCR: ITM Enable bit Position */

+#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */

+

+/* ITM Integration Write Register Definitions */

+#define ITM_IWR_ATVALIDM_Pos                0                                             /*!< ITM IWR: ATVALIDM Position */

+#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */

+

+/* ITM Integration Read Register Definitions */

+#define ITM_IRR_ATREADYM_Pos                0                                             /*!< ITM IRR: ATREADYM Position */

+#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */

+

+/* ITM Integration Mode Control Register Definitions */

+#define ITM_IMCR_INTEGRATION_Pos            0                                             /*!< ITM IMCR: INTEGRATION Position */

+#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */

+

+/* ITM Lock Status Register Definitions */

+#define ITM_LSR_ByteAcc_Pos                 2                                             /*!< ITM LSR: ByteAcc Position */

+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */

+

+#define ITM_LSR_Access_Pos                  1                                             /*!< ITM LSR: Access Position */

+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */

+

+#define ITM_LSR_Present_Pos                 0                                             /*!< ITM LSR: Present Position */

+#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */

+

+/*@}*/ /* end of group CMSIS_ITM */

+

+

+/** \ingroup  CMSIS_core_register

+    \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)

+    \brief      Type definitions for the Data Watchpoint and Trace (DWT)

+  @{

+ */

+

+/** \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).

+ */

+typedef struct

+{

+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  Control Register                          */

+  __IO uint32_t CYCCNT;                  /*!< Offset: 0x004 (R/W)  Cycle Count Register                      */

+  __IO uint32_t CPICNT;                  /*!< Offset: 0x008 (R/W)  CPI Count Register                        */

+  __IO uint32_t EXCCNT;                  /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register         */

+  __IO uint32_t SLEEPCNT;                /*!< Offset: 0x010 (R/W)  Sleep Count Register                      */

+  __IO uint32_t LSUCNT;                  /*!< Offset: 0x014 (R/W)  LSU Count Register                        */

+  __IO uint32_t FOLDCNT;                 /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register         */

+  __I  uint32_t PCSR;                    /*!< Offset: 0x01C (R/ )  Program Counter Sample Register           */

+  __IO uint32_t COMP0;                   /*!< Offset: 0x020 (R/W)  Comparator Register 0                     */

+  __IO uint32_t MASK0;                   /*!< Offset: 0x024 (R/W)  Mask Register 0                           */

+  __IO uint32_t FUNCTION0;               /*!< Offset: 0x028 (R/W)  Function Register 0                       */

+       uint32_t RESERVED0[1];

+  __IO uint32_t COMP1;                   /*!< Offset: 0x030 (R/W)  Comparator Register 1                     */

+  __IO uint32_t MASK1;                   /*!< Offset: 0x034 (R/W)  Mask Register 1                           */

+  __IO uint32_t FUNCTION1;               /*!< Offset: 0x038 (R/W)  Function Register 1                       */

+       uint32_t RESERVED1[1];

+  __IO uint32_t COMP2;                   /*!< Offset: 0x040 (R/W)  Comparator Register 2                     */

+  __IO uint32_t MASK2;                   /*!< Offset: 0x044 (R/W)  Mask Register 2                           */

+  __IO uint32_t FUNCTION2;               /*!< Offset: 0x048 (R/W)  Function Register 2                       */

+       uint32_t RESERVED2[1];

+  __IO uint32_t COMP3;                   /*!< Offset: 0x050 (R/W)  Comparator Register 3                     */

+  __IO uint32_t MASK3;                   /*!< Offset: 0x054 (R/W)  Mask Register 3                           */

+  __IO uint32_t FUNCTION3;               /*!< Offset: 0x058 (R/W)  Function Register 3                       */

+} DWT_Type;

+

+/* DWT Control Register Definitions */

+#define DWT_CTRL_NUMCOMP_Pos               28                                          /*!< DWT CTRL: NUMCOMP Position */

+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */

+

+#define DWT_CTRL_NOTRCPKT_Pos              27                                          /*!< DWT CTRL: NOTRCPKT Position */

+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */

+

+#define DWT_CTRL_NOEXTTRIG_Pos             26                                          /*!< DWT CTRL: NOEXTTRIG Position */

+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */

+

+#define DWT_CTRL_NOCYCCNT_Pos              25                                          /*!< DWT CTRL: NOCYCCNT Position */

+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */

+

+#define DWT_CTRL_NOPRFCNT_Pos              24                                          /*!< DWT CTRL: NOPRFCNT Position */

+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */

+

+#define DWT_CTRL_CYCEVTENA_Pos             22                                          /*!< DWT CTRL: CYCEVTENA Position */

+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */

+

+#define DWT_CTRL_FOLDEVTENA_Pos            21                                          /*!< DWT CTRL: FOLDEVTENA Position */

+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */

+

+#define DWT_CTRL_LSUEVTENA_Pos             20                                          /*!< DWT CTRL: LSUEVTENA Position */

+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */

+

+#define DWT_CTRL_SLEEPEVTENA_Pos           19                                          /*!< DWT CTRL: SLEEPEVTENA Position */

+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */

+

+#define DWT_CTRL_EXCEVTENA_Pos             18                                          /*!< DWT CTRL: EXCEVTENA Position */

+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */

+

+#define DWT_CTRL_CPIEVTENA_Pos             17                                          /*!< DWT CTRL: CPIEVTENA Position */

+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */

+

+#define DWT_CTRL_EXCTRCENA_Pos             16                                          /*!< DWT CTRL: EXCTRCENA Position */

+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */

+

+#define DWT_CTRL_PCSAMPLENA_Pos            12                                          /*!< DWT CTRL: PCSAMPLENA Position */

+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */

+

+#define DWT_CTRL_SYNCTAP_Pos               10                                          /*!< DWT CTRL: SYNCTAP Position */

+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */

+

+#define DWT_CTRL_CYCTAP_Pos                 9                                          /*!< DWT CTRL: CYCTAP Position */

+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */

+

+#define DWT_CTRL_POSTINIT_Pos               5                                          /*!< DWT CTRL: POSTINIT Position */

+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */

+

+#define DWT_CTRL_POSTPRESET_Pos             1                                          /*!< DWT CTRL: POSTPRESET Position */

+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */

+

+#define DWT_CTRL_CYCCNTENA_Pos              0                                          /*!< DWT CTRL: CYCCNTENA Position */

+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */

+

+/* DWT CPI Count Register Definitions */

+#define DWT_CPICNT_CPICNT_Pos               0                                          /*!< DWT CPICNT: CPICNT Position */

+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */

+

+/* DWT Exception Overhead Count Register Definitions */

+#define DWT_EXCCNT_EXCCNT_Pos               0                                          /*!< DWT EXCCNT: EXCCNT Position */

+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */

+

+/* DWT Sleep Count Register Definitions */

+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0                                          /*!< DWT SLEEPCNT: SLEEPCNT Position */

+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */

+

+/* DWT LSU Count Register Definitions */

+#define DWT_LSUCNT_LSUCNT_Pos               0                                          /*!< DWT LSUCNT: LSUCNT Position */

+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */

+

+/* DWT Folded-instruction Count Register Definitions */

+#define DWT_FOLDCNT_FOLDCNT_Pos             0                                          /*!< DWT FOLDCNT: FOLDCNT Position */

+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */

+

+/* DWT Comparator Mask Register Definitions */

+#define DWT_MASK_MASK_Pos                   0                                          /*!< DWT MASK: MASK Position */

+#define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */

+

+/* DWT Comparator Function Register Definitions */

+#define DWT_FUNCTION_MATCHED_Pos           24                                          /*!< DWT FUNCTION: MATCHED Position */

+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */

+

+#define DWT_FUNCTION_DATAVADDR1_Pos        16                                          /*!< DWT FUNCTION: DATAVADDR1 Position */

+#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */

+

+#define DWT_FUNCTION_DATAVADDR0_Pos        12                                          /*!< DWT FUNCTION: DATAVADDR0 Position */

+#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */

+

+#define DWT_FUNCTION_DATAVSIZE_Pos         10                                          /*!< DWT FUNCTION: DATAVSIZE Position */

+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */

+

+#define DWT_FUNCTION_LNK1ENA_Pos            9                                          /*!< DWT FUNCTION: LNK1ENA Position */

+#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */

+

+#define DWT_FUNCTION_DATAVMATCH_Pos         8                                          /*!< DWT FUNCTION: DATAVMATCH Position */

+#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */

+

+#define DWT_FUNCTION_CYCMATCH_Pos           7                                          /*!< DWT FUNCTION: CYCMATCH Position */

+#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */

+

+#define DWT_FUNCTION_EMITRANGE_Pos          5                                          /*!< DWT FUNCTION: EMITRANGE Position */

+#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */

+

+#define DWT_FUNCTION_FUNCTION_Pos           0                                          /*!< DWT FUNCTION: FUNCTION Position */

+#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */

+

+/*@}*/ /* end of group CMSIS_DWT */

+

+

+/** \ingroup  CMSIS_core_register

+    \defgroup CMSIS_TPI     Trace Port Interface (TPI)

+    \brief      Type definitions for the Trace Port Interface (TPI)

+  @{

+ */

+

+/** \brief  Structure type to access the Trace Port Interface Register (TPI).

+ */

+typedef struct

+{

+  __IO uint32_t SSPSR;                   /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register     */

+  __IO uint32_t CSPSR;                   /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */

+       uint32_t RESERVED0[2];

+  __IO uint32_t ACPR;                    /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */

+       uint32_t RESERVED1[55];

+  __IO uint32_t SPPR;                    /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */

+       uint32_t RESERVED2[131];

+  __I  uint32_t FFSR;                    /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */

+  __IO uint32_t FFCR;                    /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */

+  __I  uint32_t FSCR;                    /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */

+       uint32_t RESERVED3[759];

+  __I  uint32_t TRIGGER;                 /*!< Offset: 0xEE8 (R/ )  TRIGGER */

+  __I  uint32_t FIFO0;                   /*!< Offset: 0xEEC (R/ )  Integration ETM Data */

+  __I  uint32_t ITATBCTR2;               /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */

+       uint32_t RESERVED4[1];

+  __I  uint32_t ITATBCTR0;               /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */

+  __I  uint32_t FIFO1;                   /*!< Offset: 0xEFC (R/ )  Integration ITM Data */

+  __IO uint32_t ITCTRL;                  /*!< Offset: 0xF00 (R/W)  Integration Mode Control */

+       uint32_t RESERVED5[39];

+  __IO uint32_t CLAIMSET;                /*!< Offset: 0xFA0 (R/W)  Claim tag set */

+  __IO uint32_t CLAIMCLR;                /*!< Offset: 0xFA4 (R/W)  Claim tag clear */

+       uint32_t RESERVED7[8];

+  __I  uint32_t DEVID;                   /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */

+  __I  uint32_t DEVTYPE;                 /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */

+} TPI_Type;

+

+/* TPI Asynchronous Clock Prescaler Register Definitions */

+#define TPI_ACPR_PRESCALER_Pos              0                                          /*!< TPI ACPR: PRESCALER Position */

+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */

+

+/* TPI Selected Pin Protocol Register Definitions */

+#define TPI_SPPR_TXMODE_Pos                 0                                          /*!< TPI SPPR: TXMODE Position */

+#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */

+

+/* TPI Formatter and Flush Status Register Definitions */

+#define TPI_FFSR_FtNonStop_Pos              3                                          /*!< TPI FFSR: FtNonStop Position */

+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */

+

+#define TPI_FFSR_TCPresent_Pos              2                                          /*!< TPI FFSR: TCPresent Position */

+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */

+

+#define TPI_FFSR_FtStopped_Pos              1                                          /*!< TPI FFSR: FtStopped Position */

+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */

+

+#define TPI_FFSR_FlInProg_Pos               0                                          /*!< TPI FFSR: FlInProg Position */

+#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */

+

+/* TPI Formatter and Flush Control Register Definitions */

+#define TPI_FFCR_TrigIn_Pos                 8                                          /*!< TPI FFCR: TrigIn Position */

+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */

+

+#define TPI_FFCR_EnFCont_Pos                1                                          /*!< TPI FFCR: EnFCont Position */

+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */

+

+/* TPI TRIGGER Register Definitions */

+#define TPI_TRIGGER_TRIGGER_Pos             0                                          /*!< TPI TRIGGER: TRIGGER Position */

+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */

+

+/* TPI Integration ETM Data Register Definitions (FIFO0) */

+#define TPI_FIFO0_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO0: ITM_ATVALID Position */

+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */

+

+#define TPI_FIFO0_ITM_bytecount_Pos        27                                          /*!< TPI FIFO0: ITM_bytecount Position */

+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */

+

+#define TPI_FIFO0_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO0: ETM_ATVALID Position */

+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */

+

+#define TPI_FIFO0_ETM_bytecount_Pos        24                                          /*!< TPI FIFO0: ETM_bytecount Position */

+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */

+

+#define TPI_FIFO0_ETM2_Pos                 16                                          /*!< TPI FIFO0: ETM2 Position */

+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */

+

+#define TPI_FIFO0_ETM1_Pos                  8                                          /*!< TPI FIFO0: ETM1 Position */

+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */

+

+#define TPI_FIFO0_ETM0_Pos                  0                                          /*!< TPI FIFO0: ETM0 Position */

+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */

+

+/* TPI ITATBCTR2 Register Definitions */

+#define TPI_ITATBCTR2_ATREADY_Pos           0                                          /*!< TPI ITATBCTR2: ATREADY Position */

+#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/)    /*!< TPI ITATBCTR2: ATREADY Mask */

+

+/* TPI Integration ITM Data Register Definitions (FIFO1) */

+#define TPI_FIFO1_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO1: ITM_ATVALID Position */

+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */

+

+#define TPI_FIFO1_ITM_bytecount_Pos        27                                          /*!< TPI FIFO1: ITM_bytecount Position */

+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */

+

+#define TPI_FIFO1_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO1: ETM_ATVALID Position */

+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */

+

+#define TPI_FIFO1_ETM_bytecount_Pos        24                                          /*!< TPI FIFO1: ETM_bytecount Position */

+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */

+

+#define TPI_FIFO1_ITM2_Pos                 16                                          /*!< TPI FIFO1: ITM2 Position */

+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */

+

+#define TPI_FIFO1_ITM1_Pos                  8                                          /*!< TPI FIFO1: ITM1 Position */

+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */

+

+#define TPI_FIFO1_ITM0_Pos                  0                                          /*!< TPI FIFO1: ITM0 Position */

+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */

+

+/* TPI ITATBCTR0 Register Definitions */

+#define TPI_ITATBCTR0_ATREADY_Pos           0                                          /*!< TPI ITATBCTR0: ATREADY Position */

+#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/)    /*!< TPI ITATBCTR0: ATREADY Mask */

+

+/* TPI Integration Mode Control Register Definitions */

+#define TPI_ITCTRL_Mode_Pos                 0                                          /*!< TPI ITCTRL: Mode Position */

+#define TPI_ITCTRL_Mode_Msk                (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */

+

+/* TPI DEVID Register Definitions */

+#define TPI_DEVID_NRZVALID_Pos             11                                          /*!< TPI DEVID: NRZVALID Position */

+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */

+

+#define TPI_DEVID_MANCVALID_Pos            10                                          /*!< TPI DEVID: MANCVALID Position */

+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */

+

+#define TPI_DEVID_PTINVALID_Pos             9                                          /*!< TPI DEVID: PTINVALID Position */

+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */

+

+#define TPI_DEVID_MinBufSz_Pos              6                                          /*!< TPI DEVID: MinBufSz Position */

+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */

+

+#define TPI_DEVID_AsynClkIn_Pos             5                                          /*!< TPI DEVID: AsynClkIn Position */

+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */

+

+#define TPI_DEVID_NrTraceInput_Pos          0                                          /*!< TPI DEVID: NrTraceInput Position */

+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */

+

+/* TPI DEVTYPE Register Definitions */

+#define TPI_DEVTYPE_MajorType_Pos           4                                          /*!< TPI DEVTYPE: MajorType Position */

+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */

+

+#define TPI_DEVTYPE_SubType_Pos             0                                          /*!< TPI DEVTYPE: SubType Position */

+#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */

+

+/*@}*/ /* end of group CMSIS_TPI */

+

+

+#if (__MPU_PRESENT == 1)

+/** \ingroup  CMSIS_core_register

+    \defgroup CMSIS_MPU     Memory Protection Unit (MPU)

+    \brief      Type definitions for the Memory Protection Unit (MPU)

+  @{

+ */

+

+/** \brief  Structure type to access the Memory Protection Unit (MPU).

+ */

+typedef struct

+{

+  __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */

+  __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */

+  __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */

+  __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */

+  __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */

+  __IO uint32_t RBAR_A1;                 /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register       */

+  __IO uint32_t RASR_A1;                 /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */

+  __IO uint32_t RBAR_A2;                 /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register       */

+  __IO uint32_t RASR_A2;                 /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */

+  __IO uint32_t RBAR_A3;                 /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register       */

+  __IO uint32_t RASR_A3;                 /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */

+} MPU_Type;

+

+/* MPU Type Register */

+#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */

+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */

+

+#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */

+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */

+

+#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */

+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */

+

+/* MPU Control Register */

+#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */

+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */

+

+#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */

+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */

+

+#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */

+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */

+

+/* MPU Region Number Register */

+#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */

+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */

+

+/* MPU Region Base Address Register */

+#define MPU_RBAR_ADDR_Pos                   5                                             /*!< MPU RBAR: ADDR Position */

+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */

+

+#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */

+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */

+

+#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */

+#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */

+

+/* MPU Region Attribute and Size Register */

+#define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */

+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */

+

+#define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: ATTRS.XN Position */

+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */

+

+#define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: ATTRS.AP Position */

+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */

+

+#define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: ATTRS.TEX Position */

+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */

+

+#define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: ATTRS.S Position */

+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */

+

+#define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: ATTRS.C Position */

+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */

+

+#define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: ATTRS.B Position */

+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */

+

+#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */

+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */

+

+#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */

+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */

+

+#define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */

+#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */

+

+/*@} end of group CMSIS_MPU */

+#endif

+

+

+/** \ingroup  CMSIS_core_register

+    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)

+    \brief      Type definitions for the Core Debug Registers

+  @{

+ */

+

+/** \brief  Structure type to access the Core Debug Register (CoreDebug).

+ */

+typedef struct

+{

+  __IO uint32_t DHCSR;                   /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register    */

+  __O  uint32_t DCRSR;                   /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register        */

+  __IO uint32_t DCRDR;                   /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register            */

+  __IO uint32_t DEMCR;                   /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */

+} CoreDebug_Type;

+

+/* Debug Halting Control and Status Register */

+#define CoreDebug_DHCSR_DBGKEY_Pos         16                                             /*!< CoreDebug DHCSR: DBGKEY Position */

+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */

+

+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25                                             /*!< CoreDebug DHCSR: S_RESET_ST Position */

+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */

+

+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24                                             /*!< CoreDebug DHCSR: S_RETIRE_ST Position */

+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */

+

+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19                                             /*!< CoreDebug DHCSR: S_LOCKUP Position */

+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */

+

+#define CoreDebug_DHCSR_S_SLEEP_Pos        18                                             /*!< CoreDebug DHCSR: S_SLEEP Position */

+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */

+

+#define CoreDebug_DHCSR_S_HALT_Pos         17                                             /*!< CoreDebug DHCSR: S_HALT Position */

+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */

+

+#define CoreDebug_DHCSR_S_REGRDY_Pos       16                                             /*!< CoreDebug DHCSR: S_REGRDY Position */

+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */

+

+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5                                             /*!< CoreDebug DHCSR: C_SNAPSTALL Position */

+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */

+

+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3                                             /*!< CoreDebug DHCSR: C_MASKINTS Position */

+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */

+

+#define CoreDebug_DHCSR_C_STEP_Pos          2                                             /*!< CoreDebug DHCSR: C_STEP Position */

+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */

+

+#define CoreDebug_DHCSR_C_HALT_Pos          1                                             /*!< CoreDebug DHCSR: C_HALT Position */

+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */

+

+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0                                             /*!< CoreDebug DHCSR: C_DEBUGEN Position */

+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */

+

+/* Debug Core Register Selector Register */

+#define CoreDebug_DCRSR_REGWnR_Pos         16                                             /*!< CoreDebug DCRSR: REGWnR Position */

+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */

+

+#define CoreDebug_DCRSR_REGSEL_Pos          0                                             /*!< CoreDebug DCRSR: REGSEL Position */

+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */

+

+/* Debug Exception and Monitor Control Register */

+#define CoreDebug_DEMCR_TRCENA_Pos         24                                             /*!< CoreDebug DEMCR: TRCENA Position */

+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */

+

+#define CoreDebug_DEMCR_MON_REQ_Pos        19                                             /*!< CoreDebug DEMCR: MON_REQ Position */

+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */

+

+#define CoreDebug_DEMCR_MON_STEP_Pos       18                                             /*!< CoreDebug DEMCR: MON_STEP Position */

+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */

+

+#define CoreDebug_DEMCR_MON_PEND_Pos       17                                             /*!< CoreDebug DEMCR: MON_PEND Position */

+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */

+

+#define CoreDebug_DEMCR_MON_EN_Pos         16                                             /*!< CoreDebug DEMCR: MON_EN Position */

+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */

+

+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10                                             /*!< CoreDebug DEMCR: VC_HARDERR Position */

+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */

+

+#define CoreDebug_DEMCR_VC_INTERR_Pos       9                                             /*!< CoreDebug DEMCR: VC_INTERR Position */

+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */

+

+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8                                             /*!< CoreDebug DEMCR: VC_BUSERR Position */

+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */

+

+#define CoreDebug_DEMCR_VC_STATERR_Pos      7                                             /*!< CoreDebug DEMCR: VC_STATERR Position */

+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */

+

+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6                                             /*!< CoreDebug DEMCR: VC_CHKERR Position */

+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */

+

+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5                                             /*!< CoreDebug DEMCR: VC_NOCPERR Position */

+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */

+

+#define CoreDebug_DEMCR_VC_MMERR_Pos        4                                             /*!< CoreDebug DEMCR: VC_MMERR Position */

+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */

+

+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0                                             /*!< CoreDebug DEMCR: VC_CORERESET Position */

+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */

+

+/*@} end of group CMSIS_CoreDebug */

+

+

+/** \ingroup    CMSIS_core_register

+    \defgroup   CMSIS_core_base     Core Definitions

+    \brief      Definitions for base addresses, unions, and structures.

+  @{

+ */

+

+/* Memory mapping of Cortex-M3 Hardware */

+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address  */

+#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address                   */

+#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address                   */

+#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address                   */

+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address            */

+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address               */

+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                  */

+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address  */

+

+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */

+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */

+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */

+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */

+#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct           */

+#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct           */

+#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct           */

+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct    */

+

+#if (__MPU_PRESENT == 1)

+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */

+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */

+#endif

+

+/*@} */

+

+

+

+/*******************************************************************************

+ *                Hardware Abstraction Layer

+  Core Function Interface contains:

+  - Core NVIC Functions

+  - Core SysTick Functions

+  - Core Debug Functions

+  - Core Register Access Functions

+ ******************************************************************************/

+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference

+*/

+

+

+

+/* ##########################   NVIC functions  #################################### */

+/** \ingroup  CMSIS_Core_FunctionInterface

+    \defgroup CMSIS_Core_NVICFunctions NVIC Functions

+    \brief      Functions that manage interrupts and exceptions via the NVIC.

+    @{

+ */

+

+/** \brief  Set Priority Grouping

+

+  The function sets the priority grouping field using the required unlock sequence.

+  The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.

+  Only values from 0..7 are used.

+  In case of a conflict between priority grouping and available

+  priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.

+

+    \param [in]      PriorityGroup  Priority grouping field.

+ */

+__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)

+{

+  uint32_t reg_value;

+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */

+

+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */

+  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk));             /* clear bits to change               */

+  reg_value  =  (reg_value                                   |

+                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |

+                (PriorityGroupTmp << 8)                       );              /* Insert write key and priorty group */

+  SCB->AIRCR =  reg_value;

+}

+

+

+/** \brief  Get Priority Grouping

+

+  The function reads the priority grouping field from the NVIC Interrupt Controller.

+

+    \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).

+ */

+__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)

+{

+  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));

+}

+

+

+/** \brief  Enable External Interrupt

+

+    The function enables a device-specific interrupt in the NVIC interrupt controller.

+

+    \param [in]      IRQn  External interrupt number. Value cannot be negative.

+ */

+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)

+{

+  NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));

+}

+

+

+/** \brief  Disable External Interrupt

+

+    The function disables a device-specific interrupt in the NVIC interrupt controller.

+

+    \param [in]      IRQn  External interrupt number. Value cannot be negative.

+ */

+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)

+{

+  NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));

+}

+

+

+/** \brief  Get Pending Interrupt

+

+    The function reads the pending register in the NVIC and returns the pending bit

+    for the specified interrupt.

+

+    \param [in]      IRQn  Interrupt number.

+

+    \return             0  Interrupt status is not pending.

+    \return             1  Interrupt status is pending.

+ */

+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)

+{

+  return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));

+}

+

+

+/** \brief  Set Pending Interrupt

+

+    The function sets the pending bit of an external interrupt.

+

+    \param [in]      IRQn  Interrupt number. Value cannot be negative.

+ */

+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)

+{

+  NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));

+}

+

+

+/** \brief  Clear Pending Interrupt

+

+    The function clears the pending bit of an external interrupt.

+

+    \param [in]      IRQn  External interrupt number. Value cannot be negative.

+ */

+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)

+{

+  NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));

+}

+

+

+/** \brief  Get Active Interrupt

+

+    The function reads the active register in NVIC and returns the active bit.

+

+    \param [in]      IRQn  Interrupt number.

+

+    \return             0  Interrupt status is not active.

+    \return             1  Interrupt status is active.

+ */

+__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)

+{

+  return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));

+}

+

+

+/** \brief  Set Interrupt Priority

+

+    The function sets the priority of an interrupt.

+

+    \note The priority cannot be set for every core interrupt.

+

+    \param [in]      IRQn  Interrupt number.

+    \param [in]  priority  Priority to set.

+ */

+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)

+{

+  if((int32_t)IRQn < 0) {

+    SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);

+  }

+  else {

+    NVIC->IP[((uint32_t)(int32_t)IRQn)]               = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);

+  }

+}

+

+

+/** \brief  Get Interrupt Priority

+

+    The function reads the priority of an interrupt. The interrupt

+    number can be positive to specify an external (device specific)

+    interrupt, or negative to specify an internal (core) interrupt.

+

+

+    \param [in]   IRQn  Interrupt number.

+    \return             Interrupt Priority. Value is aligned automatically to the implemented

+                        priority bits of the microcontroller.

+ */

+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)

+{

+

+  if((int32_t)IRQn < 0) {

+    return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8 - __NVIC_PRIO_BITS)));

+  }

+  else {

+    return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)]               >> (8 - __NVIC_PRIO_BITS)));

+  }

+}

+

+

+/** \brief  Encode Priority

+

+    The function encodes the priority for an interrupt with the given priority group,

+    preemptive priority value, and subpriority value.

+    In case of a conflict between priority grouping and available

+    priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.

+

+    \param [in]     PriorityGroup  Used priority group.

+    \param [in]   PreemptPriority  Preemptive priority value (starting from 0).

+    \param [in]       SubPriority  Subpriority value (starting from 0).

+    \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().

+ */

+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)

+{

+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */

+  uint32_t PreemptPriorityBits;

+  uint32_t SubPriorityBits;

+

+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);

+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));

+

+  return (

+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |

+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))

+         );

+}

+

+

+/** \brief  Decode Priority

+

+    The function decodes an interrupt priority value with a given priority group to

+    preemptive priority value and subpriority value.

+    In case of a conflict between priority grouping and available

+    priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.

+

+    \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().

+    \param [in]     PriorityGroup  Used priority group.

+    \param [out] pPreemptPriority  Preemptive priority value (starting from 0).

+    \param [out]     pSubPriority  Subpriority value (starting from 0).

+ */

+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)

+{

+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */

+  uint32_t PreemptPriorityBits;

+  uint32_t SubPriorityBits;

+

+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);

+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));

+

+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);

+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);

+}

+

+

+/** \brief  System Reset

+

+    The function initiates a system reset request to reset the MCU.

+ */

+__STATIC_INLINE void NVIC_SystemReset(void)

+{

+  __DSB();                                                          /* Ensure all outstanding memory accesses included

+                                                                       buffered write are completed before reset */

+  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |

+                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |

+                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */

+  __DSB();                                                          /* Ensure completion of memory access */

+  while(1) { __NOP(); }                                             /* wait until reset */

+}

+

+/*@} end of CMSIS_Core_NVICFunctions */

+

+

+

+/* ##################################    SysTick function  ############################################ */

+/** \ingroup  CMSIS_Core_FunctionInterface

+    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions

+    \brief      Functions that configure the System.

+  @{

+ */

+

+#if (__Vendor_SysTickConfig == 0)

+

+/** \brief  System Tick Configuration

+

+    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.

+    Counter is in free running mode to generate periodic interrupts.

+

+    \param [in]  ticks  Number of ticks between two interrupts.

+

+    \return          0  Function succeeded.

+    \return          1  Function failed.

+

+    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the

+    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>

+    must contain a vendor-specific implementation of this function.

+

+ */

+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)

+{

+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); }    /* Reload value impossible */

+

+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */

+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */

+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */

+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |

+                   SysTick_CTRL_TICKINT_Msk   |

+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */

+  return (0UL);                                                     /* Function successful */

+}

+

+#endif

+

+/*@} end of CMSIS_Core_SysTickFunctions */

+

+

+

+/* ##################################### Debug In/Output function ########################################### */

+/** \ingroup  CMSIS_Core_FunctionInterface

+    \defgroup CMSIS_core_DebugFunctions ITM Functions

+    \brief   Functions that access the ITM debug interface.

+  @{

+ */

+

+extern volatile int32_t ITM_RxBuffer;                    /*!< External variable to receive characters.                         */

+#define                 ITM_RXBUFFER_EMPTY    0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */

+

+

+/** \brief  ITM Send Character

+

+    The function transmits a character via the ITM channel 0, and

+    \li Just returns when no debugger is connected that has booked the output.

+    \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.

+

+    \param [in]     ch  Character to transmit.

+

+    \returns            Character to transmit.

+ */

+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)

+{

+  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */

+      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */

+  {

+    while (ITM->PORT[0].u32 == 0UL) { __NOP(); }

+    ITM->PORT[0].u8 = (uint8_t)ch;

+  }

+  return (ch);

+}

+

+

+/** \brief  ITM Receive Character

+

+    The function inputs a character via the external variable \ref ITM_RxBuffer.

+

+    \return             Received character.

+    \return         -1  No character pending.

+ */

+__STATIC_INLINE int32_t ITM_ReceiveChar (void) {

+  int32_t ch = -1;                           /* no character available */

+

+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {

+    ch = ITM_RxBuffer;

+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */

+  }

+

+  return (ch);

+}

+

+

+/** \brief  ITM Check Character

+

+    The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.

+

+    \return          0  No character available.

+    \return          1  Character available.

+ */

+__STATIC_INLINE int32_t ITM_CheckChar (void) {

+

+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {

+    return (0);                                 /* no character available */

+  } else {

+    return (1);                                 /*    character available */

+  }

+}

+

+/*@} end of CMSIS_core_DebugFunctions */

+

+

+

+

+#ifdef __cplusplus

+}

+#endif

+

+#endif /* __CORE_CM3_H_DEPENDANT */

+

+#endif /* __CMSIS_GENERIC */

diff --git a/ext/TARGET_LPC1768/core_cm4.h b/ext/TARGET_LPC1768/core_cm4.h
new file mode 100644
index 0000000..544d414
--- /dev/null
+++ b/ext/TARGET_LPC1768/core_cm4.h
@@ -0,0 +1,1858 @@
+/**************************************************************************//**

+ * @file     core_cm4.h

+ * @brief    CMSIS Cortex-M4 Core Peripheral Access Layer Header File

+ * @version  V4.10

+ * @date     18. March 2015

+ *

+ * @note

+ *

+ ******************************************************************************/

+/* Copyright (c) 2009 - 2015 ARM LIMITED

+

+   All rights reserved.

+   Redistribution and use in source and binary forms, with or without

+   modification, are permitted provided that the following conditions are met:

+   - Redistributions of source code must retain the above copyright

+     notice, this list of conditions and the following disclaimer.

+   - Redistributions in binary form must reproduce the above copyright

+     notice, this list of conditions and the following disclaimer in the

+     documentation and/or other materials provided with the distribution.

+   - Neither the name of ARM nor the names of its contributors may be used

+     to endorse or promote products derived from this software without

+     specific prior written permission.

+   *

+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"

+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE

+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE

+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE

+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR

+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF

+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS

+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN

+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)

+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE

+   POSSIBILITY OF SUCH DAMAGE.

+   ---------------------------------------------------------------------------*/

+

+

+#if defined ( __ICCARM__ )

+ #pragma system_include  /* treat file as system include file for MISRA check */

+#endif

+

+#ifndef __CORE_CM4_H_GENERIC

+#define __CORE_CM4_H_GENERIC

+

+#ifdef __cplusplus

+ extern "C" {

+#endif

+

+/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions

+  CMSIS violates the following MISRA-C:2004 rules:

+

+   \li Required Rule 8.5, object/function definition in header file.<br>

+     Function definitions in header files are used to allow 'inlining'.

+

+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>

+     Unions are used for effective representation of core registers.

+

+   \li Advisory Rule 19.7, Function-like macro defined.<br>

+     Function-like macros are used to allow more efficient code.

+ */

+

+

+/*******************************************************************************

+ *                 CMSIS definitions

+ ******************************************************************************/

+/** \ingroup Cortex_M4

+  @{

+ */

+

+/*  CMSIS CM4 definitions */

+#define __CM4_CMSIS_VERSION_MAIN  (0x04)                                   /*!< [31:16] CMSIS HAL main version   */

+#define __CM4_CMSIS_VERSION_SUB   (0x00)                                   /*!< [15:0]  CMSIS HAL sub version    */

+#define __CM4_CMSIS_VERSION       ((__CM4_CMSIS_VERSION_MAIN << 16) | \

+                                    __CM4_CMSIS_VERSION_SUB          )     /*!< CMSIS HAL version number         */

+

+#define __CORTEX_M                (0x04)                                   /*!< Cortex-M Core                    */

+

+

+#if   defined ( __CC_ARM )

+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */

+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */

+  #define __STATIC_INLINE  static __inline

+

+#elif defined ( __GNUC__ )

+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */

+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */

+  #define __STATIC_INLINE  static inline

+

+#elif defined ( __ICCARM__ )

+  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */

+  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */

+  #define __STATIC_INLINE  static inline

+

+#elif defined ( __TMS470__ )

+  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler       */

+  #define __STATIC_INLINE  static inline

+

+#elif defined ( __TASKING__ )

+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */

+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */

+  #define __STATIC_INLINE  static inline

+

+#elif defined ( __CSMC__ )

+  #define __packed

+  #define __ASM            _asm                                      /*!< asm keyword for COSMIC Compiler      */

+  #define __INLINE         inline                                    /*use -pc99 on compile line !< inline keyword for COSMIC Compiler   */

+  #define __STATIC_INLINE  static inline

+

+#endif

+

+/** __FPU_USED indicates whether an FPU is used or not.

+    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.

+*/

+#if defined ( __CC_ARM )

+  #if defined __TARGET_FPU_VFP

+    #if (__FPU_PRESENT == 1)

+      #define __FPU_USED       1

+    #else

+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"

+      #define __FPU_USED       0

+    #endif

+  #else

+    #define __FPU_USED         0

+  #endif

+

+#elif defined ( __GNUC__ )

+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)

+    #if (__FPU_PRESENT == 1)

+      #define __FPU_USED       1

+    #else

+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"

+      #define __FPU_USED       0

+    #endif

+  #else

+    #define __FPU_USED         0

+  #endif

+

+#elif defined ( __ICCARM__ )

+  #if defined __ARMVFP__

+    #if (__FPU_PRESENT == 1)

+      #define __FPU_USED       1

+    #else

+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"

+      #define __FPU_USED       0

+    #endif

+  #else

+    #define __FPU_USED         0

+  #endif

+

+#elif defined ( __TMS470__ )

+  #if defined __TI_VFP_SUPPORT__

+    #if (__FPU_PRESENT == 1)

+      #define __FPU_USED       1

+    #else

+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"

+      #define __FPU_USED       0

+    #endif

+  #else

+    #define __FPU_USED         0

+  #endif

+

+#elif defined ( __TASKING__ )

+  #if defined __FPU_VFP__

+    #if (__FPU_PRESENT == 1)

+      #define __FPU_USED       1

+    #else

+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"

+      #define __FPU_USED       0

+    #endif

+  #else

+    #define __FPU_USED         0

+  #endif

+

+#elif defined ( __CSMC__ )		/* Cosmic */

+  #if ( __CSMC__ & 0x400)		// FPU present for parser

+    #if (__FPU_PRESENT == 1)

+      #define __FPU_USED       1

+    #else

+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"

+      #define __FPU_USED       0

+    #endif

+  #else

+    #define __FPU_USED         0

+  #endif

+#endif

+

+#include <stdint.h>                      /* standard types definitions                      */

+#include <core_cmInstr.h>                /* Core Instruction Access                         */

+#include <core_cmFunc.h>                 /* Core Function Access                            */

+#include <core_cmSimd.h>                 /* Compiler specific SIMD Intrinsics               */

+

+#ifdef __cplusplus

+}

+#endif

+

+#endif /* __CORE_CM4_H_GENERIC */

+

+#ifndef __CMSIS_GENERIC

+

+#ifndef __CORE_CM4_H_DEPENDANT

+#define __CORE_CM4_H_DEPENDANT

+

+#ifdef __cplusplus

+ extern "C" {

+#endif

+

+/* check device defines and use defaults */

+#if defined __CHECK_DEVICE_DEFINES

+  #ifndef __CM4_REV

+    #define __CM4_REV               0x0000

+    #warning "__CM4_REV not defined in device header file; using default!"

+  #endif

+

+  #ifndef __FPU_PRESENT

+    #define __FPU_PRESENT             0

+    #warning "__FPU_PRESENT not defined in device header file; using default!"

+  #endif

+

+  #ifndef __MPU_PRESENT

+    #define __MPU_PRESENT             0

+    #warning "__MPU_PRESENT not defined in device header file; using default!"

+  #endif

+

+  #ifndef __NVIC_PRIO_BITS

+    #define __NVIC_PRIO_BITS          4

+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"

+  #endif

+

+  #ifndef __Vendor_SysTickConfig

+    #define __Vendor_SysTickConfig    0

+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"

+  #endif

+#endif

+

+/* IO definitions (access restrictions to peripheral registers) */

+/**

+    \defgroup CMSIS_glob_defs CMSIS Global Defines

+

+    <strong>IO Type Qualifiers</strong> are used

+    \li to specify the access to peripheral variables.

+    \li for automatic generation of peripheral register debug information.

+*/

+#ifdef __cplusplus

+  #define   __I     volatile             /*!< Defines 'read only' permissions                 */

+#else

+  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */

+#endif

+#define     __O     volatile             /*!< Defines 'write only' permissions                */

+#define     __IO    volatile             /*!< Defines 'read / write' permissions              */

+

+/*@} end of group Cortex_M4 */

+

+

+

+/*******************************************************************************

+ *                 Register Abstraction

+  Core Register contain:

+  - Core Register

+  - Core NVIC Register

+  - Core SCB Register

+  - Core SysTick Register

+  - Core Debug Register

+  - Core MPU Register

+  - Core FPU Register

+ ******************************************************************************/

+/** \defgroup CMSIS_core_register Defines and Type Definitions

+    \brief Type definitions and defines for Cortex-M processor based devices.

+*/

+

+/** \ingroup    CMSIS_core_register

+    \defgroup   CMSIS_CORE  Status and Control Registers

+    \brief  Core Register type definitions.

+  @{

+ */

+

+/** \brief  Union type to access the Application Program Status Register (APSR).

+ */

+typedef union

+{

+  struct

+  {

+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */

+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */

+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */

+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */

+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */

+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */

+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */

+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */

+  } b;                                   /*!< Structure used for bit  access                  */

+  uint32_t w;                            /*!< Type      used for word access                  */

+} APSR_Type;

+

+/* APSR Register Definitions */

+#define APSR_N_Pos                         31                                             /*!< APSR: N Position */

+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */

+

+#define APSR_Z_Pos                         30                                             /*!< APSR: Z Position */

+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */

+

+#define APSR_C_Pos                         29                                             /*!< APSR: C Position */

+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */

+

+#define APSR_V_Pos                         28                                             /*!< APSR: V Position */

+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */

+

+#define APSR_Q_Pos                         27                                             /*!< APSR: Q Position */

+#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */

+

+#define APSR_GE_Pos                        16                                             /*!< APSR: GE Position */

+#define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR: GE Mask */

+

+

+/** \brief  Union type to access the Interrupt Program Status Register (IPSR).

+ */

+typedef union

+{

+  struct

+  {

+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */

+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */

+  } b;                                   /*!< Structure used for bit  access                  */

+  uint32_t w;                            /*!< Type      used for word access                  */

+} IPSR_Type;

+

+/* IPSR Register Definitions */

+#define IPSR_ISR_Pos                        0                                             /*!< IPSR: ISR Position */

+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */

+

+

+/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).

+ */

+typedef union

+{

+  struct

+  {

+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */

+    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */

+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */

+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */

+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */

+    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */

+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */

+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */

+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */

+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */

+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */

+  } b;                                   /*!< Structure used for bit  access                  */

+  uint32_t w;                            /*!< Type      used for word access                  */

+} xPSR_Type;

+

+/* xPSR Register Definitions */

+#define xPSR_N_Pos                         31                                             /*!< xPSR: N Position */

+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */

+

+#define xPSR_Z_Pos                         30                                             /*!< xPSR: Z Position */

+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */

+

+#define xPSR_C_Pos                         29                                             /*!< xPSR: C Position */

+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */

+

+#define xPSR_V_Pos                         28                                             /*!< xPSR: V Position */

+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */

+

+#define xPSR_Q_Pos                         27                                             /*!< xPSR: Q Position */

+#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */

+

+#define xPSR_IT_Pos                        25                                             /*!< xPSR: IT Position */

+#define xPSR_IT_Msk                        (3UL << xPSR_IT_Pos)                           /*!< xPSR: IT Mask */

+

+#define xPSR_T_Pos                         24                                             /*!< xPSR: T Position */

+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */

+

+#define xPSR_GE_Pos                        16                                             /*!< xPSR: GE Position */

+#define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR: GE Mask */

+

+#define xPSR_ISR_Pos                        0                                             /*!< xPSR: ISR Position */

+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */

+

+

+/** \brief  Union type to access the Control Registers (CONTROL).

+ */

+typedef union

+{

+  struct

+  {

+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */

+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */

+    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */

+    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */

+  } b;                                   /*!< Structure used for bit  access                  */

+  uint32_t w;                            /*!< Type      used for word access                  */

+} CONTROL_Type;

+

+/* CONTROL Register Definitions */

+#define CONTROL_FPCA_Pos                    2                                             /*!< CONTROL: FPCA Position */

+#define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONTROL: FPCA Mask */

+

+#define CONTROL_SPSEL_Pos                   1                                             /*!< CONTROL: SPSEL Position */

+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */

+

+#define CONTROL_nPRIV_Pos                   0                                             /*!< CONTROL: nPRIV Position */

+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */

+

+/*@} end of group CMSIS_CORE */

+

+

+/** \ingroup    CMSIS_core_register

+    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)

+    \brief      Type definitions for the NVIC Registers

+  @{

+ */

+

+/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).

+ */

+typedef struct

+{

+  __IO uint32_t ISER[8];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */

+       uint32_t RESERVED0[24];

+  __IO uint32_t ICER[8];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register         */

+       uint32_t RSERVED1[24];

+  __IO uint32_t ISPR[8];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register          */

+       uint32_t RESERVED2[24];

+  __IO uint32_t ICPR[8];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register        */

+       uint32_t RESERVED3[24];

+  __IO uint32_t IABR[8];                 /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register           */

+       uint32_t RESERVED4[56];

+  __IO uint8_t  IP[240];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */

+       uint32_t RESERVED5[644];

+  __O  uint32_t STIR;                    /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register     */

+}  NVIC_Type;

+

+/* Software Triggered Interrupt Register Definitions */

+#define NVIC_STIR_INTID_Pos                 0                                          /*!< STIR: INTLINESNUM Position */

+#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */

+

+/*@} end of group CMSIS_NVIC */

+

+

+/** \ingroup  CMSIS_core_register

+    \defgroup CMSIS_SCB     System Control Block (SCB)

+    \brief      Type definitions for the System Control Block Registers

+  @{

+ */

+

+/** \brief  Structure type to access the System Control Block (SCB).

+ */

+typedef struct

+{

+  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */

+  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */

+  __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */

+  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */

+  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */

+  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */

+  __IO uint8_t  SHP[12];                 /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */

+  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */

+  __IO uint32_t CFSR;                    /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register                    */

+  __IO uint32_t HFSR;                    /*!< Offset: 0x02C (R/W)  HardFault Status Register                             */

+  __IO uint32_t DFSR;                    /*!< Offset: 0x030 (R/W)  Debug Fault Status Register                           */

+  __IO uint32_t MMFAR;                   /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register                      */

+  __IO uint32_t BFAR;                    /*!< Offset: 0x038 (R/W)  BusFault Address Register                             */

+  __IO uint32_t AFSR;                    /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register                       */

+  __I  uint32_t PFR[2];                  /*!< Offset: 0x040 (R/ )  Processor Feature Register                            */

+  __I  uint32_t DFR;                     /*!< Offset: 0x048 (R/ )  Debug Feature Register                                */

+  __I  uint32_t ADR;                     /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register                            */

+  __I  uint32_t MMFR[4];                 /*!< Offset: 0x050 (R/ )  Memory Model Feature Register                         */

+  __I  uint32_t ISAR[5];                 /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register                   */

+       uint32_t RESERVED0[5];

+  __IO uint32_t CPACR;                   /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register                   */

+} SCB_Type;

+

+/* SCB CPUID Register Definitions */

+#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */

+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */

+

+#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */

+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */

+

+#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */

+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */

+

+#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */

+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */

+

+#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */

+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */

+

+/* SCB Interrupt Control State Register Definitions */

+#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */

+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */

+

+#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */

+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */

+

+#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */

+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */

+

+#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */

+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */

+

+#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */

+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */

+

+#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */

+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */

+

+#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */

+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */

+

+#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */

+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */

+

+#define SCB_ICSR_RETTOBASE_Pos             11                                             /*!< SCB ICSR: RETTOBASE Position */

+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */

+

+#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */

+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */

+

+/* SCB Vector Table Offset Register Definitions */

+#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */

+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */

+

+/* SCB Application Interrupt and Reset Control Register Definitions */

+#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */

+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */

+

+#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */

+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */

+

+#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */

+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */

+

+#define SCB_AIRCR_PRIGROUP_Pos              8                                             /*!< SCB AIRCR: PRIGROUP Position */

+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */

+

+#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */

+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */

+

+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */

+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */

+

+#define SCB_AIRCR_VECTRESET_Pos             0                                             /*!< SCB AIRCR: VECTRESET Position */

+#define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */

+

+/* SCB System Control Register Definitions */

+#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */

+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */

+

+#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */

+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */

+

+#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */

+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */

+

+/* SCB Configuration Control Register Definitions */

+#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */

+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */

+

+#define SCB_CCR_BFHFNMIGN_Pos               8                                             /*!< SCB CCR: BFHFNMIGN Position */

+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */

+

+#define SCB_CCR_DIV_0_TRP_Pos               4                                             /*!< SCB CCR: DIV_0_TRP Position */

+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */

+

+#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */

+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */

+

+#define SCB_CCR_USERSETMPEND_Pos            1                                             /*!< SCB CCR: USERSETMPEND Position */

+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */

+

+#define SCB_CCR_NONBASETHRDENA_Pos          0                                             /*!< SCB CCR: NONBASETHRDENA Position */

+#define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */

+

+/* SCB System Handler Control and State Register Definitions */

+#define SCB_SHCSR_USGFAULTENA_Pos          18                                             /*!< SCB SHCSR: USGFAULTENA Position */

+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */

+

+#define SCB_SHCSR_BUSFAULTENA_Pos          17                                             /*!< SCB SHCSR: BUSFAULTENA Position */

+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */

+

+#define SCB_SHCSR_MEMFAULTENA_Pos          16                                             /*!< SCB SHCSR: MEMFAULTENA Position */

+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */

+

+#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */

+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */

+

+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14                                             /*!< SCB SHCSR: BUSFAULTPENDED Position */

+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */

+

+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13                                             /*!< SCB SHCSR: MEMFAULTPENDED Position */

+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */

+

+#define SCB_SHCSR_USGFAULTPENDED_Pos       12                                             /*!< SCB SHCSR: USGFAULTPENDED Position */

+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */

+

+#define SCB_SHCSR_SYSTICKACT_Pos           11                                             /*!< SCB SHCSR: SYSTICKACT Position */

+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */

+

+#define SCB_SHCSR_PENDSVACT_Pos            10                                             /*!< SCB SHCSR: PENDSVACT Position */

+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */

+

+#define SCB_SHCSR_MONITORACT_Pos            8                                             /*!< SCB SHCSR: MONITORACT Position */

+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */

+

+#define SCB_SHCSR_SVCALLACT_Pos             7                                             /*!< SCB SHCSR: SVCALLACT Position */

+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */

+

+#define SCB_SHCSR_USGFAULTACT_Pos           3                                             /*!< SCB SHCSR: USGFAULTACT Position */

+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */

+

+#define SCB_SHCSR_BUSFAULTACT_Pos           1                                             /*!< SCB SHCSR: BUSFAULTACT Position */

+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */

+

+#define SCB_SHCSR_MEMFAULTACT_Pos           0                                             /*!< SCB SHCSR: MEMFAULTACT Position */

+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */

+

+/* SCB Configurable Fault Status Registers Definitions */

+#define SCB_CFSR_USGFAULTSR_Pos            16                                             /*!< SCB CFSR: Usage Fault Status Register Position */

+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */

+

+#define SCB_CFSR_BUSFAULTSR_Pos             8                                             /*!< SCB CFSR: Bus Fault Status Register Position */

+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */

+

+#define SCB_CFSR_MEMFAULTSR_Pos             0                                             /*!< SCB CFSR: Memory Manage Fault Status Register Position */

+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */

+

+/* SCB Hard Fault Status Registers Definitions */

+#define SCB_HFSR_DEBUGEVT_Pos              31                                             /*!< SCB HFSR: DEBUGEVT Position */

+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */

+

+#define SCB_HFSR_FORCED_Pos                30                                             /*!< SCB HFSR: FORCED Position */

+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */

+

+#define SCB_HFSR_VECTTBL_Pos                1                                             /*!< SCB HFSR: VECTTBL Position */

+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */

+

+/* SCB Debug Fault Status Register Definitions */

+#define SCB_DFSR_EXTERNAL_Pos               4                                             /*!< SCB DFSR: EXTERNAL Position */

+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */

+

+#define SCB_DFSR_VCATCH_Pos                 3                                             /*!< SCB DFSR: VCATCH Position */

+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */

+

+#define SCB_DFSR_DWTTRAP_Pos                2                                             /*!< SCB DFSR: DWTTRAP Position */

+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */

+

+#define SCB_DFSR_BKPT_Pos                   1                                             /*!< SCB DFSR: BKPT Position */

+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */

+

+#define SCB_DFSR_HALTED_Pos                 0                                             /*!< SCB DFSR: HALTED Position */

+#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */

+

+/*@} end of group CMSIS_SCB */

+

+

+/** \ingroup  CMSIS_core_register

+    \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)

+    \brief      Type definitions for the System Control and ID Register not in the SCB

+  @{

+ */

+

+/** \brief  Structure type to access the System Control and ID Register not in the SCB.

+ */

+typedef struct

+{

+       uint32_t RESERVED0[1];

+  __I  uint32_t ICTR;                    /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register      */

+  __IO uint32_t ACTLR;                   /*!< Offset: 0x008 (R/W)  Auxiliary Control Register              */

+} SCnSCB_Type;

+

+/* Interrupt Controller Type Register Definitions */

+#define SCnSCB_ICTR_INTLINESNUM_Pos         0                                          /*!< ICTR: INTLINESNUM Position */

+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */

+

+/* Auxiliary Control Register Definitions */

+#define SCnSCB_ACTLR_DISOOFP_Pos            9                                          /*!< ACTLR: DISOOFP Position */

+#define SCnSCB_ACTLR_DISOOFP_Msk           (1UL << SCnSCB_ACTLR_DISOOFP_Pos)           /*!< ACTLR: DISOOFP Mask */

+

+#define SCnSCB_ACTLR_DISFPCA_Pos            8                                          /*!< ACTLR: DISFPCA Position */

+#define SCnSCB_ACTLR_DISFPCA_Msk           (1UL << SCnSCB_ACTLR_DISFPCA_Pos)           /*!< ACTLR: DISFPCA Mask */

+

+#define SCnSCB_ACTLR_DISFOLD_Pos            2                                          /*!< ACTLR: DISFOLD Position */

+#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */

+

+#define SCnSCB_ACTLR_DISDEFWBUF_Pos         1                                          /*!< ACTLR: DISDEFWBUF Position */

+#define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */

+

+#define SCnSCB_ACTLR_DISMCYCINT_Pos         0                                          /*!< ACTLR: DISMCYCINT Position */

+#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */

+

+/*@} end of group CMSIS_SCnotSCB */

+

+

+/** \ingroup  CMSIS_core_register

+    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)

+    \brief      Type definitions for the System Timer Registers.

+  @{

+ */

+

+/** \brief  Structure type to access the System Timer (SysTick).

+ */

+typedef struct

+{

+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */

+  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */

+  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */

+  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */

+} SysTick_Type;

+

+/* SysTick Control / Status Register Definitions */

+#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */

+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */

+

+#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */

+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */

+

+#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */

+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */

+

+#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */

+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */

+

+/* SysTick Reload Register Definitions */

+#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */

+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */

+

+/* SysTick Current Register Definitions */

+#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */

+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */

+

+/* SysTick Calibration Register Definitions */

+#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */

+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */

+

+#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */

+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */

+

+#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */

+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */

+

+/*@} end of group CMSIS_SysTick */

+

+

+/** \ingroup  CMSIS_core_register

+    \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)

+    \brief      Type definitions for the Instrumentation Trace Macrocell (ITM)

+  @{

+ */

+

+/** \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).

+ */

+typedef struct

+{

+  __O  union

+  {

+    __O  uint8_t    u8;                  /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit                   */

+    __O  uint16_t   u16;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit                  */

+    __O  uint32_t   u32;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit                  */

+  }  PORT [32];                          /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers               */

+       uint32_t RESERVED0[864];

+  __IO uint32_t TER;                     /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register                 */

+       uint32_t RESERVED1[15];

+  __IO uint32_t TPR;                     /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register              */

+       uint32_t RESERVED2[15];

+  __IO uint32_t TCR;                     /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register                */

+       uint32_t RESERVED3[29];

+  __O  uint32_t IWR;                     /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register            */

+  __I  uint32_t IRR;                     /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register             */

+  __IO uint32_t IMCR;                    /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register     */

+       uint32_t RESERVED4[43];

+  __O  uint32_t LAR;                     /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register                  */

+  __I  uint32_t LSR;                     /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register                  */

+       uint32_t RESERVED5[6];

+  __I  uint32_t PID4;                    /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */

+  __I  uint32_t PID5;                    /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */

+  __I  uint32_t PID6;                    /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */

+  __I  uint32_t PID7;                    /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */

+  __I  uint32_t PID0;                    /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */

+  __I  uint32_t PID1;                    /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */

+  __I  uint32_t PID2;                    /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */

+  __I  uint32_t PID3;                    /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */

+  __I  uint32_t CID0;                    /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */

+  __I  uint32_t CID1;                    /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */

+  __I  uint32_t CID2;                    /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */

+  __I  uint32_t CID3;                    /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */

+} ITM_Type;

+

+/* ITM Trace Privilege Register Definitions */

+#define ITM_TPR_PRIVMASK_Pos                0                                             /*!< ITM TPR: PRIVMASK Position */

+#define ITM_TPR_PRIVMASK_Msk               (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)            /*!< ITM TPR: PRIVMASK Mask */

+

+/* ITM Trace Control Register Definitions */

+#define ITM_TCR_BUSY_Pos                   23                                             /*!< ITM TCR: BUSY Position */

+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */

+

+#define ITM_TCR_TraceBusID_Pos             16                                             /*!< ITM TCR: ATBID Position */

+#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */

+

+#define ITM_TCR_GTSFREQ_Pos                10                                             /*!< ITM TCR: Global timestamp frequency Position */

+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */

+

+#define ITM_TCR_TSPrescale_Pos              8                                             /*!< ITM TCR: TSPrescale Position */

+#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */

+

+#define ITM_TCR_SWOENA_Pos                  4                                             /*!< ITM TCR: SWOENA Position */

+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */

+

+#define ITM_TCR_DWTENA_Pos                  3                                             /*!< ITM TCR: DWTENA Position */

+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */

+

+#define ITM_TCR_SYNCENA_Pos                 2                                             /*!< ITM TCR: SYNCENA Position */

+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */

+

+#define ITM_TCR_TSENA_Pos                   1                                             /*!< ITM TCR: TSENA Position */

+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */

+

+#define ITM_TCR_ITMENA_Pos                  0                                             /*!< ITM TCR: ITM Enable bit Position */

+#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */

+

+/* ITM Integration Write Register Definitions */

+#define ITM_IWR_ATVALIDM_Pos                0                                             /*!< ITM IWR: ATVALIDM Position */

+#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */

+

+/* ITM Integration Read Register Definitions */

+#define ITM_IRR_ATREADYM_Pos                0                                             /*!< ITM IRR: ATREADYM Position */

+#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */

+

+/* ITM Integration Mode Control Register Definitions */

+#define ITM_IMCR_INTEGRATION_Pos            0                                             /*!< ITM IMCR: INTEGRATION Position */

+#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */

+

+/* ITM Lock Status Register Definitions */

+#define ITM_LSR_ByteAcc_Pos                 2                                             /*!< ITM LSR: ByteAcc Position */

+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */

+

+#define ITM_LSR_Access_Pos                  1                                             /*!< ITM LSR: Access Position */

+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */

+

+#define ITM_LSR_Present_Pos                 0                                             /*!< ITM LSR: Present Position */

+#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */

+

+/*@}*/ /* end of group CMSIS_ITM */

+

+

+/** \ingroup  CMSIS_core_register

+    \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)

+    \brief      Type definitions for the Data Watchpoint and Trace (DWT)

+  @{

+ */

+

+/** \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).

+ */

+typedef struct

+{

+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  Control Register                          */

+  __IO uint32_t CYCCNT;                  /*!< Offset: 0x004 (R/W)  Cycle Count Register                      */

+  __IO uint32_t CPICNT;                  /*!< Offset: 0x008 (R/W)  CPI Count Register                        */

+  __IO uint32_t EXCCNT;                  /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register         */

+  __IO uint32_t SLEEPCNT;                /*!< Offset: 0x010 (R/W)  Sleep Count Register                      */

+  __IO uint32_t LSUCNT;                  /*!< Offset: 0x014 (R/W)  LSU Count Register                        */

+  __IO uint32_t FOLDCNT;                 /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register         */

+  __I  uint32_t PCSR;                    /*!< Offset: 0x01C (R/ )  Program Counter Sample Register           */

+  __IO uint32_t COMP0;                   /*!< Offset: 0x020 (R/W)  Comparator Register 0                     */

+  __IO uint32_t MASK0;                   /*!< Offset: 0x024 (R/W)  Mask Register 0                           */

+  __IO uint32_t FUNCTION0;               /*!< Offset: 0x028 (R/W)  Function Register 0                       */

+       uint32_t RESERVED0[1];

+  __IO uint32_t COMP1;                   /*!< Offset: 0x030 (R/W)  Comparator Register 1                     */

+  __IO uint32_t MASK1;                   /*!< Offset: 0x034 (R/W)  Mask Register 1                           */

+  __IO uint32_t FUNCTION1;               /*!< Offset: 0x038 (R/W)  Function Register 1                       */

+       uint32_t RESERVED1[1];

+  __IO uint32_t COMP2;                   /*!< Offset: 0x040 (R/W)  Comparator Register 2                     */

+  __IO uint32_t MASK2;                   /*!< Offset: 0x044 (R/W)  Mask Register 2                           */

+  __IO uint32_t FUNCTION2;               /*!< Offset: 0x048 (R/W)  Function Register 2                       */

+       uint32_t RESERVED2[1];

+  __IO uint32_t COMP3;                   /*!< Offset: 0x050 (R/W)  Comparator Register 3                     */

+  __IO uint32_t MASK3;                   /*!< Offset: 0x054 (R/W)  Mask Register 3                           */

+  __IO uint32_t FUNCTION3;               /*!< Offset: 0x058 (R/W)  Function Register 3                       */

+} DWT_Type;

+

+/* DWT Control Register Definitions */

+#define DWT_CTRL_NUMCOMP_Pos               28                                          /*!< DWT CTRL: NUMCOMP Position */

+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */

+

+#define DWT_CTRL_NOTRCPKT_Pos              27                                          /*!< DWT CTRL: NOTRCPKT Position */

+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */

+

+#define DWT_CTRL_NOEXTTRIG_Pos             26                                          /*!< DWT CTRL: NOEXTTRIG Position */

+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */

+

+#define DWT_CTRL_NOCYCCNT_Pos              25                                          /*!< DWT CTRL: NOCYCCNT Position */

+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */

+

+#define DWT_CTRL_NOPRFCNT_Pos              24                                          /*!< DWT CTRL: NOPRFCNT Position */

+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */

+

+#define DWT_CTRL_CYCEVTENA_Pos             22                                          /*!< DWT CTRL: CYCEVTENA Position */

+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */

+

+#define DWT_CTRL_FOLDEVTENA_Pos            21                                          /*!< DWT CTRL: FOLDEVTENA Position */

+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */

+

+#define DWT_CTRL_LSUEVTENA_Pos             20                                          /*!< DWT CTRL: LSUEVTENA Position */

+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */

+

+#define DWT_CTRL_SLEEPEVTENA_Pos           19                                          /*!< DWT CTRL: SLEEPEVTENA Position */

+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */

+

+#define DWT_CTRL_EXCEVTENA_Pos             18                                          /*!< DWT CTRL: EXCEVTENA Position */

+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */

+

+#define DWT_CTRL_CPIEVTENA_Pos             17                                          /*!< DWT CTRL: CPIEVTENA Position */

+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */

+

+#define DWT_CTRL_EXCTRCENA_Pos             16                                          /*!< DWT CTRL: EXCTRCENA Position */

+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */

+

+#define DWT_CTRL_PCSAMPLENA_Pos            12                                          /*!< DWT CTRL: PCSAMPLENA Position */

+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */

+

+#define DWT_CTRL_SYNCTAP_Pos               10                                          /*!< DWT CTRL: SYNCTAP Position */

+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */

+

+#define DWT_CTRL_CYCTAP_Pos                 9                                          /*!< DWT CTRL: CYCTAP Position */

+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */

+

+#define DWT_CTRL_POSTINIT_Pos               5                                          /*!< DWT CTRL: POSTINIT Position */

+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */

+

+#define DWT_CTRL_POSTPRESET_Pos             1                                          /*!< DWT CTRL: POSTPRESET Position */

+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */

+

+#define DWT_CTRL_CYCCNTENA_Pos              0                                          /*!< DWT CTRL: CYCCNTENA Position */

+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */

+

+/* DWT CPI Count Register Definitions */

+#define DWT_CPICNT_CPICNT_Pos               0                                          /*!< DWT CPICNT: CPICNT Position */

+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */

+

+/* DWT Exception Overhead Count Register Definitions */

+#define DWT_EXCCNT_EXCCNT_Pos               0                                          /*!< DWT EXCCNT: EXCCNT Position */

+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */

+

+/* DWT Sleep Count Register Definitions */

+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0                                          /*!< DWT SLEEPCNT: SLEEPCNT Position */

+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */

+

+/* DWT LSU Count Register Definitions */

+#define DWT_LSUCNT_LSUCNT_Pos               0                                          /*!< DWT LSUCNT: LSUCNT Position */

+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */

+

+/* DWT Folded-instruction Count Register Definitions */

+#define DWT_FOLDCNT_FOLDCNT_Pos             0                                          /*!< DWT FOLDCNT: FOLDCNT Position */

+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */

+

+/* DWT Comparator Mask Register Definitions */

+#define DWT_MASK_MASK_Pos                   0                                          /*!< DWT MASK: MASK Position */

+#define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */

+

+/* DWT Comparator Function Register Definitions */

+#define DWT_FUNCTION_MATCHED_Pos           24                                          /*!< DWT FUNCTION: MATCHED Position */

+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */

+

+#define DWT_FUNCTION_DATAVADDR1_Pos        16                                          /*!< DWT FUNCTION: DATAVADDR1 Position */

+#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */

+

+#define DWT_FUNCTION_DATAVADDR0_Pos        12                                          /*!< DWT FUNCTION: DATAVADDR0 Position */

+#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */

+

+#define DWT_FUNCTION_DATAVSIZE_Pos         10                                          /*!< DWT FUNCTION: DATAVSIZE Position */

+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */

+

+#define DWT_FUNCTION_LNK1ENA_Pos            9                                          /*!< DWT FUNCTION: LNK1ENA Position */

+#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */

+

+#define DWT_FUNCTION_DATAVMATCH_Pos         8                                          /*!< DWT FUNCTION: DATAVMATCH Position */

+#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */

+

+#define DWT_FUNCTION_CYCMATCH_Pos           7                                          /*!< DWT FUNCTION: CYCMATCH Position */

+#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */

+

+#define DWT_FUNCTION_EMITRANGE_Pos          5                                          /*!< DWT FUNCTION: EMITRANGE Position */

+#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */

+

+#define DWT_FUNCTION_FUNCTION_Pos           0                                          /*!< DWT FUNCTION: FUNCTION Position */

+#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */

+

+/*@}*/ /* end of group CMSIS_DWT */

+

+

+/** \ingroup  CMSIS_core_register

+    \defgroup CMSIS_TPI     Trace Port Interface (TPI)

+    \brief      Type definitions for the Trace Port Interface (TPI)

+  @{

+ */

+

+/** \brief  Structure type to access the Trace Port Interface Register (TPI).

+ */

+typedef struct

+{

+  __IO uint32_t SSPSR;                   /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register     */

+  __IO uint32_t CSPSR;                   /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */

+       uint32_t RESERVED0[2];

+  __IO uint32_t ACPR;                    /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */

+       uint32_t RESERVED1[55];

+  __IO uint32_t SPPR;                    /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */

+       uint32_t RESERVED2[131];

+  __I  uint32_t FFSR;                    /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */

+  __IO uint32_t FFCR;                    /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */

+  __I  uint32_t FSCR;                    /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */

+       uint32_t RESERVED3[759];

+  __I  uint32_t TRIGGER;                 /*!< Offset: 0xEE8 (R/ )  TRIGGER */

+  __I  uint32_t FIFO0;                   /*!< Offset: 0xEEC (R/ )  Integration ETM Data */

+  __I  uint32_t ITATBCTR2;               /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */

+       uint32_t RESERVED4[1];

+  __I  uint32_t ITATBCTR0;               /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */

+  __I  uint32_t FIFO1;                   /*!< Offset: 0xEFC (R/ )  Integration ITM Data */

+  __IO uint32_t ITCTRL;                  /*!< Offset: 0xF00 (R/W)  Integration Mode Control */

+       uint32_t RESERVED5[39];

+  __IO uint32_t CLAIMSET;                /*!< Offset: 0xFA0 (R/W)  Claim tag set */

+  __IO uint32_t CLAIMCLR;                /*!< Offset: 0xFA4 (R/W)  Claim tag clear */

+       uint32_t RESERVED7[8];

+  __I  uint32_t DEVID;                   /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */

+  __I  uint32_t DEVTYPE;                 /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */

+} TPI_Type;

+

+/* TPI Asynchronous Clock Prescaler Register Definitions */

+#define TPI_ACPR_PRESCALER_Pos              0                                          /*!< TPI ACPR: PRESCALER Position */

+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */

+

+/* TPI Selected Pin Protocol Register Definitions */

+#define TPI_SPPR_TXMODE_Pos                 0                                          /*!< TPI SPPR: TXMODE Position */

+#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */

+

+/* TPI Formatter and Flush Status Register Definitions */

+#define TPI_FFSR_FtNonStop_Pos              3                                          /*!< TPI FFSR: FtNonStop Position */

+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */

+

+#define TPI_FFSR_TCPresent_Pos              2                                          /*!< TPI FFSR: TCPresent Position */

+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */

+

+#define TPI_FFSR_FtStopped_Pos              1                                          /*!< TPI FFSR: FtStopped Position */

+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */

+

+#define TPI_FFSR_FlInProg_Pos               0                                          /*!< TPI FFSR: FlInProg Position */

+#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */

+

+/* TPI Formatter and Flush Control Register Definitions */

+#define TPI_FFCR_TrigIn_Pos                 8                                          /*!< TPI FFCR: TrigIn Position */

+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */

+

+#define TPI_FFCR_EnFCont_Pos                1                                          /*!< TPI FFCR: EnFCont Position */

+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */

+

+/* TPI TRIGGER Register Definitions */

+#define TPI_TRIGGER_TRIGGER_Pos             0                                          /*!< TPI TRIGGER: TRIGGER Position */

+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */

+

+/* TPI Integration ETM Data Register Definitions (FIFO0) */

+#define TPI_FIFO0_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO0: ITM_ATVALID Position */

+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */

+

+#define TPI_FIFO0_ITM_bytecount_Pos        27                                          /*!< TPI FIFO0: ITM_bytecount Position */

+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */

+

+#define TPI_FIFO0_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO0: ETM_ATVALID Position */

+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */

+

+#define TPI_FIFO0_ETM_bytecount_Pos        24                                          /*!< TPI FIFO0: ETM_bytecount Position */

+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */

+

+#define TPI_FIFO0_ETM2_Pos                 16                                          /*!< TPI FIFO0: ETM2 Position */

+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */

+

+#define TPI_FIFO0_ETM1_Pos                  8                                          /*!< TPI FIFO0: ETM1 Position */

+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */

+

+#define TPI_FIFO0_ETM0_Pos                  0                                          /*!< TPI FIFO0: ETM0 Position */

+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */

+

+/* TPI ITATBCTR2 Register Definitions */

+#define TPI_ITATBCTR2_ATREADY_Pos           0                                          /*!< TPI ITATBCTR2: ATREADY Position */

+#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/)    /*!< TPI ITATBCTR2: ATREADY Mask */

+

+/* TPI Integration ITM Data Register Definitions (FIFO1) */

+#define TPI_FIFO1_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO1: ITM_ATVALID Position */

+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */

+

+#define TPI_FIFO1_ITM_bytecount_Pos        27                                          /*!< TPI FIFO1: ITM_bytecount Position */

+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */

+

+#define TPI_FIFO1_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO1: ETM_ATVALID Position */

+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */

+

+#define TPI_FIFO1_ETM_bytecount_Pos        24                                          /*!< TPI FIFO1: ETM_bytecount Position */

+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */

+

+#define TPI_FIFO1_ITM2_Pos                 16                                          /*!< TPI FIFO1: ITM2 Position */

+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */

+

+#define TPI_FIFO1_ITM1_Pos                  8                                          /*!< TPI FIFO1: ITM1 Position */

+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */

+

+#define TPI_FIFO1_ITM0_Pos                  0                                          /*!< TPI FIFO1: ITM0 Position */

+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */

+

+/* TPI ITATBCTR0 Register Definitions */

+#define TPI_ITATBCTR0_ATREADY_Pos           0                                          /*!< TPI ITATBCTR0: ATREADY Position */

+#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/)    /*!< TPI ITATBCTR0: ATREADY Mask */

+

+/* TPI Integration Mode Control Register Definitions */

+#define TPI_ITCTRL_Mode_Pos                 0                                          /*!< TPI ITCTRL: Mode Position */

+#define TPI_ITCTRL_Mode_Msk                (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */

+

+/* TPI DEVID Register Definitions */

+#define TPI_DEVID_NRZVALID_Pos             11                                          /*!< TPI DEVID: NRZVALID Position */

+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */

+

+#define TPI_DEVID_MANCVALID_Pos            10                                          /*!< TPI DEVID: MANCVALID Position */

+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */

+

+#define TPI_DEVID_PTINVALID_Pos             9                                          /*!< TPI DEVID: PTINVALID Position */

+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */

+

+#define TPI_DEVID_MinBufSz_Pos              6                                          /*!< TPI DEVID: MinBufSz Position */

+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */

+

+#define TPI_DEVID_AsynClkIn_Pos             5                                          /*!< TPI DEVID: AsynClkIn Position */

+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */

+

+#define TPI_DEVID_NrTraceInput_Pos          0                                          /*!< TPI DEVID: NrTraceInput Position */

+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */

+

+/* TPI DEVTYPE Register Definitions */

+#define TPI_DEVTYPE_MajorType_Pos           4                                          /*!< TPI DEVTYPE: MajorType Position */

+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */

+

+#define TPI_DEVTYPE_SubType_Pos             0                                          /*!< TPI DEVTYPE: SubType Position */

+#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */

+

+/*@}*/ /* end of group CMSIS_TPI */

+

+

+#if (__MPU_PRESENT == 1)

+/** \ingroup  CMSIS_core_register

+    \defgroup CMSIS_MPU     Memory Protection Unit (MPU)

+    \brief      Type definitions for the Memory Protection Unit (MPU)

+  @{

+ */

+

+/** \brief  Structure type to access the Memory Protection Unit (MPU).

+ */

+typedef struct

+{

+  __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */

+  __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */

+  __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */

+  __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */

+  __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */

+  __IO uint32_t RBAR_A1;                 /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register       */

+  __IO uint32_t RASR_A1;                 /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */

+  __IO uint32_t RBAR_A2;                 /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register       */

+  __IO uint32_t RASR_A2;                 /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */

+  __IO uint32_t RBAR_A3;                 /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register       */

+  __IO uint32_t RASR_A3;                 /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */

+} MPU_Type;

+

+/* MPU Type Register */

+#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */

+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */

+

+#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */

+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */

+

+#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */

+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */

+

+/* MPU Control Register */

+#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */

+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */

+

+#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */

+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */

+

+#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */

+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */

+

+/* MPU Region Number Register */

+#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */

+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */

+

+/* MPU Region Base Address Register */

+#define MPU_RBAR_ADDR_Pos                   5                                             /*!< MPU RBAR: ADDR Position */

+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */

+

+#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */

+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */

+

+#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */

+#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */

+

+/* MPU Region Attribute and Size Register */

+#define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */

+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */

+

+#define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: ATTRS.XN Position */

+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */

+

+#define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: ATTRS.AP Position */

+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */

+

+#define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: ATTRS.TEX Position */

+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */

+

+#define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: ATTRS.S Position */

+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */

+

+#define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: ATTRS.C Position */

+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */

+

+#define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: ATTRS.B Position */

+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */

+

+#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */

+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */

+

+#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */

+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */

+

+#define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */

+#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */

+

+/*@} end of group CMSIS_MPU */

+#endif

+

+

+#if (__FPU_PRESENT == 1)

+/** \ingroup  CMSIS_core_register

+    \defgroup CMSIS_FPU     Floating Point Unit (FPU)

+    \brief      Type definitions for the Floating Point Unit (FPU)

+  @{

+ */

+

+/** \brief  Structure type to access the Floating Point Unit (FPU).

+ */

+typedef struct

+{

+       uint32_t RESERVED0[1];

+  __IO uint32_t FPCCR;                   /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register               */

+  __IO uint32_t FPCAR;                   /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register               */

+  __IO uint32_t FPDSCR;                  /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register        */

+  __I  uint32_t MVFR0;                   /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0                       */

+  __I  uint32_t MVFR1;                   /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1                       */

+} FPU_Type;

+

+/* Floating-Point Context Control Register */

+#define FPU_FPCCR_ASPEN_Pos                31                                             /*!< FPCCR: ASPEN bit Position */

+#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */

+

+#define FPU_FPCCR_LSPEN_Pos                30                                             /*!< FPCCR: LSPEN Position */

+#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */

+

+#define FPU_FPCCR_MONRDY_Pos                8                                             /*!< FPCCR: MONRDY Position */

+#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */

+

+#define FPU_FPCCR_BFRDY_Pos                 6                                             /*!< FPCCR: BFRDY Position */

+#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */

+

+#define FPU_FPCCR_MMRDY_Pos                 5                                             /*!< FPCCR: MMRDY Position */

+#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */

+

+#define FPU_FPCCR_HFRDY_Pos                 4                                             /*!< FPCCR: HFRDY Position */

+#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */

+

+#define FPU_FPCCR_THREAD_Pos                3                                             /*!< FPCCR: processor mode bit Position */

+#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */

+

+#define FPU_FPCCR_USER_Pos                  1                                             /*!< FPCCR: privilege level bit Position */

+#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */

+

+#define FPU_FPCCR_LSPACT_Pos                0                                             /*!< FPCCR: Lazy state preservation active bit Position */

+#define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCCR: Lazy state preservation active bit Mask */

+

+/* Floating-Point Context Address Register */

+#define FPU_FPCAR_ADDRESS_Pos               3                                             /*!< FPCAR: ADDRESS bit Position */

+#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */

+

+/* Floating-Point Default Status Control Register */

+#define FPU_FPDSCR_AHP_Pos                 26                                             /*!< FPDSCR: AHP bit Position */

+#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */

+

+#define FPU_FPDSCR_DN_Pos                  25                                             /*!< FPDSCR: DN bit Position */

+#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */

+

+#define FPU_FPDSCR_FZ_Pos                  24                                             /*!< FPDSCR: FZ bit Position */

+#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */

+

+#define FPU_FPDSCR_RMode_Pos               22                                             /*!< FPDSCR: RMode bit Position */

+#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */

+

+/* Media and FP Feature Register 0 */

+#define FPU_MVFR0_FP_rounding_modes_Pos    28                                             /*!< MVFR0: FP rounding modes bits Position */

+#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */

+

+#define FPU_MVFR0_Short_vectors_Pos        24                                             /*!< MVFR0: Short vectors bits Position */

+#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */

+

+#define FPU_MVFR0_Square_root_Pos          20                                             /*!< MVFR0: Square root bits Position */

+#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */

+

+#define FPU_MVFR0_Divide_Pos               16                                             /*!< MVFR0: Divide bits Position */

+#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */

+

+#define FPU_MVFR0_FP_excep_trapping_Pos    12                                             /*!< MVFR0: FP exception trapping bits Position */

+#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */

+

+#define FPU_MVFR0_Double_precision_Pos      8                                             /*!< MVFR0: Double-precision bits Position */

+#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */

+

+#define FPU_MVFR0_Single_precision_Pos      4                                             /*!< MVFR0: Single-precision bits Position */

+#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */

+

+#define FPU_MVFR0_A_SIMD_registers_Pos      0                                             /*!< MVFR0: A_SIMD registers bits Position */

+#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)  /*!< MVFR0: A_SIMD registers bits Mask */

+

+/* Media and FP Feature Register 1 */

+#define FPU_MVFR1_FP_fused_MAC_Pos         28                                             /*!< MVFR1: FP fused MAC bits Position */

+#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */

+

+#define FPU_MVFR1_FP_HPFP_Pos              24                                             /*!< MVFR1: FP HPFP bits Position */

+#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */

+

+#define FPU_MVFR1_D_NaN_mode_Pos            4                                             /*!< MVFR1: D_NaN mode bits Position */

+#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */

+

+#define FPU_MVFR1_FtZ_mode_Pos              0                                             /*!< MVFR1: FtZ mode bits Position */

+#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)          /*!< MVFR1: FtZ mode bits Mask */

+

+/*@} end of group CMSIS_FPU */

+#endif

+

+

+/** \ingroup  CMSIS_core_register

+    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)

+    \brief      Type definitions for the Core Debug Registers

+  @{

+ */

+

+/** \brief  Structure type to access the Core Debug Register (CoreDebug).

+ */

+typedef struct

+{

+  __IO uint32_t DHCSR;                   /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register    */

+  __O  uint32_t DCRSR;                   /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register        */

+  __IO uint32_t DCRDR;                   /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register            */

+  __IO uint32_t DEMCR;                   /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */

+} CoreDebug_Type;

+

+/* Debug Halting Control and Status Register */

+#define CoreDebug_DHCSR_DBGKEY_Pos         16                                             /*!< CoreDebug DHCSR: DBGKEY Position */

+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */

+

+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25                                             /*!< CoreDebug DHCSR: S_RESET_ST Position */

+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */

+

+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24                                             /*!< CoreDebug DHCSR: S_RETIRE_ST Position */

+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */

+

+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19                                             /*!< CoreDebug DHCSR: S_LOCKUP Position */

+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */

+

+#define CoreDebug_DHCSR_S_SLEEP_Pos        18                                             /*!< CoreDebug DHCSR: S_SLEEP Position */

+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */

+

+#define CoreDebug_DHCSR_S_HALT_Pos         17                                             /*!< CoreDebug DHCSR: S_HALT Position */

+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */

+

+#define CoreDebug_DHCSR_S_REGRDY_Pos       16                                             /*!< CoreDebug DHCSR: S_REGRDY Position */

+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */

+

+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5                                             /*!< CoreDebug DHCSR: C_SNAPSTALL Position */

+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */

+

+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3                                             /*!< CoreDebug DHCSR: C_MASKINTS Position */

+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */

+

+#define CoreDebug_DHCSR_C_STEP_Pos          2                                             /*!< CoreDebug DHCSR: C_STEP Position */

+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */

+

+#define CoreDebug_DHCSR_C_HALT_Pos          1                                             /*!< CoreDebug DHCSR: C_HALT Position */

+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */

+

+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0                                             /*!< CoreDebug DHCSR: C_DEBUGEN Position */

+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */

+

+/* Debug Core Register Selector Register */

+#define CoreDebug_DCRSR_REGWnR_Pos         16                                             /*!< CoreDebug DCRSR: REGWnR Position */

+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */

+

+#define CoreDebug_DCRSR_REGSEL_Pos          0                                             /*!< CoreDebug DCRSR: REGSEL Position */

+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */

+

+/* Debug Exception and Monitor Control Register */

+#define CoreDebug_DEMCR_TRCENA_Pos         24                                             /*!< CoreDebug DEMCR: TRCENA Position */

+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */

+

+#define CoreDebug_DEMCR_MON_REQ_Pos        19                                             /*!< CoreDebug DEMCR: MON_REQ Position */

+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */

+

+#define CoreDebug_DEMCR_MON_STEP_Pos       18                                             /*!< CoreDebug DEMCR: MON_STEP Position */

+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */

+

+#define CoreDebug_DEMCR_MON_PEND_Pos       17                                             /*!< CoreDebug DEMCR: MON_PEND Position */

+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */

+

+#define CoreDebug_DEMCR_MON_EN_Pos         16                                             /*!< CoreDebug DEMCR: MON_EN Position */

+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */

+

+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10                                             /*!< CoreDebug DEMCR: VC_HARDERR Position */

+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */

+

+#define CoreDebug_DEMCR_VC_INTERR_Pos       9                                             /*!< CoreDebug DEMCR: VC_INTERR Position */

+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */

+

+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8                                             /*!< CoreDebug DEMCR: VC_BUSERR Position */

+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */

+

+#define CoreDebug_DEMCR_VC_STATERR_Pos      7                                             /*!< CoreDebug DEMCR: VC_STATERR Position */

+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */

+

+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6                                             /*!< CoreDebug DEMCR: VC_CHKERR Position */

+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */

+

+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5                                             /*!< CoreDebug DEMCR: VC_NOCPERR Position */

+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */

+

+#define CoreDebug_DEMCR_VC_MMERR_Pos        4                                             /*!< CoreDebug DEMCR: VC_MMERR Position */

+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */

+

+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0                                             /*!< CoreDebug DEMCR: VC_CORERESET Position */

+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */

+

+/*@} end of group CMSIS_CoreDebug */

+

+

+/** \ingroup    CMSIS_core_register

+    \defgroup   CMSIS_core_base     Core Definitions

+    \brief      Definitions for base addresses, unions, and structures.

+  @{

+ */

+

+/* Memory mapping of Cortex-M4 Hardware */

+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address  */

+#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address                   */

+#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address                   */

+#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address                   */

+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address            */

+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address               */

+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                  */

+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address  */

+

+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */

+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */

+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */

+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */

+#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct           */

+#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct           */

+#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct           */

+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct    */

+

+#if (__MPU_PRESENT == 1)

+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */

+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */

+#endif

+

+#if (__FPU_PRESENT == 1)

+  #define FPU_BASE          (SCS_BASE +  0x0F30UL)                    /*!< Floating Point Unit                */

+  #define FPU               ((FPU_Type       *)     FPU_BASE      )   /*!< Floating Point Unit                */

+#endif

+

+/*@} */

+

+

+

+/*******************************************************************************

+ *                Hardware Abstraction Layer

+  Core Function Interface contains:

+  - Core NVIC Functions

+  - Core SysTick Functions

+  - Core Debug Functions

+  - Core Register Access Functions

+ ******************************************************************************/

+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference

+*/

+

+

+

+/* ##########################   NVIC functions  #################################### */

+/** \ingroup  CMSIS_Core_FunctionInterface

+    \defgroup CMSIS_Core_NVICFunctions NVIC Functions

+    \brief      Functions that manage interrupts and exceptions via the NVIC.

+    @{

+ */

+

+/** \brief  Set Priority Grouping

+

+  The function sets the priority grouping field using the required unlock sequence.

+  The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.

+  Only values from 0..7 are used.

+  In case of a conflict between priority grouping and available

+  priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.

+

+    \param [in]      PriorityGroup  Priority grouping field.

+ */

+__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)

+{

+  uint32_t reg_value;

+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */

+

+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */

+  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk));             /* clear bits to change               */

+  reg_value  =  (reg_value                                   |

+                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |

+                (PriorityGroupTmp << 8)                       );              /* Insert write key and priorty group */

+  SCB->AIRCR =  reg_value;

+}

+

+

+/** \brief  Get Priority Grouping

+

+  The function reads the priority grouping field from the NVIC Interrupt Controller.

+

+    \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).

+ */

+__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)

+{

+  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));

+}

+

+

+/** \brief  Enable External Interrupt

+

+    The function enables a device-specific interrupt in the NVIC interrupt controller.

+

+    \param [in]      IRQn  External interrupt number. Value cannot be negative.

+ */

+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)

+{

+  NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));

+}

+

+

+/** \brief  Disable External Interrupt

+

+    The function disables a device-specific interrupt in the NVIC interrupt controller.

+

+    \param [in]      IRQn  External interrupt number. Value cannot be negative.

+ */

+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)

+{

+  NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));

+}

+

+

+/** \brief  Get Pending Interrupt

+

+    The function reads the pending register in the NVIC and returns the pending bit

+    for the specified interrupt.

+

+    \param [in]      IRQn  Interrupt number.

+

+    \return             0  Interrupt status is not pending.

+    \return             1  Interrupt status is pending.

+ */

+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)

+{

+  return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));

+}

+

+

+/** \brief  Set Pending Interrupt

+

+    The function sets the pending bit of an external interrupt.

+

+    \param [in]      IRQn  Interrupt number. Value cannot be negative.

+ */

+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)

+{

+  NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));

+}

+

+

+/** \brief  Clear Pending Interrupt

+

+    The function clears the pending bit of an external interrupt.

+

+    \param [in]      IRQn  External interrupt number. Value cannot be negative.

+ */

+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)

+{

+  NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));

+}

+

+

+/** \brief  Get Active Interrupt

+

+    The function reads the active register in NVIC and returns the active bit.

+

+    \param [in]      IRQn  Interrupt number.

+

+    \return             0  Interrupt status is not active.

+    \return             1  Interrupt status is active.

+ */

+__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)

+{

+  return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));

+}

+

+

+/** \brief  Set Interrupt Priority

+

+    The function sets the priority of an interrupt.

+

+    \note The priority cannot be set for every core interrupt.

+

+    \param [in]      IRQn  Interrupt number.

+    \param [in]  priority  Priority to set.

+ */

+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)

+{

+  if((int32_t)IRQn < 0) {

+    SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);

+  }

+  else {

+    NVIC->IP[((uint32_t)(int32_t)IRQn)]               = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);

+  }

+}

+

+

+/** \brief  Get Interrupt Priority

+

+    The function reads the priority of an interrupt. The interrupt

+    number can be positive to specify an external (device specific)

+    interrupt, or negative to specify an internal (core) interrupt.

+

+

+    \param [in]   IRQn  Interrupt number.

+    \return             Interrupt Priority. Value is aligned automatically to the implemented

+                        priority bits of the microcontroller.

+ */

+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)

+{

+

+  if((int32_t)IRQn < 0) {

+    return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8 - __NVIC_PRIO_BITS)));

+  }

+  else {

+    return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)]               >> (8 - __NVIC_PRIO_BITS)));

+  }

+}

+

+

+/** \brief  Encode Priority

+

+    The function encodes the priority for an interrupt with the given priority group,

+    preemptive priority value, and subpriority value.

+    In case of a conflict between priority grouping and available

+    priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.

+

+    \param [in]     PriorityGroup  Used priority group.

+    \param [in]   PreemptPriority  Preemptive priority value (starting from 0).

+    \param [in]       SubPriority  Subpriority value (starting from 0).

+    \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().

+ */

+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)

+{

+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */

+  uint32_t PreemptPriorityBits;

+  uint32_t SubPriorityBits;

+

+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);

+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));

+

+  return (

+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |

+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))

+         );

+}

+

+

+/** \brief  Decode Priority

+

+    The function decodes an interrupt priority value with a given priority group to

+    preemptive priority value and subpriority value.

+    In case of a conflict between priority grouping and available

+    priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.

+

+    \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().

+    \param [in]     PriorityGroup  Used priority group.

+    \param [out] pPreemptPriority  Preemptive priority value (starting from 0).

+    \param [out]     pSubPriority  Subpriority value (starting from 0).

+ */

+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)

+{

+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */

+  uint32_t PreemptPriorityBits;

+  uint32_t SubPriorityBits;

+

+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);

+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));

+

+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);

+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);

+}

+

+

+/** \brief  System Reset

+

+    The function initiates a system reset request to reset the MCU.

+ */

+__STATIC_INLINE void NVIC_SystemReset(void)

+{

+  __DSB();                                                          /* Ensure all outstanding memory accesses included

+                                                                       buffered write are completed before reset */

+  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |

+                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |

+                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */

+  __DSB();                                                          /* Ensure completion of memory access */

+  while(1) { __NOP(); }                                             /* wait until reset */

+}

+

+/*@} end of CMSIS_Core_NVICFunctions */

+

+

+

+/* ##################################    SysTick function  ############################################ */

+/** \ingroup  CMSIS_Core_FunctionInterface

+    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions

+    \brief      Functions that configure the System.

+  @{

+ */

+

+#if (__Vendor_SysTickConfig == 0)

+

+/** \brief  System Tick Configuration

+

+    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.

+    Counter is in free running mode to generate periodic interrupts.

+

+    \param [in]  ticks  Number of ticks between two interrupts.

+

+    \return          0  Function succeeded.

+    \return          1  Function failed.

+

+    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the

+    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>

+    must contain a vendor-specific implementation of this function.

+

+ */

+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)

+{

+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); }    /* Reload value impossible */

+

+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */

+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */

+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */

+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |

+                   SysTick_CTRL_TICKINT_Msk   |

+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */

+  return (0UL);                                                     /* Function successful */

+}

+

+#endif

+

+/*@} end of CMSIS_Core_SysTickFunctions */

+

+

+

+/* ##################################### Debug In/Output function ########################################### */

+/** \ingroup  CMSIS_Core_FunctionInterface

+    \defgroup CMSIS_core_DebugFunctions ITM Functions

+    \brief   Functions that access the ITM debug interface.

+  @{

+ */

+

+extern volatile int32_t ITM_RxBuffer;                    /*!< External variable to receive characters.                         */

+#define                 ITM_RXBUFFER_EMPTY    0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */

+

+

+/** \brief  ITM Send Character

+

+    The function transmits a character via the ITM channel 0, and

+    \li Just returns when no debugger is connected that has booked the output.

+    \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.

+

+    \param [in]     ch  Character to transmit.

+

+    \returns            Character to transmit.

+ */

+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)

+{

+  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */

+      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */

+  {

+    while (ITM->PORT[0].u32 == 0UL) { __NOP(); }

+    ITM->PORT[0].u8 = (uint8_t)ch;

+  }

+  return (ch);

+}

+

+

+/** \brief  ITM Receive Character

+

+    The function inputs a character via the external variable \ref ITM_RxBuffer.

+

+    \return             Received character.

+    \return         -1  No character pending.

+ */

+__STATIC_INLINE int32_t ITM_ReceiveChar (void) {

+  int32_t ch = -1;                           /* no character available */

+

+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {

+    ch = ITM_RxBuffer;

+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */

+  }

+

+  return (ch);

+}

+

+

+/** \brief  ITM Check Character

+

+    The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.

+

+    \return          0  No character available.

+    \return          1  Character available.

+ */

+__STATIC_INLINE int32_t ITM_CheckChar (void) {

+

+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {

+    return (0);                                 /* no character available */

+  } else {

+    return (1);                                 /*    character available */

+  }

+}

+

+/*@} end of CMSIS_core_DebugFunctions */

+

+

+

+

+#ifdef __cplusplus

+}

+#endif

+

+#endif /* __CORE_CM4_H_DEPENDANT */

+

+#endif /* __CMSIS_GENERIC */

diff --git a/ext/TARGET_LPC1768/core_cm4_simd.h b/ext/TARGET_LPC1768/core_cm4_simd.h
new file mode 100644
index 0000000..af1831e
--- /dev/null
+++ b/ext/TARGET_LPC1768/core_cm4_simd.h
@@ -0,0 +1,673 @@
+/**************************************************************************//**

+ * @file     core_cm4_simd.h

+ * @brief    CMSIS Cortex-M4 SIMD Header File

+ * @version  V3.20

+ * @date     25. February 2013

+ *

+ * @note

+ *

+ ******************************************************************************/

+/* Copyright (c) 2009 - 2013 ARM LIMITED

+

+   All rights reserved.

+   Redistribution and use in source and binary forms, with or without

+   modification, are permitted provided that the following conditions are met:

+   - Redistributions of source code must retain the above copyright

+     notice, this list of conditions and the following disclaimer.

+   - Redistributions in binary form must reproduce the above copyright

+     notice, this list of conditions and the following disclaimer in the

+     documentation and/or other materials provided with the distribution.

+   - Neither the name of ARM nor the names of its contributors may be used

+     to endorse or promote products derived from this software without

+     specific prior written permission.

+   *

+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"

+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE

+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE

+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE

+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR

+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF

+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS

+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN

+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)

+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE

+   POSSIBILITY OF SUCH DAMAGE.

+   ---------------------------------------------------------------------------*/

+

+

+#ifdef __cplusplus

+ extern "C" {

+#endif

+

+#ifndef __CORE_CM4_SIMD_H

+#define __CORE_CM4_SIMD_H

+

+

+/*******************************************************************************

+ *                Hardware Abstraction Layer

+ ******************************************************************************/

+

+

+/* ###################  Compiler specific Intrinsics  ########################### */

+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics

+  Access to dedicated SIMD instructions

+  @{

+*/

+

+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/

+/* ARM armcc specific functions */

+

+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/

+#define __SADD8                           __sadd8

+#define __QADD8                           __qadd8

+#define __SHADD8                          __shadd8

+#define __UADD8                           __uadd8

+#define __UQADD8                          __uqadd8

+#define __UHADD8                          __uhadd8

+#define __SSUB8                           __ssub8

+#define __QSUB8                           __qsub8

+#define __SHSUB8                          __shsub8

+#define __USUB8                           __usub8

+#define __UQSUB8                          __uqsub8

+#define __UHSUB8                          __uhsub8

+#define __SADD16                          __sadd16

+#define __QADD16                          __qadd16

+#define __SHADD16                         __shadd16

+#define __UADD16                          __uadd16

+#define __UQADD16                         __uqadd16

+#define __UHADD16                         __uhadd16

+#define __SSUB16                          __ssub16

+#define __QSUB16                          __qsub16

+#define __SHSUB16                         __shsub16

+#define __USUB16                          __usub16

+#define __UQSUB16                         __uqsub16

+#define __UHSUB16                         __uhsub16

+#define __SASX                            __sasx

+#define __QASX                            __qasx

+#define __SHASX                           __shasx

+#define __UASX                            __uasx

+#define __UQASX                           __uqasx

+#define __UHASX                           __uhasx

+#define __SSAX                            __ssax

+#define __QSAX                            __qsax

+#define __SHSAX                           __shsax

+#define __USAX                            __usax

+#define __UQSAX                           __uqsax

+#define __UHSAX                           __uhsax

+#define __USAD8                           __usad8

+#define __USADA8                          __usada8

+#define __SSAT16                          __ssat16

+#define __USAT16                          __usat16

+#define __UXTB16                          __uxtb16

+#define __UXTAB16                         __uxtab16

+#define __SXTB16                          __sxtb16

+#define __SXTAB16                         __sxtab16

+#define __SMUAD                           __smuad

+#define __SMUADX                          __smuadx

+#define __SMLAD                           __smlad

+#define __SMLADX                          __smladx

+#define __SMLALD                          __smlald

+#define __SMLALDX                         __smlaldx

+#define __SMUSD                           __smusd

+#define __SMUSDX                          __smusdx

+#define __SMLSD                           __smlsd

+#define __SMLSDX                          __smlsdx

+#define __SMLSLD                          __smlsld

+#define __SMLSLDX                         __smlsldx

+#define __SEL                             __sel

+#define __QADD                            __qadd

+#define __QSUB                            __qsub

+

+#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \

+                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )

+

+#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \

+                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )

+

+#define __SMMLA(ARG1,ARG2,ARG3)          ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \

+                                                      ((int64_t)(ARG3) << 32)      ) >> 32))

+

+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/

+

+

+

+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/

+/* IAR iccarm specific functions */

+

+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/

+#include <cmsis_iar.h>

+

+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/

+

+

+

+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/

+/* TI CCS specific functions */

+

+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/

+#include <cmsis_ccs.h>

+

+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/

+

+

+

+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/

+/* GNU gcc specific functions */

+

+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/

+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)

+{

+  uint32_t result;

+

+  __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  return(result);

+}

+

+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)

+{

+  uint32_t result;

+

+  __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  return(result);

+}

+

+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)

+{

+  uint32_t result;

+

+  __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  return(result);

+}

+

+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)

+{

+  uint32_t result;

+

+  __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  return(result);

+}

+

+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)

+{

+  uint32_t result;

+

+  __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  return(result);

+}

+

+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)

+{

+  uint32_t result;

+

+  __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  return(result);

+}

+

+

+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)

+{

+  uint32_t result;

+

+  __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  return(result);

+}

+

+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)

+{

+  uint32_t result;

+

+  __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  return(result);

+}

+

+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)

+{

+  uint32_t result;

+

+  __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  return(result);

+}

+

+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)

+{

+  uint32_t result;

+

+  __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  return(result);

+}

+

+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)

+{

+  uint32_t result;

+

+  __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  return(result);

+}

+

+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)

+{

+  uint32_t result;

+

+  __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  return(result);

+}

+

+

+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)

+{

+  uint32_t result;

+

+  __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  return(result);

+}

+

+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)

+{

+  uint32_t result;

+

+  __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  return(result);

+}

+

+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)

+{

+  uint32_t result;

+

+  __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  return(result);

+}

+

+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)

+{

+  uint32_t result;

+

+  __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  return(result);

+}

+

+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)

+{

+  uint32_t result;

+

+  __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  return(result);

+}

+

+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)

+{

+  uint32_t result;

+

+  __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  return(result);

+}

+

+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)

+{

+  uint32_t result;

+

+  __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  return(result);

+}

+

+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)

+{

+  uint32_t result;

+

+  __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  return(result);

+}

+

+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)

+{

+  uint32_t result;

+

+  __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  return(result);

+}

+

+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)

+{

+  uint32_t result;

+

+  __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  return(result);

+}

+

+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)

+{

+  uint32_t result;

+

+  __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  return(result);

+}

+

+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)

+{

+  uint32_t result;

+

+  __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  return(result);

+}

+

+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)

+{

+  uint32_t result;

+

+  __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  return(result);

+}

+

+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)

+{

+  uint32_t result;

+

+  __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  return(result);

+}

+

+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)

+{

+  uint32_t result;

+

+  __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  return(result);

+}

+

+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)

+{

+  uint32_t result;

+

+  __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  return(result);

+}

+

+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)

+{

+  uint32_t result;

+

+  __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  return(result);

+}

+

+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)

+{

+  uint32_t result;

+

+  __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  return(result);

+}

+

+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)

+{

+  uint32_t result;

+

+  __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  return(result);

+}

+

+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)

+{

+  uint32_t result;

+

+  __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  return(result);

+}

+

+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)

+{

+  uint32_t result;

+

+  __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  return(result);

+}

+

+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)

+{

+  uint32_t result;

+

+  __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  return(result);

+}

+

+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)

+{

+  uint32_t result;

+

+  __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  return(result);

+}

+

+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)

+{

+  uint32_t result;

+

+  __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  return(result);

+}

+

+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)

+{

+  uint32_t result;

+

+  __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  return(result);

+}

+

+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)

+{

+  uint32_t result;

+

+  __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );

+  return(result);

+}

+

+#define __SSAT16(ARG1,ARG2) \

+({                          \

+  uint32_t __RES, __ARG1 = (ARG1); \

+  __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \

+  __RES; \

+ })

+

+#define __USAT16(ARG1,ARG2) \

+({                          \

+  uint32_t __RES, __ARG1 = (ARG1); \

+  __ASM ("usat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \

+  __RES; \

+ })

+

+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)

+{

+  uint32_t result;

+

+  __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));

+  return(result);

+}

+

+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)

+{

+  uint32_t result;

+

+  __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  return(result);

+}

+

+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)

+{

+  uint32_t result;

+

+  __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));

+  return(result);

+}

+

+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)

+{

+  uint32_t result;

+

+  __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  return(result);

+}

+

+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD  (uint32_t op1, uint32_t op2)

+{

+  uint32_t result;

+

+  __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  return(result);

+}

+

+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)

+{

+  uint32_t result;

+

+  __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  return(result);

+}

+

+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)

+{

+  uint32_t result;

+

+  __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );

+  return(result);

+}

+

+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)

+{

+  uint32_t result;

+

+  __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );

+  return(result);

+}

+

+#define __SMLALD(ARG1,ARG2,ARG3) \

+({ \

+  uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \

+  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \

+  (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \

+ })

+

+#define __SMLALDX(ARG1,ARG2,ARG3) \

+({ \

+  uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \

+  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \

+  (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \

+ })

+

+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD  (uint32_t op1, uint32_t op2)

+{

+  uint32_t result;

+

+  __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  return(result);

+}

+

+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)

+{

+  uint32_t result;

+

+  __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  return(result);

+}

+

+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)

+{

+  uint32_t result;

+

+  __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );

+  return(result);

+}

+

+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)

+{

+  uint32_t result;

+

+  __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );

+  return(result);

+}

+

+#define __SMLSLD(ARG1,ARG2,ARG3) \

+({ \

+  uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \

+  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \

+  (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \

+ })

+

+#define __SMLSLDX(ARG1,ARG2,ARG3) \

+({ \

+  uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \

+  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \

+  (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \

+ })

+

+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL  (uint32_t op1, uint32_t op2)

+{

+  uint32_t result;

+

+  __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  return(result);

+}

+

+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)

+{

+  uint32_t result;

+

+  __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  return(result);

+}

+

+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)

+{

+  uint32_t result;

+

+  __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  return(result);

+}

+

+#define __PKHBT(ARG1,ARG2,ARG3) \

+({                          \

+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \

+  __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \

+  __RES; \

+ })

+

+#define __PKHTB(ARG1,ARG2,ARG3) \

+({                          \

+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \

+  if (ARG3 == 0) \

+    __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2)  ); \

+  else \

+    __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \

+  __RES; \

+ })

+

+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)

+{

+ int32_t result;

+

+ __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r"  (op1), "r" (op2), "r" (op3) );

+ return(result);

+}

+

+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/

+

+

+

+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/

+/* TASKING carm specific functions */

+

+

+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/

+/* not yet supported */

+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/

+

+

+#endif

+

+/*@} end of group CMSIS_SIMD_intrinsics */

+

+

+#endif /* __CORE_CM4_SIMD_H */

+

+#ifdef __cplusplus

+}

+#endif

diff --git a/ext/TARGET_LPC1768/core_cm7.h b/ext/TARGET_LPC1768/core_cm7.h
new file mode 100644
index 0000000..842e323
--- /dev/null
+++ b/ext/TARGET_LPC1768/core_cm7.h
@@ -0,0 +1,2397 @@
+/**************************************************************************//**
+ * @file     core_cm7.h
+ * @brief    CMSIS Cortex-M7 Core Peripheral Access Layer Header File
+ * @version  V4.10
+ * @date     18. March 2015
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include  /* treat file as system include file for MISRA check */
+#endif
+
+#ifndef __CORE_CM7_H_GENERIC
+#define __CORE_CM7_H_GENERIC
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/** \ingroup Cortex_M7
+  @{
+ */
+
+/*  CMSIS CM7 definitions */
+#define __CM7_CMSIS_VERSION_MAIN  (0x04)                                   /*!< [31:16] CMSIS HAL main version   */
+#define __CM7_CMSIS_VERSION_SUB   (0x00)                                   /*!< [15:0]  CMSIS HAL sub version    */
+#define __CM7_CMSIS_VERSION       ((__CM7_CMSIS_VERSION_MAIN << 16) | \
+                                    __CM7_CMSIS_VERSION_SUB          )     /*!< CMSIS HAL version number         */
+
+#define __CORTEX_M                (0x07)                                   /*!< Cortex-M Core                    */
+
+
+#if   defined ( __CC_ARM )
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
+  #define __STATIC_INLINE  static __inline
+
+#elif defined ( __GNUC__ )
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __ICCARM__ )
+  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TMS470__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TASKING__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __CSMC__ )
+  #define __packed
+  #define __ASM            _asm                                      /*!< asm keyword for COSMIC Compiler      */
+  #define __INLINE         inline                                    /*use -pc99 on compile line !< inline keyword for COSMIC Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+
+#elif defined ( __TMS470__ )
+  #if defined __TI_VFP_SUPPORT__
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+
+#elif defined ( __CSMC__ )		/* Cosmic */
+  #if ( __CSMC__ & 0x400)		// FPU present for parser
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+#endif
+
+#include <stdint.h>                      /* standard types definitions                      */
+#include <core_cmInstr.h>                /* Core Instruction Access                         */
+#include <core_cmFunc.h>                 /* Core Function Access                            */
+#include <core_cmSimd.h>                 /* Compiler specific SIMD Intrinsics               */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM7_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM7_H_DEPENDANT
+#define __CORE_CM7_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM7_REV
+    #define __CM7_REV               0x0000
+    #warning "__CM7_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __FPU_PRESENT
+    #define __FPU_PRESENT             0
+    #warning "__FPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __ICACHE_PRESENT
+    #define __ICACHE_PRESENT          0
+    #warning "__ICACHE_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __DCACHE_PRESENT
+    #define __DCACHE_PRESENT          0
+    #warning "__DCACHE_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __DTCM_PRESENT
+    #define __DTCM_PRESENT            0
+    #warning "__DTCM_PRESENT        not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          3
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions                */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
+
+/*@} end of group Cortex_M7 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+  - Core FPU Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+    \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_CORE  Status and Control Registers
+    \brief  Core Register type definitions.
+  @{
+ */
+
+/** \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31                                             /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30                                             /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29                                             /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28                                             /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+#define APSR_Q_Pos                         27                                             /*!< APSR: Q Position */
+#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos                        16                                             /*!< APSR: GE Position */
+#define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR: GE Mask */
+
+
+/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0                                             /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
+    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31                                             /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30                                             /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29                                             /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28                                             /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos                         27                                             /*!< xPSR: Q Position */
+#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
+
+#define xPSR_IT_Pos                        25                                             /*!< xPSR: IT Position */
+#define xPSR_IT_Msk                        (3UL << xPSR_IT_Pos)                           /*!< xPSR: IT Mask */
+
+#define xPSR_T_Pos                         24                                             /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos                        16                                             /*!< xPSR: GE Position */
+#define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR: GE Mask */
+
+#define xPSR_ISR_Pos                        0                                             /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/** \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
+    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */
+    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_FPCA_Pos                    2                                             /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos                   1                                             /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0                                             /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+    \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IO uint32_t ISER[8];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
+       uint32_t RESERVED0[24];
+  __IO uint32_t ICER[8];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register         */
+       uint32_t RSERVED1[24];
+  __IO uint32_t ISPR[8];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register          */
+       uint32_t RESERVED2[24];
+  __IO uint32_t ICPR[8];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register        */
+       uint32_t RESERVED3[24];
+  __IO uint32_t IABR[8];                 /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register           */
+       uint32_t RESERVED4[56];
+  __IO uint8_t  IP[240];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+       uint32_t RESERVED5[644];
+  __O  uint32_t STIR;                    /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register     */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0                                          /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCB     System Control Block (SCB)
+    \brief      Type definitions for the System Control Block Registers
+  @{
+ */
+
+/** \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
+  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
+  __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
+  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
+  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
+  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
+  __IO uint8_t  SHPR[12];                /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
+  __IO uint32_t CFSR;                    /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register                    */
+  __IO uint32_t HFSR;                    /*!< Offset: 0x02C (R/W)  HardFault Status Register                             */
+  __IO uint32_t DFSR;                    /*!< Offset: 0x030 (R/W)  Debug Fault Status Register                           */
+  __IO uint32_t MMFAR;                   /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register                      */
+  __IO uint32_t BFAR;                    /*!< Offset: 0x038 (R/W)  BusFault Address Register                             */
+  __IO uint32_t AFSR;                    /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register                       */
+  __I  uint32_t ID_PFR[2];               /*!< Offset: 0x040 (R/ )  Processor Feature Register                            */
+  __I  uint32_t ID_DFR;                  /*!< Offset: 0x048 (R/ )  Debug Feature Register                                */
+  __I  uint32_t ID_AFR;                  /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register                            */
+  __I  uint32_t ID_MFR[4];               /*!< Offset: 0x050 (R/ )  Memory Model Feature Register                         */
+  __I  uint32_t ID_ISAR[5];              /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register                   */
+       uint32_t RESERVED0[1];
+  __I  uint32_t CLIDR;                   /*!< Offset: 0x078 (R/ )  Cache Level ID register                               */
+  __I  uint32_t CTR;                     /*!< Offset: 0x07C (R/ )  Cache Type register                                   */
+  __I  uint32_t CCSIDR;                  /*!< Offset: 0x080 (R/ )  Cache Size ID Register                                */
+  __IO uint32_t CSSELR;                  /*!< Offset: 0x084 (R/W)  Cache Size Selection Register                         */
+  __IO uint32_t CPACR;                   /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register                   */
+       uint32_t RESERVED3[93];
+  __O  uint32_t STIR;                    /*!< Offset: 0x200 ( /W)  Software Triggered Interrupt Register                 */
+       uint32_t RESERVED4[15];
+  __I  uint32_t MVFR0;                   /*!< Offset: 0x240 (R/ )  Media and VFP Feature Register 0                      */
+  __I  uint32_t MVFR1;                   /*!< Offset: 0x244 (R/ )  Media and VFP Feature Register 1                      */
+  __I  uint32_t MVFR2;                   /*!< Offset: 0x248 (R/ )  Media and VFP Feature Register 1                      */
+       uint32_t RESERVED5[1];
+  __O  uint32_t ICIALLU;                 /*!< Offset: 0x250 ( /W)  I-Cache Invalidate All to PoU                         */
+       uint32_t RESERVED6[1];
+  __O  uint32_t ICIMVAU;                 /*!< Offset: 0x258 ( /W)  I-Cache Invalidate by MVA to PoU                      */
+  __O  uint32_t DCIMVAC;                 /*!< Offset: 0x25C ( /W)  D-Cache Invalidate by MVA to PoC                      */
+  __O  uint32_t DCISW;                   /*!< Offset: 0x260 ( /W)  D-Cache Invalidate by Set-way                         */
+  __O  uint32_t DCCMVAU;                 /*!< Offset: 0x264 ( /W)  D-Cache Clean by MVA to PoU                           */
+  __O  uint32_t DCCMVAC;                 /*!< Offset: 0x268 ( /W)  D-Cache Clean by MVA to PoC                           */
+  __O  uint32_t DCCSW;                   /*!< Offset: 0x26C ( /W)  D-Cache Clean by Set-way                              */
+  __O  uint32_t DCCIMVAC;                /*!< Offset: 0x270 ( /W)  D-Cache Clean and Invalidate by MVA to PoC            */
+  __O  uint32_t DCCISW;                  /*!< Offset: 0x274 ( /W)  D-Cache Clean and Invalidate by Set-way               */
+       uint32_t RESERVED7[6];
+  __IO uint32_t ITCMCR;                  /*!< Offset: 0x290 (R/W)  Instruction Tightly-Coupled Memory Control Register   */
+  __IO uint32_t DTCMCR;                  /*!< Offset: 0x294 (R/W)  Data Tightly-Coupled Memory Control Registers         */
+  __IO uint32_t AHBPCR;                  /*!< Offset: 0x298 (R/W)  AHBP Control Register                                 */
+  __IO uint32_t CACR;                    /*!< Offset: 0x29C (R/W)  L1 Cache Control Register                             */
+  __IO uint32_t AHBSCR;                  /*!< Offset: 0x2A0 (R/W)  AHB Slave Control Register                            */
+       uint32_t RESERVED8[1];
+  __IO uint32_t ABFSR;                   /*!< Offset: 0x2A8 (R/W)  Auxiliary Bus Fault Status Register                   */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11                                             /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8                                             /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos             0                                             /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos                      18                                            /*!< SCB CCR: Branch prediction enable bit Position */
+#define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: Branch prediction enable bit Mask */
+
+#define SCB_CCR_IC_Pos                      17                                            /*!< SCB CCR: Instruction cache enable bit Position */
+#define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: Instruction cache enable bit Mask */
+
+#define SCB_CCR_DC_Pos                      16                                            /*!< SCB CCR: Cache enable bit Position */
+#define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: Cache enable bit Mask */
+
+#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8                                             /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4                                             /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1                                             /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos          0                                             /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos          18                                             /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17                                             /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16                                             /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14                                             /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13                                             /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12                                             /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11                                             /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10                                             /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8                                             /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7                                             /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3                                             /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1                                             /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0                                             /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Registers Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16                                             /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8                                             /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0                                             /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* SCB Hard Fault Status Registers Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31                                             /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30                                             /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1                                             /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4                                             /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3                                             /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2                                             /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1                                             /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0                                             /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
+
+/* Cache Level ID register */
+#define SCB_CLIDR_LOUU_Pos                 27                                             /*!< SCB CLIDR: LoUU Position */
+#define SCB_CLIDR_LOUU_Msk                 (7UL << SCB_CLIDR_LOUU_Pos)                    /*!< SCB CLIDR: LoUU Mask */
+
+#define SCB_CLIDR_LOC_Pos                  24                                             /*!< SCB CLIDR: LoC Position */
+#define SCB_CLIDR_LOC_Msk                  (7UL << SCB_CLIDR_FORMAT_Pos)                  /*!< SCB CLIDR: LoC Mask */
+
+/* Cache Type register */
+#define SCB_CTR_FORMAT_Pos                 29                                             /*!< SCB CTR: Format Position */
+#define SCB_CTR_FORMAT_Msk                 (7UL << SCB_CTR_FORMAT_Pos)                    /*!< SCB CTR: Format Mask */
+
+#define SCB_CTR_CWG_Pos                    24                                             /*!< SCB CTR: CWG Position */
+#define SCB_CTR_CWG_Msk                    (0xFUL << SCB_CTR_CWG_Pos)                     /*!< SCB CTR: CWG Mask */
+
+#define SCB_CTR_ERG_Pos                    20                                             /*!< SCB CTR: ERG Position */
+#define SCB_CTR_ERG_Msk                    (0xFUL << SCB_CTR_ERG_Pos)                     /*!< SCB CTR: ERG Mask */
+
+#define SCB_CTR_DMINLINE_Pos               16                                             /*!< SCB CTR: DminLine Position */
+#define SCB_CTR_DMINLINE_Msk               (0xFUL << SCB_CTR_DMINLINE_Pos)                /*!< SCB CTR: DminLine Mask */
+
+#define SCB_CTR_IMINLINE_Pos                0                                             /*!< SCB CTR: ImInLine Position */
+#define SCB_CTR_IMINLINE_Msk               (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)            /*!< SCB CTR: ImInLine Mask */
+
+/* Cache Size ID Register */
+#define SCB_CCSIDR_WT_Pos                  31                                             /*!< SCB CCSIDR: WT Position */
+#define SCB_CCSIDR_WT_Msk                  (7UL << SCB_CCSIDR_WT_Pos)                     /*!< SCB CCSIDR: WT Mask */
+
+#define SCB_CCSIDR_WB_Pos                  30                                             /*!< SCB CCSIDR: WB Position */
+#define SCB_CCSIDR_WB_Msk                  (7UL << SCB_CCSIDR_WB_Pos)                     /*!< SCB CCSIDR: WB Mask */
+
+#define SCB_CCSIDR_RA_Pos                  29                                             /*!< SCB CCSIDR: RA Position */
+#define SCB_CCSIDR_RA_Msk                  (7UL << SCB_CCSIDR_RA_Pos)                     /*!< SCB CCSIDR: RA Mask */
+
+#define SCB_CCSIDR_WA_Pos                  28                                             /*!< SCB CCSIDR: WA Position */
+#define SCB_CCSIDR_WA_Msk                  (7UL << SCB_CCSIDR_WA_Pos)                     /*!< SCB CCSIDR: WA Mask */
+
+#define SCB_CCSIDR_NUMSETS_Pos             13                                             /*!< SCB CCSIDR: NumSets Position */
+#define SCB_CCSIDR_NUMSETS_Msk             (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)           /*!< SCB CCSIDR: NumSets Mask */
+
+#define SCB_CCSIDR_ASSOCIATIVITY_Pos        3                                             /*!< SCB CCSIDR: Associativity Position */
+#define SCB_CCSIDR_ASSOCIATIVITY_Msk       (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)      /*!< SCB CCSIDR: Associativity Mask */
+
+#define SCB_CCSIDR_LINESIZE_Pos             0                                             /*!< SCB CCSIDR: LineSize Position */
+#define SCB_CCSIDR_LINESIZE_Msk            (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)           /*!< SCB CCSIDR: LineSize Mask */
+
+/* Cache Size Selection Register */
+#define SCB_CSSELR_LEVEL_Pos                1                                             /*!< SCB CSSELR: Level Position */
+#define SCB_CSSELR_LEVEL_Msk               (7UL << SCB_CSSELR_LEVEL_Pos)                  /*!< SCB CSSELR: Level Mask */
+
+#define SCB_CSSELR_IND_Pos                  0                                             /*!< SCB CSSELR: InD Position */
+#define SCB_CSSELR_IND_Msk                 (1UL /*<< SCB_CSSELR_IND_Pos*/)                /*!< SCB CSSELR: InD Mask */
+
+/* SCB Software Triggered Interrupt Register */
+#define SCB_STIR_INTID_Pos                  0                                             /*!< SCB STIR: INTID Position */
+#define SCB_STIR_INTID_Msk                 (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)            /*!< SCB STIR: INTID Mask */
+
+/* Instruction Tightly-Coupled Memory Control Register*/
+#define SCB_ITCMCR_SZ_Pos                   3                                             /*!< SCB ITCMCR: SZ Position */
+#define SCB_ITCMCR_SZ_Msk                  (0xFUL << SCB_ITCMCR_SZ_Pos)                   /*!< SCB ITCMCR: SZ Mask */
+
+#define SCB_ITCMCR_RETEN_Pos                2                                             /*!< SCB ITCMCR: RETEN Position */
+#define SCB_ITCMCR_RETEN_Msk               (1UL << SCB_ITCMCR_RETEN_Pos)                  /*!< SCB ITCMCR: RETEN Mask */
+
+#define SCB_ITCMCR_RMW_Pos                  1                                             /*!< SCB ITCMCR: RMW Position */
+#define SCB_ITCMCR_RMW_Msk                 (1UL << SCB_ITCMCR_RMW_Pos)                    /*!< SCB ITCMCR: RMW Mask */
+
+#define SCB_ITCMCR_EN_Pos                   0                                             /*!< SCB ITCMCR: EN Position */
+#define SCB_ITCMCR_EN_Msk                  (1UL /*<< SCB_ITCMCR_EN_Pos*/)                 /*!< SCB ITCMCR: EN Mask */
+
+/* Data Tightly-Coupled Memory Control Registers */
+#define SCB_DTCMCR_SZ_Pos                   3                                             /*!< SCB DTCMCR: SZ Position */
+#define SCB_DTCMCR_SZ_Msk                  (0xFUL << SCB_DTCMCR_SZ_Pos)                   /*!< SCB DTCMCR: SZ Mask */
+
+#define SCB_DTCMCR_RETEN_Pos                2                                             /*!< SCB DTCMCR: RETEN Position */
+#define SCB_DTCMCR_RETEN_Msk               (1UL << SCB_DTCMCR_RETEN_Pos)                   /*!< SCB DTCMCR: RETEN Mask */
+
+#define SCB_DTCMCR_RMW_Pos                  1                                             /*!< SCB DTCMCR: RMW Position */
+#define SCB_DTCMCR_RMW_Msk                 (1UL << SCB_DTCMCR_RMW_Pos)                    /*!< SCB DTCMCR: RMW Mask */
+
+#define SCB_DTCMCR_EN_Pos                   0                                             /*!< SCB DTCMCR: EN Position */
+#define SCB_DTCMCR_EN_Msk                  (1UL /*<< SCB_DTCMCR_EN_Pos*/)                 /*!< SCB DTCMCR: EN Mask */
+
+/* AHBP Control Register */
+#define SCB_AHBPCR_SZ_Pos                   1                                             /*!< SCB AHBPCR: SZ Position */
+#define SCB_AHBPCR_SZ_Msk                  (7UL << SCB_AHBPCR_SZ_Pos)                     /*!< SCB AHBPCR: SZ Mask */
+
+#define SCB_AHBPCR_EN_Pos                   0                                             /*!< SCB AHBPCR: EN Position */
+#define SCB_AHBPCR_EN_Msk                  (1UL /*<< SCB_AHBPCR_EN_Pos*/)                 /*!< SCB AHBPCR: EN Mask */
+
+/* L1 Cache Control Register */
+#define SCB_CACR_FORCEWT_Pos                2                                             /*!< SCB CACR: FORCEWT Position */
+#define SCB_CACR_FORCEWT_Msk               (1UL << SCB_CACR_FORCEWT_Pos)                  /*!< SCB CACR: FORCEWT Mask */
+
+#define SCB_CACR_ECCEN_Pos                  1                                             /*!< SCB CACR: ECCEN Position */
+#define SCB_CACR_ECCEN_Msk                 (1UL << SCB_CACR_ECCEN_Pos)                    /*!< SCB CACR: ECCEN Mask */
+
+#define SCB_CACR_SIWT_Pos                   0                                             /*!< SCB CACR: SIWT Position */
+#define SCB_CACR_SIWT_Msk                  (1UL /*<< SCB_CACR_SIWT_Pos*/)                 /*!< SCB CACR: SIWT Mask */
+
+/* AHBS control register */
+#define SCB_AHBSCR_INITCOUNT_Pos           11                                             /*!< SCB AHBSCR: INITCOUNT Position */
+#define SCB_AHBSCR_INITCOUNT_Msk           (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos)           /*!< SCB AHBSCR: INITCOUNT Mask */
+
+#define SCB_AHBSCR_TPRI_Pos                 2                                             /*!< SCB AHBSCR: TPRI Position */
+#define SCB_AHBSCR_TPRI_Msk                (0x1FFUL << SCB_AHBPCR_TPRI_Pos)               /*!< SCB AHBSCR: TPRI Mask */
+
+#define SCB_AHBSCR_CTL_Pos                  0                                             /*!< SCB AHBSCR: CTL Position*/
+#define SCB_AHBSCR_CTL_Msk                 (3UL /*<< SCB_AHBPCR_CTL_Pos*/)                /*!< SCB AHBSCR: CTL Mask */
+
+/* Auxiliary Bus Fault Status Register */
+#define SCB_ABFSR_AXIMTYPE_Pos              8                                             /*!< SCB ABFSR: AXIMTYPE Position*/
+#define SCB_ABFSR_AXIMTYPE_Msk             (3UL << SCB_ABFSR_AXIMTYPE_Pos)                /*!< SCB ABFSR: AXIMTYPE Mask */
+
+#define SCB_ABFSR_EPPB_Pos                  4                                             /*!< SCB ABFSR: EPPB Position*/
+#define SCB_ABFSR_EPPB_Msk                 (1UL << SCB_ABFSR_EPPB_Pos)                    /*!< SCB ABFSR: EPPB Mask */
+
+#define SCB_ABFSR_AXIM_Pos                  3                                             /*!< SCB ABFSR: AXIM Position*/
+#define SCB_ABFSR_AXIM_Msk                 (1UL << SCB_ABFSR_AXIM_Pos)                    /*!< SCB ABFSR: AXIM Mask */
+
+#define SCB_ABFSR_AHBP_Pos                  2                                             /*!< SCB ABFSR: AHBP Position*/
+#define SCB_ABFSR_AHBP_Msk                 (1UL << SCB_ABFSR_AHBP_Pos)                    /*!< SCB ABFSR: AHBP Mask */
+
+#define SCB_ABFSR_DTCM_Pos                  1                                             /*!< SCB ABFSR: DTCM Position*/
+#define SCB_ABFSR_DTCM_Msk                 (1UL << SCB_ABFSR_DTCM_Pos)                    /*!< SCB ABFSR: DTCM Mask */
+
+#define SCB_ABFSR_ITCM_Pos                  0                                             /*!< SCB ABFSR: ITCM Position*/
+#define SCB_ABFSR_ITCM_Msk                 (1UL /*<< SCB_ABFSR_ITCM_Pos*/)                /*!< SCB ABFSR: ITCM Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+    \brief      Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/** \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+       uint32_t RESERVED0[1];
+  __I  uint32_t ICTR;                    /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register      */
+  __IO uint32_t ACTLR;                   /*!< Offset: 0x008 (R/W)  Auxiliary Control Register              */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0                                          /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos    12                                          /*!< ACTLR: DISITMATBFLUSH Position */
+#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk    (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos)    /*!< ACTLR: DISITMATBFLUSH Mask */
+
+#define SCnSCB_ACTLR_DISRAMODE_Pos         11                                          /*!< ACTLR: DISRAMODE Position */
+#define SCnSCB_ACTLR_DISRAMODE_Msk         (1UL << SCnSCB_ACTLR_DISRAMODE_Pos)         /*!< ACTLR: DISRAMODE Mask */
+
+#define SCnSCB_ACTLR_FPEXCODIS_Pos         10                                          /*!< ACTLR: FPEXCODIS Position */
+#define SCnSCB_ACTLR_FPEXCODIS_Msk         (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos)         /*!< ACTLR: FPEXCODIS Mask */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos            2                                          /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos         0                                          /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+    \brief      Type definitions for the System Timer Registers.
+  @{
+ */
+
+/** \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
+  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
+  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+    \brief      Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/** \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+  __O  union
+  {
+    __O  uint8_t    u8;                  /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit                   */
+    __O  uint16_t   u16;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit                  */
+    __O  uint32_t   u32;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit                  */
+  }  PORT [32];                          /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers               */
+       uint32_t RESERVED0[864];
+  __IO uint32_t TER;                     /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register                 */
+       uint32_t RESERVED1[15];
+  __IO uint32_t TPR;                     /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register              */
+       uint32_t RESERVED2[15];
+  __IO uint32_t TCR;                     /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register                */
+       uint32_t RESERVED3[29];
+  __O  uint32_t IWR;                     /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register            */
+  __I  uint32_t IRR;                     /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register             */
+  __IO uint32_t IMCR;                    /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register     */
+       uint32_t RESERVED4[43];
+  __O  uint32_t LAR;                     /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register                  */
+  __I  uint32_t LSR;                     /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register                  */
+       uint32_t RESERVED5[6];
+  __I  uint32_t PID4;                    /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+  __I  uint32_t PID5;                    /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+  __I  uint32_t PID6;                    /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+  __I  uint32_t PID7;                    /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+  __I  uint32_t PID0;                    /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+  __I  uint32_t PID1;                    /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+  __I  uint32_t PID2;                    /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+  __I  uint32_t PID3;                    /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+  __I  uint32_t CID0;                    /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+  __I  uint32_t CID1;                    /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+  __I  uint32_t CID2;                    /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+  __I  uint32_t CID3;                    /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0                                             /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)            /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23                                             /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos             16                                             /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10                                             /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos              8                                             /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4                                             /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3                                             /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2                                             /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1                                             /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0                                             /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos                0                                             /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos                0                                             /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos            0                                             /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2                                             /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1                                             /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0                                             /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+    \brief      Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/** \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  Control Register                          */
+  __IO uint32_t CYCCNT;                  /*!< Offset: 0x004 (R/W)  Cycle Count Register                      */
+  __IO uint32_t CPICNT;                  /*!< Offset: 0x008 (R/W)  CPI Count Register                        */
+  __IO uint32_t EXCCNT;                  /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register         */
+  __IO uint32_t SLEEPCNT;                /*!< Offset: 0x010 (R/W)  Sleep Count Register                      */
+  __IO uint32_t LSUCNT;                  /*!< Offset: 0x014 (R/W)  LSU Count Register                        */
+  __IO uint32_t FOLDCNT;                 /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register         */
+  __I  uint32_t PCSR;                    /*!< Offset: 0x01C (R/ )  Program Counter Sample Register           */
+  __IO uint32_t COMP0;                   /*!< Offset: 0x020 (R/W)  Comparator Register 0                     */
+  __IO uint32_t MASK0;                   /*!< Offset: 0x024 (R/W)  Mask Register 0                           */
+  __IO uint32_t FUNCTION0;               /*!< Offset: 0x028 (R/W)  Function Register 0                       */
+       uint32_t RESERVED0[1];
+  __IO uint32_t COMP1;                   /*!< Offset: 0x030 (R/W)  Comparator Register 1                     */
+  __IO uint32_t MASK1;                   /*!< Offset: 0x034 (R/W)  Mask Register 1                           */
+  __IO uint32_t FUNCTION1;               /*!< Offset: 0x038 (R/W)  Function Register 1                       */
+       uint32_t RESERVED1[1];
+  __IO uint32_t COMP2;                   /*!< Offset: 0x040 (R/W)  Comparator Register 2                     */
+  __IO uint32_t MASK2;                   /*!< Offset: 0x044 (R/W)  Mask Register 2                           */
+  __IO uint32_t FUNCTION2;               /*!< Offset: 0x048 (R/W)  Function Register 2                       */
+       uint32_t RESERVED2[1];
+  __IO uint32_t COMP3;                   /*!< Offset: 0x050 (R/W)  Comparator Register 3                     */
+  __IO uint32_t MASK3;                   /*!< Offset: 0x054 (R/W)  Mask Register 3                           */
+  __IO uint32_t FUNCTION3;               /*!< Offset: 0x058 (R/W)  Function Register 3                       */
+       uint32_t RESERVED3[981];
+  __O  uint32_t LAR;                     /*!< Offset: 0xFB0 (  W)  Lock Access Register                      */
+  __I  uint32_t LSR;                     /*!< Offset: 0xFB4 (R  )  Lock Status Register                      */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28                                          /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27                                          /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26                                          /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25                                          /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24                                          /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22                                          /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21                                          /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20                                          /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19                                          /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18                                          /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17                                          /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16                                          /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12                                          /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10                                          /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9                                          /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5                                          /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1                                          /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0                                          /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0                                          /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0                                          /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0                                          /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0                                          /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0                                          /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos                   0                                          /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos           24                                          /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos        16                                          /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos        12                                          /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10                                          /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos            9                                          /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos         8                                          /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos           7                                          /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos          5                                          /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos           0                                          /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+    \brief      Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/** \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IO uint32_t SSPSR;                   /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register     */
+  __IO uint32_t CSPSR;                   /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+       uint32_t RESERVED0[2];
+  __IO uint32_t ACPR;                    /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+       uint32_t RESERVED1[55];
+  __IO uint32_t SPPR;                    /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+       uint32_t RESERVED2[131];
+  __I  uint32_t FFSR;                    /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IO uint32_t FFCR;                    /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __I  uint32_t FSCR;                    /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+       uint32_t RESERVED3[759];
+  __I  uint32_t TRIGGER;                 /*!< Offset: 0xEE8 (R/ )  TRIGGER */
+  __I  uint32_t FIFO0;                   /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+  __I  uint32_t ITATBCTR2;               /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+       uint32_t RESERVED4[1];
+  __I  uint32_t ITATBCTR0;               /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+  __I  uint32_t FIFO1;                   /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+  __IO uint32_t ITCTRL;                  /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+       uint32_t RESERVED5[39];
+  __IO uint32_t CLAIMSET;                /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IO uint32_t CLAIMCLR;                /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+       uint32_t RESERVED7[8];
+  __I  uint32_t DEVID;                   /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+  __I  uint32_t DEVTYPE;                 /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0                                          /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0                                          /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3                                          /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2                                          /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1                                          /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0                                          /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8                                          /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1                                          /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0                                          /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos        27                                          /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos        24                                          /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos                 16                                          /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos                  8                                          /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos                  0                                          /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos           0                                          /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/)    /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos        27                                          /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos        24                                          /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos                 16                                          /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos                  8                                          /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos                  0                                          /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos           0                                          /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/)    /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0                                          /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11                                          /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10                                          /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9                                          /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos              6                                          /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos             5                                          /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0                                          /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_MajorType_Pos           4                                          /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+#define TPI_DEVTYPE_SubType_Pos             0                                          /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+    \brief      Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/** \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */
+  __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */
+  __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */
+  __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */
+  __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */
+  __IO uint32_t RBAR_A1;                 /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register       */
+  __IO uint32_t RASR_A1;                 /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
+  __IO uint32_t RBAR_A2;                 /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register       */
+  __IO uint32_t RASR_A2;                 /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
+  __IO uint32_t RBAR_A3;                 /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register       */
+  __IO uint32_t RASR_A3;                 /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos                   5                                             /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if (__FPU_PRESENT == 1)
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_FPU     Floating Point Unit (FPU)
+    \brief      Type definitions for the Floating Point Unit (FPU)
+  @{
+ */
+
+/** \brief  Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+       uint32_t RESERVED0[1];
+  __IO uint32_t FPCCR;                   /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register               */
+  __IO uint32_t FPCAR;                   /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register               */
+  __IO uint32_t FPDSCR;                  /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register        */
+  __I  uint32_t MVFR0;                   /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0                       */
+  __I  uint32_t MVFR1;                   /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1                       */
+  __I  uint32_t MVFR2;                   /*!< Offset: 0x018 (R/ )  Media and FP Feature Register 2                       */
+} FPU_Type;
+
+/* Floating-Point Context Control Register */
+#define FPU_FPCCR_ASPEN_Pos                31                                             /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos                30                                             /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos                8                                             /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos                 6                                             /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos                 5                                             /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos                 4                                             /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos                3                                             /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_USER_Pos                  1                                             /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos                0                                             /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register */
+#define FPU_FPCAR_ADDRESS_Pos               3                                             /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register */
+#define FPU_FPDSCR_AHP_Pos                 26                                             /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos                  25                                             /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos                  24                                             /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos               22                                             /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 */
+#define FPU_MVFR0_FP_rounding_modes_Pos    28                                             /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos        24                                             /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos          20                                             /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos               16                                             /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos    12                                             /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos      8                                             /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos      4                                             /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos      0                                             /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)  /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 */
+#define FPU_MVFR1_FP_fused_MAC_Pos         28                                             /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos              24                                             /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos            4                                             /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos              0                                             /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)          /*!< MVFR1: FtZ mode bits Mask */
+
+/* Media and FP Feature Register 2 */
+
+/*@} end of group CMSIS_FPU */
+#endif
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+    \brief      Type definitions for the Core Debug Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IO uint32_t DHCSR;                   /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register    */
+  __O  uint32_t DCRSR;                   /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register        */
+  __IO uint32_t DCRDR;                   /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register            */
+  __IO uint32_t DEMCR;                   /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16                                             /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25                                             /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24                                             /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19                                             /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18                                             /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17                                             /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16                                             /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5                                             /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3                                             /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2                                             /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1                                             /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0                                             /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register */
+#define CoreDebug_DCRSR_REGWnR_Pos         16                                             /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0                                             /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_TRCENA_Pos         24                                             /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19                                             /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18                                             /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17                                             /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16                                             /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10                                             /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9                                             /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8                                             /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7                                             /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6                                             /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5                                             /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4                                             /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0                                             /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_core_base     Core Definitions
+    \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Cortex-M4 Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address  */
+#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address                   */
+#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address                   */
+#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address                   */
+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address            */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address               */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                  */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address  */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
+#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct           */
+#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct           */
+#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct           */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct    */
+
+#if (__MPU_PRESENT == 1)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */
+#endif
+
+#if (__FPU_PRESENT == 1)
+  #define FPU_BASE          (SCS_BASE +  0x0F30UL)                    /*!< Floating Point Unit                */
+  #define FPU               ((FPU_Type       *)     FPU_BASE      )   /*!< Floating Point Unit                */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+    \brief      Functions that manage interrupts and exceptions via the NVIC.
+    @{
+ */
+
+/** \brief  Set Priority Grouping
+
+  The function sets the priority grouping field using the required unlock sequence.
+  The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+  Only values from 0..7 are used.
+  In case of a conflict between priority grouping and available
+  priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+
+    \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
+
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk));             /* clear bits to change               */
+  reg_value  =  (reg_value                                   |
+                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << 8)                       );              /* Insert write key and priorty group */
+  SCB->AIRCR =  reg_value;
+}
+
+
+/** \brief  Get Priority Grouping
+
+  The function reads the priority grouping field from the NVIC Interrupt Controller.
+
+    \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
+{
+  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/** \brief  Enable External Interrupt
+
+    The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/** \brief  Disable External Interrupt
+
+    The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/** \brief  Get Pending Interrupt
+
+    The function reads the pending register in the NVIC and returns the pending bit
+    for the specified interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not pending.
+    \return             1  Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+}
+
+
+/** \brief  Set Pending Interrupt
+
+    The function sets the pending bit of an external interrupt.
+
+    \param [in]      IRQn  Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/** \brief  Clear Pending Interrupt
+
+    The function clears the pending bit of an external interrupt.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/** \brief  Get Active Interrupt
+
+    The function reads the active register in NVIC and returns the active bit.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not active.
+    \return             1  Interrupt status is active.
+ */
+__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+{
+  return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+}
+
+
+/** \brief  Set Interrupt Priority
+
+    The function sets the priority of an interrupt.
+
+    \note The priority cannot be set for every core interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+    \param [in]  priority  Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if((int32_t)IRQn < 0) {
+    SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+  else {
+    NVIC->IP[((uint32_t)(int32_t)IRQn)]                = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+}
+
+
+/** \brief  Get Interrupt Priority
+
+    The function reads the priority of an interrupt. The interrupt
+    number can be positive to specify an external (device specific)
+    interrupt, or negative to specify an internal (core) interrupt.
+
+
+    \param [in]   IRQn  Interrupt number.
+    \return             Interrupt Priority. Value is aligned automatically to the implemented
+                        priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if((int32_t)IRQn < 0) {
+    return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8 - __NVIC_PRIO_BITS)));
+  }
+  else {
+    return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)]               >> (8 - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/** \brief  Encode Priority
+
+    The function encodes the priority for an interrupt with the given priority group,
+    preemptive priority value, and subpriority value.
+    In case of a conflict between priority grouping and available
+    priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+
+    \param [in]     PriorityGroup  Used priority group.
+    \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+    \param [in]       SubPriority  Subpriority value (starting from 0).
+    \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/** \brief  Decode Priority
+
+    The function decodes an interrupt priority value with a given priority group to
+    preemptive priority value and subpriority value.
+    In case of a conflict between priority grouping and available
+    priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+
+    \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+    \param [in]     PriorityGroup  Used priority group.
+    \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+    \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+/** \brief  System Reset
+
+    The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
+                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
+  __DSB();                                                          /* Ensure completion of memory access */
+  while(1) { __NOP(); }                                             /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ##########################  FPU functions  #################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_FpuFunctions FPU Functions
+    \brief      Function that provides FPU type.
+    @{
+ */
+
+/**
+  \fn          uint32_t SCB_GetFPUType(void)
+  \brief       get FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+  uint32_t mvfr0;
+
+  mvfr0 = SCB->MVFR0;
+  if        ((mvfr0 & 0x00000FF0UL) == 0x220UL) {
+    return 2UL;           // Double + Single precision FPU
+  } else if ((mvfr0 & 0x00000FF0UL) == 0x020UL) {
+    return 1UL;           // Single precision FPU
+  } else {
+    return 0UL;           // No FPU
+  }
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##########################  Cache functions  #################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_CacheFunctions Cache Functions
+    \brief      Functions that configure Instruction and Data cache.
+    @{
+ */
+
+/* Cache Size ID Register Macros */
+#define CCSIDR_WAYS(x)         (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)
+#define CCSIDR_SETS(x)         (((x) & SCB_CCSIDR_NUMSETS_Msk      ) >> SCB_CCSIDR_NUMSETS_Pos      )
+#define CCSIDR_LSSHIFT(x)      (((x) & SCB_CCSIDR_LINESIZE_Msk     ) /*>> SCB_CCSIDR_LINESIZE_Pos*/ )
+
+
+/** \brief Enable I-Cache
+
+    The function turns on I-Cache
+  */
+__STATIC_INLINE void SCB_EnableICache (void)
+{
+  #if (__ICACHE_PRESENT == 1)
+    __DSB();
+    __ISB();
+    SCB->ICIALLU = 0UL;                     // invalidate I-Cache
+    SCB->CCR |=  (uint32_t)SCB_CCR_IC_Msk;  // enable I-Cache
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/** \brief Disable I-Cache
+
+    The function turns off I-Cache
+  */
+__STATIC_INLINE void SCB_DisableICache (void)
+{
+  #if (__ICACHE_PRESENT == 1)
+    __DSB();
+    __ISB();
+    SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk;  // disable I-Cache
+    SCB->ICIALLU = 0UL;                     // invalidate I-Cache
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/** \brief Invalidate I-Cache
+
+    The function invalidates I-Cache
+  */
+__STATIC_INLINE void SCB_InvalidateICache (void)
+{
+  #if (__ICACHE_PRESENT == 1)
+    __DSB();
+    __ISB();
+    SCB->ICIALLU = 0UL;
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/** \brief Enable D-Cache
+
+    The function turns on D-Cache
+  */
+__STATIC_INLINE void SCB_EnableDCache (void)
+{
+  #if (__DCACHE_PRESENT == 1)
+    uint32_t ccsidr, sshift, wshift, sw;
+    uint32_t sets, ways;
+
+    SCB->CSSELR = (0UL << 1) | 0UL;         // Level 1 data cache
+    ccsidr  = SCB->CCSIDR;
+    sets    = (uint32_t)(CCSIDR_SETS(ccsidr));
+    sshift  = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);
+    ways    = (uint32_t)(CCSIDR_WAYS(ccsidr));
+    wshift  = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);
+
+    __DSB();
+
+    do {                                   // invalidate D-Cache
+         uint32_t tmpways = ways;
+         do {
+              sw = ((tmpways << wshift) | (sets << sshift));
+              SCB->DCISW = sw;
+            } while(tmpways--);
+        } while(sets--);
+    __DSB();
+
+    SCB->CCR |=  (uint32_t)SCB_CCR_DC_Msk;   // enable D-Cache
+
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/** \brief Disable D-Cache
+
+    The function turns off D-Cache
+  */
+__STATIC_INLINE void SCB_DisableDCache (void)
+{
+  #if (__DCACHE_PRESENT == 1)
+    uint32_t ccsidr, sshift, wshift, sw;
+    uint32_t sets, ways;
+
+    SCB->CSSELR = (0UL << 1) | 0UL;         // Level 1 data cache
+    ccsidr  = SCB->CCSIDR;
+    sets    = (uint32_t)(CCSIDR_SETS(ccsidr));
+    sshift  = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);
+    ways    = (uint32_t)(CCSIDR_WAYS(ccsidr));
+    wshift  = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);
+
+    __DSB();
+
+    SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk;  // disable D-Cache
+
+    do {                                    // clean & invalidate D-Cache
+         uint32_t tmpways = ways;
+         do {
+              sw = ((tmpways << wshift) | (sets << sshift));
+              SCB->DCCISW = sw;
+            } while(tmpways--);
+        } while(sets--);
+
+
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/** \brief Invalidate D-Cache
+
+    The function invalidates D-Cache
+  */
+__STATIC_INLINE void SCB_InvalidateDCache (void)
+{
+  #if (__DCACHE_PRESENT == 1)
+    uint32_t ccsidr, sshift, wshift, sw;
+    uint32_t sets, ways;
+
+    SCB->CSSELR = (0UL << 1) | 0UL;         // Level 1 data cache
+    ccsidr  = SCB->CCSIDR;
+    sets    = (uint32_t)(CCSIDR_SETS(ccsidr));
+    sshift  = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);
+    ways    = (uint32_t)(CCSIDR_WAYS(ccsidr));
+    wshift  = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);
+
+    __DSB();
+
+    do {                                    // invalidate D-Cache
+         uint32_t tmpways = ways;
+         do {
+              sw = ((tmpways << wshift) | (sets << sshift));
+              SCB->DCISW = sw;
+            } while(tmpways--);
+        } while(sets--);
+
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/** \brief Clean D-Cache
+
+    The function cleans D-Cache
+  */
+__STATIC_INLINE void SCB_CleanDCache (void)
+{
+  #if (__DCACHE_PRESENT == 1)
+    uint32_t ccsidr, sshift, wshift, sw;
+    uint32_t sets, ways;
+
+    SCB->CSSELR = (0UL << 1) | 0UL;         // Level 1 data cache
+    ccsidr  = SCB->CCSIDR;
+    sets    = (uint32_t)(CCSIDR_SETS(ccsidr));
+    sshift  = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);
+    ways    = (uint32_t)(CCSIDR_WAYS(ccsidr));
+    wshift  = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);
+
+    __DSB();
+
+    do {                                    // clean D-Cache
+         uint32_t tmpways = ways;
+         do {
+              sw = ((tmpways << wshift) | (sets << sshift));
+              SCB->DCCSW = sw;
+            } while(tmpways--);
+        } while(sets--);
+
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/** \brief Clean & Invalidate D-Cache
+
+    The function cleans and Invalidates D-Cache
+  */
+__STATIC_INLINE void SCB_CleanInvalidateDCache (void)
+{
+  #if (__DCACHE_PRESENT == 1)
+    uint32_t ccsidr, sshift, wshift, sw;
+    uint32_t sets, ways;
+
+    SCB->CSSELR = (0UL << 1) | 0UL;         // Level 1 data cache
+    ccsidr  = SCB->CCSIDR;
+    sets    = (uint32_t)(CCSIDR_SETS(ccsidr));
+    sshift  = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);
+    ways    = (uint32_t)(CCSIDR_WAYS(ccsidr));
+    wshift  = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);
+
+    __DSB();
+
+    do {                                    // clean & invalidate D-Cache
+         uint32_t tmpways = ways;
+         do {
+              sw = ((tmpways << wshift) | (sets << sshift));
+              SCB->DCCISW = sw;
+            } while(tmpways--);
+        } while(sets--);
+
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \fn          void SCB_InvalidateDCache_by_Addr(volatile uint32_t *addr, int32_t dsize)
+  \brief       D-Cache Invalidate by address
+  \param[in]   addr    address (aligned to 32-byte boundary)
+  \param[in]   dsize   size of memory block (in number of bytes)
+*/
+__STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
+{
+  #if (__DCACHE_PRESENT == 1)
+    int32_t  op_size = dsize;
+    uint32_t op_addr = (uint32_t)addr;
+    uint32_t linesize = 32UL;               // in Cortex-M7 size of cache line is fixed to 8 words (32 bytes)
+
+    __DSB();
+
+    while (op_size > 0) {
+      SCB->DCIMVAC = op_addr;
+      op_addr +=          linesize;
+      op_size -= (int32_t)linesize;
+    }
+
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \fn          void SCB_CleanDCache_by_Addr(volatile uint32_t *addr, int32_t dsize)
+  \brief       D-Cache Clean by address
+  \param[in]   addr    address (aligned to 32-byte boundary)
+  \param[in]   dsize   size of memory block (in number of bytes)
+*/
+__STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize)
+{
+  #if (__DCACHE_PRESENT == 1)
+    int32_t  op_size = dsize;
+    uint32_t op_addr = (uint32_t) addr;
+    uint32_t linesize = 32UL;               // in Cortex-M7 size of cache line is fixed to 8 words (32 bytes)
+
+    __DSB();
+
+    while (op_size > 0) {
+      SCB->DCCMVAC = op_addr;
+      op_addr +=          linesize;
+      op_size -= (int32_t)linesize;
+    }
+
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \fn          void SCB_CleanInvalidateDCache_by_Addr(volatile uint32_t *addr, int32_t dsize)
+  \brief       D-Cache Clean and Invalidate by address
+  \param[in]   addr    address (aligned to 32-byte boundary)
+  \param[in]   dsize   size of memory block (in number of bytes)
+*/
+__STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
+{
+  #if (__DCACHE_PRESENT == 1)
+    int32_t  op_size = dsize;
+    uint32_t op_addr = (uint32_t) addr;
+    uint32_t linesize = 32UL;               // in Cortex-M7 size of cache line is fixed to 8 words (32 bytes)
+
+    __DSB();
+
+    while (op_size > 0) {
+      SCB->DCCIMVAC = op_addr;
+      op_addr +=          linesize;
+      op_size -= (int32_t)linesize;
+    }
+
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/*@} end of CMSIS_Core_CacheFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+    \brief      Functions that configure the System.
+  @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief  System Tick Configuration
+
+    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+    Counter is in free running mode to generate periodic interrupts.
+
+    \param [in]  ticks  Number of ticks between two interrupts.
+
+    \return          0  Function succeeded.
+    \return          1  Function failed.
+
+    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+    must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); }    /* Reload value impossible */
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_core_DebugFunctions ITM Functions
+    \brief   Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                    /*!< External variable to receive characters.                         */
+#define                 ITM_RXBUFFER_EMPTY    0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/** \brief  ITM Send Character
+
+    The function transmits a character via the ITM channel 0, and
+    \li Just returns when no debugger is connected that has booked the output.
+    \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+
+    \param [in]     ch  Character to transmit.
+
+    \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
+      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */
+  {
+    while (ITM->PORT[0].u32 == 0UL) { __NOP(); }
+    ITM->PORT[0].u8 = (uint8_t)ch;
+  }
+  return (ch);
+}
+
+
+/** \brief  ITM Receive Character
+
+    The function inputs a character via the external variable \ref ITM_RxBuffer.
+
+    \return             Received character.
+    \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
+  int32_t ch = -1;                           /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+
+  return (ch);
+}
+
+
+/** \brief  ITM Check Character
+
+    The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+
+    \return          0  No character available.
+    \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void) {
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
+    return (0);                                 /* no character available */
+  } else {
+    return (1);                                 /*    character available */
+  }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM7_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/ext/TARGET_LPC1768/core_cmFunc.h b/ext/TARGET_LPC1768/core_cmFunc.h
new file mode 100644
index 0000000..e3c057e
--- /dev/null
+++ b/ext/TARGET_LPC1768/core_cmFunc.h
@@ -0,0 +1,664 @@
+/**************************************************************************//**

+ * @file     core_cmFunc.h

+ * @brief    CMSIS Cortex-M Core Function Access Header File

+ * @version  V4.10

+ * @date     18. March 2015

+ *

+ * @note

+ *

+ ******************************************************************************/

+/* Copyright (c) 2009 - 2015 ARM LIMITED

+

+   All rights reserved.

+   Redistribution and use in source and binary forms, with or without

+   modification, are permitted provided that the following conditions are met:

+   - Redistributions of source code must retain the above copyright

+     notice, this list of conditions and the following disclaimer.

+   - Redistributions in binary form must reproduce the above copyright

+     notice, this list of conditions and the following disclaimer in the

+     documentation and/or other materials provided with the distribution.

+   - Neither the name of ARM nor the names of its contributors may be used

+     to endorse or promote products derived from this software without

+     specific prior written permission.

+   *

+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"

+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE

+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE

+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE

+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR

+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF

+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS

+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN

+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)

+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE

+   POSSIBILITY OF SUCH DAMAGE.

+   ---------------------------------------------------------------------------*/

+

+

+#ifndef __CORE_CMFUNC_H

+#define __CORE_CMFUNC_H

+

+

+/* ###########################  Core Function Access  ########################### */

+/** \ingroup  CMSIS_Core_FunctionInterface

+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions

+  @{

+ */

+

+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/

+/* ARM armcc specific functions */

+

+#if (__ARMCC_VERSION < 400677)

+  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"

+#endif

+

+/* intrinsic void __enable_irq();     */

+/* intrinsic void __disable_irq();    */

+

+/** \brief  Get Control Register

+

+    This function returns the content of the Control Register.

+

+    \return               Control Register value

+ */

+__STATIC_INLINE uint32_t __get_CONTROL(void)

+{

+  register uint32_t __regControl         __ASM("control");

+  return(__regControl);

+}

+

+

+/** \brief  Set Control Register

+

+    This function writes the given value to the Control Register.

+

+    \param [in]    control  Control Register value to set

+ */

+__STATIC_INLINE void __set_CONTROL(uint32_t control)

+{

+  register uint32_t __regControl         __ASM("control");

+  __regControl = control;

+}

+

+

+/** \brief  Get IPSR Register

+

+    This function returns the content of the IPSR Register.

+

+    \return               IPSR Register value

+ */

+__STATIC_INLINE uint32_t __get_IPSR(void)

+{

+  register uint32_t __regIPSR          __ASM("ipsr");

+  return(__regIPSR);

+}

+

+

+/** \brief  Get APSR Register

+

+    This function returns the content of the APSR Register.

+

+    \return               APSR Register value

+ */

+__STATIC_INLINE uint32_t __get_APSR(void)

+{

+  register uint32_t __regAPSR          __ASM("apsr");

+  return(__regAPSR);

+}

+

+

+/** \brief  Get xPSR Register

+

+    This function returns the content of the xPSR Register.

+

+    \return               xPSR Register value

+ */

+__STATIC_INLINE uint32_t __get_xPSR(void)

+{

+  register uint32_t __regXPSR          __ASM("xpsr");

+  return(__regXPSR);

+}

+

+

+/** \brief  Get Process Stack Pointer

+

+    This function returns the current value of the Process Stack Pointer (PSP).

+

+    \return               PSP Register value

+ */

+__STATIC_INLINE uint32_t __get_PSP(void)

+{

+  register uint32_t __regProcessStackPointer  __ASM("psp");

+  return(__regProcessStackPointer);

+}

+

+

+/** \brief  Set Process Stack Pointer

+

+    This function assigns the given value to the Process Stack Pointer (PSP).

+

+    \param [in]    topOfProcStack  Process Stack Pointer value to set

+ */

+__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)

+{

+  register uint32_t __regProcessStackPointer  __ASM("psp");

+  __regProcessStackPointer = topOfProcStack;

+}

+

+

+/** \brief  Get Main Stack Pointer

+

+    This function returns the current value of the Main Stack Pointer (MSP).

+

+    \return               MSP Register value

+ */

+__STATIC_INLINE uint32_t __get_MSP(void)

+{

+  register uint32_t __regMainStackPointer     __ASM("msp");

+  return(__regMainStackPointer);

+}

+

+

+/** \brief  Set Main Stack Pointer

+

+    This function assigns the given value to the Main Stack Pointer (MSP).

+

+    \param [in]    topOfMainStack  Main Stack Pointer value to set

+ */

+__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)

+{

+  register uint32_t __regMainStackPointer     __ASM("msp");

+  __regMainStackPointer = topOfMainStack;

+}

+

+

+/** \brief  Get Priority Mask

+

+    This function returns the current state of the priority mask bit from the Priority Mask Register.

+

+    \return               Priority Mask value

+ */

+__STATIC_INLINE uint32_t __get_PRIMASK(void)

+{

+  register uint32_t __regPriMask         __ASM("primask");

+  return(__regPriMask);

+}

+

+

+/** \brief  Set Priority Mask

+

+    This function assigns the given value to the Priority Mask Register.

+

+    \param [in]    priMask  Priority Mask

+ */

+__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)

+{

+  register uint32_t __regPriMask         __ASM("primask");

+  __regPriMask = (priMask);

+}

+

+

+#if       (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)

+

+/** \brief  Enable FIQ

+

+    This function enables FIQ interrupts by clearing the F-bit in the CPSR.

+    Can only be executed in Privileged modes.

+ */

+#define __enable_fault_irq                __enable_fiq

+

+

+/** \brief  Disable FIQ

+

+    This function disables FIQ interrupts by setting the F-bit in the CPSR.

+    Can only be executed in Privileged modes.

+ */

+#define __disable_fault_irq               __disable_fiq

+

+

+/** \brief  Get Base Priority

+

+    This function returns the current value of the Base Priority register.

+

+    \return               Base Priority register value

+ */

+__STATIC_INLINE uint32_t  __get_BASEPRI(void)

+{

+  register uint32_t __regBasePri         __ASM("basepri");

+  return(__regBasePri);

+}

+

+

+/** \brief  Set Base Priority

+

+    This function assigns the given value to the Base Priority register.

+

+    \param [in]    basePri  Base Priority value to set

+ */

+__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)

+{

+  register uint32_t __regBasePri         __ASM("basepri");

+  __regBasePri = (basePri & 0xff);

+}

+

+

+/** \brief  Set Base Priority with condition

+

+    This function assigns the given value to the Base Priority register only if BASEPRI masking is disabled,

+    or the new value increases the BASEPRI priority level.

+

+    \param [in]    basePri  Base Priority value to set

+ */

+__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)

+{

+  register uint32_t __regBasePriMax      __ASM("basepri_max");

+  __regBasePriMax = (basePri & 0xff);

+}

+

+

+/** \brief  Get Fault Mask

+

+    This function returns the current value of the Fault Mask register.

+

+    \return               Fault Mask register value

+ */

+__STATIC_INLINE uint32_t __get_FAULTMASK(void)

+{

+  register uint32_t __regFaultMask       __ASM("faultmask");

+  return(__regFaultMask);

+}

+

+

+/** \brief  Set Fault Mask

+

+    This function assigns the given value to the Fault Mask register.

+

+    \param [in]    faultMask  Fault Mask value to set

+ */

+__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)

+{

+  register uint32_t __regFaultMask       __ASM("faultmask");

+  __regFaultMask = (faultMask & (uint32_t)1);

+}

+

+#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */

+

+

+#if       (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)

+

+/** \brief  Get FPSCR

+

+    This function returns the current value of the Floating Point Status/Control register.

+

+    \return               Floating Point Status/Control register value

+ */

+__STATIC_INLINE uint32_t __get_FPSCR(void)

+{

+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)

+  register uint32_t __regfpscr         __ASM("fpscr");

+  return(__regfpscr);

+#else

+   return(0);

+#endif

+}

+

+

+/** \brief  Set FPSCR

+

+    This function assigns the given value to the Floating Point Status/Control register.

+

+    \param [in]    fpscr  Floating Point Status/Control value to set

+ */

+__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)

+{

+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)

+  register uint32_t __regfpscr         __ASM("fpscr");

+  __regfpscr = (fpscr);

+#endif

+}

+

+#endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */

+

+

+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/

+/* GNU gcc specific functions */

+

+/** \brief  Enable IRQ Interrupts

+

+  This function enables IRQ interrupts by clearing the I-bit in the CPSR.

+  Can only be executed in Privileged modes.

+ */

+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)

+{

+  __ASM volatile ("cpsie i" : : : "memory");

+}

+

+

+/** \brief  Disable IRQ Interrupts

+

+  This function disables IRQ interrupts by setting the I-bit in the CPSR.

+  Can only be executed in Privileged modes.

+ */

+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)

+{

+  __ASM volatile ("cpsid i" : : : "memory");

+}

+

+

+/** \brief  Get Control Register

+

+    This function returns the content of the Control Register.

+

+    \return               Control Register value

+ */

+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)

+{

+  uint32_t result;

+

+  __ASM volatile ("MRS %0, control" : "=r" (result) );

+  return(result);

+}

+

+

+/** \brief  Set Control Register

+

+    This function writes the given value to the Control Register.

+

+    \param [in]    control  Control Register value to set

+ */

+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)

+{

+  __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");

+}

+

+

+/** \brief  Get IPSR Register

+

+    This function returns the content of the IPSR Register.

+

+    \return               IPSR Register value

+ */

+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)

+{

+  uint32_t result;

+

+  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );

+  return(result);

+}

+

+

+/** \brief  Get APSR Register

+

+    This function returns the content of the APSR Register.

+

+    \return               APSR Register value

+ */

+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)

+{

+  uint32_t result;

+

+  __ASM volatile ("MRS %0, apsr" : "=r" (result) );

+  return(result);

+}

+

+

+/** \brief  Get xPSR Register

+

+    This function returns the content of the xPSR Register.

+

+    \return               xPSR Register value

+ */

+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)

+{

+  uint32_t result;

+

+  __ASM volatile ("MRS %0, xpsr" : "=r" (result) );

+  return(result);

+}

+

+

+/** \brief  Get Process Stack Pointer

+

+    This function returns the current value of the Process Stack Pointer (PSP).

+

+    \return               PSP Register value

+ */

+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)

+{

+  register uint32_t result;

+

+  __ASM volatile ("MRS %0, psp\n"  : "=r" (result) );

+  return(result);

+}

+

+

+/** \brief  Set Process Stack Pointer

+

+    This function assigns the given value to the Process Stack Pointer (PSP).

+

+    \param [in]    topOfProcStack  Process Stack Pointer value to set

+ */

+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)

+{

+  __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");

+}

+

+

+/** \brief  Get Main Stack Pointer

+

+    This function returns the current value of the Main Stack Pointer (MSP).

+

+    \return               MSP Register value

+ */

+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)

+{

+  register uint32_t result;

+

+  __ASM volatile ("MRS %0, msp\n" : "=r" (result) );

+  return(result);

+}

+

+

+/** \brief  Set Main Stack Pointer

+

+    This function assigns the given value to the Main Stack Pointer (MSP).

+

+    \param [in]    topOfMainStack  Main Stack Pointer value to set

+ */

+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)

+{

+  __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");

+}

+

+

+/** \brief  Get Priority Mask

+

+    This function returns the current state of the priority mask bit from the Priority Mask Register.

+

+    \return               Priority Mask value

+ */

+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)

+{

+  uint32_t result;

+

+  __ASM volatile ("MRS %0, primask" : "=r" (result) );

+  return(result);

+}

+

+

+/** \brief  Set Priority Mask

+

+    This function assigns the given value to the Priority Mask Register.

+

+    \param [in]    priMask  Priority Mask

+ */

+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)

+{

+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");

+}

+

+

+#if       (__CORTEX_M >= 0x03)

+

+/** \brief  Enable FIQ

+

+    This function enables FIQ interrupts by clearing the F-bit in the CPSR.

+    Can only be executed in Privileged modes.

+ */

+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)

+{

+  __ASM volatile ("cpsie f" : : : "memory");

+}

+

+

+/** \brief  Disable FIQ

+

+    This function disables FIQ interrupts by setting the F-bit in the CPSR.

+    Can only be executed in Privileged modes.

+ */

+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)

+{

+  __ASM volatile ("cpsid f" : : : "memory");

+}

+

+

+/** \brief  Get Base Priority

+

+    This function returns the current value of the Base Priority register.

+

+    \return               Base Priority register value

+ */

+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)

+{

+  uint32_t result;

+

+  __ASM volatile ("MRS %0, basepri" : "=r" (result) );

+  return(result);

+}

+

+

+/** \brief  Set Base Priority

+

+    This function assigns the given value to the Base Priority register.

+

+    \param [in]    basePri  Base Priority value to set

+ */

+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)

+{

+  __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");

+}

+

+

+/** \brief  Set Base Priority with condition

+

+    This function assigns the given value to the Base Priority register only if BASEPRI masking is disabled,

+	or the new value increases the BASEPRI priority level.

+

+    \param [in]    basePri  Base Priority value to set

+ */

+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value)

+{

+  __ASM volatile ("MSR basepri_max, %0" : : "r" (value) : "memory");

+}

+

+

+/** \brief  Get Fault Mask

+

+    This function returns the current value of the Fault Mask register.

+

+    \return               Fault Mask register value

+ */

+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)

+{

+  uint32_t result;

+

+  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );

+  return(result);

+}

+

+

+/** \brief  Set Fault Mask

+

+    This function assigns the given value to the Fault Mask register.

+

+    \param [in]    faultMask  Fault Mask value to set

+ */

+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)

+{

+  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");

+}

+

+#endif /* (__CORTEX_M >= 0x03) */

+

+

+#if       (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)

+

+/** \brief  Get FPSCR

+

+    This function returns the current value of the Floating Point Status/Control register.

+

+    \return               Floating Point Status/Control register value

+ */

+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)

+{

+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)

+  uint32_t result;

+

+  /* Empty asm statement works as a scheduling barrier */

+  __ASM volatile ("");

+  __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );

+  __ASM volatile ("");

+  return(result);

+#else

+   return(0);

+#endif

+}

+

+

+/** \brief  Set FPSCR

+

+    This function assigns the given value to the Floating Point Status/Control register.

+

+    \param [in]    fpscr  Floating Point Status/Control value to set

+ */

+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)

+{

+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)

+  /* Empty asm statement works as a scheduling barrier */

+  __ASM volatile ("");

+  __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");

+  __ASM volatile ("");

+#endif

+}

+

+#endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */

+

+

+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/

+/* IAR iccarm specific functions */

+#include <cmsis_iar.h>

+

+

+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/

+/* TI CCS specific functions */

+#include <cmsis_ccs.h>

+

+

+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/

+/* TASKING carm specific functions */

+/*

+ * The CMSIS functions have been implemented as intrinsics in the compiler.

+ * Please use "carm -?i" to get an up to date list of all intrinsics,

+ * Including the CMSIS ones.

+ */

+

+

+#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/

+/* Cosmic specific functions */

+#include <cmsis_csm.h>

+

+#endif

+

+/*@} end of CMSIS_Core_RegAccFunctions */

+

+#endif /* __CORE_CMFUNC_H */

diff --git a/ext/TARGET_LPC1768/core_cmInstr.h b/ext/TARGET_LPC1768/core_cmInstr.h
new file mode 100644
index 0000000..c8e045f
--- /dev/null
+++ b/ext/TARGET_LPC1768/core_cmInstr.h
@@ -0,0 +1,916 @@
+/**************************************************************************//**

+ * @file     core_cmInstr.h

+ * @brief    CMSIS Cortex-M Core Instruction Access Header File

+ * @version  V4.10

+ * @date     18. March 2015

+ *

+ * @note

+ *

+ ******************************************************************************/

+/* Copyright (c) 2009 - 2014 ARM LIMITED

+

+   All rights reserved.

+   Redistribution and use in source and binary forms, with or without

+   modification, are permitted provided that the following conditions are met:

+   - Redistributions of source code must retain the above copyright

+     notice, this list of conditions and the following disclaimer.

+   - Redistributions in binary form must reproduce the above copyright

+     notice, this list of conditions and the following disclaimer in the

+     documentation and/or other materials provided with the distribution.

+   - Neither the name of ARM nor the names of its contributors may be used

+     to endorse or promote products derived from this software without

+     specific prior written permission.

+   *

+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"

+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE

+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE

+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE

+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR

+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF

+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS

+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN

+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)

+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE

+   POSSIBILITY OF SUCH DAMAGE.

+   ---------------------------------------------------------------------------*/

+

+

+#ifndef __CORE_CMINSTR_H

+#define __CORE_CMINSTR_H

+

+

+/* ##########################  Core Instruction Access  ######################### */

+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface

+  Access to dedicated instructions

+  @{

+*/

+

+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/

+/* ARM armcc specific functions */

+

+#if (__ARMCC_VERSION < 400677)

+  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"

+#endif

+

+

+/** \brief  No Operation

+

+    No Operation does nothing. This instruction can be used for code alignment purposes.

+ */

+#define __NOP                             __nop

+

+

+/** \brief  Wait For Interrupt

+

+    Wait For Interrupt is a hint instruction that suspends execution

+    until one of a number of events occurs.

+ */

+#define __WFI                             __wfi

+

+

+/** \brief  Wait For Event

+

+    Wait For Event is a hint instruction that permits the processor to enter

+    a low-power state until one of a number of events occurs.

+ */

+#define __WFE                             __wfe

+

+

+/** \brief  Send Event

+

+    Send Event is a hint instruction. It causes an event to be signaled to the CPU.

+ */

+#define __SEV                             __sev

+

+

+/** \brief  Instruction Synchronization Barrier

+

+    Instruction Synchronization Barrier flushes the pipeline in the processor,

+    so that all instructions following the ISB are fetched from cache or

+    memory, after the instruction has been completed.

+ */

+#define __ISB() do {\

+                   __schedule_barrier();\

+                   __isb(0xF);\

+                   __schedule_barrier();\

+                } while (0)

+

+/** \brief  Data Synchronization Barrier

+

+    This function acts as a special kind of Data Memory Barrier.

+    It completes when all explicit memory accesses before this instruction complete.

+ */

+#define __DSB() do {\

+                   __schedule_barrier();\

+                   __dsb(0xF);\

+                   __schedule_barrier();\

+                } while (0)

+

+/** \brief  Data Memory Barrier

+

+    This function ensures the apparent order of the explicit memory operations before

+    and after the instruction, without ensuring their completion.

+ */

+#define __DMB() do {\

+                   __schedule_barrier();\

+                   __dmb(0xF);\

+                   __schedule_barrier();\

+                } while (0)

+

+/** \brief  Reverse byte order (32 bit)

+

+    This function reverses the byte order in integer value.

+

+    \param [in]    value  Value to reverse

+    \return               Reversed value

+ */

+#define __REV                             __rev

+

+

+/** \brief  Reverse byte order (16 bit)

+

+    This function reverses the byte order in two unsigned short values.

+

+    \param [in]    value  Value to reverse

+    \return               Reversed value

+ */

+#ifndef __NO_EMBEDDED_ASM

+__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)

+{

+  rev16 r0, r0

+  bx lr

+}

+#endif

+

+/** \brief  Reverse byte order in signed short value

+

+    This function reverses the byte order in a signed short value with sign extension to integer.

+

+    \param [in]    value  Value to reverse

+    \return               Reversed value

+ */

+#ifndef __NO_EMBEDDED_ASM

+__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)

+{

+  revsh r0, r0

+  bx lr

+}

+#endif

+

+

+/** \brief  Rotate Right in unsigned value (32 bit)

+

+    This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.

+

+    \param [in]    value  Value to rotate

+    \param [in]    value  Number of Bits to rotate

+    \return               Rotated value

+ */

+#define __ROR                             __ror

+

+

+/** \brief  Breakpoint

+

+    This function causes the processor to enter Debug state.

+    Debug tools can use this to investigate system state when the instruction at a particular address is reached.

+

+    \param [in]    value  is ignored by the processor.

+                   If required, a debugger can use it to store additional information about the breakpoint.

+ */

+#define __BKPT(value)                       __breakpoint(value)

+

+

+/** \brief  Reverse bit order of value

+

+    This function reverses the bit order of the given value.

+

+    \param [in]    value  Value to reverse

+    \return               Reversed value

+ */

+#if       (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)

+  #define __RBIT                          __rbit

+#else

+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)

+{

+  uint32_t result;

+  int32_t s = 4 /*sizeof(v)*/ * 8 - 1; // extra shift needed at end

+

+  result = value;                      // r will be reversed bits of v; first get LSB of v

+  for (value >>= 1; value; value >>= 1)

+  {

+    result <<= 1;

+    result |= value & 1;

+    s--;

+  }

+  result <<= s;                       // shift when v's highest bits are zero

+  return(result);

+}

+#endif

+

+

+/** \brief  Count leading zeros

+

+    This function counts the number of leading zeros of a data value.

+

+    \param [in]  value  Value to count the leading zeros

+    \return             number of leading zeros in value

+ */

+#define __CLZ                             __clz

+

+

+#if       (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)

+

+/** \brief  LDR Exclusive (8 bit)

+

+    This function executes a exclusive LDR instruction for 8 bit value.

+

+    \param [in]    ptr  Pointer to data

+    \return             value of type uint8_t at (*ptr)

+ */

+#define __LDREXB(ptr)                     ((uint8_t ) __ldrex(ptr))

+

+

+/** \brief  LDR Exclusive (16 bit)

+

+    This function executes a exclusive LDR instruction for 16 bit values.

+

+    \param [in]    ptr  Pointer to data

+    \return        value of type uint16_t at (*ptr)

+ */

+#define __LDREXH(ptr)                     ((uint16_t) __ldrex(ptr))

+

+

+/** \brief  LDR Exclusive (32 bit)

+

+    This function executes a exclusive LDR instruction for 32 bit values.

+

+    \param [in]    ptr  Pointer to data

+    \return        value of type uint32_t at (*ptr)

+ */

+#define __LDREXW(ptr)                     ((uint32_t ) __ldrex(ptr))

+

+

+/** \brief  STR Exclusive (8 bit)

+

+    This function executes a exclusive STR instruction for 8 bit values.

+

+    \param [in]  value  Value to store

+    \param [in]    ptr  Pointer to location

+    \return          0  Function succeeded

+    \return          1  Function failed

+ */

+#define __STREXB(value, ptr)              __strex(value, ptr)

+

+

+/** \brief  STR Exclusive (16 bit)

+

+    This function executes a exclusive STR instruction for 16 bit values.

+

+    \param [in]  value  Value to store

+    \param [in]    ptr  Pointer to location

+    \return          0  Function succeeded

+    \return          1  Function failed

+ */

+#define __STREXH(value, ptr)              __strex(value, ptr)

+

+

+/** \brief  STR Exclusive (32 bit)

+

+    This function executes a exclusive STR instruction for 32 bit values.

+

+    \param [in]  value  Value to store

+    \param [in]    ptr  Pointer to location

+    \return          0  Function succeeded

+    \return          1  Function failed

+ */

+#define __STREXW(value, ptr)              __strex(value, ptr)

+

+

+/** \brief  Remove the exclusive lock

+

+    This function removes the exclusive lock which is created by LDREX.

+

+ */

+#define __CLREX                           __clrex

+

+

+/** \brief  Signed Saturate

+

+    This function saturates a signed value.

+

+    \param [in]  value  Value to be saturated

+    \param [in]    sat  Bit position to saturate to (1..32)

+    \return             Saturated value

+ */

+#define __SSAT                            __ssat

+

+

+/** \brief  Unsigned Saturate

+

+    This function saturates an unsigned value.

+

+    \param [in]  value  Value to be saturated

+    \param [in]    sat  Bit position to saturate to (0..31)

+    \return             Saturated value

+ */

+#define __USAT                            __usat

+

+

+/** \brief  Rotate Right with Extend (32 bit)

+

+    This function moves each bit of a bitstring right by one bit.

+    The carry input is shifted in at the left end of the bitstring.

+

+    \param [in]    value  Value to rotate

+    \return               Rotated value

+ */

+#ifndef __NO_EMBEDDED_ASM

+__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)

+{

+  rrx r0, r0

+  bx lr

+}

+#endif

+

+

+/** \brief  LDRT Unprivileged (8 bit)

+

+    This function executes a Unprivileged LDRT instruction for 8 bit value.

+

+    \param [in]    ptr  Pointer to data

+    \return             value of type uint8_t at (*ptr)

+ */

+#define __LDRBT(ptr)                      ((uint8_t )  __ldrt(ptr))

+

+

+/** \brief  LDRT Unprivileged (16 bit)

+

+    This function executes a Unprivileged LDRT instruction for 16 bit values.

+

+    \param [in]    ptr  Pointer to data

+    \return        value of type uint16_t at (*ptr)

+ */

+#define __LDRHT(ptr)                      ((uint16_t)  __ldrt(ptr))

+

+

+/** \brief  LDRT Unprivileged (32 bit)

+

+    This function executes a Unprivileged LDRT instruction for 32 bit values.

+

+    \param [in]    ptr  Pointer to data

+    \return        value of type uint32_t at (*ptr)

+ */

+#define __LDRT(ptr)                       ((uint32_t ) __ldrt(ptr))

+

+

+/** \brief  STRT Unprivileged (8 bit)

+

+    This function executes a Unprivileged STRT instruction for 8 bit values.

+

+    \param [in]  value  Value to store

+    \param [in]    ptr  Pointer to location

+ */

+#define __STRBT(value, ptr)               __strt(value, ptr)

+

+

+/** \brief  STRT Unprivileged (16 bit)

+

+    This function executes a Unprivileged STRT instruction for 16 bit values.

+

+    \param [in]  value  Value to store

+    \param [in]    ptr  Pointer to location

+ */

+#define __STRHT(value, ptr)               __strt(value, ptr)

+

+

+/** \brief  STRT Unprivileged (32 bit)

+

+    This function executes a Unprivileged STRT instruction for 32 bit values.

+

+    \param [in]  value  Value to store

+    \param [in]    ptr  Pointer to location

+ */

+#define __STRT(value, ptr)                __strt(value, ptr)

+

+#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */

+

+

+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/

+/* GNU gcc specific functions */

+

+/* Define macros for porting to both thumb1 and thumb2.

+ * For thumb1, use low register (r0-r7), specified by constrant "l"

+ * Otherwise, use general registers, specified by constrant "r" */

+#if defined (__thumb__) && !defined (__thumb2__)

+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)

+#define __CMSIS_GCC_USE_REG(r) "l" (r)

+#else

+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)

+#define __CMSIS_GCC_USE_REG(r) "r" (r)

+#endif

+

+/** \brief  No Operation

+

+    No Operation does nothing. This instruction can be used for code alignment purposes.

+ */

+__attribute__((always_inline)) __STATIC_INLINE void __NOP(void)

+{

+  __ASM volatile ("nop");

+}

+

+

+/** \brief  Wait For Interrupt

+

+    Wait For Interrupt is a hint instruction that suspends execution

+    until one of a number of events occurs.

+ */

+__attribute__((always_inline)) __STATIC_INLINE void __WFI(void)

+{

+  __ASM volatile ("wfi");

+}

+

+

+/** \brief  Wait For Event

+

+    Wait For Event is a hint instruction that permits the processor to enter

+    a low-power state until one of a number of events occurs.

+ */

+__attribute__((always_inline)) __STATIC_INLINE void __WFE(void)

+{

+  __ASM volatile ("wfe");

+}

+

+

+/** \brief  Send Event

+

+    Send Event is a hint instruction. It causes an event to be signaled to the CPU.

+ */

+__attribute__((always_inline)) __STATIC_INLINE void __SEV(void)

+{

+  __ASM volatile ("sev");

+}

+

+

+/** \brief  Instruction Synchronization Barrier

+

+    Instruction Synchronization Barrier flushes the pipeline in the processor,

+    so that all instructions following the ISB are fetched from cache or

+    memory, after the instruction has been completed.

+ */

+__attribute__((always_inline)) __STATIC_INLINE void __ISB(void)

+{

+  __ASM volatile ("isb 0xF":::"memory");

+}

+

+

+/** \brief  Data Synchronization Barrier

+

+    This function acts as a special kind of Data Memory Barrier.

+    It completes when all explicit memory accesses before this instruction complete.

+ */

+__attribute__((always_inline)) __STATIC_INLINE void __DSB(void)

+{

+  __ASM volatile ("dsb 0xF":::"memory");

+}

+

+

+/** \brief  Data Memory Barrier

+

+    This function ensures the apparent order of the explicit memory operations before

+    and after the instruction, without ensuring their completion.

+ */

+__attribute__((always_inline)) __STATIC_INLINE void __DMB(void)

+{

+  __ASM volatile ("dmb 0xF":::"memory");

+}

+

+

+/** \brief  Reverse byte order (32 bit)

+

+    This function reverses the byte order in integer value.

+

+    \param [in]    value  Value to reverse

+    \return               Reversed value

+ */

+__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value)

+{

+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)

+  return __builtin_bswap32(value);

+#else

+  uint32_t result;

+

+  __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );

+  return(result);

+#endif

+}

+

+

+/** \brief  Reverse byte order (16 bit)

+

+    This function reverses the byte order in two unsigned short values.

+

+    \param [in]    value  Value to reverse

+    \return               Reversed value

+ */

+__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value)

+{

+  uint32_t result;

+

+  __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );

+  return(result);

+}

+

+

+/** \brief  Reverse byte order in signed short value

+

+    This function reverses the byte order in a signed short value with sign extension to integer.

+

+    \param [in]    value  Value to reverse

+    \return               Reversed value

+ */

+__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value)

+{

+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)

+  return (short)__builtin_bswap16(value);

+#else

+  uint32_t result;

+

+  __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );

+  return(result);

+#endif

+}

+

+

+/** \brief  Rotate Right in unsigned value (32 bit)

+

+    This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.

+

+    \param [in]    value  Value to rotate

+    \param [in]    value  Number of Bits to rotate

+    \return               Rotated value

+ */

+__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)

+{

+  return (op1 >> op2) | (op1 << (32 - op2));

+}

+

+

+/** \brief  Breakpoint

+

+    This function causes the processor to enter Debug state.

+    Debug tools can use this to investigate system state when the instruction at a particular address is reached.

+

+    \param [in]    value  is ignored by the processor.

+                   If required, a debugger can use it to store additional information about the breakpoint.

+ */

+#define __BKPT(value)                       __ASM volatile ("bkpt "#value)

+

+

+/** \brief  Reverse bit order of value

+

+    This function reverses the bit order of the given value.

+

+    \param [in]    value  Value to reverse

+    \return               Reversed value

+ */

+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)

+{

+  uint32_t result;

+

+#if       (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)

+   __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );

+#else

+  int32_t s = 4 /*sizeof(v)*/ * 8 - 1; // extra shift needed at end

+

+  result = value;                      // r will be reversed bits of v; first get LSB of v

+  for (value >>= 1; value; value >>= 1)

+  {

+    result <<= 1;

+    result |= value & 1;

+    s--;

+  }

+  result <<= s;                       // shift when v's highest bits are zero

+#endif

+  return(result);

+}

+

+

+/** \brief  Count leading zeros

+

+    This function counts the number of leading zeros of a data value.

+

+    \param [in]  value  Value to count the leading zeros

+    \return             number of leading zeros in value

+ */

+#define __CLZ             __builtin_clz

+

+

+#if       (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)

+

+/** \brief  LDR Exclusive (8 bit)

+

+    This function executes a exclusive LDR instruction for 8 bit value.

+

+    \param [in]    ptr  Pointer to data

+    \return             value of type uint8_t at (*ptr)

+ */

+__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)

+{

+    uint32_t result;

+

+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)

+   __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );

+#else

+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not

+       accepted by assembler. So has to use following less efficient pattern.

+    */

+   __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );

+#endif

+   return ((uint8_t) result);    /* Add explicit type cast here */

+}

+

+

+/** \brief  LDR Exclusive (16 bit)

+

+    This function executes a exclusive LDR instruction for 16 bit values.

+

+    \param [in]    ptr  Pointer to data

+    \return        value of type uint16_t at (*ptr)

+ */

+__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)

+{

+    uint32_t result;

+

+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)

+   __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );

+#else

+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not

+       accepted by assembler. So has to use following less efficient pattern.

+    */

+   __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );

+#endif

+   return ((uint16_t) result);    /* Add explicit type cast here */

+}

+

+

+/** \brief  LDR Exclusive (32 bit)

+

+    This function executes a exclusive LDR instruction for 32 bit values.

+

+    \param [in]    ptr  Pointer to data

+    \return        value of type uint32_t at (*ptr)

+ */

+__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)

+{

+    uint32_t result;

+

+   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );

+   return(result);

+}

+

+

+/** \brief  STR Exclusive (8 bit)

+

+    This function executes a exclusive STR instruction for 8 bit values.

+

+    \param [in]  value  Value to store

+    \param [in]    ptr  Pointer to location

+    \return          0  Function succeeded

+    \return          1  Function failed

+ */

+__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)

+{

+   uint32_t result;

+

+   __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );

+   return(result);

+}

+

+

+/** \brief  STR Exclusive (16 bit)

+

+    This function executes a exclusive STR instruction for 16 bit values.

+

+    \param [in]  value  Value to store

+    \param [in]    ptr  Pointer to location

+    \return          0  Function succeeded

+    \return          1  Function failed

+ */

+__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)

+{

+   uint32_t result;

+

+   __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );

+   return(result);

+}

+

+

+/** \brief  STR Exclusive (32 bit)

+

+    This function executes a exclusive STR instruction for 32 bit values.

+

+    \param [in]  value  Value to store

+    \param [in]    ptr  Pointer to location

+    \return          0  Function succeeded

+    \return          1  Function failed

+ */

+__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)

+{

+   uint32_t result;

+

+   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );

+   return(result);

+}

+

+

+/** \brief  Remove the exclusive lock

+

+    This function removes the exclusive lock which is created by LDREX.

+

+ */

+__attribute__((always_inline)) __STATIC_INLINE void __CLREX(void)

+{

+  __ASM volatile ("clrex" ::: "memory");

+}

+

+

+/** \brief  Signed Saturate

+

+    This function saturates a signed value.

+

+    \param [in]  value  Value to be saturated

+    \param [in]    sat  Bit position to saturate to (1..32)

+    \return             Saturated value

+ */

+#define __SSAT(ARG1,ARG2) \

+({                          \

+  uint32_t __RES, __ARG1 = (ARG1); \

+  __ASM ("ssat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \

+  __RES; \

+ })

+

+

+/** \brief  Unsigned Saturate

+

+    This function saturates an unsigned value.

+

+    \param [in]  value  Value to be saturated

+    \param [in]    sat  Bit position to saturate to (0..31)

+    \return             Saturated value

+ */

+#define __USAT(ARG1,ARG2) \

+({                          \

+  uint32_t __RES, __ARG1 = (ARG1); \

+  __ASM ("usat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \

+  __RES; \

+ })

+

+

+/** \brief  Rotate Right with Extend (32 bit)

+

+    This function moves each bit of a bitstring right by one bit.

+    The carry input is shifted in at the left end of the bitstring.

+

+    \param [in]    value  Value to rotate

+    \return               Rotated value

+ */

+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value)

+{

+  uint32_t result;

+

+  __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );

+  return(result);

+}

+

+

+/** \brief  LDRT Unprivileged (8 bit)

+

+    This function executes a Unprivileged LDRT instruction for 8 bit value.

+

+    \param [in]    ptr  Pointer to data

+    \return             value of type uint8_t at (*ptr)

+ */

+__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr)

+{

+    uint32_t result;

+

+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)

+   __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*addr) );

+#else

+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not

+       accepted by assembler. So has to use following less efficient pattern.

+    */

+   __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );

+#endif

+   return ((uint8_t) result);    /* Add explicit type cast here */

+}

+

+

+/** \brief  LDRT Unprivileged (16 bit)

+

+    This function executes a Unprivileged LDRT instruction for 16 bit values.

+

+    \param [in]    ptr  Pointer to data

+    \return        value of type uint16_t at (*ptr)

+ */

+__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr)

+{

+    uint32_t result;

+

+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)

+   __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*addr) );

+#else

+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not

+       accepted by assembler. So has to use following less efficient pattern.

+    */

+   __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );

+#endif

+   return ((uint16_t) result);    /* Add explicit type cast here */

+}

+

+

+/** \brief  LDRT Unprivileged (32 bit)

+

+    This function executes a Unprivileged LDRT instruction for 32 bit values.

+

+    \param [in]    ptr  Pointer to data

+    \return        value of type uint32_t at (*ptr)

+ */

+__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr)

+{

+    uint32_t result;

+

+   __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*addr) );

+   return(result);

+}

+

+

+/** \brief  STRT Unprivileged (8 bit)

+

+    This function executes a Unprivileged STRT instruction for 8 bit values.

+

+    \param [in]  value  Value to store

+    \param [in]    ptr  Pointer to location

+ */

+__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr)

+{

+   __ASM volatile ("strbt %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );

+}

+

+

+/** \brief  STRT Unprivileged (16 bit)

+

+    This function executes a Unprivileged STRT instruction for 16 bit values.

+

+    \param [in]  value  Value to store

+    \param [in]    ptr  Pointer to location

+ */

+__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr)

+{

+   __ASM volatile ("strht %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );

+}

+

+

+/** \brief  STRT Unprivileged (32 bit)

+

+    This function executes a Unprivileged STRT instruction for 32 bit values.

+

+    \param [in]  value  Value to store

+    \param [in]    ptr  Pointer to location

+ */

+__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr)

+{

+   __ASM volatile ("strt %1, %0" : "=Q" (*addr) : "r" (value) );

+}

+

+#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */

+

+

+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/

+/* IAR iccarm specific functions */

+#include <cmsis_iar.h>

+

+

+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/

+/* TI CCS specific functions */

+#include <cmsis_ccs.h>

+

+

+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/

+/* TASKING carm specific functions */

+/*

+ * The CMSIS functions have been implemented as intrinsics in the compiler.

+ * Please use "carm -?i" to get an up to date list of all intrinsics,

+ * Including the CMSIS ones.

+ */

+

+

+#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/

+/* Cosmic specific functions */

+#include <cmsis_csm.h>

+

+#endif

+

+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */

+

+#endif /* __CORE_CMINSTR_H */

diff --git a/ext/TARGET_LPC1768/core_cmSimd.h b/ext/TARGET_LPC1768/core_cmSimd.h
new file mode 100644
index 0000000..7b8e37f
--- /dev/null
+++ b/ext/TARGET_LPC1768/core_cmSimd.h
@@ -0,0 +1,697 @@
+/**************************************************************************//**
+ * @file     core_cmSimd.h
+ * @brief    CMSIS Cortex-M SIMD Header File
+ * @version  V4.10
+ * @date     18. March 2015
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2014 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include  /* treat file as system include file for MISRA check */
+#endif
+
+#ifndef __CORE_CMSIMD_H
+#define __CORE_CMSIMD_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+ ******************************************************************************/
+
+
+/* ###################  Compiler specific Intrinsics  ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+  Access to dedicated SIMD instructions
+  @{
+*/
+
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+#define __SADD8                           __sadd8
+#define __QADD8                           __qadd8
+#define __SHADD8                          __shadd8
+#define __UADD8                           __uadd8
+#define __UQADD8                          __uqadd8
+#define __UHADD8                          __uhadd8
+#define __SSUB8                           __ssub8
+#define __QSUB8                           __qsub8
+#define __SHSUB8                          __shsub8
+#define __USUB8                           __usub8
+#define __UQSUB8                          __uqsub8
+#define __UHSUB8                          __uhsub8
+#define __SADD16                          __sadd16
+#define __QADD16                          __qadd16
+#define __SHADD16                         __shadd16
+#define __UADD16                          __uadd16
+#define __UQADD16                         __uqadd16
+#define __UHADD16                         __uhadd16
+#define __SSUB16                          __ssub16
+#define __QSUB16                          __qsub16
+#define __SHSUB16                         __shsub16
+#define __USUB16                          __usub16
+#define __UQSUB16                         __uqsub16
+#define __UHSUB16                         __uhsub16
+#define __SASX                            __sasx
+#define __QASX                            __qasx
+#define __SHASX                           __shasx
+#define __UASX                            __uasx
+#define __UQASX                           __uqasx
+#define __UHASX                           __uhasx
+#define __SSAX                            __ssax
+#define __QSAX                            __qsax
+#define __SHSAX                           __shsax
+#define __USAX                            __usax
+#define __UQSAX                           __uqsax
+#define __UHSAX                           __uhsax
+#define __USAD8                           __usad8
+#define __USADA8                          __usada8
+#define __SSAT16                          __ssat16
+#define __USAT16                          __usat16
+#define __UXTB16                          __uxtb16
+#define __UXTAB16                         __uxtab16
+#define __SXTB16                          __sxtb16
+#define __SXTAB16                         __sxtab16
+#define __SMUAD                           __smuad
+#define __SMUADX                          __smuadx
+#define __SMLAD                           __smlad
+#define __SMLADX                          __smladx
+#define __SMLALD                          __smlald
+#define __SMLALDX                         __smlaldx
+#define __SMUSD                           __smusd
+#define __SMUSDX                          __smusdx
+#define __SMLSD                           __smlsd
+#define __SMLSDX                          __smlsdx
+#define __SMLSLD                          __smlsld
+#define __SMLSLDX                         __smlsldx
+#define __SEL                             __sel
+#define __QADD                            __qadd
+#define __QSUB                            __qsub
+
+#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
+                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
+
+#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
+                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
+
+#define __SMMLA(ARG1,ARG2,ARG3)          ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
+                                                      ((int64_t)(ARG3) << 32)      ) >> 32))
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+#define __SSAT16(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+#define __USAT16(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("usat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
+{
+  uint32_t result;
+
+  __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
+{
+  uint32_t result;
+
+  __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   // Little endian
+  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               // Big endian
+  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   // Little endian
+  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               // Big endian
+  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   // Little endian
+  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               // Big endian
+  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   // Little endian
+  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               // Big endian
+  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+#define __PKHBT(ARG1,ARG2,ARG3) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+
+#define __PKHTB(ARG1,ARG2,ARG3) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  if (ARG3 == 0) \
+    __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2)  ); \
+  else \
+    __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+ int32_t result;
+
+ __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r"  (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+#include <cmsis_iar.h>
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+#include <cmsis_ccs.h>
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+/* not yet supported */
+
+
+#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
+/* Cosmic specific functions */
+#include <cmsis_csm.h>
+
+#endif
+
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CMSIMD_H */
diff --git a/ext/TARGET_LPC1768/core_sc000.h b/ext/TARGET_LPC1768/core_sc000.h
new file mode 100644
index 0000000..44cb027
--- /dev/null
+++ b/ext/TARGET_LPC1768/core_sc000.h
@@ -0,0 +1,864 @@
+/**************************************************************************//**
+ * @file     core_sc000.h
+ * @brief    CMSIS SC000 Core Peripheral Access Layer Header File
+ * @version  V4.10
+ * @date     18. March 2015
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include  /* treat file as system include file for MISRA check */
+#endif
+
+#ifndef __CORE_SC000_H_GENERIC
+#define __CORE_SC000_H_GENERIC
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/** \ingroup SC000
+  @{
+ */
+
+/*  CMSIS SC000 definitions */
+#define __SC000_CMSIS_VERSION_MAIN  (0x04)                                   /*!< [31:16] CMSIS HAL main version */
+#define __SC000_CMSIS_VERSION_SUB   (0x00)                                   /*!< [15:0]  CMSIS HAL sub version  */
+#define __SC000_CMSIS_VERSION       ((__SC000_CMSIS_VERSION_MAIN << 16) | \
+                                      __SC000_CMSIS_VERSION_SUB          )   /*!< CMSIS HAL version number       */
+
+#define __CORTEX_SC                 (000)                                       /*!< Cortex secure core             */
+
+
+#if   defined ( __CC_ARM )
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
+  #define __STATIC_INLINE  static __inline
+
+#elif defined ( __GNUC__ )
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __ICCARM__ )
+  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TMS470__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TASKING__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __CSMC__ )
+  #define __packed
+  #define __ASM            _asm                                      /*!< asm keyword for COSMIC Compiler      */
+  #define __INLINE         inline                                    /*use -pc99 on compile line !< inline keyword for COSMIC Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TMS470__ )
+  #if defined __TI__VFP_SUPPORT____
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )		/* Cosmic */
+  #if ( __CSMC__ & 0x400)		// FPU present for parser
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+#endif
+
+#include <stdint.h>                      /* standard types definitions                      */
+#include <core_cmInstr.h>                /* Core Instruction Access                         */
+#include <core_cmFunc.h>                 /* Core Function Access                            */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_SC000_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_SC000_H_DEPENDANT
+#define __CORE_SC000_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __SC000_REV
+    #define __SC000_REV             0x0000
+    #warning "__SC000_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          2
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions                */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
+
+/*@} end of group SC000 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core MPU Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+    \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_CORE  Status and Control Registers
+    \brief  Core Register type definitions.
+  @{
+ */
+
+/** \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved                           */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31                                             /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30                                             /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29                                             /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28                                             /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+
+/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0                                             /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
+    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved                           */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31                                             /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30                                             /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29                                             /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28                                             /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos                         24                                             /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos                        0                                             /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/** \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:1;               /*!< bit:      0  Reserved                           */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos                   1                                             /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+    \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IO uint32_t ISER[1];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
+       uint32_t RESERVED0[31];
+  __IO uint32_t ICER[1];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register          */
+       uint32_t RSERVED1[31];
+  __IO uint32_t ISPR[1];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register           */
+       uint32_t RESERVED2[31];
+  __IO uint32_t ICPR[1];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register         */
+       uint32_t RESERVED3[31];
+       uint32_t RESERVED4[64];
+  __IO uint32_t IP[8];                   /*!< Offset: 0x300 (R/W)  Interrupt Priority Register              */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCB     System Control Block (SCB)
+    \brief      Type definitions for the System Control Block Registers
+  @{
+ */
+
+/** \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
+  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
+  __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
+  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
+  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
+  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
+       uint32_t RESERVED0[1];
+  __IO uint32_t SHP[2];                  /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED   */
+  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
+       uint32_t RESERVED1[154];
+  __IO uint32_t SFCR;                    /*!< Offset: 0x290 (R/W)  Security Features Control Register                    */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+    \brief      Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/** \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+       uint32_t RESERVED0[2];
+  __IO uint32_t ACTLR;                   /*!< Offset: 0x008 (R/W)  Auxiliary Control Register      */
+} SCnSCB_Type;
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISMCYCINT_Pos         0                                          /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+    \brief      Type definitions for the System Timer Registers.
+  @{
+ */
+
+/** \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
+  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
+  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+    \brief      Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/** \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */
+  __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */
+  __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */
+  __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */
+  __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos                   8                                             /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0xFFFFFFUL << MPU_RBAR_ADDR_Pos)              /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+    \brief      SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR)
+                are only accessible over DAP and not via processor. Therefore
+                they are not covered by the Cortex-M0 header file.
+  @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_core_base     Core Definitions
+    \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of SC000 Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address              */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                 */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
+
+#if (__MPU_PRESENT == 1)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+    \brief      Functions that manage interrupts and exceptions via the NVIC.
+    @{
+ */
+
+/* Interrupt Priorities are WORD accessible only under ARMv6M                   */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
+#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
+#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
+
+
+/** \brief  Enable External Interrupt
+
+    The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/** \brief  Disable External Interrupt
+
+    The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/** \brief  Get Pending Interrupt
+
+    The function reads the pending register in the NVIC and returns the pending bit
+    for the specified interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not pending.
+    \return             1  Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  return((uint32_t)(((NVIC->ISPR[0] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+}
+
+
+/** \brief  Set Pending Interrupt
+
+    The function sets the pending bit of an external interrupt.
+
+    \param [in]      IRQn  Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/** \brief  Clear Pending Interrupt
+
+    The function clears the pending bit of an external interrupt.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/** \brief  Set Interrupt Priority
+
+    The function sets the priority of an interrupt.
+
+    \note The priority cannot be set for every core interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+    \param [in]  priority  Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if((int32_t)(IRQn) < 0) {
+    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+  else {
+    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+}
+
+
+/** \brief  Get Interrupt Priority
+
+    The function reads the priority of an interrupt. The interrupt
+    number can be positive to specify an external (device specific)
+    interrupt, or negative to specify an internal (core) interrupt.
+
+
+    \param [in]   IRQn  Interrupt number.
+    \return             Interrupt Priority. Value is aligned automatically to the implemented
+                        priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if((int32_t)(IRQn) < 0) {
+    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
+  }
+  else {
+    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/** \brief  System Reset
+
+    The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+  __DSB();                                                     /* Ensure all outstanding memory accesses included
+                                                                  buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                 SCB_AIRCR_SYSRESETREQ_Msk);
+  __DSB();                                                     /* Ensure completion of memory access */
+  while(1) { __NOP(); }                                        /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+    \brief      Functions that configure the System.
+  @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief  System Tick Configuration
+
+    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+    Counter is in free running mode to generate periodic interrupts.
+
+    \param [in]  ticks  Number of ticks between two interrupts.
+
+    \return          0  Function succeeded.
+    \return          1  Function failed.
+
+    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+    must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {return (1UL);}      /* Reload value impossible */
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_SC000_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/ext/TARGET_LPC1768/core_sc300.h b/ext/TARGET_LPC1768/core_sc300.h
new file mode 100644
index 0000000..7e40672
--- /dev/null
+++ b/ext/TARGET_LPC1768/core_sc300.h
@@ -0,0 +1,1675 @@
+/**************************************************************************//**
+ * @file     core_sc300.h
+ * @brief    CMSIS SC300 Core Peripheral Access Layer Header File
+ * @version  V4.10
+ * @date     18. March 2015
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include  /* treat file as system include file for MISRA check */
+#endif
+
+#ifndef __CORE_SC300_H_GENERIC
+#define __CORE_SC300_H_GENERIC
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/** \ingroup SC3000
+  @{
+ */
+
+/*  CMSIS SC300 definitions */
+#define __SC300_CMSIS_VERSION_MAIN  (0x04)                                   /*!< [31:16] CMSIS HAL main version */
+#define __SC300_CMSIS_VERSION_SUB   (0x00)                                   /*!< [15:0]  CMSIS HAL sub version  */
+#define __SC300_CMSIS_VERSION       ((__SC300_CMSIS_VERSION_MAIN << 16) | \
+                                      __SC300_CMSIS_VERSION_SUB          )   /*!< CMSIS HAL version number       */
+
+#define __CORTEX_SC                 (300)                                     /*!< Cortex secure core             */
+
+
+#if   defined ( __CC_ARM )
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
+  #define __STATIC_INLINE  static __inline
+
+#elif defined ( __GNUC__ )
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __ICCARM__ )
+  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TMS470__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TASKING__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __CSMC__ )
+  #define __packed
+  #define __ASM            _asm                                      /*!< asm keyword for COSMIC Compiler      */
+  #define __INLINE         inline                                    /*use -pc99 on compile line !< inline keyword for COSMIC Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TMS470__ )
+  #if defined __TI__VFP_SUPPORT____
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )		/* Cosmic */
+  #if ( __CSMC__ & 0x400)		// FPU present for parser
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+#endif
+
+#include <stdint.h>                      /* standard types definitions                      */
+#include <core_cmInstr.h>                /* Core Instruction Access                         */
+#include <core_cmFunc.h>                 /* Core Function Access                            */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_SC300_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_SC300_H_DEPENDANT
+#define __CORE_SC300_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __SC300_REV
+    #define __SC300_REV               0x0000
+    #warning "__SC300_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          4
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions                */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
+
+/*@} end of group SC300 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+    \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_CORE  Status and Control Registers
+    \brief  Core Register type definitions.
+  @{
+ */
+
+/** \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31                                             /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30                                             /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29                                             /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28                                             /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+#define APSR_Q_Pos                         27                                             /*!< APSR: Q Position */
+#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
+
+
+/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0                                             /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
+    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31                                             /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30                                             /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29                                             /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28                                             /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos                         27                                             /*!< xPSR: Q Position */
+#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
+
+#define xPSR_IT_Pos                        25                                             /*!< xPSR: IT Position */
+#define xPSR_IT_Msk                        (3UL << xPSR_IT_Pos)                           /*!< xPSR: IT Mask */
+
+#define xPSR_T_Pos                         24                                             /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos                        0                                             /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/** \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos                   1                                             /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0                                             /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+    \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IO uint32_t ISER[8];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
+       uint32_t RESERVED0[24];
+  __IO uint32_t ICER[8];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register         */
+       uint32_t RSERVED1[24];
+  __IO uint32_t ISPR[8];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register          */
+       uint32_t RESERVED2[24];
+  __IO uint32_t ICPR[8];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register        */
+       uint32_t RESERVED3[24];
+  __IO uint32_t IABR[8];                 /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register           */
+       uint32_t RESERVED4[56];
+  __IO uint8_t  IP[240];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+       uint32_t RESERVED5[644];
+  __O  uint32_t STIR;                    /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register     */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0                                          /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCB     System Control Block (SCB)
+    \brief      Type definitions for the System Control Block Registers
+  @{
+ */
+
+/** \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
+  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
+  __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
+  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
+  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
+  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
+  __IO uint8_t  SHP[12];                 /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
+  __IO uint32_t CFSR;                    /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register                    */
+  __IO uint32_t HFSR;                    /*!< Offset: 0x02C (R/W)  HardFault Status Register                             */
+  __IO uint32_t DFSR;                    /*!< Offset: 0x030 (R/W)  Debug Fault Status Register                           */
+  __IO uint32_t MMFAR;                   /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register                      */
+  __IO uint32_t BFAR;                    /*!< Offset: 0x038 (R/W)  BusFault Address Register                             */
+  __IO uint32_t AFSR;                    /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register                       */
+  __I  uint32_t PFR[2];                  /*!< Offset: 0x040 (R/ )  Processor Feature Register                            */
+  __I  uint32_t DFR;                     /*!< Offset: 0x048 (R/ )  Debug Feature Register                                */
+  __I  uint32_t ADR;                     /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register                            */
+  __I  uint32_t MMFR[4];                 /*!< Offset: 0x050 (R/ )  Memory Model Feature Register                         */
+  __I  uint32_t ISAR[5];                 /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register                   */
+       uint32_t RESERVED0[5];
+  __IO uint32_t CPACR;                   /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register                   */
+       uint32_t RESERVED1[129];
+  __IO uint32_t SFCR;                    /*!< Offset: 0x290 (R/W)  Security Features Control Register                    */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11                                             /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLBASE_Pos               29                                             /*!< SCB VTOR: TBLBASE Position */
+#define SCB_VTOR_TBLBASE_Msk               (1UL << SCB_VTOR_TBLBASE_Pos)                  /*!< SCB VTOR: TBLBASE Mask */
+
+#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8                                             /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos             0                                             /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8                                             /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4                                             /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1                                             /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos          0                                             /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos          18                                             /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17                                             /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16                                             /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14                                             /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13                                             /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12                                             /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11                                             /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10                                             /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8                                             /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7                                             /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3                                             /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1                                             /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0                                             /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Registers Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16                                             /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8                                             /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0                                             /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* SCB Hard Fault Status Registers Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31                                             /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30                                             /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1                                             /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4                                             /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3                                             /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2                                             /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1                                             /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0                                             /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+    \brief      Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/** \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+       uint32_t RESERVED0[1];
+  __I  uint32_t ICTR;                    /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register      */
+       uint32_t RESERVED1[1];
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0                                          /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+    \brief      Type definitions for the System Timer Registers.
+  @{
+ */
+
+/** \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
+  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
+  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+    \brief      Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/** \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+  __O  union
+  {
+    __O  uint8_t    u8;                  /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit                   */
+    __O  uint16_t   u16;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit                  */
+    __O  uint32_t   u32;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit                  */
+  }  PORT [32];                          /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers               */
+       uint32_t RESERVED0[864];
+  __IO uint32_t TER;                     /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register                 */
+       uint32_t RESERVED1[15];
+  __IO uint32_t TPR;                     /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register              */
+       uint32_t RESERVED2[15];
+  __IO uint32_t TCR;                     /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register                */
+       uint32_t RESERVED3[29];
+  __O  uint32_t IWR;                     /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register            */
+  __I  uint32_t IRR;                     /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register             */
+  __IO uint32_t IMCR;                    /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register     */
+       uint32_t RESERVED4[43];
+  __O  uint32_t LAR;                     /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register                  */
+  __I  uint32_t LSR;                     /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register                  */
+       uint32_t RESERVED5[6];
+  __I  uint32_t PID4;                    /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+  __I  uint32_t PID5;                    /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+  __I  uint32_t PID6;                    /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+  __I  uint32_t PID7;                    /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+  __I  uint32_t PID0;                    /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+  __I  uint32_t PID1;                    /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+  __I  uint32_t PID2;                    /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+  __I  uint32_t PID3;                    /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+  __I  uint32_t CID0;                    /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+  __I  uint32_t CID1;                    /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+  __I  uint32_t CID2;                    /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+  __I  uint32_t CID3;                    /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0                                             /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)            /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23                                             /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos             16                                             /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10                                             /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos              8                                             /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4                                             /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3                                             /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2                                             /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1                                             /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0                                             /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos                0                                             /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos                0                                             /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos            0                                             /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2                                             /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1                                             /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0                                             /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+    \brief      Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/** \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  Control Register                          */
+  __IO uint32_t CYCCNT;                  /*!< Offset: 0x004 (R/W)  Cycle Count Register                      */
+  __IO uint32_t CPICNT;                  /*!< Offset: 0x008 (R/W)  CPI Count Register                        */
+  __IO uint32_t EXCCNT;                  /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register         */
+  __IO uint32_t SLEEPCNT;                /*!< Offset: 0x010 (R/W)  Sleep Count Register                      */
+  __IO uint32_t LSUCNT;                  /*!< Offset: 0x014 (R/W)  LSU Count Register                        */
+  __IO uint32_t FOLDCNT;                 /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register         */
+  __I  uint32_t PCSR;                    /*!< Offset: 0x01C (R/ )  Program Counter Sample Register           */
+  __IO uint32_t COMP0;                   /*!< Offset: 0x020 (R/W)  Comparator Register 0                     */
+  __IO uint32_t MASK0;                   /*!< Offset: 0x024 (R/W)  Mask Register 0                           */
+  __IO uint32_t FUNCTION0;               /*!< Offset: 0x028 (R/W)  Function Register 0                       */
+       uint32_t RESERVED0[1];
+  __IO uint32_t COMP1;                   /*!< Offset: 0x030 (R/W)  Comparator Register 1                     */
+  __IO uint32_t MASK1;                   /*!< Offset: 0x034 (R/W)  Mask Register 1                           */
+  __IO uint32_t FUNCTION1;               /*!< Offset: 0x038 (R/W)  Function Register 1                       */
+       uint32_t RESERVED1[1];
+  __IO uint32_t COMP2;                   /*!< Offset: 0x040 (R/W)  Comparator Register 2                     */
+  __IO uint32_t MASK2;                   /*!< Offset: 0x044 (R/W)  Mask Register 2                           */
+  __IO uint32_t FUNCTION2;               /*!< Offset: 0x048 (R/W)  Function Register 2                       */
+       uint32_t RESERVED2[1];
+  __IO uint32_t COMP3;                   /*!< Offset: 0x050 (R/W)  Comparator Register 3                     */
+  __IO uint32_t MASK3;                   /*!< Offset: 0x054 (R/W)  Mask Register 3                           */
+  __IO uint32_t FUNCTION3;               /*!< Offset: 0x058 (R/W)  Function Register 3                       */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28                                          /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27                                          /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26                                          /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25                                          /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24                                          /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22                                          /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21                                          /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20                                          /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19                                          /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18                                          /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17                                          /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16                                          /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12                                          /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10                                          /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9                                          /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5                                          /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1                                          /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0                                          /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0                                          /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0                                          /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0                                          /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0                                          /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0                                          /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos                   0                                          /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos           24                                          /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos        16                                          /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos        12                                          /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10                                          /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos            9                                          /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos         8                                          /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos           7                                          /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos          5                                          /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos           0                                          /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+    \brief      Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/** \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IO uint32_t SSPSR;                   /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register     */
+  __IO uint32_t CSPSR;                   /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+       uint32_t RESERVED0[2];
+  __IO uint32_t ACPR;                    /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+       uint32_t RESERVED1[55];
+  __IO uint32_t SPPR;                    /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+       uint32_t RESERVED2[131];
+  __I  uint32_t FFSR;                    /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IO uint32_t FFCR;                    /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __I  uint32_t FSCR;                    /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+       uint32_t RESERVED3[759];
+  __I  uint32_t TRIGGER;                 /*!< Offset: 0xEE8 (R/ )  TRIGGER */
+  __I  uint32_t FIFO0;                   /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+  __I  uint32_t ITATBCTR2;               /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+       uint32_t RESERVED4[1];
+  __I  uint32_t ITATBCTR0;               /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+  __I  uint32_t FIFO1;                   /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+  __IO uint32_t ITCTRL;                  /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+       uint32_t RESERVED5[39];
+  __IO uint32_t CLAIMSET;                /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IO uint32_t CLAIMCLR;                /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+       uint32_t RESERVED7[8];
+  __I  uint32_t DEVID;                   /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+  __I  uint32_t DEVTYPE;                 /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0                                          /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0                                          /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3                                          /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2                                          /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1                                          /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0                                          /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8                                          /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1                                          /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0                                          /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos        27                                          /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos        24                                          /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos                 16                                          /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos                  8                                          /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos                  0                                          /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos           0                                          /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/)    /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos        27                                          /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos        24                                          /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos                 16                                          /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos                  8                                          /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos                  0                                          /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos           0                                          /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/)    /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0                                          /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11                                          /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10                                          /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9                                          /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos              6                                          /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos             5                                          /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0                                          /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_MajorType_Pos           4                                          /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+#define TPI_DEVTYPE_SubType_Pos             0                                          /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+    \brief      Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/** \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */
+  __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */
+  __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */
+  __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */
+  __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */
+  __IO uint32_t RBAR_A1;                 /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register       */
+  __IO uint32_t RASR_A1;                 /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
+  __IO uint32_t RBAR_A2;                 /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register       */
+  __IO uint32_t RASR_A2;                 /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
+  __IO uint32_t RBAR_A3;                 /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register       */
+  __IO uint32_t RASR_A3;                 /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos                   5                                             /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+    \brief      Type definitions for the Core Debug Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IO uint32_t DHCSR;                   /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register    */
+  __O  uint32_t DCRSR;                   /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register        */
+  __IO uint32_t DCRDR;                   /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register            */
+  __IO uint32_t DEMCR;                   /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16                                             /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25                                             /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24                                             /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19                                             /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18                                             /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17                                             /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16                                             /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5                                             /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3                                             /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2                                             /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1                                             /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0                                             /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register */
+#define CoreDebug_DCRSR_REGWnR_Pos         16                                             /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0                                             /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_TRCENA_Pos         24                                             /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19                                             /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18                                             /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17                                             /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16                                             /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10                                             /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9                                             /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8                                             /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7                                             /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6                                             /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5                                             /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4                                             /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0                                             /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_core_base     Core Definitions
+    \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Cortex-M3 Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address  */
+#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address                   */
+#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address                   */
+#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address                   */
+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address            */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address               */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                  */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address  */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
+#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct           */
+#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct           */
+#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct           */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct    */
+
+#if (__MPU_PRESENT == 1)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+    \brief      Functions that manage interrupts and exceptions via the NVIC.
+    @{
+ */
+
+/** \brief  Set Priority Grouping
+
+  The function sets the priority grouping field using the required unlock sequence.
+  The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+  Only values from 0..7 are used.
+  In case of a conflict between priority grouping and available
+  priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+
+    \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
+
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk));             /* clear bits to change               */
+  reg_value  =  (reg_value                                   |
+                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << 8)                       );              /* Insert write key and priorty group */
+  SCB->AIRCR =  reg_value;
+}
+
+
+/** \brief  Get Priority Grouping
+
+  The function reads the priority grouping field from the NVIC Interrupt Controller.
+
+    \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
+{
+  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/** \brief  Enable External Interrupt
+
+    The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/** \brief  Disable External Interrupt
+
+    The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/** \brief  Get Pending Interrupt
+
+    The function reads the pending register in the NVIC and returns the pending bit
+    for the specified interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not pending.
+    \return             1  Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+}
+
+
+/** \brief  Set Pending Interrupt
+
+    The function sets the pending bit of an external interrupt.
+
+    \param [in]      IRQn  Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/** \brief  Clear Pending Interrupt
+
+    The function clears the pending bit of an external interrupt.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/** \brief  Get Active Interrupt
+
+    The function reads the active register in NVIC and returns the active bit.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not active.
+    \return             1  Interrupt status is active.
+ */
+__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+{
+  return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+}
+
+
+/** \brief  Set Interrupt Priority
+
+    The function sets the priority of an interrupt.
+
+    \note The priority cannot be set for every core interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+    \param [in]  priority  Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if((int32_t)IRQn < 0) {
+    SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+  else {
+    NVIC->IP[((uint32_t)(int32_t)IRQn)]               = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+}
+
+
+/** \brief  Get Interrupt Priority
+
+    The function reads the priority of an interrupt. The interrupt
+    number can be positive to specify an external (device specific)
+    interrupt, or negative to specify an internal (core) interrupt.
+
+
+    \param [in]   IRQn  Interrupt number.
+    \return             Interrupt Priority. Value is aligned automatically to the implemented
+                        priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if((int32_t)IRQn < 0) {
+    return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8 - __NVIC_PRIO_BITS)));
+  }
+  else {
+    return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)]               >> (8 - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/** \brief  Encode Priority
+
+    The function encodes the priority for an interrupt with the given priority group,
+    preemptive priority value, and subpriority value.
+    In case of a conflict between priority grouping and available
+    priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+
+    \param [in]     PriorityGroup  Used priority group.
+    \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+    \param [in]       SubPriority  Subpriority value (starting from 0).
+    \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/** \brief  Decode Priority
+
+    The function decodes an interrupt priority value with a given priority group to
+    preemptive priority value and subpriority value.
+    In case of a conflict between priority grouping and available
+    priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+
+    \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+    \param [in]     PriorityGroup  Used priority group.
+    \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+    \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+/** \brief  System Reset
+
+    The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
+                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
+  __DSB();                                                          /* Ensure completion of memory access */
+  while(1) { __NOP(); }                                             /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+    \brief      Functions that configure the System.
+  @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief  System Tick Configuration
+
+    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+    Counter is in free running mode to generate periodic interrupts.
+
+    \param [in]  ticks  Number of ticks between two interrupts.
+
+    \return          0  Function succeeded.
+    \return          1  Function failed.
+
+    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+    must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); }    /* Reload value impossible */
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_core_DebugFunctions ITM Functions
+    \brief   Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                    /*!< External variable to receive characters.                         */
+#define                 ITM_RXBUFFER_EMPTY    0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/** \brief  ITM Send Character
+
+    The function transmits a character via the ITM channel 0, and
+    \li Just returns when no debugger is connected that has booked the output.
+    \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+
+    \param [in]     ch  Character to transmit.
+
+    \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
+      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */
+  {
+    while (ITM->PORT[0].u32 == 0UL) { __NOP(); }
+    ITM->PORT[0].u8 = (uint8_t)ch;
+  }
+  return (ch);
+}
+
+
+/** \brief  ITM Receive Character
+
+    The function inputs a character via the external variable \ref ITM_RxBuffer.
+
+    \return             Received character.
+    \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
+  int32_t ch = -1;                           /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+
+  return (ch);
+}
+
+
+/** \brief  ITM Check Character
+
+    The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+
+    \return          0  No character available.
+    \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void) {
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
+    return (0);                                 /* no character available */
+  } else {
+    return (1);                                 /*    character available */
+  }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_SC300_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/ext/TARGET_LPC1768/system_LPC17xx.h b/ext/TARGET_LPC1768/system_LPC17xx.h
new file mode 100644
index 0000000..1f7a47d
--- /dev/null
+++ b/ext/TARGET_LPC1768/system_LPC17xx.h
@@ -0,0 +1,60 @@
+/******************************************************************************

+ * @file:    system_LPC17xx.h

+ * @purpose: CMSIS Cortex-M3 Device Peripheral Access Layer Header File

+ *           for the NXP LPC17xx Device Series 

+ * @version: V1.02

+ * @date:    27. July 2009

+ *----------------------------------------------------------------------------

+ *

+ * Copyright (C) 2009 ARM Limited. All rights reserved.

+ *

+ * ARM Limited (ARM) is supplying this software for use with Cortex-M3 

+ * processor based microcontrollers.  This file can be freely distributed 

+ * within development tools that are supporting such ARM based processors. 

+ *

+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED

+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF

+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.

+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR

+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.

+ *

+ ******************************************************************************/

+

+

+#ifndef __SYSTEM_LPC17xx_H

+#define __SYSTEM_LPC17xx_H

+

+#ifdef __cplusplus

+ extern "C" {

+#endif 

+

+extern uint32_t SystemCoreClock;     /*!< System Clock Frequency (Core Clock)  */

+

+

+/**

+ * Initialize the system

+ *

+ * @param  none

+ * @return none

+ *

+ * @brief  Setup the microcontroller system.

+ *         Initialize the System and update the SystemCoreClock variable.

+ */

+extern void SystemInit (void);

+

+/**

+ * Update SystemCoreClock variable

+ *

+ * @param  none

+ * @return none

+ *

+ * @brief  Updates the SystemCoreClock with current core Clock 

+ *         retrieved from cpu registers.

+ */

+extern void SystemCoreClockUpdate (void);

+

+#ifdef __cplusplus

+}

+#endif

+

+#endif /* __SYSTEM_LPC17xx_H */

diff --git a/ext/Ticker.h b/ext/Ticker.h
new file mode 100644
index 0000000..16c2469
--- /dev/null
+++ b/ext/Ticker.h
@@ -0,0 +1,127 @@
+/* mbed Microcontroller Library

+ * Copyright (c) 2006-2013 ARM Limited

+ *

+ * Licensed under the Apache License, Version 2.0 (the "License");

+ * you may not use this file except in compliance with the License.

+ * You may obtain a copy of the License at

+ *

+ *     http://www.apache.org/licenses/LICENSE-2.0

+ *

+ * Unless required by applicable law or agreed to in writing, software

+ * distributed under the License is distributed on an "AS IS" BASIS,

+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

+ * See the License for the specific language governing permissions and

+ * limitations under the License.

+ */

+#ifndef MBED_TICKER_H

+#define MBED_TICKER_H

+

+#include "TimerEvent.h"

+#include "FunctionPointer.h"

+

+namespace mbed {

+

+/** A Ticker is used to call a function at a recurring interval

+ *

+ *  You can use as many seperate Ticker objects as you require.

+ *

+ * Example:

+ * @code

+ * // Toggle the blinking led after 5 seconds

+ *

+ * #include "mbed.h"

+ *

+ * Ticker timer;

+ * DigitalOut led1(LED1);

+ * DigitalOut led2(LED2);

+ *

+ * int flip = 0;

+ *

+ * void attime() {

+ *     flip = !flip;

+ * }

+ *

+ * int main() {

+ *     timer.attach(&attime, 5);

+ *     while(1) {

+ *         if(flip == 0) {

+ *             led1 = !led1;

+ *         } else {

+ *             led2 = !led2;

+ *         }

+ *         wait(0.2);

+ *     }

+ * }

+ * @endcode

+ */

+class Ticker : public TimerEvent {

+

+public:

+    Ticker() : TimerEvent() {

+    }

+

+    Ticker(const ticker_data_t *data) : TimerEvent(data) {

+    }

+

+    /** Attach a function to be called by the Ticker, specifiying the interval in seconds

+     *

+     *  @param fptr pointer to the function to be called

+     *  @param t the time between calls in seconds

+     */

+    void attach(void (*fptr)(void), float t) {

+        attach_us(fptr, t * 1000000.0f);

+    }

+

+    /** Attach a member function to be called by the Ticker, specifiying the interval in seconds

+     *

+     *  @param tptr pointer to the object to call the member function on

+     *  @param mptr pointer to the member function to be called

+     *  @param t the time between calls in seconds

+     */

+    template<typename T>

+    void attach(T* tptr, void (T::*mptr)(void), float t) {

+        attach_us(tptr, mptr, t * 1000000.0f);

+    }

+

+    /** Attach a function to be called by the Ticker, specifiying the interval in micro-seconds

+     *

+     *  @param fptr pointer to the function to be called

+     *  @param t the time between calls in micro-seconds

+     */

+    void attach_us(void (*fptr)(void), timestamp_t t) {

+        _function.attach(fptr);

+        setup(t);

+    }

+

+    /** Attach a member function to be called by the Ticker, specifiying the interval in micro-seconds

+     *

+     *  @param tptr pointer to the object to call the member function on

+     *  @param mptr pointer to the member function to be called

+     *  @param t the time between calls in micro-seconds

+     */

+    template<typename T>

+    void attach_us(T* tptr, void (T::*mptr)(void), timestamp_t t) {

+        _function.attach(tptr, mptr);

+        setup(t);

+    }

+

+    virtual ~Ticker() {

+        detach();

+    }

+

+    /** Detach the function

+     */

+    void detach();

+

+protected:

+    void setup(timestamp_t t);

+    virtual void handler();

+

+protected:

+    timestamp_t     _delay;     /**< Time delay (in microseconds) for re-setting the multi-shot callback. */

+    FunctionPointer _function;  /**< Callback. */

+};

+

+} // namespace mbed

+

+#endif

diff --git a/ext/Timeout.h b/ext/Timeout.h
new file mode 100644
index 0000000..6937341
--- /dev/null
+++ b/ext/Timeout.h
@@ -0,0 +1,59 @@
+/* mbed Microcontroller Library

+ * Copyright (c) 2006-2013 ARM Limited

+ *

+ * Licensed under the Apache License, Version 2.0 (the "License");

+ * you may not use this file except in compliance with the License.

+ * You may obtain a copy of the License at

+ *

+ *     http://www.apache.org/licenses/LICENSE-2.0

+ *

+ * Unless required by applicable law or agreed to in writing, software

+ * distributed under the License is distributed on an "AS IS" BASIS,

+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

+ * See the License for the specific language governing permissions and

+ * limitations under the License.

+ */

+#ifndef MBED_TIMEOUT_H

+#define MBED_TIMEOUT_H

+

+#include "Ticker.h"

+

+namespace mbed {

+

+/** A Timeout is used to call a function at a point in the future

+ *

+ * You can use as many seperate Timeout objects as you require.

+ *

+ * Example:

+ * @code

+ * // Blink until timeout.

+ *

+ * #include "mbed.h"

+ *

+ * Timeout timeout;

+ * DigitalOut led(LED1);

+ *

+ * int on = 1;

+ *

+ * void attimeout() {

+ *     on = 0;

+ * }

+ *

+ * int main() {

+ *     timeout.attach(&attimeout, 5);

+ *     while(on) {

+ *         led = !led;

+ *         wait(0.2);

+ *     }

+ * }

+ * @endcode

+ */

+class Timeout : public Ticker {

+

+protected:

+    virtual void handler();

+};

+

+} // namespace mbed

+

+#endif

diff --git a/ext/Timer.h b/ext/Timer.h
new file mode 100644
index 0000000..167ac88
--- /dev/null
+++ b/ext/Timer.h
@@ -0,0 +1,91 @@
+/* mbed Microcontroller Library

+ * Copyright (c) 2006-2013 ARM Limited

+ *

+ * Licensed under the Apache License, Version 2.0 (the "License");

+ * you may not use this file except in compliance with the License.

+ * You may obtain a copy of the License at

+ *

+ *     http://www.apache.org/licenses/LICENSE-2.0

+ *

+ * Unless required by applicable law or agreed to in writing, software

+ * distributed under the License is distributed on an "AS IS" BASIS,

+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

+ * See the License for the specific language governing permissions and

+ * limitations under the License.

+ */

+#ifndef MBED_TIMER_H

+#define MBED_TIMER_H

+

+#include "platform.h"

+#include "ticker_api.h"

+

+namespace mbed {

+

+/** A general purpose timer

+ *

+ * Example:

+ * @code

+ * // Count the time to toggle a LED

+ *

+ * #include "mbed.h"

+ *

+ * Timer timer;

+ * DigitalOut led(LED1);

+ * int begin, end;

+ *

+ * int main() {

+ *     timer.start();

+ *     begin = timer.read_us();

+ *     led = !led;

+ *     end = timer.read_us();

+ *     printf("Toggle the led takes %d us", end - begin);

+ * }

+ * @endcode

+ */

+class Timer {

+

+public:

+    Timer();

+    Timer(const ticker_data_t *data);

+

+    /** Start the timer

+     */

+    void start();

+

+    /** Stop the timer

+     */

+    void stop();

+

+    /** Reset the timer to 0.

+     *

+     * If it was already counting, it will continue

+     */

+    void reset();

+

+    /** Get the time passed in seconds

+     */

+    float read();

+

+    /** Get the time passed in mili-seconds

+     */

+    int read_ms();

+

+    /** Get the time passed in micro-seconds

+     */

+    int read_us();

+

+#ifdef MBED_OPERATORS

+    operator float();

+#endif

+

+protected:

+    int slicetime();

+    int _running;          // whether the timer is running

+    unsigned int _start;   // the start time of the latest slice

+    int _time;             // any accumulated time from previous slices

+    const ticker_data_t *_ticker_data;

+};

+

+} // namespace mbed

+

+#endif

diff --git a/ext/TimerEvent.h b/ext/TimerEvent.h
new file mode 100644
index 0000000..9dfb0ae
--- /dev/null
+++ b/ext/TimerEvent.h
@@ -0,0 +1,56 @@
+/* mbed Microcontroller Library

+ * Copyright (c) 2006-2013 ARM Limited

+ *

+ * Licensed under the Apache License, Version 2.0 (the "License");

+ * you may not use this file except in compliance with the License.

+ * You may obtain a copy of the License at

+ *

+ *     http://www.apache.org/licenses/LICENSE-2.0

+ *

+ * Unless required by applicable law or agreed to in writing, software

+ * distributed under the License is distributed on an "AS IS" BASIS,

+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

+ * See the License for the specific language governing permissions and

+ * limitations under the License.

+ */

+#ifndef MBED_TIMEREVENT_H

+#define MBED_TIMEREVENT_H

+

+#include "ticker_api.h"

+#include "us_ticker_api.h"

+

+namespace mbed {

+

+/** Base abstraction for timer interrupts

+*/

+class TimerEvent {

+public:

+    TimerEvent();

+    TimerEvent(const ticker_data_t *data);

+

+    /** The handler registered with the underlying timer interrupt

+     */

+    static void irq(uint32_t id);

+

+    /** Destruction removes it...

+     */

+    virtual ~TimerEvent();

+

+protected:

+    // The handler called to service the timer event of the derived class

+    virtual void handler() = 0;

+

+    // insert in to linked list

+    void insert(timestamp_t timestamp);

+

+    // remove from linked list, if in it

+    void remove();

+

+    ticker_event_t event;

+

+    const ticker_data_t *_ticker_data;

+};

+

+} // namespace mbed

+

+#endif

diff --git a/ext/Transaction.h b/ext/Transaction.h
new file mode 100644
index 0000000..92852e2
--- /dev/null
+++ b/ext/Transaction.h
@@ -0,0 +1,73 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_TRANSACTION_H
+#define MBED_TRANSACTION_H
+
+#include "platform.h"
+#include "FunctionPointer.h"
+
+namespace mbed {
+
+/** Transaction structure
+ */
+typedef struct {
+    void *tx_buffer;           /**< Tx buffer */
+    size_t tx_length;          /**< Length of Tx buffer*/
+    void *rx_buffer;           /**< Rx buffer */
+    size_t rx_length;          /**< Length of Rx buffer */
+    uint32_t event;            /**< Event for a transaction */
+    event_callback_t callback; /**< User's callback */
+    uint8_t width;             /**< Buffer's word width (8, 16, 32, 64) */
+} transaction_t;
+
+/** Transaction class defines a transaction.
+ */
+template<typename Class>
+class Transaction {
+public:
+    Transaction(Class *tpointer, const transaction_t& transaction) : _obj(tpointer), _data(transaction) {
+    }
+
+    Transaction() : _obj(), _data() {
+    }
+
+    ~Transaction() {
+    }
+
+    /** Get object's instance for the transaction
+     *
+     * @return The object which was stored
+     */
+    Class* get_object() {
+        return _obj;
+    }
+
+    /** Get the transaction
+     *
+     * @return The transaction which was stored
+     */
+    transaction_t* get_transaction() {
+        return &_data;
+    }
+
+private:
+    Class* _obj;
+    transaction_t _data;
+};
+
+}
+
+#endif
diff --git a/ext/analogin_api.h b/ext/analogin_api.h
new file mode 100644
index 0000000..01b88ad
--- /dev/null
+++ b/ext/analogin_api.h
@@ -0,0 +1,39 @@
+/* mbed Microcontroller Library

+ * Copyright (c) 2006-2013 ARM Limited

+ *

+ * Licensed under the Apache License, Version 2.0 (the "License");

+ * you may not use this file except in compliance with the License.

+ * You may obtain a copy of the License at

+ *

+ *     http://www.apache.org/licenses/LICENSE-2.0

+ *

+ * Unless required by applicable law or agreed to in writing, software

+ * distributed under the License is distributed on an "AS IS" BASIS,

+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

+ * See the License for the specific language governing permissions and

+ * limitations under the License.

+ */

+#ifndef MBED_ANALOGIN_API_H

+#define MBED_ANALOGIN_API_H

+

+#include "device.h"

+

+#if DEVICE_ANALOGIN

+

+#ifdef __cplusplus

+extern "C" {

+#endif

+

+typedef struct analogin_s analogin_t;

+

+void     analogin_init    (analogin_t *obj, PinName pin);

+float    analogin_read    (analogin_t *obj);

+uint16_t analogin_read_u16(analogin_t *obj);

+

+#ifdef __cplusplus

+}

+#endif

+

+#endif

+

+#endif

diff --git a/ext/analogout_api.h b/ext/analogout_api.h
new file mode 100644
index 0000000..67d1c2a
--- /dev/null
+++ b/ext/analogout_api.h
@@ -0,0 +1,42 @@
+/* mbed Microcontroller Library

+ * Copyright (c) 2006-2013 ARM Limited

+ *

+ * Licensed under the Apache License, Version 2.0 (the "License");

+ * you may not use this file except in compliance with the License.

+ * You may obtain a copy of the License at

+ *

+ *     http://www.apache.org/licenses/LICENSE-2.0

+ *

+ * Unless required by applicable law or agreed to in writing, software

+ * distributed under the License is distributed on an "AS IS" BASIS,

+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

+ * See the License for the specific language governing permissions and

+ * limitations under the License.

+ */

+#ifndef MBED_ANALOGOUT_API_H

+#define MBED_ANALOGOUT_API_H

+

+#include "device.h"

+

+#if DEVICE_ANALOGOUT

+

+#ifdef __cplusplus

+extern "C" {

+#endif

+

+typedef struct dac_s dac_t;

+

+void     analogout_init     (dac_t *obj, PinName pin);

+void     analogout_free     (dac_t *obj);

+void     analogout_write    (dac_t *obj, float value);

+void     analogout_write_u16(dac_t *obj, uint16_t value);

+float    analogout_read     (dac_t *obj);

+uint16_t analogout_read_u16 (dac_t *obj);

+

+#ifdef __cplusplus

+}

+#endif

+

+#endif

+

+#endif

diff --git a/ext/buffer.h b/ext/buffer.h
new file mode 100644
index 0000000..2238691
--- /dev/null
+++ b/ext/buffer.h
@@ -0,0 +1,30 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2014-2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_BUFFER_H
+#define MBED_BUFFER_H
+
+#include <stddef.h>
+
+/** Generic buffer structure
+ */
+typedef struct buffer_s {
+    void    *buffer; /**< the pointer to a buffer */
+    size_t   length; /**< the buffer length */
+    size_t   pos;    /**< actual buffer position */
+    uint8_t  width;  /**< The buffer unit width (8, 16, 32, 64), used for proper *buffer casting */
+} buffer_t;
+
+#endif
diff --git a/ext/can_api.h b/ext/can_api.h
new file mode 100644
index 0000000..f946cce
--- /dev/null
+++ b/ext/can_api.h
@@ -0,0 +1,80 @@
+/* mbed Microcontroller Library

+ * Copyright (c) 2006-2016 ARM Limited

+ *

+ * Licensed under the Apache License, Version 2.0 (the "License");

+ * you may not use this file except in compliance with the License.

+ * You may obtain a copy of the License at

+ *

+ *     http://www.apache.org/licenses/LICENSE-2.0

+ *

+ * Unless required by applicable law or agreed to in writing, software

+ * distributed under the License is distributed on an "AS IS" BASIS,

+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

+ * See the License for the specific language governing permissions and

+ * limitations under the License.

+ */

+#ifndef MBED_CAN_API_H

+#define MBED_CAN_API_H

+

+#include "device.h"

+

+#if DEVICE_CAN

+

+#include "PinNames.h"

+#include "PeripheralNames.h"

+#include "can_helper.h"

+

+#ifdef __cplusplus

+extern "C" {

+#endif

+

+typedef enum {

+    IRQ_RX,

+    IRQ_TX,

+    IRQ_ERROR,

+    IRQ_OVERRUN,

+    IRQ_WAKEUP,

+    IRQ_PASSIVE,

+    IRQ_ARB,

+    IRQ_BUS,

+    IRQ_READY

+} CanIrqType;

+

+

+typedef enum {

+    MODE_RESET,

+    MODE_NORMAL,

+    MODE_SILENT,

+    MODE_TEST_LOCAL,

+    MODE_TEST_GLOBAL,

+    MODE_TEST_SILENT

+} CanMode;

+

+typedef void (*can_irq_handler)(uint32_t id, CanIrqType type);

+

+typedef struct can_s can_t;

+

+void          can_init     (can_t *obj, PinName rd, PinName td);

+void          can_free     (can_t *obj);

+int           can_frequency(can_t *obj, int hz);

+

+void          can_irq_init (can_t *obj, can_irq_handler handler, uint32_t id);

+void          can_irq_free (can_t *obj);

+void          can_irq_set  (can_t *obj, CanIrqType irq, uint32_t enable);

+

+int           can_write    (can_t *obj, CAN_Message, int cc);

+int           can_read     (can_t *obj, CAN_Message *msg, int handle);

+int           can_mode     (can_t *obj, CanMode mode);

+int           can_filter(can_t *obj, uint32_t id, uint32_t mask, CANFormat format, int32_t handle);

+void          can_reset    (can_t *obj);

+unsigned char can_rderror  (can_t *obj);

+unsigned char can_tderror  (can_t *obj);

+void          can_monitor  (can_t *obj, int silent);

+

+#ifdef __cplusplus

+};

+#endif

+

+#endif    // MBED_CAN_API_H

+

+#endif

diff --git a/ext/can_helper.h b/ext/can_helper.h
new file mode 100644
index 0000000..74bcdf6
--- /dev/null
+++ b/ext/can_helper.h
@@ -0,0 +1,53 @@
+/* mbed Microcontroller Library

+ * Copyright (c) 2006-2013 ARM Limited

+ *

+ * Licensed under the Apache License, Version 2.0 (the "License");

+ * you may not use this file except in compliance with the License.

+ * You may obtain a copy of the License at

+ *

+ *     http://www.apache.org/licenses/LICENSE-2.0

+ *

+ * Unless required by applicable law or agreed to in writing, software

+ * distributed under the License is distributed on an "AS IS" BASIS,

+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

+ * See the License for the specific language governing permissions and

+ * limitations under the License.

+ */

+#ifndef MBED_CAN_HELPER_H

+#define MBED_CAN_HELPER_H

+

+#if DEVICE_CAN

+

+#ifdef __cplusplus

+extern "C" {

+#endif

+

+enum CANFormat {

+    CANStandard = 0,

+    CANExtended = 1,

+    CANAny = 2

+};

+typedef enum CANFormat CANFormat;

+

+enum CANType {

+    CANData   = 0,

+    CANRemote = 1

+};

+typedef enum CANType CANType;

+

+struct CAN_Message {

+    unsigned int   id;                 // 29 bit identifier

+    unsigned char  data[8];            // Data field

+    unsigned char  len;                // Length of data field in bytes

+    CANFormat      format;             // 0 - STANDARD, 1- EXTENDED IDENTIFIER

+    CANType        type;               // 0 - DATA FRAME, 1 - REMOTE FRAME

+};

+typedef struct CAN_Message CAN_Message;

+

+#ifdef __cplusplus

+};

+#endif

+

+#endif

+

+#endif // MBED_CAN_HELPER_H

diff --git a/ext/dma_api.h b/ext/dma_api.h
new file mode 100644
index 0000000..8af5cbe
--- /dev/null
+++ b/ext/dma_api.h
@@ -0,0 +1,45 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2014-2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_DMA_API_H
+#define MBED_DMA_API_H
+
+#include <stdint.h>
+
+#define DMA_ERROR_OUT_OF_CHANNELS (-1)
+
+typedef enum {
+    DMA_USAGE_NEVER,
+    DMA_USAGE_OPPORTUNISTIC,
+    DMA_USAGE_ALWAYS,
+    DMA_USAGE_TEMPORARY_ALLOCATED,
+    DMA_USAGE_ALLOCATED
+} DMAUsage;
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void dma_init(void);
+
+int dma_channel_allocate(uint32_t capabilities);
+
+int dma_channel_free(int channelid);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/ext/ethernet_api.h b/ext/ethernet_api.h
new file mode 100644
index 0000000..db030ed
--- /dev/null
+++ b/ext/ethernet_api.h
@@ -0,0 +1,63 @@
+/* mbed Microcontroller Library

+ * Copyright (c) 2006-2013 ARM Limited

+ *

+ * Licensed under the Apache License, Version 2.0 (the "License");

+ * you may not use this file except in compliance with the License.

+ * You may obtain a copy of the License at

+ *

+ *     http://www.apache.org/licenses/LICENSE-2.0

+ *

+ * Unless required by applicable law or agreed to in writing, software

+ * distributed under the License is distributed on an "AS IS" BASIS,

+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

+ * See the License for the specific language governing permissions and

+ * limitations under the License.

+ */

+#ifndef MBED_ETHERNET_API_H

+#define MBED_ETHERNET_API_H

+

+#include "device.h"

+

+#if DEVICE_ETHERNET

+

+#ifdef __cplusplus

+extern "C" {

+#endif

+

+// Connection constants

+

+int ethernet_init(void);

+void ethernet_free(void);

+

+// write size bytes from data to ethernet buffer

+// return num bytes written

+// or -1 if size is too big

+int ethernet_write(const char *data, int size);

+

+// send ethernet write buffer, returning the packet size sent

+int ethernet_send(void);

+

+// recieve from ethernet buffer, returning packet size, or 0 if no packet

+int ethernet_receive(void);

+

+// read size bytes in to data, return actual num bytes read (0..size)

+// if data == NULL, throw the bytes away

+int ethernet_read(char *data, int size);

+

+// get the ethernet address

+void ethernet_address(char *mac);

+

+// see if the link is up

+int ethernet_link(void);

+

+// force link settings

+void ethernet_set_link(int speed, int duplex);

+

+#ifdef __cplusplus

+}

+#endif

+

+#endif

+

+#endif

+

diff --git a/ext/glcdfont.h b/ext/glcdfont.h
new file mode 100644
index 0000000..a15e23b
--- /dev/null
+++ b/ext/glcdfont.h
@@ -0,0 +1,285 @@
+/*********************************************************************
+This is a library for our Monochrome OLEDs based on SSD1306 drivers
+
+  Pick one up today in the adafruit shop!
+  ------> http://www.adafruit.com/category/63_98
+
+These displays use SPI to communicate, 4 or 5 pins are required to  
+interface
+
+Adafruit invests time and resources providing this open source code, 
+please support Adafruit and open-source hardware by purchasing 
+products from Adafruit!
+
+Written by Limor Fried/Ladyada  for Adafruit Industries.  
+BSD license, check license.txt for more information
+All text above, and the splash screen must be included in any redistribution
+*********************************************************************/
+
+/*
+ *  Modified by Neal Horman 7/14/2012 for use in LPC1768
+ */
+ 
+#ifndef FONT5X7_H
+#define FONT5X7_H
+
+// standard ascii 5x7 font
+
+static unsigned char  font[] = {
+    0x00, 0x00, 0x00, 0x00, 0x00,   
+    0x3E, 0x5B, 0x4F, 0x5B, 0x3E,     
+    0x3E, 0x6B, 0x4F, 0x6B, 0x3E,     
+    0x1C, 0x3E, 0x7C, 0x3E, 0x1C, 
+    0x18, 0x3C, 0x7E, 0x3C, 0x18, 
+    0x1C, 0x57, 0x7D, 0x57, 0x1C, 
+    0x1C, 0x5E, 0x7F, 0x5E, 0x1C, 
+    0x00, 0x18, 0x3C, 0x18, 0x00, 
+    0xFF, 0xE7, 0xC3, 0xE7, 0xFF, 
+    0x00, 0x18, 0x24, 0x18, 0x00, 
+    0xFF, 0xE7, 0xDB, 0xE7, 0xFF, 
+    0x30, 0x48, 0x3A, 0x06, 0x0E, 
+    0x26, 0x29, 0x79, 0x29, 0x26, 
+    0x40, 0x7F, 0x05, 0x05, 0x07, 
+    0x40, 0x7F, 0x05, 0x25, 0x3F, 
+    0x5A, 0x3C, 0xE7, 0x3C, 0x5A, 
+    0x7F, 0x3E, 0x1C, 0x1C, 0x08, 
+    0x08, 0x1C, 0x1C, 0x3E, 0x7F, 
+    0x14, 0x22, 0x7F, 0x22, 0x14, 
+    0x5F, 0x5F, 0x00, 0x5F, 0x5F, 
+    0x06, 0x09, 0x7F, 0x01, 0x7F, 
+    0x00, 0x66, 0x89, 0x95, 0x6A, 
+    0x60, 0x60, 0x60, 0x60, 0x60, 
+    0x94, 0xA2, 0xFF, 0xA2, 0x94, 
+    0x08, 0x04, 0x7E, 0x04, 0x08, 
+    0x10, 0x20, 0x7E, 0x20, 0x10, 
+    0x08, 0x08, 0x2A, 0x1C, 0x08, 
+    0x08, 0x1C, 0x2A, 0x08, 0x08, 
+    0x1E, 0x10, 0x10, 0x10, 0x10, 
+    0x0C, 0x1E, 0x0C, 0x1E, 0x0C, 
+    0x30, 0x38, 0x3E, 0x38, 0x30, 
+    0x06, 0x0E, 0x3E, 0x0E, 0x06, 
+    0x00, 0x00, 0x00, 0x00, 0x00, 
+    0x00, 0x00, 0x5F, 0x00, 0x00, 
+    0x00, 0x07, 0x00, 0x07, 0x00, 
+    0x14, 0x7F, 0x14, 0x7F, 0x14, 
+    0x24, 0x2A, 0x7F, 0x2A, 0x12, 
+    0x23, 0x13, 0x08, 0x64, 0x62, 
+    0x36, 0x49, 0x56, 0x20, 0x50, 
+    0x00, 0x08, 0x07, 0x03, 0x00, 
+    0x00, 0x1C, 0x22, 0x41, 0x00, 
+    0x00, 0x41, 0x22, 0x1C, 0x00, 
+    0x2A, 0x1C, 0x7F, 0x1C, 0x2A, 
+    0x08, 0x08, 0x3E, 0x08, 0x08, 
+    0x00, 0x80, 0x70, 0x30, 0x00, 
+    0x08, 0x08, 0x08, 0x08, 0x08, 
+    0x00, 0x00, 0x60, 0x60, 0x00, 
+    0x20, 0x10, 0x08, 0x04, 0x02, 
+    0x3E, 0x51, 0x49, 0x45, 0x3E, 
+    0x00, 0x42, 0x7F, 0x40, 0x00, 
+    0x72, 0x49, 0x49, 0x49, 0x46, 
+    0x21, 0x41, 0x49, 0x4D, 0x33, 
+    0x18, 0x14, 0x12, 0x7F, 0x10, 
+    0x27, 0x45, 0x45, 0x45, 0x39, 
+    0x3C, 0x4A, 0x49, 0x49, 0x31, 
+    0x41, 0x21, 0x11, 0x09, 0x07, 
+    0x36, 0x49, 0x49, 0x49, 0x36, 
+    0x46, 0x49, 0x49, 0x29, 0x1E, 
+    0x00, 0x00, 0x14, 0x00, 0x00, 
+    0x00, 0x40, 0x34, 0x00, 0x00, 
+    0x00, 0x08, 0x14, 0x22, 0x41, 
+    0x14, 0x14, 0x14, 0x14, 0x14, 
+    0x00, 0x41, 0x22, 0x14, 0x08, 
+    0x02, 0x01, 0x59, 0x09, 0x06, 
+    0x3E, 0x41, 0x5D, 0x59, 0x4E, 
+    0x7C, 0x12, 0x11, 0x12, 0x7C, 
+    0x7F, 0x49, 0x49, 0x49, 0x36, 
+    0x3E, 0x41, 0x41, 0x41, 0x22, 
+    0x7F, 0x41, 0x41, 0x41, 0x3E, 
+    0x7F, 0x49, 0x49, 0x49, 0x41, 
+    0x7F, 0x09, 0x09, 0x09, 0x01, 
+    0x3E, 0x41, 0x41, 0x51, 0x73, 
+    0x7F, 0x08, 0x08, 0x08, 0x7F, 
+    0x00, 0x41, 0x7F, 0x41, 0x00, 
+    0x20, 0x40, 0x41, 0x3F, 0x01, 
+    0x7F, 0x08, 0x14, 0x22, 0x41, 
+    0x7F, 0x40, 0x40, 0x40, 0x40, 
+    0x7F, 0x02, 0x1C, 0x02, 0x7F, 
+    0x7F, 0x04, 0x08, 0x10, 0x7F, 
+    0x3E, 0x41, 0x41, 0x41, 0x3E, 
+    0x7F, 0x09, 0x09, 0x09, 0x06, 
+    0x3E, 0x41, 0x51, 0x21, 0x5E, 
+    0x7F, 0x09, 0x19, 0x29, 0x46, 
+    0x26, 0x49, 0x49, 0x49, 0x32, 
+    0x03, 0x01, 0x7F, 0x01, 0x03, 
+    0x3F, 0x40, 0x40, 0x40, 0x3F, 
+    0x1F, 0x20, 0x40, 0x20, 0x1F, 
+    0x3F, 0x40, 0x38, 0x40, 0x3F, 
+    0x63, 0x14, 0x08, 0x14, 0x63, 
+    0x03, 0x04, 0x78, 0x04, 0x03, 
+    0x61, 0x59, 0x49, 0x4D, 0x43, 
+    0x00, 0x7F, 0x41, 0x41, 0x41, 
+    0x02, 0x04, 0x08, 0x10, 0x20, 
+    0x00, 0x41, 0x41, 0x41, 0x7F, 
+    0x04, 0x02, 0x01, 0x02, 0x04, 
+    0x40, 0x40, 0x40, 0x40, 0x40, 
+    0x00, 0x03, 0x07, 0x08, 0x00, 
+    0x20, 0x54, 0x54, 0x78, 0x40, 
+    0x7F, 0x28, 0x44, 0x44, 0x38, 
+    0x38, 0x44, 0x44, 0x44, 0x28, 
+    0x38, 0x44, 0x44, 0x28, 0x7F, 
+    0x38, 0x54, 0x54, 0x54, 0x18, 
+    0x00, 0x08, 0x7E, 0x09, 0x02, 
+    0x18, 0xA4, 0xA4, 0x9C, 0x78, 
+    0x7F, 0x08, 0x04, 0x04, 0x78, 
+    0x00, 0x44, 0x7D, 0x40, 0x00, 
+    0x20, 0x40, 0x40, 0x3D, 0x00, 
+    0x7F, 0x10, 0x28, 0x44, 0x00, 
+    0x00, 0x41, 0x7F, 0x40, 0x00, 
+    0x7C, 0x04, 0x78, 0x04, 0x78, 
+    0x7C, 0x08, 0x04, 0x04, 0x78, 
+    0x38, 0x44, 0x44, 0x44, 0x38, 
+    0xFC, 0x18, 0x24, 0x24, 0x18, 
+    0x18, 0x24, 0x24, 0x18, 0xFC, 
+    0x7C, 0x08, 0x04, 0x04, 0x08, 
+    0x48, 0x54, 0x54, 0x54, 0x24, 
+    0x04, 0x04, 0x3F, 0x44, 0x24, 
+    0x3C, 0x40, 0x40, 0x20, 0x7C, 
+    0x1C, 0x20, 0x40, 0x20, 0x1C, 
+    0x3C, 0x40, 0x30, 0x40, 0x3C, 
+    0x44, 0x28, 0x10, 0x28, 0x44, 
+    0x4C, 0x90, 0x90, 0x90, 0x7C, 
+    0x44, 0x64, 0x54, 0x4C, 0x44, 
+    0x00, 0x08, 0x36, 0x41, 0x00, 
+    0x00, 0x00, 0x77, 0x00, 0x00, 
+    0x00, 0x41, 0x36, 0x08, 0x00, 
+    0x02, 0x01, 0x02, 0x04, 0x02, 
+    0x3C, 0x26, 0x23, 0x26, 0x3C, 
+    0x1E, 0xA1, 0xA1, 0x61, 0x12, 
+    0x3A, 0x40, 0x40, 0x20, 0x7A, 
+    0x38, 0x54, 0x54, 0x55, 0x59, 
+    0x21, 0x55, 0x55, 0x79, 0x41, 
+    0x21, 0x54, 0x54, 0x78, 0x41, 
+    0x21, 0x55, 0x54, 0x78, 0x40, 
+    0x20, 0x54, 0x55, 0x79, 0x40, 
+    0x0C, 0x1E, 0x52, 0x72, 0x12, 
+    0x39, 0x55, 0x55, 0x55, 0x59, 
+    0x39, 0x54, 0x54, 0x54, 0x59, 
+    0x39, 0x55, 0x54, 0x54, 0x58, 
+    0x00, 0x00, 0x45, 0x7C, 0x41, 
+    0x00, 0x02, 0x45, 0x7D, 0x42, 
+    0x00, 0x01, 0x45, 0x7C, 0x40, 
+    0xF0, 0x29, 0x24, 0x29, 0xF0, 
+    0xF0, 0x28, 0x25, 0x28, 0xF0, 
+    0x7C, 0x54, 0x55, 0x45, 0x00, 
+    0x20, 0x54, 0x54, 0x7C, 0x54, 
+    0x7C, 0x0A, 0x09, 0x7F, 0x49, 
+    0x32, 0x49, 0x49, 0x49, 0x32, 
+    0x32, 0x48, 0x48, 0x48, 0x32, 
+    0x32, 0x4A, 0x48, 0x48, 0x30, 
+    0x3A, 0x41, 0x41, 0x21, 0x7A, 
+    0x3A, 0x42, 0x40, 0x20, 0x78, 
+    0x00, 0x9D, 0xA0, 0xA0, 0x7D, 
+    0x39, 0x44, 0x44, 0x44, 0x39, 
+    0x3D, 0x40, 0x40, 0x40, 0x3D, 
+    0x3C, 0x24, 0xFF, 0x24, 0x24, 
+    0x48, 0x7E, 0x49, 0x43, 0x66, 
+    0x2B, 0x2F, 0xFC, 0x2F, 0x2B, 
+    0xFF, 0x09, 0x29, 0xF6, 0x20, 
+    0xC0, 0x88, 0x7E, 0x09, 0x03, 
+    0x20, 0x54, 0x54, 0x79, 0x41, 
+    0x00, 0x00, 0x44, 0x7D, 0x41, 
+    0x30, 0x48, 0x48, 0x4A, 0x32, 
+    0x38, 0x40, 0x40, 0x22, 0x7A, 
+    0x00, 0x7A, 0x0A, 0x0A, 0x72, 
+    0x7D, 0x0D, 0x19, 0x31, 0x7D, 
+    0x26, 0x29, 0x29, 0x2F, 0x28, 
+    0x26, 0x29, 0x29, 0x29, 0x26, 
+    0x30, 0x48, 0x4D, 0x40, 0x20, 
+    0x38, 0x08, 0x08, 0x08, 0x08, 
+    0x08, 0x08, 0x08, 0x08, 0x38, 
+    0x2F, 0x10, 0xC8, 0xAC, 0xBA, 
+    0x2F, 0x10, 0x28, 0x34, 0xFA, 
+    0x00, 0x00, 0x7B, 0x00, 0x00, 
+    0x08, 0x14, 0x2A, 0x14, 0x22, 
+    0x22, 0x14, 0x2A, 0x14, 0x08, 
+    0xAA, 0x00, 0x55, 0x00, 0xAA, 
+    0xAA, 0x55, 0xAA, 0x55, 0xAA, 
+    0x00, 0x00, 0x00, 0xFF, 0x00, 
+    0x10, 0x10, 0x10, 0xFF, 0x00, 
+    0x14, 0x14, 0x14, 0xFF, 0x00, 
+    0x10, 0x10, 0xFF, 0x00, 0xFF, 
+    0x10, 0x10, 0xF0, 0x10, 0xF0, 
+    0x14, 0x14, 0x14, 0xFC, 0x00, 
+    0x14, 0x14, 0xF7, 0x00, 0xFF, 
+    0x00, 0x00, 0xFF, 0x00, 0xFF, 
+    0x14, 0x14, 0xF4, 0x04, 0xFC, 
+    0x14, 0x14, 0x17, 0x10, 0x1F, 
+    0x10, 0x10, 0x1F, 0x10, 0x1F, 
+    0x14, 0x14, 0x14, 0x1F, 0x00, 
+    0x10, 0x10, 0x10, 0xF0, 0x00, 
+    0x00, 0x00, 0x00, 0x1F, 0x10, 
+    0x10, 0x10, 0x10, 0x1F, 0x10, 
+    0x10, 0x10, 0x10, 0xF0, 0x10, 
+    0x00, 0x00, 0x00, 0xFF, 0x10, 
+    0x10, 0x10, 0x10, 0x10, 0x10, 
+    0x10, 0x10, 0x10, 0xFF, 0x10, 
+    0x00, 0x00, 0x00, 0xFF, 0x14, 
+    0x00, 0x00, 0xFF, 0x00, 0xFF, 
+    0x00, 0x00, 0x1F, 0x10, 0x17, 
+    0x00, 0x00, 0xFC, 0x04, 0xF4, 
+    0x14, 0x14, 0x17, 0x10, 0x17, 
+    0x14, 0x14, 0xF4, 0x04, 0xF4, 
+    0x00, 0x00, 0xFF, 0x00, 0xF7, 
+    0x14, 0x14, 0x14, 0x14, 0x14, 
+    0x14, 0x14, 0xF7, 0x00, 0xF7, 
+    0x14, 0x14, 0x14, 0x17, 0x14, 
+    0x10, 0x10, 0x1F, 0x10, 0x1F, 
+    0x14, 0x14, 0x14, 0xF4, 0x14, 
+    0x10, 0x10, 0xF0, 0x10, 0xF0, 
+    0x00, 0x00, 0x1F, 0x10, 0x1F, 
+    0x00, 0x00, 0x00, 0x1F, 0x14, 
+    0x00, 0x00, 0x00, 0xFC, 0x14, 
+    0x00, 0x00, 0xF0, 0x10, 0xF0, 
+    0x10, 0x10, 0xFF, 0x10, 0xFF, 
+    0x14, 0x14, 0x14, 0xFF, 0x14, 
+    0x10, 0x10, 0x10, 0x1F, 0x00, 
+    0x00, 0x00, 0x00, 0xF0, 0x10, 
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 
+    0xF0, 0xF0, 0xF0, 0xF0, 0xF0, 
+    0xFF, 0xFF, 0xFF, 0x00, 0x00, 
+    0x00, 0x00, 0x00, 0xFF, 0xFF, 
+    0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 
+    0x38, 0x44, 0x44, 0x38, 0x44, 
+    0x7C, 0x2A, 0x2A, 0x3E, 0x14, 
+    0x7E, 0x02, 0x02, 0x06, 0x06, 
+    0x02, 0x7E, 0x02, 0x7E, 0x02, 
+    0x63, 0x55, 0x49, 0x41, 0x63, 
+    0x38, 0x44, 0x44, 0x3C, 0x04, 
+    0x40, 0x7E, 0x20, 0x1E, 0x20, 
+    0x06, 0x02, 0x7E, 0x02, 0x02, 
+    0x99, 0xA5, 0xE7, 0xA5, 0x99, 
+    0x1C, 0x2A, 0x49, 0x2A, 0x1C, 
+    0x4C, 0x72, 0x01, 0x72, 0x4C, 
+    0x30, 0x4A, 0x4D, 0x4D, 0x30, 
+    0x30, 0x48, 0x78, 0x48, 0x30, 
+    0xBC, 0x62, 0x5A, 0x46, 0x3D, 
+    0x3E, 0x49, 0x49, 0x49, 0x00, 
+    0x7E, 0x01, 0x01, 0x01, 0x7E, 
+    0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 
+    0x44, 0x44, 0x5F, 0x44, 0x44, 
+    0x40, 0x51, 0x4A, 0x44, 0x40, 
+    0x40, 0x44, 0x4A, 0x51, 0x40, 
+    0x00, 0x00, 0xFF, 0x01, 0x03, 
+    0xE0, 0x80, 0xFF, 0x00, 0x00, 
+    0x08, 0x08, 0x6B, 0x6B, 0x08,
+    0x36, 0x12, 0x36, 0x24, 0x36, 
+    0x06, 0x0F, 0x09, 0x0F, 0x06, 
+    0x00, 0x00, 0x18, 0x18, 0x00, 
+    0x00, 0x00, 0x10, 0x10, 0x00, 
+    0x30, 0x40, 0xFF, 0x01, 0x01, 
+    0x00, 0x1F, 0x01, 0x01, 0x1E, 
+    0x00, 0x19, 0x1D, 0x17, 0x12, 
+    0x00, 0x3C, 0x3C, 0x3C, 0x3C, 
+    0x00, 0x00, 0x00, 0x00, 0x00, 
+};
+#endif
diff --git a/ext/gpio_api.h b/ext/gpio_api.h
new file mode 100644
index 0000000..64140ea
--- /dev/null
+++ b/ext/gpio_api.h
@@ -0,0 +1,57 @@
+/* mbed Microcontroller Library

+ * Copyright (c) 2006-2013 ARM Limited

+ *

+ * Licensed under the Apache License, Version 2.0 (the "License");

+ * you may not use this file except in compliance with the License.

+ * You may obtain a copy of the License at

+ *

+ *     http://www.apache.org/licenses/LICENSE-2.0

+ *

+ * Unless required by applicable law or agreed to in writing, software

+ * distributed under the License is distributed on an "AS IS" BASIS,

+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

+ * See the License for the specific language governing permissions and

+ * limitations under the License.

+ */

+#ifndef MBED_GPIO_API_H

+#define MBED_GPIO_API_H

+

+#include "device.h"

+

+#ifdef __cplusplus

+extern "C" {

+#endif

+

+/* Set the given pin as GPIO

+ * @param pin The pin to be set as GPIO

+ * @return The GPIO port mask for this pin

+ **/

+uint32_t gpio_set(PinName pin);

+

+/* Checks if gpio object is connected (pin was not initialized with NC)

+ * @param pin The pin to be set as GPIO

+ * @return 0 if port is initialized with NC

+ **/

+int gpio_is_connected(const gpio_t *obj);

+

+/* GPIO object */

+void gpio_init(gpio_t *obj, PinName pin);

+

+void gpio_mode (gpio_t *obj, PinMode mode);

+void gpio_dir  (gpio_t *obj, PinDirection direction);

+

+void gpio_write(gpio_t *obj, int value);

+int  gpio_read (gpio_t *obj);

+

+// the following set of functions are generic and are implemented in the common gpio.c file

+void gpio_init_in(gpio_t* gpio, PinName pin);

+void gpio_init_in_ex(gpio_t* gpio, PinName pin, PinMode mode);

+void gpio_init_out(gpio_t* gpio, PinName pin);

+void gpio_init_out_ex(gpio_t* gpio, PinName pin, int value);

+void gpio_init_inout(gpio_t* gpio, PinName pin, PinDirection direction, PinMode mode, int value);

+

+#ifdef __cplusplus

+}

+#endif

+

+#endif

diff --git a/ext/gpio_irq_api.h b/ext/gpio_irq_api.h
new file mode 100644
index 0000000..d7d6d15
--- /dev/null
+++ b/ext/gpio_irq_api.h
@@ -0,0 +1,49 @@
+/* mbed Microcontroller Library

+ * Copyright (c) 2006-2013 ARM Limited

+ *

+ * Licensed under the Apache License, Version 2.0 (the "License");

+ * you may not use this file except in compliance with the License.

+ * You may obtain a copy of the License at

+ *

+ *     http://www.apache.org/licenses/LICENSE-2.0

+ *

+ * Unless required by applicable law or agreed to in writing, software

+ * distributed under the License is distributed on an "AS IS" BASIS,

+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

+ * See the License for the specific language governing permissions and

+ * limitations under the License.

+ */

+#ifndef MBED_GPIO_IRQ_API_H

+#define MBED_GPIO_IRQ_API_H

+

+#include "device.h"

+

+#if DEVICE_INTERRUPTIN

+

+#ifdef __cplusplus

+extern "C" {

+#endif

+

+typedef enum {

+    IRQ_NONE,

+    IRQ_RISE,

+    IRQ_FALL

+} gpio_irq_event;

+

+typedef struct gpio_irq_s gpio_irq_t;

+

+typedef void (*gpio_irq_handler)(uint32_t id, gpio_irq_event event);

+

+int  gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id);

+void gpio_irq_free(gpio_irq_t *obj);

+void gpio_irq_set (gpio_irq_t *obj, gpio_irq_event event, uint32_t enable);

+void gpio_irq_enable(gpio_irq_t *obj);

+void gpio_irq_disable(gpio_irq_t *obj);

+

+#ifdef __cplusplus

+}

+#endif

+

+#endif

+

+#endif

diff --git a/ext/i2c_api.h b/ext/i2c_api.h
new file mode 100644
index 0000000..fdb05a0
--- /dev/null
+++ b/ext/i2c_api.h
@@ -0,0 +1,223 @@
+/* mbed Microcontroller Library

+ * Copyright (c) 2006-2015 ARM Limited

+ *

+ * Licensed under the Apache License, Version 2.0 (the "License");

+ * you may not use this file except in compliance with the License.

+ * You may obtain a copy of the License at

+ *

+ *     http://www.apache.org/licenses/LICENSE-2.0

+ *

+ * Unless required by applicable law or agreed to in writing, software

+ * distributed under the License is distributed on an "AS IS" BASIS,

+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

+ * See the License for the specific language governing permissions and

+ * limitations under the License.

+ */

+#ifndef MBED_I2C_API_H

+#define MBED_I2C_API_H

+

+#include "device.h"

+#include "buffer.h"

+

+#if DEVICE_I2C

+

+/**

+ * @defgroup I2CEvents I2C Events Macros

+ *

+ * @{

+ */

+#define I2C_EVENT_ERROR               (1 << 1)

+#define I2C_EVENT_ERROR_NO_SLAVE      (1 << 2)

+#define I2C_EVENT_TRANSFER_COMPLETE   (1 << 3)

+#define I2C_EVENT_TRANSFER_EARLY_NACK (1 << 4)

+#define I2C_EVENT_ALL                 (I2C_EVENT_ERROR |  I2C_EVENT_TRANSFER_COMPLETE | I2C_EVENT_ERROR_NO_SLAVE | I2C_EVENT_TRANSFER_EARLY_NACK)

+

+/**@}*/

+

+#if DEVICE_I2C_ASYNCH

+/** Asynch i2c hal structure

+ */

+typedef struct {

+    struct i2c_s    i2c;     /**< Target specific i2c structure */

+    struct buffer_s tx_buff; /**< Tx buffer */

+    struct buffer_s rx_buff; /**< Rx buffer */

+} i2c_t;

+

+#else

+/** Non-asynch i2c hal structure

+ */

+typedef struct i2c_s i2c_t;

+

+#endif

+

+enum {

+  I2C_ERROR_NO_SLAVE = -1,

+  I2C_ERROR_BUS_BUSY = -2

+};

+

+#ifdef __cplusplus

+extern "C" {

+#endif

+

+/**

+ * \defgroup GeneralI2C I2C Configuration Functions

+ * @{

+ */

+

+/** Initialize the I2C peripheral. It sets the default parameters for I2C

+ *  peripheral, and configure its specifieds pins.

+ *  @param obj  The i2c object

+ *  @param sda  The sda pin

+ *  @param scl  The scl pin

+ */

+void i2c_init(i2c_t *obj, PinName sda, PinName scl);

+

+/** Configure the I2C frequency.

+ *  @param obj The i2c object

+ *  @param hz  Frequency in Hz

+ */

+void i2c_frequency(i2c_t *obj, int hz);

+

+/** Send START command.

+ *  @param obj The i2c object

+ */

+int  i2c_start(i2c_t *obj);

+

+/** Send STOP command.

+ *  @param obj The i2c object

+ */

+int  i2c_stop(i2c_t *obj);

+

+/** Blocking reading data.

+ *  @param obj     The i2c object

+ *  @param address 7-bit address (last bit is 1)

+ *  @param data    The buffer for receiving

+ *  @param length  Number of bytes to read

+ *  @param stop    Stop to be generated after the transfer is done

+ *  @return Number of read bytes

+ */

+int  i2c_read(i2c_t *obj, int address, char *data, int length, int stop);

+

+/** Blocking sending data.

+ *  @param obj     The i2c object

+ *  @param address 7-bit address (last bit is 0)

+ *  @param data    The buffer for sending

+ *  @param length  Number of bytes to wrte

+ *  @param stop    Stop to be generated after the transfer is done

+ *  @return Number of written bytes

+ */

+int  i2c_write(i2c_t *obj, int address, const char *data, int length, int stop);

+

+/** Reset I2C peripheral. TODO: The action here. Most of the implementation sends stop().

+ *  @param obj The i2c object

+ */

+void i2c_reset(i2c_t *obj);

+

+/** Read one byte.

+ *  @param obj The i2c object

+ *  @param last Acknoledge

+ *  @return The read byte

+ */

+int  i2c_byte_read(i2c_t *obj, int last);

+

+/** Write one byte.

+ *  @param obj The i2c object

+ *  @param data Byte to be written

+ *  @return 1 if NAK was received, 0 if ACK was received, 2 for timeout.

+ */

+int  i2c_byte_write(i2c_t *obj, int data);

+

+/**@}*/

+

+#if DEVICE_I2CSLAVE

+

+/**

+ * \defgroup SynchI2C Synchronous I2C Hardware Abstraction Layer for slave

+ * @{

+ */

+

+/** Configure I2C as slave or master.

+ *  @param obj The I2C object

+ *  @return non-zero if a value is available

+ */

+void i2c_slave_mode(i2c_t *obj, int enable_slave);

+

+/** Check to see if the I2C slave has been addressed.

+ *  @param obj The I2C object

+ *  @return The status - 1 - read addresses, 2 - write to all slaves,

+ *         3 write addressed, 0 - the slave has not been addressed

+ */

+int  i2c_slave_receive(i2c_t *obj);

+

+/** Configure I2C as slave or master.

+ *  @param obj The I2C object

+ *  @return non-zero if a value is available

+ */

+int  i2c_slave_read(i2c_t *obj, char *data, int length);

+

+/** Configure I2C as slave or master.

+ *  @param obj The I2C object

+ *  @return non-zero if a value is available

+ */

+int  i2c_slave_write(i2c_t *obj, const char *data, int length);

+

+/** Configure I2C address.

+ *  @param obj     The I2C object

+ *  @param idx     Currently not used

+ *  @param address The address to be set

+ *  @param mask    Currently not used

+ */

+void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask);

+

+#endif

+

+/**@}*/

+

+#if DEVICE_I2C_ASYNCH

+

+/**

+ * \defgroup AsynchI2C Asynchronous I2C Hardware Abstraction Layer

+ * @{

+ */

+

+/** Start i2c asynchronous transfer.

+ *  @param obj       The I2C object

+ *  @param tx        The buffer to send

+ *  @param tx_length The number of words to transmit

+ *  @param rx        The buffer to receive

+ *  @param rx_length The number of words to receive

+ *  @param address   The address to be set - 7bit or 9 bit

+ *  @param stop      If true, stop will be generated after the transfer is done

+ *  @param handler   The I2C IRQ handler to be set

+ *  @param hint      DMA hint usage

+ */

+void i2c_transfer_asynch(i2c_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length, uint32_t address, uint32_t stop, uint32_t handler, uint32_t event, DMAUsage hint);

+

+/** The asynchronous IRQ handler

+ *  @param obj The I2C object which holds the transfer information

+ *  @return event flags if a transfer termination condition was met or 0 otherwise.

+ */

+uint32_t i2c_irq_handler_asynch(i2c_t *obj);

+

+/** Attempts to determine if I2C peripheral is already in use.

+ *  @param obj The I2C object

+ *  @return non-zero if the I2C module is active or zero if it is not

+ */

+uint8_t i2c_active(i2c_t *obj);

+

+/** Abort ongoing asynchronous transaction.

+ *  @param obj The I2C object

+ */

+void i2c_abort_asynch(i2c_t *obj);

+

+#endif

+

+/**@}*/

+

+#ifdef __cplusplus

+}

+#endif

+

+#endif

+

+#endif

diff --git a/ext/lp_ticker_api.h b/ext/lp_ticker_api.h
new file mode 100644
index 0000000..7e652ea
--- /dev/null
+++ b/ext/lp_ticker_api.h
@@ -0,0 +1,82 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_LPTICKER_API_H
+#define MBED_LPTICKER_API_H
+
+#include "device.h"
+
+#if DEVICE_LOWPOWERTIMER
+
+#include "ticker_api.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \defgroup LpTicker Low Power Ticker Functions
+ * @{
+ */
+
+/** Get low power ticker's data
+ *
+ * @return The low power ticker data
+ */
+const ticker_data_t* get_lp_ticker_data(void);
+
+/** The wrapper for ticker_irq_handler, to pass lp ticker's data
+ *
+ */
+void lp_ticker_irq_handler(void);
+
+/* HAL lp ticker */
+
+/** Initialize the low power ticker
+ *
+ */
+void lp_ticker_init(void);
+
+/** Read the current counter
+ *
+ * @return The current timer's counter value in microseconds
+ */
+uint32_t lp_ticker_read(void);
+
+/** Set interrupt for specified timestamp
+ *
+ * @param timestamp The time in microseconds to be set
+ */
+void lp_ticker_set_interrupt(timestamp_t timestamp);
+
+/** Disable low power ticker interrupt
+ *
+ */
+void lp_ticker_disable_interrupt(void);
+
+/** Clear the low power ticker interrupt
+ *
+ */
+void lp_ticker_clear_interrupt(void);
+
+/**@}*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+#endif
diff --git a/ext/mbed.h b/ext/mbed.h
new file mode 100644
index 0000000..77cf4c6
--- /dev/null
+++ b/ext/mbed.h
@@ -0,0 +1,69 @@
+/* mbed Microcontroller Library

+ * Copyright (c) 2006-2013 ARM Limited

+ *

+ * Licensed under the Apache License, Version 2.0 (the "License");

+ * you may not use this file except in compliance with the License.

+ * You may obtain a copy of the License at

+ *

+ *     http://www.apache.org/licenses/LICENSE-2.0

+ *

+ * Unless required by applicable law or agreed to in writing, software

+ * distributed under the License is distributed on an "AS IS" BASIS,

+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

+ * See the License for the specific language governing permissions and

+ * limitations under the License.

+ */

+#ifndef MBED_H

+#define MBED_H

+

+#define MBED_LIBRARY_VERSION 117

+

+#include "platform.h"

+

+// Useful C libraries

+#include <math.h>

+#include <time.h>

+

+// mbed Debug libraries

+#include "mbed_error.h"

+#include "mbed_interface.h"

+

+// mbed Peripheral components

+#include "DigitalIn.h"

+#include "DigitalOut.h"

+#include "DigitalInOut.h"

+#include "BusIn.h"

+#include "BusOut.h"

+#include "BusInOut.h"

+#include "PortIn.h"

+#include "PortInOut.h"

+#include "PortOut.h"

+#include "AnalogIn.h"

+#include "AnalogOut.h"

+#include "PwmOut.h"

+#include "Serial.h"

+#include "SPI.h"

+#include "SPISlave.h"

+#include "I2C.h"

+#include "I2CSlave.h"

+#include "Ethernet.h"

+#include "CAN.h"

+#include "RawSerial.h"

+

+// mbed Internal components

+#include "Timer.h"

+#include "Ticker.h"

+#include "Timeout.h"

+#include "LowPowerTimeout.h"

+#include "LowPowerTicker.h"

+#include "LowPowerTimer.h"

+#include "LocalFileSystem.h"

+#include "InterruptIn.h"

+#include "wait_api.h"

+#include "sleep_api.h"

+#include "rtc_time.h"

+

+using namespace mbed;

+using namespace std;

+

+#endif

diff --git a/ext/mbed_assert.h b/ext/mbed_assert.h
new file mode 100644
index 0000000..1de7d6c
--- /dev/null
+++ b/ext/mbed_assert.h
@@ -0,0 +1,49 @@
+/* mbed Microcontroller Library

+ * Copyright (c) 2006-2013 ARM Limited

+ *

+ * Licensed under the Apache License, Version 2.0 (the "License");

+ * you may not use this file except in compliance with the License.

+ * You may obtain a copy of the License at

+ *

+ *     http://www.apache.org/licenses/LICENSE-2.0

+ *

+ * Unless required by applicable law or agreed to in writing, software

+ * distributed under the License is distributed on an "AS IS" BASIS,

+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

+ * See the License for the specific language governing permissions and

+ * limitations under the License.

+ */

+#ifndef MBED_ASSERT_H

+#define MBED_ASSERT_H

+

+#ifdef __cplusplus

+extern "C" {

+#endif

+

+/** Internal mbed assert function which is invoked when MBED_ASSERT macro failes.

+ *  This function is active only if NDEBUG is not defined prior to including this

+ *  assert header file.

+ *  In case of MBED_ASSERT failing condition, error() is called with the assertation message.

+ *  @param expr Expresion to be checked.

+ *  @param file File where assertation failed.

+ *  @param line Failing assertation line number.

+ */

+void mbed_assert_internal(const char *expr, const char *file, int line);

+

+#ifdef __cplusplus

+}

+#endif

+

+#ifdef NDEBUG

+#define MBED_ASSERT(expr) ((void)0)

+

+#else

+#define MBED_ASSERT(expr)                                \

+do {                                                     \

+    if (!(expr)) {                                       \

+        mbed_assert_internal(#expr, __FILE__, __LINE__); \

+    }                                                    \

+} while (0)

+#endif

+

+#endif

diff --git a/ext/mbed_debug.h b/ext/mbed_debug.h
new file mode 100644
index 0000000..0ac6cfa
--- /dev/null
+++ b/ext/mbed_debug.h
@@ -0,0 +1,66 @@
+/* mbed Microcontroller Library

+ * Copyright (c) 2006-2013 ARM Limited

+ *

+ * Licensed under the Apache License, Version 2.0 (the "License");

+ * you may not use this file except in compliance with the License.

+ * You may obtain a copy of the License at

+ *

+ *     http://www.apache.org/licenses/LICENSE-2.0

+ *

+ * Unless required by applicable law or agreed to in writing, software

+ * distributed under the License is distributed on an "AS IS" BASIS,

+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

+ * See the License for the specific language governing permissions and

+ * limitations under the License.

+ */

+#ifndef MBED_DEBUG_H

+#define MBED_DEBUG_H

+#include "device.h"

+

+#ifdef __cplusplus

+extern "C" {

+#endif

+

+#if DEVICE_STDIO_MESSAGES

+#include <stdio.h>

+#include <stdarg.h>

+

+/** Output a debug message

+ *

+ * @param format printf-style format string, followed by variables

+ */

+static inline void debug(const char *format, ...) {

+    va_list args;

+    va_start(args, format);

+    vfprintf(stderr, format, args);

+    va_end(args);

+}

+

+/** Conditionally output a debug message

+ *

+ * NOTE: If the condition is constant false (!= 1) and the compiler optimization

+ * level is greater than 0, then the whole function will be compiled away.

+ *

+ * @param condition output only if condition is true (== 1)

+ * @param format printf-style format string, followed by variables

+ */

+static inline void debug_if(int condition, const char *format, ...) {

+    if (condition == 1) {

+        va_list args;

+        va_start(args, format);

+        vfprintf(stderr, format, args);

+        va_end(args);

+    }

+}

+

+#else

+static inline void debug(const char *format, ...) {}

+static inline void debug_if(int condition, const char *format, ...) {}

+

+#endif

+

+#ifdef __cplusplus

+}

+#endif

+

+#endif

diff --git a/ext/mbed_error.h b/ext/mbed_error.h
new file mode 100644
index 0000000..3dfa553
--- /dev/null
+++ b/ext/mbed_error.h
@@ -0,0 +1,66 @@
+/* mbed Microcontroller Library

+ * Copyright (c) 2006-2013 ARM Limited

+ *

+ * Licensed under the Apache License, Version 2.0 (the "License");

+ * you may not use this file except in compliance with the License.

+ * You may obtain a copy of the License at

+ *

+ *     http://www.apache.org/licenses/LICENSE-2.0

+ *

+ * Unless required by applicable law or agreed to in writing, software

+ * distributed under the License is distributed on an "AS IS" BASIS,

+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

+ * See the License for the specific language governing permissions and

+ * limitations under the License.

+ */

+#ifndef MBED_ERROR_H

+#define MBED_ERROR_H

+

+/** To generate a fatal compile-time error, you can use the pre-processor #error directive.

+ *

+ * @code

+ * #error "That shouldn't have happened!"

+ * @endcode

+ *

+ * If the compiler evaluates this line, it will report the error and stop the compile.

+ *

+ * For example, you could use this to check some user-defined compile-time variables:

+ *

+ * @code

+ * #define NUM_PORTS 7

+ * #if (NUM_PORTS > 4)

+ *     #error "NUM_PORTS must be less than 4"

+ * #endif

+ * @endcode

+ *

+ * Reporting Run-Time Errors:

+ * To generate a fatal run-time error, you can use the mbed error() function.

+ *

+ * @code

+ * error("That shouldn't have happened!");

+ * @endcode

+ *

+ * If the mbed running the program executes this function, it will print the

+ * message via the USB serial port, and then die with the blue lights of death!

+ *

+ * The message can use printf-style formatting, so you can report variables in the

+ * message too. For example, you could use this to check a run-time condition:

+ *

+ * @code

+ * if(x >= 5) {

+ *     error("expected x to be less than 5, but got %d", x);

+ * }

+ * #endcode

+ */

+

+#ifdef __cplusplus

+extern "C" {

+#endif

+

+void error(const char* format, ...);

+

+#ifdef __cplusplus

+}

+#endif

+

+#endif

diff --git a/ext/mbed_interface.h b/ext/mbed_interface.h
new file mode 100644
index 0000000..4b3a377
--- /dev/null
+++ b/ext/mbed_interface.h
@@ -0,0 +1,114 @@
+/* mbed Microcontroller Library

+ * Copyright (c) 2006-2013 ARM Limited

+ *

+ * Licensed under the Apache License, Version 2.0 (the "License");

+ * you may not use this file except in compliance with the License.

+ * You may obtain a copy of the License at

+ *

+ *     http://www.apache.org/licenses/LICENSE-2.0

+ *

+ * Unless required by applicable law or agreed to in writing, software

+ * distributed under the License is distributed on an "AS IS" BASIS,

+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

+ * See the License for the specific language governing permissions and

+ * limitations under the License.

+ */

+#ifndef MBED_INTERFACE_H

+#define MBED_INTERFACE_H

+

+#include "device.h"

+

+/* Mbed interface mac address

+ * if MBED_MAC_ADD_x are zero, interface uid sets mac address,

+ * otherwise MAC_ADD_x are used.

+ */

+#define MBED_MAC_ADDR_INTERFACE 0x00

+#define MBED_MAC_ADDR_0  MBED_MAC_ADDR_INTERFACE

+#define MBED_MAC_ADDR_1  MBED_MAC_ADDR_INTERFACE

+#define MBED_MAC_ADDR_2  MBED_MAC_ADDR_INTERFACE

+#define MBED_MAC_ADDR_3  MBED_MAC_ADDR_INTERFACE

+#define MBED_MAC_ADDR_4  MBED_MAC_ADDR_INTERFACE

+#define MBED_MAC_ADDR_5  MBED_MAC_ADDR_INTERFACE

+#define MBED_MAC_ADDRESS_SUM (MBED_MAC_ADDR_0 | MBED_MAC_ADDR_1 | MBED_MAC_ADDR_2 | MBED_MAC_ADDR_3 | MBED_MAC_ADDR_4 | MBED_MAC_ADDR_5)

+

+#ifdef __cplusplus

+extern "C" {

+#endif

+

+#if DEVICE_SEMIHOST

+

+/** Functions to control the mbed interface

+ *

+ * mbed Microcontrollers have a built-in interface to provide functionality such as

+ * drag-n-drop download, reset, serial-over-usb, and access to the mbed local file

+ * system. These functions provide means to control the interface suing semihost

+ * calls it supports.

+ */

+

+/** Determine whether the mbed interface is connected, based on whether debug is enabled

+ *

+ *  @returns

+ *    1 if interface is connected,

+ *    0 otherwise

+ */

+int mbed_interface_connected(void);

+

+/** Instruct the mbed interface to reset, as if the reset button had been pressed

+ *

+ *  @returns

+ *    1 if successful,

+ *    0 otherwise (e.g. interface not present)

+ */

+int mbed_interface_reset(void);

+

+/** This will disconnect the debug aspect of the interface, so semihosting will be disabled.

+ * The interface will still support the USB serial aspect

+ *

+ *  @returns

+ *    0 if successful,

+ *   -1 otherwise (e.g. interface not present)

+ */

+int mbed_interface_disconnect(void);

+

+/** This will disconnect the debug aspect of the interface, and if the USB cable is not

+ * connected, also power down the interface. If the USB cable is connected, the interface

+ * will remain powered up and visible to the host

+ *

+ *  @returns

+ *    0 if successful,

+ *   -1 otherwise (e.g. interface not present)

+ */

+int mbed_interface_powerdown(void);

+

+/** This returns a string containing the 32-character UID of the mbed interface

+ *  This is a weak function that can be overwritten if required

+ *

+ *  @param uid A 33-byte array to write the null terminated 32-byte string

+ *

+ *  @returns

+ *    0 if successful,

+ *   -1 otherwise (e.g. interface not present)

+ */

+int mbed_interface_uid(char *uid);

+

+#endif

+

+/** This returns a unique 6-byte MAC address, based on the interface UID

+ * If the interface is not present, it returns a default fixed MAC address (00:02:F7:F0:00:00)

+ *

+ * This is a weak function that can be overwritten if you want to provide your own mechanism to

+ * provide a MAC address.

+ *

+ *  @param mac A 6-byte array to write the MAC address

+ */

+void mbed_mac_address(char *mac);

+

+/** Cause the mbed to flash the BLOD (Blue LEDs Of Death) sequence

+ */

+void mbed_die(void);

+

+#ifdef __cplusplus

+}

+#endif

+

+#endif

diff --git a/ext/pinmap.h b/ext/pinmap.h
new file mode 100644
index 0000000..7014aec
--- /dev/null
+++ b/ext/pinmap.h
@@ -0,0 +1,45 @@
+/* mbed Microcontroller Library

+ * Copyright (c) 2006-2013 ARM Limited

+ *

+ * Licensed under the Apache License, Version 2.0 (the "License");

+ * you may not use this file except in compliance with the License.

+ * You may obtain a copy of the License at

+ *

+ *     http://www.apache.org/licenses/LICENSE-2.0

+ *

+ * Unless required by applicable law or agreed to in writing, software

+ * distributed under the License is distributed on an "AS IS" BASIS,

+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

+ * See the License for the specific language governing permissions and

+ * limitations under the License.

+ */

+#ifndef MBED_PINMAP_H

+#define MBED_PINMAP_H

+

+#include "PinNames.h"

+

+#ifdef __cplusplus

+extern "C" {

+#endif

+

+typedef struct {

+    PinName pin;

+    int peripheral;

+    int function;

+} PinMap;

+

+void pin_function(PinName pin, int function);

+void pin_mode    (PinName pin, PinMode mode);

+

+uint32_t pinmap_peripheral(PinName pin, const PinMap* map);

+uint32_t pinmap_function(PinName pin, const PinMap* map);

+uint32_t pinmap_merge     (uint32_t a, uint32_t b);

+void     pinmap_pinout    (PinName pin, const PinMap *map);

+uint32_t pinmap_find_peripheral(PinName pin, const PinMap* map);

+uint32_t pinmap_find_function(PinName pin, const PinMap* map);

+

+#ifdef __cplusplus

+}

+#endif

+

+#endif

diff --git a/ext/platform.h b/ext/platform.h
new file mode 100644
index 0000000..4466db1
--- /dev/null
+++ b/ext/platform.h
@@ -0,0 +1,30 @@
+/* mbed Microcontroller Library

+ * Copyright (c) 2006-2013 ARM Limited

+ *

+ * Licensed under the Apache License, Version 2.0 (the "License");

+ * you may not use this file except in compliance with the License.

+ * You may obtain a copy of the License at

+ *

+ *     http://www.apache.org/licenses/LICENSE-2.0

+ *

+ * Unless required by applicable law or agreed to in writing, software

+ * distributed under the License is distributed on an "AS IS" BASIS,

+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

+ * See the License for the specific language governing permissions and

+ * limitations under the License.

+ */

+#ifndef MBED_PLATFORM_H

+#define MBED_PLATFORM_H

+

+#define MBED_OPERATORS    1

+

+#include "device.h"

+#include "PinNames.h"

+#include "PeripheralNames.h"

+

+#include <cstddef>

+#include <cstdlib>

+#include <cstdio>

+#include <cstring>

+

+#endif

diff --git a/ext/port_api.h b/ext/port_api.h
new file mode 100644
index 0000000..d56d102
--- /dev/null
+++ b/ext/port_api.h
@@ -0,0 +1,42 @@
+/* mbed Microcontroller Library

+ * Copyright (c) 2006-2013 ARM Limited

+ *

+ * Licensed under the Apache License, Version 2.0 (the "License");

+ * you may not use this file except in compliance with the License.

+ * You may obtain a copy of the License at

+ *

+ *     http://www.apache.org/licenses/LICENSE-2.0

+ *

+ * Unless required by applicable law or agreed to in writing, software

+ * distributed under the License is distributed on an "AS IS" BASIS,

+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

+ * See the License for the specific language governing permissions and

+ * limitations under the License.

+ */

+#ifndef MBED_PORTMAP_H

+#define MBED_PORTMAP_H

+

+#include "device.h"

+

+#if DEVICE_PORTIN || DEVICE_PORTOUT

+

+#ifdef __cplusplus

+extern "C" {

+#endif

+

+typedef struct port_s port_t;

+

+PinName port_pin(PortName port, int pin_n);

+

+void port_init (port_t *obj, PortName port, int mask, PinDirection dir);

+void port_mode (port_t *obj, PinMode mode);

+void port_dir  (port_t *obj, PinDirection dir);

+void port_write(port_t *obj, int value);

+int  port_read (port_t *obj);

+

+#ifdef __cplusplus

+}

+#endif

+#endif

+

+#endif

diff --git a/ext/pwmout_api.h b/ext/pwmout_api.h
new file mode 100644
index 0000000..3f518ec
--- /dev/null
+++ b/ext/pwmout_api.h
@@ -0,0 +1,49 @@
+/* mbed Microcontroller Library

+ * Copyright (c) 2006-2013 ARM Limited

+ *

+ * Licensed under the Apache License, Version 2.0 (the "License");

+ * you may not use this file except in compliance with the License.

+ * You may obtain a copy of the License at

+ *

+ *     http://www.apache.org/licenses/LICENSE-2.0

+ *

+ * Unless required by applicable law or agreed to in writing, software

+ * distributed under the License is distributed on an "AS IS" BASIS,

+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

+ * See the License for the specific language governing permissions and

+ * limitations under the License.

+ */

+#ifndef MBED_PWMOUT_API_H

+#define MBED_PWMOUT_API_H

+

+#include "device.h"

+

+#if DEVICE_PWMOUT

+

+#ifdef __cplusplus

+extern "C" {

+#endif

+

+typedef struct pwmout_s pwmout_t;

+

+void pwmout_init         (pwmout_t* obj, PinName pin);

+void pwmout_free         (pwmout_t* obj);

+

+void  pwmout_write       (pwmout_t* obj, float percent);

+float pwmout_read        (pwmout_t* obj);

+

+void pwmout_period       (pwmout_t* obj, float seconds);

+void pwmout_period_ms    (pwmout_t* obj, int ms);

+void pwmout_period_us    (pwmout_t* obj, int us);

+

+void pwmout_pulsewidth   (pwmout_t* obj, float seconds);

+void pwmout_pulsewidth_ms(pwmout_t* obj, int ms);

+void pwmout_pulsewidth_us(pwmout_t* obj, int us);

+

+#ifdef __cplusplus

+}

+#endif

+

+#endif

+

+#endif

diff --git a/ext/rtc_api.h b/ext/rtc_api.h
new file mode 100644
index 0000000..68949e3
--- /dev/null
+++ b/ext/rtc_api.h
@@ -0,0 +1,42 @@
+/* mbed Microcontroller Library

+ * Copyright (c) 2006-2013 ARM Limited

+ *

+ * Licensed under the Apache License, Version 2.0 (the "License");

+ * you may not use this file except in compliance with the License.

+ * You may obtain a copy of the License at

+ *

+ *     http://www.apache.org/licenses/LICENSE-2.0

+ *

+ * Unless required by applicable law or agreed to in writing, software

+ * distributed under the License is distributed on an "AS IS" BASIS,

+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

+ * See the License for the specific language governing permissions and

+ * limitations under the License.

+ */

+#ifndef MBED_RTC_API_H

+#define MBED_RTC_API_H

+

+#include "device.h"

+

+#if DEVICE_RTC

+

+#include <time.h>

+

+#ifdef __cplusplus

+extern "C" {

+#endif

+

+void rtc_init(void);

+void rtc_free(void);

+int rtc_isenabled(void);

+

+time_t rtc_read(void);

+void rtc_write(time_t t);

+

+#ifdef __cplusplus

+}

+#endif

+

+#endif

+

+#endif

diff --git a/ext/rtc_time.h b/ext/rtc_time.h
new file mode 100644
index 0000000..94af2c9
--- /dev/null
+++ b/ext/rtc_time.h
@@ -0,0 +1,85 @@
+/* mbed Microcontroller Library

+ * Copyright (c) 2006-2013 ARM Limited

+ *

+ * Licensed under the Apache License, Version 2.0 (the "License");

+ * you may not use this file except in compliance with the License.

+ * You may obtain a copy of the License at

+ *

+ *     http://www.apache.org/licenses/LICENSE-2.0

+ *

+ * Unless required by applicable law or agreed to in writing, software

+ * distributed under the License is distributed on an "AS IS" BASIS,

+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

+ * See the License for the specific language governing permissions and

+ * limitations under the License.

+ */

+

+#include <time.h>

+

+#ifdef __cplusplus

+extern "C" {

+#endif

+

+/** Implementation of the C time.h functions

+ *

+ * Provides mechanisms to set and read the current time, based

+ * on the microcontroller Real-Time Clock (RTC), plus some

+ * standard C manipulation and formating functions.

+ *

+ * Example:

+ * @code

+ * #include "mbed.h"

+ *

+ * int main() {

+ *     set_time(1256729737);  // Set RTC time to Wed, 28 Oct 2009 11:35:37

+ *

+ *     while(1) {

+ *         time_t seconds = time(NULL);

+ *

+ *         printf("Time as seconds since January 1, 1970 = %d\n", seconds);

+ *

+ *         printf("Time as a basic string = %s", ctime(&seconds));

+ *

+ *         char buffer[32];

+ *         strftime(buffer, 32, "%I:%M %p\n", localtime(&seconds));

+ *         printf("Time as a custom formatted string = %s", buffer);

+ *

+ *         wait(1);

+ *     }

+ * }

+ * @endcode

+ */

+

+/** Set the current time

+ *

+ * Initialises and sets the time of the microcontroller Real-Time Clock (RTC)

+ * to the time represented by the number of seconds since January 1, 1970

+ * (the UNIX timestamp).

+ *

+ * @param t Number of seconds since January 1, 1970 (the UNIX timestamp)

+ *

+ * Example:

+ * @code

+ * #include "mbed.h"

+ *

+ * int main() {

+ *     set_time(1256729737); // Set time to Wed, 28 Oct 2009 11:35:37

+ * }

+ * @endcode

+ */

+void set_time(time_t t);

+

+/** Attach an external RTC to be used for the C time functions

+ *

+ * Do not call this function from an interrupt while an RTC read/write operation may be occurring 

+ *

+ * @param read_rtc pointer to function which returns current UNIX timestamp

+ * @param write_rtc pointer to function which sets current UNIX timestamp, can be NULL

+ * @param init_rtc pointer to funtion which initializes RTC, can be NULL

+ * @param isenabled_rtc pointer to function wich returns if the rtc is enabled, can be NULL

+ */

+void attach_rtc(time_t (*read_rtc)(void), void (*write_rtc)(time_t), void (*init_rtc)(void), int (*isenabled_rtc)(void));

+

+#ifdef __cplusplus

+}

+#endif

diff --git a/ext/semihost_api.h b/ext/semihost_api.h
new file mode 100644
index 0000000..866521c
--- /dev/null
+++ b/ext/semihost_api.h
@@ -0,0 +1,93 @@
+/* mbed Microcontroller Library

+ * Copyright (c) 2006-2013 ARM Limited

+ *

+ * Licensed under the Apache License, Version 2.0 (the "License");

+ * you may not use this file except in compliance with the License.

+ * You may obtain a copy of the License at

+ *

+ *     http://www.apache.org/licenses/LICENSE-2.0

+ *

+ * Unless required by applicable law or agreed to in writing, software

+ * distributed under the License is distributed on an "AS IS" BASIS,

+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

+ * See the License for the specific language governing permissions and

+ * limitations under the License.

+ */

+#ifndef MBED_SEMIHOST_H

+#define MBED_SEMIHOST_H

+

+#include "device.h"

+#include "toolchain.h"

+

+#ifdef __cplusplus

+extern "C" {

+#endif

+

+#if DEVICE_SEMIHOST

+

+#ifndef __CC_ARM

+

+#if defined(__ICCARM__)

+inline int __semihost(int reason, const void *arg) {

+    return __semihosting(reason, (void*)arg);

+}

+#else

+

+#ifdef __thumb__

+#   define AngelSWI            0xAB

+#   define AngelSWIInsn        "bkpt"

+#   define AngelSWIAsm          bkpt

+#else

+#   define AngelSWI            0x123456

+#   define AngelSWIInsn        "swi"

+#   define AngelSWIAsm          swi

+#endif

+

+static inline int __semihost(int reason, const void *arg) {

+    int value;

+

+    asm volatile (

+       "mov r0, %1"          "\n\t"

+       "mov r1, %2"          "\n\t"

+       AngelSWIInsn " %a3"   "\n\t"

+       "mov %0, r0"

+       : "=r" (value)                                         /* output operands             */

+       : "r" (reason), "r" (arg), "i" (AngelSWI)              /* input operands              */

+       : "r0", "r1", "r2", "r3", "ip", "lr", "memory", "cc"   /* list of clobbered registers */

+    );

+

+    return value;

+}

+#endif

+#endif

+

+#if DEVICE_LOCALFILESYSTEM

+FILEHANDLE semihost_open(const char* name, int openmode);

+int semihost_close (FILEHANDLE fh);

+int semihost_read  (FILEHANDLE fh, unsigned char* buffer, unsigned int length, int mode);

+int semihost_write (FILEHANDLE fh, const unsigned char* buffer, unsigned int length, int mode);

+int semihost_ensure(FILEHANDLE fh);

+long semihost_flen (FILEHANDLE fh);

+int semihost_seek  (FILEHANDLE fh, long position);

+int semihost_istty (FILEHANDLE fh);

+

+int semihost_remove(const char *name);

+int semihost_rename(const char *old_name, const char *new_name);

+#endif

+

+int semihost_uid(char *uid);

+int semihost_reset(void);

+int semihost_vbus(void);

+int semihost_powerdown(void);

+int semihost_exit(void);

+

+int semihost_connected(void);

+int semihost_disabledebug(void);

+

+#endif

+

+#ifdef __cplusplus

+}

+#endif

+

+#endif

diff --git a/ext/serial_api.h b/ext/serial_api.h
new file mode 100644
index 0000000..3181734
--- /dev/null
+++ b/ext/serial_api.h
@@ -0,0 +1,302 @@
+/* mbed Microcontroller Library

+ * Copyright (c) 2006-2013 ARM Limited

+ *

+ * Licensed under the Apache License, Version 2.0 (the "License");

+ * you may not use this file except in compliance with the License.

+ * You may obtain a copy of the License at

+ *

+ *     http://www.apache.org/licenses/LICENSE-2.0

+ *

+ * Unless required by applicable law or agreed to in writing, software

+ * distributed under the License is distributed on an "AS IS" BASIS,

+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

+ * See the License for the specific language governing permissions and

+ * limitations under the License.

+ */

+#ifndef MBED_SERIAL_API_H

+#define MBED_SERIAL_API_H

+

+#include "device.h"

+#include "buffer.h"

+#include "dma_api.h"

+

+#if DEVICE_SERIAL

+

+#define SERIAL_EVENT_TX_SHIFT (2)

+#define SERIAL_EVENT_RX_SHIFT (8)

+

+#define SERIAL_EVENT_TX_MASK (0x00FC)

+#define SERIAL_EVENT_RX_MASK (0x3F00)

+

+#define SERIAL_EVENT_ERROR (1 << 1)

+

+/**

+ * @defgroup SerialTXEvents Serial TX Events Macros

+ *

+ * @{

+ */

+#define SERIAL_EVENT_TX_COMPLETE (1 << (SERIAL_EVENT_TX_SHIFT + 0))

+#define SERIAL_EVENT_TX_ALL      (SERIAL_EVENT_TX_COMPLETE)

+/**@}*/

+

+/**

+ * @defgroup SerialRXEvents Serial RX Events Macros

+ *

+ * @{

+ */

+#define SERIAL_EVENT_RX_COMPLETE        (1 << (SERIAL_EVENT_RX_SHIFT + 0))

+#define SERIAL_EVENT_RX_OVERRUN_ERROR   (1 << (SERIAL_EVENT_RX_SHIFT + 1))

+#define SERIAL_EVENT_RX_FRAMING_ERROR   (1 << (SERIAL_EVENT_RX_SHIFT + 2))

+#define SERIAL_EVENT_RX_PARITY_ERROR    (1 << (SERIAL_EVENT_RX_SHIFT + 3))

+#define SERIAL_EVENT_RX_OVERFLOW        (1 << (SERIAL_EVENT_RX_SHIFT + 4))

+#define SERIAL_EVENT_RX_CHARACTER_MATCH (1 << (SERIAL_EVENT_RX_SHIFT + 5))

+#define SERIAL_EVENT_RX_ALL             (SERIAL_EVENT_RX_OVERFLOW | SERIAL_EVENT_RX_PARITY_ERROR | \

+                                         SERIAL_EVENT_RX_FRAMING_ERROR | SERIAL_EVENT_RX_OVERRUN_ERROR | \

+                                         SERIAL_EVENT_RX_COMPLETE | SERIAL_EVENT_RX_CHARACTER_MATCH)

+/**@}*/

+

+#define SERIAL_RESERVED_CHAR_MATCH (255)

+

+typedef enum {

+    ParityNone = 0,

+    ParityOdd = 1,

+    ParityEven = 2,

+    ParityForced1 = 3,

+    ParityForced0 = 4

+} SerialParity;

+

+typedef enum {

+    RxIrq,

+    TxIrq

+} SerialIrq;

+

+typedef enum {

+    FlowControlNone,

+    FlowControlRTS,

+    FlowControlCTS,

+    FlowControlRTSCTS

+} FlowControl;

+

+typedef void (*uart_irq_handler)(uint32_t id, SerialIrq event);

+

+#if DEVICE_SERIAL_ASYNCH

+/** Asynch serial hal structure

+ */

+typedef struct {

+    struct serial_s serial;  /**< Target specific serial structure */

+    struct buffer_s tx_buff; /**< Tx buffer */

+    struct buffer_s rx_buff; /**< Rx buffer */

+    uint8_t char_match;      /**< Character to be matched */

+    uint8_t char_found;      /**< State of the matched character */

+} serial_t;

+

+#else

+/** Non-asynch serial hal structure

+ */

+typedef struct serial_s serial_t;

+

+#endif

+

+#ifdef __cplusplus

+extern "C" {

+#endif

+

+/**

+ * \defgroup GeneralSerial Serial Configuration Functions

+ * @{

+ */

+

+/** Initialize the serial peripheral. It sets the default parameters for serial

+ *  peripheral, and configure its specifieds pins.

+ *

+ * @param obj The serial object

+ * @param tx  The TX pin

+ * @param rx  The RX pin

+ */

+void serial_init(serial_t *obj, PinName tx, PinName rx);

+

+/** Release the serial peripheral, not currently invoked. It requires further

+ *  resource management.

+ *

+ * @param obj The serial object

+ */

+void serial_free(serial_t *obj);

+

+/** Configure the baud rate

+ *

+ * @param obj      The serial object

+ * @param baudrate The baud rate to be configured

+ */

+void serial_baud(serial_t *obj, int baudrate);

+

+/** Configure the format. Set the number of bits, parity and the number of stop bits

+ *

+ * @param obj       The serial object

+ * @param data_bits The number of data bits

+ * @param parity    The parity

+ * @param stop_bits The number of stop bits

+ */

+void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits);

+

+/** The serial interrupt handler registration.

+ *

+ * @param obj     The serial object

+ * @param handler The interrupt handler which will be invoked when interrupt fires.

+ * @param id      The SerialBase object

+ */

+void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id);

+

+/** Configure serial interrupt. This function is used for word-approach

+ *

+ * @param obj    The serial object

+ * @param irq    The serial IRQ type (RX or TX)

+ * @param enable Set to non-zero to enable events, or zero to disable them

+ */

+void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable);

+

+/** Get character. This is a blocking call, waiting for a character

+ *

+ * @param obj The serial object

+ */

+int  serial_getc(serial_t *obj);

+

+/** Put a character. This is a blocking call, waiting for a peripheral to be available

+ *  for writing

+ *

+ * @param obj The serial object

+ * @param c   The character to be sent

+ */

+void serial_putc(serial_t *obj, int c);

+

+/** Check if the serial peripheral is readable

+ *

+ * @param obj The serial object

+ * @return Non-zero value if a character can be read, 0 if nothing to read.

+ */

+int  serial_readable(serial_t *obj);

+

+/** Check if the serial peripheral is writable

+ *

+ * @param obj The serial object

+ * @return Non-zero value if a character can be written, 0 otherwise.

+ */

+int  serial_writable(serial_t *obj);

+

+/** Clear the serial peripheral

+ *

+ * @param obj The serial object

+ */

+void serial_clear(serial_t *obj);

+

+/** Set the break

+ *

+ * @param obj The serial object

+ */

+void serial_break_set(serial_t *obj);

+

+/** Clear the break

+ *

+ * @param obj The serial object

+ */

+void serial_break_clear(serial_t *obj);

+

+/** Configure the TX pin for UART function.

+ *

+ * @param tx The pin used for TX

+ */

+void serial_pinout_tx(PinName tx);

+

+/** Configure the serial for the flow control. It sets flow control in the hardware

+ *  if a serial peripheral supports it, otherwise software emulation is used.

+ *

+ * @param obj    The serial object

+ * @param type   The type of the flow control. Look at the available FlowControl types.

+ * @param rxflow The tx pin

+ * @param txflow The rx pin

+ */

+void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow);

+

+#if DEVICE_SERIAL_ASYNCH

+

+/**@}*/

+

+/**

+ * \defgroup AsynchSerial Asynchronous Serial Hardware Abstraction Layer

+ * @{

+ */

+

+/** Begin asynchronous TX transfer. The used buffer is specified in the serial object,

+ *  tx_buff

+ *

+ * @param obj       The serial object

+ * @param tx        The buffer for sending

+ * @param tx_length The number of words to transmit

+ * @param tx_width  The bit width of buffer word

+ * @param handler   The serial handler

+ * @param event     The logical OR of events to be registered

+ * @param hint      A suggestion for how to use DMA with this transfer

+ * @return Returns number of data transfered, or 0 otherwise

+ */

+int serial_tx_asynch(serial_t *obj, const void *tx, size_t tx_length, uint8_t tx_width, uint32_t handler, uint32_t event, DMAUsage hint);

+

+/** Begin asynchronous RX transfer (enable interrupt for data collecting)

+ *  The used buffer is specified in the serial object - rx_buff

+ *

+ * @param obj        The serial object

+ * @param rx         The buffer for sending

+ * @param rx_length  The number of words to transmit

+ * @param rx_width   The bit width of buffer word

+ * @param handler    The serial handler

+ * @param event      The logical OR of events to be registered

+ * @param handler    The serial handler

+ * @param char_match A character in range 0-254 to be matched

+ * @param hint       A suggestion for how to use DMA with this transfer

+ */

+void serial_rx_asynch(serial_t *obj, void *rx, size_t rx_length, uint8_t rx_width, uint32_t handler, uint32_t event, uint8_t char_match, DMAUsage hint);

+

+/** Attempts to determine if the serial peripheral is already in use for TX

+ *

+ * @param obj The serial object

+ * @return Non-zero if the RX transaction is ongoing, 0 otherwise

+ */

+uint8_t serial_tx_active(serial_t *obj);

+

+/** Attempts to determine if the serial peripheral is already in use for RX

+ *

+ * @param obj The serial object

+ * @return Non-zero if the RX transaction is ongoing, 0 otherwise

+ */

+uint8_t serial_rx_active(serial_t *obj);

+

+/** The asynchronous TX and RX handler.

+ *

+ * @param obj The serial object

+ * @return Returns event flags if a RX transfer termination condition was met or 0 otherwise

+ */

+int serial_irq_handler_asynch(serial_t *obj);

+

+/** Abort the ongoing TX transaction. It disables the enabled interupt for TX and

+ *  flush TX hardware buffer if TX FIFO is used

+ *

+ * @param obj The serial object

+ */

+void serial_tx_abort_asynch(serial_t *obj);

+

+/** Abort the ongoing RX transaction It disables the enabled interrupt for RX and

+ *  flush RX hardware buffer if RX FIFO is used

+ *

+ * @param obj The serial object

+ */

+void serial_rx_abort_asynch(serial_t *obj);

+

+/**@}*/

+

+#endif

+

+#ifdef __cplusplus

+}

+#endif

+

+#endif

+

+#endif

diff --git a/ext/sleep_api.h b/ext/sleep_api.h
new file mode 100644
index 0000000..9d25671
--- /dev/null
+++ b/ext/sleep_api.h
@@ -0,0 +1,64 @@
+/* mbed Microcontroller Library

+ * Copyright (c) 2006-2013 ARM Limited

+ *

+ * Licensed under the Apache License, Version 2.0 (the "License");

+ * you may not use this file except in compliance with the License.

+ * You may obtain a copy of the License at

+ *

+ *     http://www.apache.org/licenses/LICENSE-2.0

+ *

+ * Unless required by applicable law or agreed to in writing, software

+ * distributed under the License is distributed on an "AS IS" BASIS,

+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

+ * See the License for the specific language governing permissions and

+ * limitations under the License.

+ */

+#ifndef MBED_SLEEP_API_H

+#define MBED_SLEEP_API_H

+

+#include "device.h"

+

+#if DEVICE_SLEEP

+

+#ifdef __cplusplus

+extern "C" {

+#endif

+

+/** Send the microcontroller to sleep

+ *

+ * The processor is setup ready for sleep, and sent to sleep using __WFI(). In this mode, the

+ * system clock to the core is stopped until a reset or an interrupt occurs. This eliminates

+ * dynamic power used by the processor, memory systems and buses. The processor, peripheral and

+ * memory state are maintained, and the peripherals continue to work and can generate interrupts.

+ *

+ * The processor can be woken up by any internal peripheral interrupt or external pin interrupt.

+ *

+ * @note

+ *  The mbed interface semihosting is disconnected as part of going to sleep, and can not be restored.

+ * Flash re-programming and the USB serial port will remain active, but the mbed program will no longer be

+ * able to access the LocalFileSystem

+ */

+void sleep(void);

+

+/** Send the microcontroller to deep sleep

+ *

+ * This processor is setup ready for deep sleep, and sent to sleep using __WFI(). This mode

+ * has the same sleep features as sleep plus it powers down peripherals and clocks. All state

+ * is still maintained.

+ *

+ * The processor can only be woken up by an external interrupt on a pin or a watchdog timer.

+ *

+ * @note

+ *  The mbed interface semihosting is disconnected as part of going to sleep, and can not be restored.

+ * Flash re-programming and the USB serial port will remain active, but the mbed program will no longer be

+ * able to access the LocalFileSystem

+ */

+void deepsleep(void);

+

+#ifdef __cplusplus

+}

+#endif

+

+#endif

+

+#endif

diff --git a/ext/spi_api.h b/ext/spi_api.h
new file mode 100644
index 0000000..8235eb0
--- /dev/null
+++ b/ext/spi_api.h
@@ -0,0 +1,213 @@
+/* mbed Microcontroller Library

+ * Copyright (c) 2006-2013 ARM Limited

+ *

+ * Licensed under the Apache License, Version 2.0 (the "License");

+ * you may not use this file except in compliance with the License.

+ * You may obtain a copy of the License at

+ *

+ *     http://www.apache.org/licenses/LICENSE-2.0

+ *

+ * Unless required by applicable law or agreed to in writing, software

+ * distributed under the License is distributed on an "AS IS" BASIS,

+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

+ * See the License for the specific language governing permissions and

+ * limitations under the License.

+ */

+#ifndef MBED_SPI_API_H

+#define MBED_SPI_API_H

+

+#include "device.h"

+#include "dma_api.h"

+#include "buffer.h"

+

+#if DEVICE_SPI

+

+#define SPI_EVENT_ERROR       (1 << 1)

+#define SPI_EVENT_COMPLETE    (1 << 2)

+#define SPI_EVENT_RX_OVERFLOW (1 << 3)

+#define SPI_EVENT_ALL         (SPI_EVENT_ERROR | SPI_EVENT_COMPLETE | SPI_EVENT_RX_OVERFLOW)

+

+#define SPI_EVENT_INTERNAL_TRANSFER_COMPLETE (1 << 30) // internal flag to report an event occurred

+

+#define SPI_FILL_WORD         (0xFFFF)

+

+#if DEVICE_SPI_ASYNCH

+/** Asynch spi hal structure

+ */

+typedef struct {

+    struct spi_s spi;        /**< Target specific spi structure */

+    struct buffer_s tx_buff; /**< Tx buffer */

+    struct buffer_s rx_buff; /**< Rx buffer */

+} spi_t;

+

+#else

+/** Non-asynch spi hal structure

+ */

+typedef struct spi_s spi_t;

+

+#endif

+

+#ifdef __cplusplus

+extern "C" {

+#endif

+

+/**

+ * \defgroup GeneralSPI SPI Configuration Functions

+ * @{

+ */

+

+/** Initialize the SPI peripheral

+ *

+ * Configures the pins used by SPI, sets a default format and frequency, and enables the peripheral

+ * @param[out] obj  The SPI object to initialize

+ * @param[in]  mosi The pin to use for MOSI

+ * @param[in]  miso The pin to use for MISO

+ * @param[in]  sclk The pin to use for SCLK

+ * @param[in]  ssel The pin to use for SSEL

+ */

+void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel);

+

+/** Release a SPI object

+ *

+ * TODO: spi_free is currently unimplemented

+ * This will require reference counting at the C++ level to be safe

+ *

+ * Return the pins owned by the SPI object to their reset state

+ * Disable the SPI peripheral

+ * Disable the SPI clock

+ * @param[in] obj The SPI object to deinitialize

+ */

+void spi_free(spi_t *obj);

+

+/** Configure the SPI format

+ *

+ * Set the number of bits per frame, configure clock polarity and phase, shift order and master/slave mode

+ * @param[in,out] obj   The SPI object to configure

+ * @param[in]     bits  The number of bits per frame

+ * @param[in]     mode  The SPI mode (clock polarity, phase, and shift direction)

+ * @param[in]     slave Zero for master mode or non-zero for slave mode

+ */

+void spi_format(spi_t *obj, int bits, int mode, int slave);

+

+/** Set the SPI baud rate

+ *

+ * Actual frequency may differ from the desired frequency due to available dividers and bus clock

+ * Configures the SPI peripheral's baud rate

+ * @param[in,out] obj The SPI object to configure

+ * @param[in]     hz  The baud rate in Hz

+ */

+void spi_frequency(spi_t *obj, int hz);

+

+/**@}*/

+/**

+ * \defgroup SynchSPI Synchronous SPI Hardware Abstraction Layer

+ * @{

+ */

+

+/** Write a byte out in master mode and receive a value

+ *

+ * @param[in] obj   The SPI peripheral to use for sending

+ * @param[in] value The value to send

+ * @return Returns the value received during send

+ */

+int  spi_master_write(spi_t *obj, int value);

+

+/** Check if a value is available to read

+ *

+ * @param[in] obj The SPI peripheral to check

+ * @return non-zero if a value is available

+ */

+int  spi_slave_receive(spi_t *obj);

+

+/** Get a received value out of the SPI receive buffer in slave mode

+ *

+ * Blocks until a value is available

+ * @param[in] obj The SPI peripheral to read

+ * @return The value received

+ */

+int  spi_slave_read(spi_t *obj);

+

+/** Write a value to the SPI peripheral in slave mode

+ *

+ * Blocks until the SPI peripheral can be written to

+ * @param[in] obj   The SPI peripheral to write

+ * @param[in] value The value to write

+ */

+void spi_slave_write(spi_t *obj, int value);

+

+/** Checks if the specified SPI peripheral is in use

+ *

+ * @param[in] obj The SPI peripheral to check

+ * @return non-zero if the peripheral is currently transmitting

+ */

+int  spi_busy(spi_t *obj);

+

+/** Get the module number

+ *

+ * @param[in] obj The SPI peripheral to check

+ * @return The module number

+ */

+uint8_t spi_get_module(spi_t *obj);

+

+/**@}*/

+

+#if DEVICE_SPI_ASYNCH

+/**

+ * \defgroup AsynchSPI Asynchronous SPI Hardware Abstraction Layer

+ * @{

+ */

+

+/** Begin the SPI transfer. Buffer pointers and lengths are specified in tx_buff and rx_buff

+ *

+ * @param[in] obj       The SPI object which holds the transfer information

+ * @param[in] tx        The buffer to send

+ * @param[in] tx_length The number of words to transmit

+ * @param[in] rx        The buffer to receive

+ * @param[in] rx_length The number of words to receive

+ * @param[in] bit_width The bit width of buffer words

+ * @param[in] event     The logical OR of events to be registered

+ * @param[in] handler   SPI interrupt handler

+ * @param[in] hint      A suggestion for how to use DMA with this transfer

+ */

+void spi_master_transfer(spi_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length, uint8_t bit_width, uint32_t handler, uint32_t event, DMAUsage hint);

+

+/** The asynchronous IRQ handler

+ *

+ * Reads the received values out of the RX FIFO, writes values into the TX FIFO and checks for transfer termination

+ * conditions, such as buffer overflows or transfer complete.

+ * @param[in] obj     The SPI object which holds the transfer information

+ * @return event flags if a transfer termination condition was met or 0 otherwise.

+ */

+uint32_t spi_irq_handler_asynch(spi_t *obj);

+

+/** Attempts to determine if the SPI peripheral is already in use.

+ *

+ * If a temporary DMA channel has been allocated, peripheral is in use.

+ * If a permanent DMA channel has been allocated, check if the DMA channel is in use.  If not, proceed as though no DMA

+ * channel were allocated.

+ * If no DMA channel is allocated, check whether tx and rx buffers have been assigned.  For each assigned buffer, check

+ * if the corresponding buffer position is less than the buffer length.  If buffers do not indicate activity, check if

+ * there are any bytes in the FIFOs.

+ * @param[in] obj The SPI object to check for activity

+ * @return non-zero if the SPI port is active or zero if it is not.

+ */

+uint8_t spi_active(spi_t *obj);

+

+/** Abort an SPI transfer

+ *

+ * @param obj The SPI peripheral to stop

+ */

+void spi_abort_asynch(spi_t *obj);

+

+

+#endif

+

+/**@}*/

+

+#ifdef __cplusplus

+}

+#endif // __cplusplus

+

+#endif // SPI_DEVICE

+

+#endif // MBED_SPI_API_H

diff --git a/ext/ticker_api.h b/ext/ticker_api.h
new file mode 100644
index 0000000..5f24d27
--- /dev/null
+++ b/ext/ticker_api.h
@@ -0,0 +1,108 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_TICKER_API_H
+#define MBED_TICKER_API_H
+
+#include "device.h"
+
+typedef uint32_t timestamp_t;
+
+/** Ticker's event structure
+ */
+typedef struct ticker_event_s {
+    timestamp_t            timestamp; /**< Event's timestamp */
+    uint32_t               id;        /**< TimerEvent object */
+    struct ticker_event_s *next;      /**< Next event in the queue */
+} ticker_event_t;
+
+typedef void (*ticker_event_handler)(uint32_t id);
+
+/** Ticker's interface structure - required API for a ticker
+ */
+typedef struct {
+    void (*init)(void);                           /**< Init function */
+    uint32_t (*read)(void);                       /**< Read function */
+    void (*disable_interrupt)(void);              /**< Disable interrupt function */
+    void (*clear_interrupt)(void);                /**< Clear interrupt function */
+    void (*set_interrupt)(timestamp_t timestamp); /**< Set interrupt function */
+} ticker_interface_t;
+
+/** Tickers events queue structure
+ */
+typedef struct {
+    ticker_event_handler event_handler; /**< Event handler */
+    ticker_event_t *head;               /**< A pointer to head */
+} ticker_event_queue_t;
+
+/** Tickers data structure
+ */
+typedef struct {
+    const ticker_interface_t *interface; /**< Ticker's interface */
+    ticker_event_queue_t *queue;         /**< Ticker's events queue */
+} ticker_data_t;
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Initialize a ticker and sets the event handler
+ *
+ * @param data    The ticker's data
+ * @param handler A handler to be set
+ */
+void ticker_set_handler(const ticker_data_t *const data, ticker_event_handler handler);
+
+/** Irq handler which goes through the events to trigger events in the past.
+ *
+ * @param data    The ticker's data
+ */
+void ticker_irq_handler(const ticker_data_t *const data);
+
+/** Remove an event from the queue
+ *
+ * @param data The ticker's data
+ * @param obj  The event's queue to be removed
+ */
+void ticker_remove_event(const ticker_data_t *const data, ticker_event_t *obj);
+
+/** Insert an event from the queue
+ *
+ * @param data      The ticker's data
+ * @param obj       The event's queue to be removed
+ * @param timestamp The event's timestamp
+ * @param id        The event object
+ */
+void ticker_insert_event(const ticker_data_t *const data, ticker_event_t *obj, timestamp_t timestamp, uint32_t id);
+
+/** Read the current ticker's timestamp
+ *
+ * @param data The ticker's data
+ * @return The current timestamp
+ */
+timestamp_t ticker_read(const ticker_data_t *const data);
+
+/** Read the next event's timestamp
+ *
+ * @param data The ticker's data
+ * @return 1 if timestamp is pending event, 0 if there's no event pending
+ */
+int ticker_get_next_timestamp(const ticker_data_t *const data, timestamp_t *timestamp);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/ext/toolchain.h b/ext/toolchain.h
new file mode 100644
index 0000000..ce5f1aa
--- /dev/null
+++ b/ext/toolchain.h
@@ -0,0 +1,35 @@
+/* mbed Microcontroller Library

+ * Copyright (c) 2006-2013 ARM Limited

+ *

+ * Licensed under the Apache License, Version 2.0 (the "License");

+ * you may not use this file except in compliance with the License.

+ * You may obtain a copy of the License at

+ *

+ *     http://www.apache.org/licenses/LICENSE-2.0

+ *

+ * Unless required by applicable law or agreed to in writing, software

+ * distributed under the License is distributed on an "AS IS" BASIS,

+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

+ * See the License for the specific language governing permissions and

+ * limitations under the License.

+ */

+#ifndef MBED_TOOLCHAIN_H

+#define MBED_TOOLCHAIN_H

+

+#if defined(TOOLCHAIN_ARM)

+#include <rt_sys.h>

+#endif

+

+#ifndef FILEHANDLE

+typedef int FILEHANDLE;

+#endif

+

+#if defined (__ICCARM__)

+#   define WEAK     __weak

+#   define PACKED   __packed

+#else

+#   define WEAK     __attribute__((weak))

+#   define PACKED   __attribute__((packed))

+#endif

+

+#endif

diff --git a/ext/us_ticker_api.h b/ext/us_ticker_api.h
new file mode 100644
index 0000000..b8e1ed3
--- /dev/null
+++ b/ext/us_ticker_api.h
@@ -0,0 +1,78 @@
+/* mbed Microcontroller Library

+ * Copyright (c) 2006-2015 ARM Limited

+ *

+ * Licensed under the Apache License, Version 2.0 (the "License");

+ * you may not use this file except in compliance with the License.

+ * You may obtain a copy of the License at

+ *

+ *     http://www.apache.org/licenses/LICENSE-2.0

+ *

+ * Unless required by applicable law or agreed to in writing, software

+ * distributed under the License is distributed on an "AS IS" BASIS,

+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

+ * See the License for the specific language governing permissions and

+ * limitations under the License.

+ */

+#ifndef MBED_US_TICKER_API_H

+#define MBED_US_TICKER_API_H

+

+#include <stdint.h>

+#include "ticker_api.h"

+

+#ifdef __cplusplus

+extern "C" {

+#endif

+

+/**

+ * \defgroup UsTicker Microseconds Ticker Functions

+ * @{

+ */

+

+/** Get ticker's data

+ *

+ * @return The low power ticker data

+ */

+const ticker_data_t* get_us_ticker_data(void);

+

+

+/** The wrapper for ticker_irq_handler, to pass us ticker's data

+ *

+ */

+void us_ticker_irq_handler(void);

+

+/* HAL us ticker */

+

+/** Initialize the ticker

+ *

+ */

+void us_ticker_init(void);

+

+/** Read the current counter

+ *

+ * @return The current timer's counter value in microseconds

+ */

+uint32_t us_ticker_read(void);

+

+/** Set interrupt for specified timestamp

+ *

+ * @param timestamp The time in microseconds to be set

+ */

+void us_ticker_set_interrupt(timestamp_t timestamp);

+

+/** Disable us ticker interrupt

+ *

+ */

+void us_ticker_disable_interrupt(void);

+

+/** Clear us ticker interrupt

+ *

+ */

+void us_ticker_clear_interrupt(void);

+

+/**@}*/

+

+#ifdef __cplusplus

+}

+#endif

+

+#endif

diff --git a/ext/wait_api.h b/ext/wait_api.h
new file mode 100644
index 0000000..b92c731
--- /dev/null
+++ b/ext/wait_api.h
@@ -0,0 +1,66 @@
+/* mbed Microcontroller Library

+ * Copyright (c) 2006-2013 ARM Limited

+ *

+ * Licensed under the Apache License, Version 2.0 (the "License");

+ * you may not use this file except in compliance with the License.

+ * You may obtain a copy of the License at

+ *

+ *     http://www.apache.org/licenses/LICENSE-2.0

+ *

+ * Unless required by applicable law or agreed to in writing, software

+ * distributed under the License is distributed on an "AS IS" BASIS,

+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

+ * See the License for the specific language governing permissions and

+ * limitations under the License.

+ */

+#ifndef MBED_WAIT_API_H

+#define MBED_WAIT_API_H

+

+#ifdef __cplusplus

+extern "C" {

+#endif

+

+/** Generic wait functions.

+ *

+ * These provide simple NOP type wait capabilities.

+ *

+ * Example:

+ * @code

+ * #include "mbed.h"

+ *

+ * DigitalOut heartbeat(LED1);

+ *

+ * int main() {

+ *     while (1) {

+ *         heartbeat = 1;

+ *         wait(0.5);

+ *         heartbeat = 0;

+ *         wait(0.5);

+ *     }

+ * }

+ */

+

+/** Waits for a number of seconds, with microsecond resolution (within

+ *  the accuracy of single precision floating point).

+ *

+ *  @param s number of seconds to wait

+ */

+void wait(float s);

+

+/** Waits a number of milliseconds.

+ *

+ *  @param ms the whole number of milliseconds to wait

+ */

+void wait_ms(int ms);

+

+/** Waits a number of microseconds.

+ *

+ *  @param us the whole number of microseconds to wait

+ */

+void wait_us(int us);

+

+#ifdef __cplusplus

+}

+#endif

+

+#endif