From 4b6e0102d20d9ab060ce930e4b846c8be446bb06 Mon Sep 17 00:00:00 2001 From: Vasil Zlatanov Date: Mon, 12 Dec 2016 21:51:10 +0000 Subject: public push --- part_1/ex2/output_files/ex2_top.sta.rpt | 533 ++++++++++++++++++++++++++++++++ 1 file changed, 533 insertions(+) create mode 100644 part_1/ex2/output_files/ex2_top.sta.rpt (limited to 'part_1/ex2/output_files/ex2_top.sta.rpt') diff --git a/part_1/ex2/output_files/ex2_top.sta.rpt b/part_1/ex2/output_files/ex2_top.sta.rpt new file mode 100644 index 0000000..7e76881 --- /dev/null +++ b/part_1/ex2/output_files/ex2_top.sta.rpt @@ -0,0 +1,533 @@ +TimeQuest Timing Analyzer report for ex2_top +Thu Nov 17 09:56:12 2016 +Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. TimeQuest Timing Analyzer Summary + 3. Parallel Compilation + 4. Clocks + 5. Slow 1100mV 85C Model Fmax Summary + 6. Timing Closure Recommendations + 7. Slow 1100mV 85C Model Setup Summary + 8. Slow 1100mV 85C Model Hold Summary + 9. Slow 1100mV 85C Model Recovery Summary + 10. Slow 1100mV 85C Model Removal Summary + 11. Slow 1100mV 85C Model Minimum Pulse Width Summary + 12. Slow 1100mV 85C Model Metastability Summary + 13. Slow 1100mV 0C Model Fmax Summary + 14. Slow 1100mV 0C Model Setup Summary + 15. Slow 1100mV 0C Model Hold Summary + 16. Slow 1100mV 0C Model Recovery Summary + 17. Slow 1100mV 0C Model Removal Summary + 18. Slow 1100mV 0C Model Minimum Pulse Width Summary + 19. Slow 1100mV 0C Model Metastability Summary + 20. Fast 1100mV 85C Model Setup Summary + 21. Fast 1100mV 85C Model Hold Summary + 22. Fast 1100mV 85C Model Recovery Summary + 23. Fast 1100mV 85C Model Removal Summary + 24. Fast 1100mV 85C Model Minimum Pulse Width Summary + 25. Fast 1100mV 85C Model Metastability Summary + 26. Fast 1100mV 0C Model Setup Summary + 27. Fast 1100mV 0C Model Hold Summary + 28. Fast 1100mV 0C Model Recovery Summary + 29. Fast 1100mV 0C Model Removal Summary + 30. Fast 1100mV 0C Model Minimum Pulse Width Summary + 31. Fast 1100mV 0C Model Metastability Summary + 32. Multicorner Timing Analysis Summary + 33. Board Trace Model Assignments + 34. Input Transition Times + 35. Signal Integrity Metrics (Slow 1100mv 0c Model) + 36. Signal Integrity Metrics (Slow 1100mv 85c Model) + 37. Signal Integrity Metrics (Fast 1100mv 0c Model) + 38. Signal Integrity Metrics (Fast 1100mv 85c Model) + 39. Clock Transfers + 40. Report TCCS + 41. Report RSKM + 42. Unconstrained Paths Summary + 43. Unconstrained Input Ports + 44. Unconstrained Output Ports + 45. Unconstrained Input Ports + 46. Unconstrained Output Ports + 47. TimeQuest Timing Analyzer Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2016 Altera Corporation. All rights reserved. +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, the Altera Quartus Prime License Agreement, +the Altera MegaCore Function License Agreement, or other +applicable license agreement, including, without limitation, +that your use is for the sole purpose of programming logic +devices manufactured by Altera and sold by Altera or its +authorized distributors. Please refer to the applicable +agreement for further details. + + + ++---------------------------------------------------------------------------------+ +; TimeQuest Timing Analyzer Summary ; ++-----------------------+---------------------------------------------------------+ +; Quartus Prime Version ; Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition ; +; Timing Analyzer ; TimeQuest ; +; Revision Name ; ex2_top ; +; Device Family ; Cyclone V ; +; Device Name ; 5CSEMA5F31C6 ; +; Timing Models ; Final ; +; Delay Model ; Combined ; +; Rise/Fall Delays ; Enabled ; ++-----------------------+---------------------------------------------------------+ + + ++------------------------------------------+ +; Parallel Compilation ; ++----------------------------+-------------+ +; Processors ; Number ; ++----------------------------+-------------+ +; Number detected on machine ; 8 ; +; Maximum allowed ; 4 ; +; ; ; +; Average used ; 1.02 ; +; Maximum used ; 4 ; +; ; ; +; Usage by Processor ; % Time Used ; +; Processor 1 ; 100.0% ; +; Processor 2 ; 1.4% ; +; Processors 3-4 ; 0.3% ; ++----------------------------+-------------+ + + +---------- +; Clocks ; +---------- +No clocks to report. + + +-------------------------------------- +; Slow 1100mV 85C Model Fmax Summary ; +-------------------------------------- +No paths to report. + + +---------------------------------- +; Timing Closure Recommendations ; +---------------------------------- +HTML report is unavailable in plain text report export. + + +--------------------------------------- +; Slow 1100mV 85C Model Setup Summary ; +--------------------------------------- +No paths to report. + + +-------------------------------------- +; Slow 1100mV 85C Model Hold Summary ; +-------------------------------------- +No paths to report. + + +------------------------------------------ +; Slow 1100mV 85C Model Recovery Summary ; +------------------------------------------ +No paths to report. + + +----------------------------------------- +; Slow 1100mV 85C Model Removal Summary ; +----------------------------------------- +No paths to report. + + +----------------------------------------------------- +; Slow 1100mV 85C Model Minimum Pulse Width Summary ; +----------------------------------------------------- +No paths to report. + + +----------------------------------------------- +; Slow 1100mV 85C Model Metastability Summary ; +----------------------------------------------- +No synchronizer chains to report. + + +------------------------------------- +; Slow 1100mV 0C Model Fmax Summary ; +------------------------------------- +No paths to report. + + +-------------------------------------- +; Slow 1100mV 0C Model Setup Summary ; +-------------------------------------- +No paths to report. + + +------------------------------------- +; Slow 1100mV 0C Model Hold Summary ; +------------------------------------- +No paths to report. + + +----------------------------------------- +; Slow 1100mV 0C Model Recovery Summary ; +----------------------------------------- +No paths to report. + + +---------------------------------------- +; Slow 1100mV 0C Model Removal Summary ; +---------------------------------------- +No paths to report. + + +---------------------------------------------------- +; Slow 1100mV 0C Model Minimum Pulse Width Summary ; +---------------------------------------------------- +No paths to report. + + +---------------------------------------------- +; Slow 1100mV 0C Model Metastability Summary ; +---------------------------------------------- +No synchronizer chains to report. + + +--------------------------------------- +; Fast 1100mV 85C Model Setup Summary ; +--------------------------------------- +No paths to report. + + +-------------------------------------- +; Fast 1100mV 85C Model Hold Summary ; +-------------------------------------- +No paths to report. + + +------------------------------------------ +; Fast 1100mV 85C Model Recovery Summary ; +------------------------------------------ +No paths to report. + + +----------------------------------------- +; Fast 1100mV 85C Model Removal Summary ; +----------------------------------------- +No paths to report. + + +----------------------------------------------------- +; Fast 1100mV 85C Model Minimum Pulse Width Summary ; +----------------------------------------------------- +No paths to report. + + +----------------------------------------------- +; Fast 1100mV 85C Model Metastability Summary ; +----------------------------------------------- +No synchronizer chains to report. + + +-------------------------------------- +; Fast 1100mV 0C Model Setup Summary ; +-------------------------------------- +No paths to report. + + +------------------------------------- +; Fast 1100mV 0C Model Hold Summary ; +------------------------------------- +No paths to report. + + +----------------------------------------- +; Fast 1100mV 0C Model Recovery Summary ; +----------------------------------------- +No paths to report. + + +---------------------------------------- +; Fast 1100mV 0C Model Removal Summary ; +---------------------------------------- +No paths to report. + + +---------------------------------------------------- +; Fast 1100mV 0C Model Minimum Pulse Width Summary ; +---------------------------------------------------- +No paths to report. + + +---------------------------------------------- +; Fast 1100mV 0C Model Metastability Summary ; +---------------------------------------------- +No synchronizer chains to report. + + ++----------------------------------------------------------------------------+ +; Multicorner Timing Analysis Summary ; ++------------------+-------+------+----------+---------+---------------------+ +; Clock ; Setup ; Hold ; Recovery ; Removal ; Minimum Pulse Width ; ++------------------+-------+------+----------+---------+---------------------+ +; Worst-case Slack ; N/A ; N/A ; N/A ; N/A ; N/A ; +; Design-wide TNS ; 0.0 ; 0.0 ; 0.0 ; 0.0 ; 0.0 ; ++------------------+-------+------+----------+---------+---------------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Board Trace Model Assignments ; ++---------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ +; Pin ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ; ++---------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ +; HEX0[0] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX0[1] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX0[2] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX0[3] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX0[4] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX0[5] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX0[6] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; ++---------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ + + ++----------------------------------------------------------+ +; Input Transition Times ; ++-------+--------------+-----------------+-----------------+ +; Pin ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ; ++-------+--------------+-----------------+-----------------+ +; SW[0] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; SW[1] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; SW[2] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; SW[3] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; ++-------+--------------+-----------------+-----------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Signal Integrity Metrics (Slow 1100mv 0c Model) ; ++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; ++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; HEX0[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; +; HEX0[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; +; HEX0[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; +; HEX0[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; +; HEX0[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; +; HEX0[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; +; HEX0[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; ++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Signal Integrity Metrics (Slow 1100mv 85c Model) ; ++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; ++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; HEX0[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; +; HEX0[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; +; HEX0[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; +; HEX0[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; +; HEX0[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; +; HEX0[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; +; HEX0[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; ++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Signal Integrity Metrics (Fast 1100mv 0c Model) ; ++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; ++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; HEX0[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; +; HEX0[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; +; HEX0[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; +; HEX0[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; +; HEX0[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; +; HEX0[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; +; HEX0[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; ++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Signal Integrity Metrics (Fast 1100mv 85c Model) ; ++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; ++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; HEX0[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; +; HEX0[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; +; HEX0[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; +; HEX0[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; +; HEX0[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; +; HEX0[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; +; HEX0[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; ++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ + + +------------------- +; Clock Transfers ; +------------------- +Nothing to report. + + +--------------- +; Report TCCS ; +--------------- +No dedicated SERDES Transmitter circuitry present in device or used in design + + +--------------- +; Report RSKM ; +--------------- +No non-DPA dedicated SERDES Receiver circuitry present in device or used in design + + ++------------------------------------------------+ +; Unconstrained Paths Summary ; ++---------------------------------+-------+------+ +; Property ; Setup ; Hold ; ++---------------------------------+-------+------+ +; Illegal Clocks ; 0 ; 0 ; +; Unconstrained Clocks ; 0 ; 0 ; +; Unconstrained Input Ports ; 4 ; 4 ; +; Unconstrained Input Port Paths ; 28 ; 28 ; +; Unconstrained Output Ports ; 7 ; 7 ; +; Unconstrained Output Port Paths ; 28 ; 28 ; ++---------------------------------+-------+------+ + + ++---------------------------------------------------------------------------------------------------+ +; Unconstrained Input Ports ; ++------------+--------------------------------------------------------------------------------------+ +; Input Port ; Comment ; ++------------+--------------------------------------------------------------------------------------+ +; SW[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SW[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SW[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SW[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ++------------+--------------------------------------------------------------------------------------+ + + ++-----------------------------------------------------------------------------------------------------+ +; Unconstrained Output Ports ; ++-------------+---------------------------------------------------------------------------------------+ +; Output Port ; Comment ; ++-------------+---------------------------------------------------------------------------------------+ +; HEX0[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX0[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX0[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX0[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX0[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX0[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX0[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ++-------------+---------------------------------------------------------------------------------------+ + + ++---------------------------------------------------------------------------------------------------+ +; Unconstrained Input Ports ; ++------------+--------------------------------------------------------------------------------------+ +; Input Port ; Comment ; ++------------+--------------------------------------------------------------------------------------+ +; SW[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SW[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SW[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SW[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ++------------+--------------------------------------------------------------------------------------+ + + ++-----------------------------------------------------------------------------------------------------+ +; Unconstrained Output Ports ; ++-------------+---------------------------------------------------------------------------------------+ +; Output Port ; Comment ; ++-------------+---------------------------------------------------------------------------------------+ +; HEX0[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX0[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX0[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX0[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX0[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX0[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX0[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ++-------------+---------------------------------------------------------------------------------------+ + + ++------------------------------------+ +; TimeQuest Timing Analyzer Messages ; ++------------------------------------+ +Info: ******************************************************************* +Info: Running Quartus Prime TimeQuest Timing Analyzer + Info: Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition + Info: Processing started: Thu Nov 17 09:56:07 2016 +Info: Command: quartus_sta ex2 -c ex2_top +Info: qsta_default_script.tcl version: #1 +Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. +Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected +Info (21077): Low junction temperature is 0 degrees C +Info (21077): High junction temperature is 85 degrees C +Critical Warning (332012): Synopsys Design Constraints File file not found: 'ex2_top.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design. +Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0" +Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed. +Warning (332068): No clocks defined in design. +Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty" +Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers. +Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON +Info (332159): No clocks to report +Info: Analyzing Slow 1100mV 85C Model +Info (332140): No fmax paths to report +Info (332140): No Setup paths to report +Info (332140): No Hold paths to report +Info (332140): No Recovery paths to report +Info (332140): No Removal paths to report +Info (332140): No Minimum Pulse Width paths to report +Info: Analyzing Slow 1100mV 0C Model +Info (334003): Started post-fitting delay annotation +Info (334004): Delay annotation completed successfully +Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0" +Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed. +Warning (332068): No clocks defined in design. +Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers. +Info (332140): No fmax paths to report +Info (332140): No Setup paths to report +Info (332140): No Hold paths to report +Info (332140): No Recovery paths to report +Info (332140): No Removal paths to report +Info (332140): No Minimum Pulse Width paths to report +Info: Analyzing Fast 1100mV 85C Model +Info (334003): Started post-fitting delay annotation +Info (334004): Delay annotation completed successfully +Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0" +Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed. +Warning (332068): No clocks defined in design. +Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers. +Info (332140): No Setup paths to report +Info (332140): No Hold paths to report +Info (332140): No Recovery paths to report +Info (332140): No Removal paths to report +Info (332140): No Minimum Pulse Width paths to report +Info: Analyzing Fast 1100mV 0C Model +Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0" +Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed. +Warning (332068): No clocks defined in design. +Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers. +Info (332140): No Setup paths to report +Info (332140): No Hold paths to report +Info (332140): No Recovery paths to report +Info (332140): No Removal paths to report +Info (332140): No Minimum Pulse Width paths to report +Info (332102): Design is not fully constrained for setup requirements +Info (332102): Design is not fully constrained for hold requirements +Info: Quartus Prime TimeQuest Timing Analyzer was successful. 0 errors, 6 warnings + Info: Peak virtual memory: 1196 megabytes + Info: Processing ended: Thu Nov 17 09:56:12 2016 + Info: Elapsed time: 00:00:05 + Info: Total CPU time (on all processors): 00:00:04 + + -- cgit v1.2.3-54-g00ecf