From 4b6e0102d20d9ab060ce930e4b846c8be446bb06 Mon Sep 17 00:00:00 2001 From: Vasil Zlatanov Date: Mon, 12 Dec 2016 21:51:10 +0000 Subject: public push --- part_2/ex5/ex5_top_nativelink_simulation.rpt | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) create mode 100644 part_2/ex5/ex5_top_nativelink_simulation.rpt (limited to 'part_2/ex5/ex5_top_nativelink_simulation.rpt') diff --git a/part_2/ex5/ex5_top_nativelink_simulation.rpt b/part_2/ex5/ex5_top_nativelink_simulation.rpt new file mode 100644 index 0000000..833b429 --- /dev/null +++ b/part_2/ex5/ex5_top_nativelink_simulation.rpt @@ -0,0 +1,21 @@ +Info: Start Nativelink Simulation process +Info: NativeLink has detected Verilog design -- Verilog simulation models will be used + +========= EDA Simulation Settings ===================== + +Sim Mode : RTL +Family : cyclonev +Quartus root : c:/altera/16.0/quartus/bin64/ +Quartus sim root : c:/altera/16.0/quartus/eda/sim_lib +Simulation Tool : modelsim-altera +Simulation Language : verilog +Simulation Mode : GUI +Sim Output File : +Sim SDF file : +Sim dir : simulation\modelsim + +======================================================= + +Info: Starting NativeLink simulation with ModelSim-Altera software +Sourced NativeLink script c:/altera/16.0/quartus/common/tcl/internal/nativelink/modelsim.tcl +Info: Spawning ModelSim-Altera Simulation software -- cgit v1.2.3-54-g00ecf