From 4b6e0102d20d9ab060ce930e4b846c8be446bb06 Mon Sep 17 00:00:00 2001
From: Vasil Zlatanov <v@skozl.com>
Date: Mon, 12 Dec 2016 21:51:10 +0000
Subject: public push

---
 .../simulation/modelsim/ex10a_run_msim_rtl_verilog.do   |  9 +++++++++
 part_3/ex10a/simulation/modelsim/tb_spi2dac.do          | 17 +++++++++++++++++
 2 files changed, 26 insertions(+)
 create mode 100644 part_3/ex10a/simulation/modelsim/ex10a_run_msim_rtl_verilog.do
 create mode 100644 part_3/ex10a/simulation/modelsim/tb_spi2dac.do

(limited to 'part_3/ex10a/simulation')

diff --git a/part_3/ex10a/simulation/modelsim/ex10a_run_msim_rtl_verilog.do b/part_3/ex10a/simulation/modelsim/ex10a_run_msim_rtl_verilog.do
new file mode 100644
index 0000000..7c53536
--- /dev/null
+++ b/part_3/ex10a/simulation/modelsim/ex10a_run_msim_rtl_verilog.do
@@ -0,0 +1,9 @@
+transcript on
+if {[file exists rtl_work]} {
+	vdel -lib rtl_work -all
+}
+vlib rtl_work
+vmap work rtl_work
+
+vlog -vlog01compat -work work +incdir+C:/VERI/part_3/ex10a {C:/VERI/part_3/ex10a/spi2dac.v}
+
diff --git a/part_3/ex10a/simulation/modelsim/tb_spi2dac.do b/part_3/ex10a/simulation/modelsim/tb_spi2dac.do
new file mode 100644
index 0000000..b12a7d7
--- /dev/null
+++ b/part_3/ex10a/simulation/modelsim/tb_spi2dac.do
@@ -0,0 +1,17 @@
+add wave -position end  sysclk
+add wave -position end -hexadecimal data_in
+add wave -position end load
+add wave -position end  dac_sdi
+add wave -position end  dac_cs
+add wave -position end  dac_sck
+add wave -position end  dac_ld
+force sysclk 1 0, 0 10ns -r 20ns
+force data_in 10'h23b
+force load 0
+run 200ns
+force load 1
+run 400ns
+force load 0
+run 20us
+
+
-- 
cgit v1.2.3-54-g00ecf