From 4b6e0102d20d9ab060ce930e4b846c8be446bb06 Mon Sep 17 00:00:00 2001 From: Vasil Zlatanov Date: Mon, 12 Dec 2016 21:51:10 +0000 Subject: public push --- part_3/ex13/ex13_top.v | 47 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 47 insertions(+) create mode 100644 part_3/ex13/ex13_top.v (limited to 'part_3/ex13/ex13_top.v') diff --git a/part_3/ex13/ex13_top.v b/part_3/ex13/ex13_top.v new file mode 100644 index 0000000..d73043a --- /dev/null +++ b/part_3/ex13/ex13_top.v @@ -0,0 +1,47 @@ +module ex13_top ( + CLOCK_50, + DAC_SDI, + DAC_CS, + DAC_LD, + DAC_SCK, + PWM_OUT +); + input CLOCK_50; + output DAC_SDI,DAC_CS,DAC_SCK,DAC_LD,PWM_OUT; + + wire CLOCK_DIVIDED; + wire [9:0] A,D; + + divider_5000 DIV0 (CLOCK_50, CLOCK_DIVIDED); + + counter_16 COUNT0 ( + .clock(CLOCK_50), + .enable(CLOCK_DIVIDED), + .reset(1'b1), + .count(A[9:0]) + ); + + ROM ROM0 ( + .address(A), + .clock(CLOCK_DIVIDED), + .q(D[9:0]) + ); + + spi2dac SPI0 ( + .sysclk(CLOCK_50), + .data_in(D[9:0]), + .load(CLOCK_DIVIDED), + .dac_sdi(DAC_SDI), + .dac_cs(DAC_CS), + .dac_sck(DAC_SCK), + .dac_ld(DAC_LD) + ); + + pwm PWM0 ( + .clk(CLOCK_50), + .data_in(D[9:0]), + .load(CLOCK_DIVIDED), + .pwm_out(PWM_OUT) + ); + +endmodule \ No newline at end of file -- cgit v1.2.3-54-g00ecf