From 4b6e0102d20d9ab060ce930e4b846c8be446bb06 Mon Sep 17 00:00:00 2001 From: Vasil Zlatanov Date: Mon, 12 Dec 2016 21:51:10 +0000 Subject: public push --- part_4/ex16/mult4.v | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) create mode 100644 part_4/ex16/mult4.v (limited to 'part_4/ex16/mult4.v') diff --git a/part_4/ex16/mult4.v b/part_4/ex16/mult4.v new file mode 100644 index 0000000..30a1798 --- /dev/null +++ b/part_4/ex16/mult4.v @@ -0,0 +1,35 @@ +//------------------------------ +// Module name: allpass processor +// Function: Simply to pass input to output +// Creator: Peter Cheung +// Version: 1.1 +// Date: 24 Jan 2014 +//------------------------------ + +module processor (sysclk, data_in, data_out); + + input sysclk; // system clock + input [9:0] data_in; // 10-bit input data + output [9:0] data_out; // 10-bit output data + + wire sysclk; + wire [9:0] data_in; + reg [9:0] data_out; + wire [9:0] x,y,z; + + parameter ADC_OFFSET = 10'h181; + parameter DAC_OFFSET = 10'h200; + + assign x = data_in[9:0] - ADC_OFFSET; // x is input in 2's complement + + // This part should include your own processing hardware + // ... that takes x to produce y + // ... In this case, it is ALL PASS. + multiply_4 MULT4 (x,y); + + // Now clock y output with system clock + always @(posedge sysclk) + data_out <= y + DAC_OFFSET; + +endmodule + \ No newline at end of file -- cgit v1.2.3-54-g00ecf