From 4b6e0102d20d9ab060ce930e4b846c8be446bb06 Mon Sep 17 00:00:00 2001
From: Vasil Zlatanov <v@skozl.com>
Date: Mon, 12 Dec 2016 21:51:10 +0000
Subject: public push

---
 part_4/ex16/pulse_gen.v | 43 +++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 43 insertions(+)
 create mode 100644 part_4/ex16/pulse_gen.v

(limited to 'part_4/ex16/pulse_gen.v')

diff --git a/part_4/ex16/pulse_gen.v b/part_4/ex16/pulse_gen.v
new file mode 100644
index 0000000..d82fe49
--- /dev/null
+++ b/part_4/ex16/pulse_gen.v
@@ -0,0 +1,43 @@
+//------------------------------
+// Module name: pulse_gen (Moore)
+// Function: Generate one clock pulse on +ve edge of input
+// Creator:  Peter Cheung
+// Version:  1.0
+// Date:     29 Jan 2014
+//------------------------------
+
+module pulse_gen(pulse, in, clk);
+
+	output 			pulse;	// output pulse lasting one clk cycle
+	input 			in;		// input, +ve edge to be detected
+	input 			clk;		// clock signal
+
+	reg [1:0]	state;
+	reg	pulse;
+	
+	parameter	IDLE = 2'b0;	// state coding for IDLE state
+	parameter	IN_HIGH = 2'b01;
+	parameter	WAIT_LOW = 2'b10;  
+	
+	initial state = IDLE;
+	
+	always @ (posedge clk) 
+		begin	
+			pulse <= 0;		 // default output
+			case (state)
+			IDLE: 	if (in == 1'b1) begin
+							state <= IN_HIGH;	pulse <= 1'b1; end
+						else 
+							state <= IDLE; 
+			IN_HIGH: if (in == 1'b1) 
+							state <= WAIT_LOW;
+						else 
+							state <= IDLE; 
+			WAIT_LOW: if (in == 1'b1) 
+							state <= WAIT_LOW;
+						 else  
+							state <= IDLE;
+			default: ;
+			endcase
+		end			//... always
+endmodule
-- 
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