From 4b6e0102d20d9ab060ce930e4b846c8be446bb06 Mon Sep 17 00:00:00 2001 From: Vasil Zlatanov Date: Mon, 12 Dec 2016 21:51:10 +0000 Subject: public push --- part_4/ex16/simulation/modelsim/init.do | 20 +++++++++++++++++ part_4/ex16/simulation/modelsim/init_adc.do | 23 ++++++++++++++++++++ part_4/ex16/simulation/modelsim/init_cal.do | 17 +++++++++++++++ part_4/ex16/simulation/modelsim/init_spi.do | 25 ++++++++++++++++++++++ .../modelsim/top_run_msim_rtl_verilog.do | 9 ++++++++ 5 files changed, 94 insertions(+) create mode 100644 part_4/ex16/simulation/modelsim/init.do create mode 100644 part_4/ex16/simulation/modelsim/init_adc.do create mode 100644 part_4/ex16/simulation/modelsim/init_cal.do create mode 100644 part_4/ex16/simulation/modelsim/init_spi.do create mode 100644 part_4/ex16/simulation/modelsim/top_run_msim_rtl_verilog.do (limited to 'part_4/ex16/simulation') diff --git a/part_4/ex16/simulation/modelsim/init.do b/part_4/ex16/simulation/modelsim/init.do new file mode 100644 index 0000000..c39709a --- /dev/null +++ b/part_4/ex16/simulation/modelsim/init.do @@ -0,0 +1,20 @@ +add wave -position end sim:/top/CLOCK_50 +add wave -position end sim:/top/clock_25 +add wave -position end sim:/top/tone_1k +add wave -position end sim:/top/ld_pulse +add wave -position end sim:/top/reset +add wave -position end sim:/top/DAC_SDI +add wave -position end sim:/top/DAC_SCK +add wave -position end sim:/top/DAC_CS +add wave -position end sim:/top/DAC_LD +add wave -position end sim:/top/BUTTON0 +add wave -position end -hexadecimal sim:/top/mux_out +add wave -position end -hexadecimal sim:/top/SPI_1/state +add wave -position end sim:/top/SPI_1/sck_ena +add wave -position end sim:/top/SPI_1/clk_half +force CLOCK_50 1 0, 0 {10 ns} -r {20 ns} +alias ck "run 20ns" +force BUTTON0 0 +ck +force BUTTON0 1 +ck diff --git a/part_4/ex16/simulation/modelsim/init_adc.do b/part_4/ex16/simulation/modelsim/init_adc.do new file mode 100644 index 0000000..1269f00 --- /dev/null +++ b/part_4/ex16/simulation/modelsim/init_adc.do @@ -0,0 +1,23 @@ +add wave sysclk +add wave clk_1MHz +add wave start +add wave data_from_adc +add wave data_valid +add wave -hexadecimal data_out +add wave adc_cs +add wave adc_sck +add wave adc_done +add wave adc_din +add wave -hexadecimal shift_reg +add wave -hexadecimal state +add wave shift_ena +force sysclk 1 0, 0 {10 ns} -r 20 ns +force start 0 +run 200ns +force start 1 +run 200ns +force start 0 +force data_from_adc 0 @ 1us, 1 @ 6us, 0 @ 8us, 1 @ 10us, 0 @ 13us, 1 @ 15us + +run 20us + diff --git a/part_4/ex16/simulation/modelsim/init_cal.do b/part_4/ex16/simulation/modelsim/init_cal.do new file mode 100644 index 0000000..a6d14b9 --- /dev/null +++ b/part_4/ex16/simulation/modelsim/init_cal.do @@ -0,0 +1,17 @@ +add wave -position end sim:/top/CLOCK_50 +add wave -position end sim:/top/clk_10k +add wave -position end sim:/top/ld_pulse +add wave -position end -hexadecimal sim:/top/SW +add wave -position end -hexadecimal sim:/top/data +add wave -position end sim:/top/DAC_SDI +add wave -position end sim:/top/DAC_SCK +add wave -position end sim:/top/DAC_CS +add wave -position end sim:/top/DAC_LD +add wave -position end sim:/top/ADC_SDI +add wave -position end sim:/top/ADC_SCK +add wave -position end sim:/top/ADC_CS +add wave -position end sim:/top/ADC_SDO +force CLOCK_50 1 0, 0 10ns -r 20ns +force SW 10'h20f +force ADC_SDO 1 +run 400us diff --git a/part_4/ex16/simulation/modelsim/init_spi.do b/part_4/ex16/simulation/modelsim/init_spi.do new file mode 100644 index 0000000..b99ff7a --- /dev/null +++ b/part_4/ex16/simulation/modelsim/init_spi.do @@ -0,0 +1,25 @@ +add wave -position end sim:/spi2dac/sysclk +add wave -position end sim:/spi2dac/div2 +add wave -position end sim:/spi2dac/div4 +add wave -position end sim:/spi2dac/status_busy +add wave -position end -hexadecimal sim:/spi2dac/data_in +add wave -position end sim:/spi2dac/ld +add wave -position end -hexadecimal sim:/spi2dac/state +add wave -position end sim:/spi2dac/sck_ena +add wave -position end sim:/spi2dac/dac_ld +add wave -position end -hexadecimal sim:/spi2dac/shift_reg +add wave -position end sim:/spi2dac/spi_sdo +add wave -position end sim:/spi2dac/spi_cs +add wave -position end sim:/spi2dac/spi_sck +add wave -position end sim:/spi2dac/spi_ld +add wave -position end sim:/spi2dac/rs_state +force -freeze sim:/spi2dac/sysclk 1 0, 0 {10 ns} -r 20 ns +run 20ns +force data_in 10'h2c3 +force ld 0 +run 20ns +force ld 1 +run 20ns +force ld 0 +run 20ns + \ No newline at end of file diff --git a/part_4/ex16/simulation/modelsim/top_run_msim_rtl_verilog.do b/part_4/ex16/simulation/modelsim/top_run_msim_rtl_verilog.do new file mode 100644 index 0000000..377f3cd --- /dev/null +++ b/part_4/ex16/simulation/modelsim/top_run_msim_rtl_verilog.do @@ -0,0 +1,9 @@ +transcript on +if {[file exists rtl_work]} { + vdel -lib rtl_work -all +} +vlib rtl_work +vmap work rtl_work + +vlog -vlog01compat -work work +incdir+Z:/Dropbox/_My\ Documents/E2\ Digital/adc_dac {Z:/Dropbox/_My Documents/E2 Digital/adc_dac/spi2adc.v} + -- cgit v1.2.3-54-g00ecf