From 4b6e0102d20d9ab060ce930e4b846c8be446bb06 Mon Sep 17 00:00:00 2001
From: Vasil Zlatanov <v@skozl.com>
Date: Mon, 12 Dec 2016 21:51:10 +0000
Subject: public push

---
 part_4/ex19/variable_echo.v | 59 +++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 59 insertions(+)
 create mode 100644 part_4/ex19/variable_echo.v

(limited to 'part_4/ex19/variable_echo.v')

diff --git a/part_4/ex19/variable_echo.v b/part_4/ex19/variable_echo.v
new file mode 100644
index 0000000..9b86f02
--- /dev/null
+++ b/part_4/ex19/variable_echo.v
@@ -0,0 +1,59 @@
+module processor (sysclk, data_in, data_out, data_valid, SW, HEX0, HEX1, HEX2);
+
+	input			sysclk;		// system clock
+	input			data_valid;
+	input [9:0]		data_in;		// 10-bit input data
+	input [8:0]		SW;
+	output [9:0] 	data_out;	// 10-bit output data
+	output [6:0] 	HEX0, HEX1, HEX2;
+
+	wire				sysclk;
+	wire [9:0]		data_in;
+	reg [9:0] 		data_out;
+	wire [9:0]		x,y;
+	wire [8:0]		RAM_out;
+	wire 				pulse;
+	wire [19:0]		segnum;
+	wire [12:0]		count_13;
+	wire [3:0]		BCD_0, BCD_1, BCD_2, BCD_3, BCD_4;
+
+	parameter 		ADC_OFFSET = 10'h181;
+	parameter 		DAC_OFFSET = 10'h200;
+
+	assign x = data_in[9:0] - ADC_OFFSET;		// x is input in 2's complement
+	
+	assign y = x - {RAM_out[8],RAM_out[8:0]};
+	
+	pulse_gen PULSE0 (pulse, data_valid, sysclk);
+	
+	counter_13 COUNT13 (
+		.clock(~data_valid),
+		.enable(1'b0),
+		.count(count_13),
+		.reset(1'b1)
+		);
+	
+	RAM DELAY1024 (
+	.clock(sysclk),
+	.data(y[9:1]),
+	.wren(pulse),
+	.rden(pulse),
+	.rdaddress(count_13),
+	.wraddress(count_13 + {SW[8:0],4'b0000}),
+	.q(RAM_out)
+	);
+	
+	multiply_k MULTK (SW,segnum);
+	
+	bin2bcd_16 BIN0 (segnum[19:10], BCD_0, BCD_1, BCD_2, BCD_3, BCD_4);
+	
+	hex_to_7seg SEG0 (HEX0, BCD_0);
+	hex_to_7seg SEG1 (HEX1, BCD_1);
+	hex_to_7seg SEG2 (HEX2, BCD_2);
+	
+	//  Now clock y output with system clock
+	always @(posedge sysclk)
+		data_out <=  y + DAC_OFFSET;
+		
+endmodule
+	
\ No newline at end of file
-- 
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