From 4b6e0102d20d9ab060ce930e4b846c8be446bb06 Mon Sep 17 00:00:00 2001 From: Vasil Zlatanov Date: Mon, 12 Dec 2016 21:51:10 +0000 Subject: public push --- part_4/mylib/clktick_16.v | 42 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) create mode 100644 part_4/mylib/clktick_16.v (limited to 'part_4/mylib/clktick_16.v') diff --git a/part_4/mylib/clktick_16.v b/part_4/mylib/clktick_16.v new file mode 100644 index 0000000..e6b99eb --- /dev/null +++ b/part_4/mylib/clktick_16.v @@ -0,0 +1,42 @@ +// Design Name : clktick_16 +// File Name : clktick.v +// Function : divide an input clock signal by n+1 +//----------------------------------------------------- + +module clktick_16 ( + clkin, // Clock input to the design + enable, // enable clk divider + N, // Clock division factor is N+1 + tick // pulse_out goes high for one cycle (n+1) clock cycles +); // End of port list + +parameter N_BIT = 16; +//-------------Input Ports----------------------------- +input clkin; +input enable; +input [N_BIT-1:0] N; + +//-------------Output Ports---------------------------- +output tick; + +//-------------Output Ports Data Type------------------ +// Output port can be a storage element (reg) or a wire +reg [N_BIT-1:0] count; +reg tick; + +initial tick = 1'b0; + +//------------ Main Body of the module ------------------------ + + always @ (posedge clkin) + if (enable == 1'b1) + if (count == 0) begin + tick <= 1'b1; + count <= N; + end + else begin + tick <= 1'b0; + count <= count - 1'b1; + end + +endmodule // End of Module clktick \ No newline at end of file -- cgit v1.2.3-54-g00ecf