From 4b6e0102d20d9ab060ce930e4b846c8be446bb06 Mon Sep 17 00:00:00 2001 From: Vasil Zlatanov Date: Mon, 12 Dec 2016 21:51:10 +0000 Subject: public push --- part_4/ex16/add3_ge5.v | 31 + part_4/ex16/bin2bcd_16.v | 109 + part_4/ex16/clktick_16.v | 42 + part_4/ex16/delay_ram.v | 220 ++ part_4/ex16/ex16_top.asm.rpt | 92 + part_4/ex16/ex16_top.eda.rpt | 96 + part_4/ex16/ex16_top.fit.rpt | 2026 ++++++++++++++++++ part_4/ex16/ex16_top.flow.rpt | 131 ++ part_4/ex16/ex16_top.map.rpt | 629 ++++++ part_4/ex16/ex16_top.sta.rpt | 809 +++++++ part_4/ex16/ex16_top.v | 56 + part_4/ex16/hex_to_7seg.v | 38 + part_4/ex16/mult4.v | 35 + part_4/ex16/multiply_k.v | 107 + part_4/ex16/pulse_gen.v | 43 + part_4/ex16/pwm.v | 25 + part_4/ex16/simulation/modelsim/init.do | 20 + part_4/ex16/simulation/modelsim/init_adc.do | 23 + part_4/ex16/simulation/modelsim/init_cal.do | 17 + part_4/ex16/simulation/modelsim/init_spi.do | 25 + .../modelsim/top_run_msim_rtl_verilog.do | 9 + part_4/ex16/spi2adc.v | 150 ++ part_4/ex16/spi2dac.v | 128 ++ part_4/ex17/FIFO.v | 159 ++ part_4/ex17/FIFO_bb.v | 120 ++ part_4/ex17/ex17_top.v | 48 + part_4/ex17/output_files/ex17_top.asm.rpt | 92 + part_4/ex17/output_files/ex17_top.fit.rpt | 2124 +++++++++++++++++++ part_4/ex17/output_files/ex17_top.flow.rpt | 129 ++ part_4/ex17/output_files/ex17_top.map.rpt | 714 +++++++ part_4/ex17/output_files/ex17_top.sta.rpt | 791 +++++++ part_4/ex17/single_echo.v | 43 + part_4/ex18/FIFO.v | 159 ++ part_4/ex18/FIFO_bb.v | 120 ++ part_4/ex18/ex18_top.v | 48 + part_4/ex18/multi_echo.v | 52 + part_4/ex18/output_files/ex18_top.asm.rpt | 92 + part_4/ex18/output_files/ex18_top.fit.rpt | 2039 ++++++++++++++++++ part_4/ex18/output_files/ex18_top.flow.rpt | 127 ++ part_4/ex18/output_files/ex18_top.map.rpt | 714 +++++++ part_4/ex18/output_files/ex18_top.sta.rpt | 791 +++++++ part_4/ex19/RAM.v | 221 ++ part_4/ex19/RAM_bb.v | 166 ++ part_4/ex19/ex19_top.v | 45 + part_4/ex19/output_files/ex19_top.asm.rpt | 92 + part_4/ex19/output_files/ex19_top.fit.rpt | 2226 ++++++++++++++++++++ part_4/ex19/output_files/ex19_top.flow.rpt | 127 ++ part_4/ex19/output_files/ex19_top.map.rpt | 946 +++++++++ part_4/ex19/output_files/ex19_top.sta.rpt | 820 +++++++ part_4/ex19/variable_echo.v | 59 + part_4/mylib/add3_ge5.v | 31 + part_4/mylib/bin2bcd_16.v | 109 + part_4/mylib/clktick_16.v | 42 + part_4/mylib/counter_13.v | 24 + part_4/mylib/hex_to_7seg.v | 38 + part_4/mylib/multiply_4.v | 107 + part_4/mylib/multiply_k.v | 107 + part_4/mylib/pulse_gen.v | 43 + part_4/mylib/pwm.v | 25 + part_4/mylib/spi2adc.v | 157 ++ part_4/mylib/spi2dac.v | 135 ++ 61 files changed, 18743 insertions(+) create mode 100644 part_4/ex16/add3_ge5.v create mode 100644 part_4/ex16/bin2bcd_16.v create mode 100644 part_4/ex16/clktick_16.v create mode 100644 part_4/ex16/delay_ram.v create mode 100644 part_4/ex16/ex16_top.asm.rpt create mode 100644 part_4/ex16/ex16_top.eda.rpt create mode 100644 part_4/ex16/ex16_top.fit.rpt create mode 100644 part_4/ex16/ex16_top.flow.rpt create mode 100644 part_4/ex16/ex16_top.map.rpt create mode 100644 part_4/ex16/ex16_top.sta.rpt create mode 100644 part_4/ex16/ex16_top.v create mode 100644 part_4/ex16/hex_to_7seg.v create mode 100644 part_4/ex16/mult4.v create mode 100644 part_4/ex16/multiply_k.v create mode 100644 part_4/ex16/pulse_gen.v create mode 100644 part_4/ex16/pwm.v create mode 100644 part_4/ex16/simulation/modelsim/init.do create mode 100644 part_4/ex16/simulation/modelsim/init_adc.do create mode 100644 part_4/ex16/simulation/modelsim/init_cal.do create mode 100644 part_4/ex16/simulation/modelsim/init_spi.do create mode 100644 part_4/ex16/simulation/modelsim/top_run_msim_rtl_verilog.do create mode 100644 part_4/ex16/spi2adc.v create mode 100644 part_4/ex16/spi2dac.v create mode 100644 part_4/ex17/FIFO.v create mode 100644 part_4/ex17/FIFO_bb.v create mode 100644 part_4/ex17/ex17_top.v create mode 100644 part_4/ex17/output_files/ex17_top.asm.rpt create mode 100644 part_4/ex17/output_files/ex17_top.fit.rpt create mode 100644 part_4/ex17/output_files/ex17_top.flow.rpt create mode 100644 part_4/ex17/output_files/ex17_top.map.rpt create mode 100644 part_4/ex17/output_files/ex17_top.sta.rpt create mode 100644 part_4/ex17/single_echo.v create mode 100644 part_4/ex18/FIFO.v create mode 100644 part_4/ex18/FIFO_bb.v create mode 100644 part_4/ex18/ex18_top.v create mode 100644 part_4/ex18/multi_echo.v create mode 100644 part_4/ex18/output_files/ex18_top.asm.rpt create mode 100644 part_4/ex18/output_files/ex18_top.fit.rpt create mode 100644 part_4/ex18/output_files/ex18_top.flow.rpt create mode 100644 part_4/ex18/output_files/ex18_top.map.rpt create mode 100644 part_4/ex18/output_files/ex18_top.sta.rpt create mode 100644 part_4/ex19/RAM.v create mode 100644 part_4/ex19/RAM_bb.v create mode 100644 part_4/ex19/ex19_top.v create mode 100644 part_4/ex19/output_files/ex19_top.asm.rpt create mode 100644 part_4/ex19/output_files/ex19_top.fit.rpt create mode 100644 part_4/ex19/output_files/ex19_top.flow.rpt create mode 100644 part_4/ex19/output_files/ex19_top.map.rpt create mode 100644 part_4/ex19/output_files/ex19_top.sta.rpt create mode 100644 part_4/ex19/variable_echo.v create mode 100644 part_4/mylib/add3_ge5.v create mode 100644 part_4/mylib/bin2bcd_16.v create mode 100644 part_4/mylib/clktick_16.v create mode 100644 part_4/mylib/counter_13.v create mode 100644 part_4/mylib/hex_to_7seg.v create mode 100644 part_4/mylib/multiply_4.v create mode 100644 part_4/mylib/multiply_k.v create mode 100644 part_4/mylib/pulse_gen.v create mode 100644 part_4/mylib/pwm.v create mode 100644 part_4/mylib/spi2adc.v create mode 100644 part_4/mylib/spi2dac.v (limited to 'part_4') diff --git a/part_4/ex16/add3_ge5.v b/part_4/ex16/add3_ge5.v new file mode 100644 index 0000000..0daf78a --- /dev/null +++ b/part_4/ex16/add3_ge5.v @@ -0,0 +1,31 @@ +//------------------------------ +// Module name: add3_ge5 +// Function: Add 3 to input if it is 5 or above +// Creator: Peter Cheung +// Version: 1.0 +// Date: 21 Jan 2014 +//------------------------------ + +module add3_ge5(w,a); + input [3:0] w; + output [3:0] a; + reg [3:0] a; + + always @ (w) + case (w) + 4'b0000: a <= 4'b0000; + 4'b0001: a <= 4'b0001; + 4'b0010: a <= 4'b0010; + 4'b0011: a <= 4'b0011; + 4'b0100: a <= 4'b0100; + 4'b0101: a <= 4'b1000; + 4'b0110: a <= 4'b1001; + 4'b0111: a <= 4'b1010; + 4'b1000: a <= 4'b1011; + 4'b1001: a <= 4'b1100; + 4'b1010: a <= 4'b1101; + 4'b1011: a <= 4'b1110; + 4'b1100: a <= 4'b1111; + default: a <= 4'b0000; // a cannot be 13 or larger, else overflow + endcase +endmodule \ No newline at end of file diff --git a/part_4/ex16/bin2bcd_16.v b/part_4/ex16/bin2bcd_16.v new file mode 100644 index 0000000..b25d0bd --- /dev/null +++ b/part_4/ex16/bin2bcd_16.v @@ -0,0 +1,109 @@ +//------------------------------ +// Module name: bin2bcd_16 +// Function: Converts a 16-bit binary number to 5 digits BCD +// .... it uses a shift-and-add3 algorithm +// Creator: Peter Cheung +// Version: 2.0 (Correct mistake - problem with numbers 0x5000 or larger) +// Date: 24 Nov 2016 +//------------------------------ +// For more explanation of how this work, see +// ... instructions on wwww.ee.ic.ac.uk/pcheung/teaching/E2_experiment + +module bin2bcd_16 (B, BCD_0, BCD_1, BCD_2, BCD_3, BCD_4); + + input [15:0] B; // binary input number + output [3:0] BCD_0, BCD_1, BCD_2, BCD_3, BCD_4; // BCD digit LSD to MSD + + wire [3:0] w1,w2,w3,w4,w5,w6,w7,w8,w9,w10,w11,w12,w13; + wire [3:0] w14,w15,w16,w17,w18,w19,w20,w21,w22,w23,w24,w25; + wire [3:0] w26,w27,w28,w29,w30,w31,w32,w33,w34,w35; + wire [3:0] a0,a1,a2,a3,a4,a5,a6,a7,a8,a9,a10,a11,a12,a13; + wire [3:0] a14,a15,a16,a17,a18,a19,a20,a21,a22,a23,a24,a25; + wire [3:0] a26,a27,a28,a29,a30,a31,a32,a33,a34,a35; + + // Instantiate a tree of add3-if-greater than or equal to 5 cells + // ... input is w_n, and output is a_n + add3_ge5 A1 (w1,a1); + add3_ge5 A2 (w2,a2); + add3_ge5 A3 (w3,a3); + add3_ge5 A4 (w4,a4); + add3_ge5 A5 (w5,a5); + add3_ge5 A6 (w6,a6); + add3_ge5 A7 (w7,a7); + add3_ge5 A8 (w8,a8); + add3_ge5 A9 (w9,a9); + add3_ge5 A10 (w10,a10); + add3_ge5 A11 (w11,a11); + add3_ge5 A12 (w12,a12); + add3_ge5 A13 (w13,a13); + add3_ge5 A14 (w14,a14); + add3_ge5 A15 (w15,a15); + add3_ge5 A16 (w16,a16); + add3_ge5 A17 (w17,a17); + add3_ge5 A18 (w18,a18); + add3_ge5 A19 (w19,a19); + add3_ge5 A20 (w20,a20); + add3_ge5 A21 (w21,a21); + add3_ge5 A22 (w22,a22); + add3_ge5 A23 (w23,a23); + add3_ge5 A24 (w24,a24); + add3_ge5 A25 (w25,a25); + add3_ge5 A26 (w26,a26); + add3_ge5 A27 (w27,a27); + add3_ge5 A28 (w28,a28); + add3_ge5 A29 (w29,a29); + add3_ge5 A30 (w30,a30); + add3_ge5 A31 (w31,a31); + add3_ge5 A32 (w32,a32); + add3_ge5 A33 (w33,a33); + add3_ge5 A34 (w34,a34); + add3_ge5 A35 (w35,a35); + + // wire the tree of add3 modules together + assign w1 = {1'b0,B[15:13]}; // w_n is the input port to module a_n + assign w2 = {a1[2:0], B[12]}; + assign w3 = {a2[2:0], B[11]}; + assign w4 = {1'b0,a1[3],a2[3],a3[3]}; + assign w5 = {a3[2:0], B[10]}; + assign w6 = {a4[2:0], a5[3]}; + assign w7 = {a5[2:0], B[9]}; + assign w8 = {a6[2:0], a7[3]}; + assign w9 = {a7[2:0], B[8]}; + assign w10 = {1'b0, a4[3], a6[3], a8[3]}; + assign w11 = {a8[2:0], a9[3]}; + assign w12 = {a9[2:0], B[7]}; + assign w13 = {a10[2:0], a11[3]}; + assign w14 = {a11[2:0], a12[3]}; + assign w15 = {a12[2:0], B[6]}; + assign w16 = {a13[2:0], a14[3]}; + assign w17 = {a14[2:0], a15[3]}; + assign w18 = {a15[2:0], B[5]}; + assign w19 = {1'b0, a10[3], a13[3], a16[3]}; + assign w20 = {a16[2:0], a17[3]}; + assign w21 = {a17[2:0], a18[3]}; + assign w22 = {a18[2:0], B[4]}; + assign w23 = {a19[2:0], a20[3]}; + assign w24 = {a20[2:0], a21[3]}; + assign w25 = {a21[2:0], a22[3]}; + assign w26 = {a22[2:0], B[3]}; + assign w27 = {a23[2:0], a24[3]}; + assign w28 = {a24[2:0], a25[3]}; + assign w29 = {a25[2:0], a26[3]}; + assign w30 = {a26[2:0], B[2]}; + assign w31 = {1'b0,a19[3], a23[3], a27[3]}; + assign w32 = {a27[2:0], a28[3]}; + assign w33 = {a28[2:0], a29[3]}; + assign w34 = {a29[2:0], a30[3]}; + assign w35 = {a30[2:0], B[1]}; + + // connect up to four BCD digit outputs + assign BCD_0 = {a35[2:0],B[0]}; + assign BCD_1 = {a34[2:0],a35[3]}; + assign BCD_2 = {a33[2:0],a34[3]}; + assign BCD_3 = {a32[2:0],a33[3]}; + assign BCD_4 = {a31[2:0],a32[3]}; +endmodule + + + + diff --git a/part_4/ex16/clktick_16.v b/part_4/ex16/clktick_16.v new file mode 100644 index 0000000..e6b99eb --- /dev/null +++ b/part_4/ex16/clktick_16.v @@ -0,0 +1,42 @@ +// Design Name : clktick_16 +// File Name : clktick.v +// Function : divide an input clock signal by n+1 +//----------------------------------------------------- + +module clktick_16 ( + clkin, // Clock input to the design + enable, // enable clk divider + N, // Clock division factor is N+1 + tick // pulse_out goes high for one cycle (n+1) clock cycles +); // End of port list + +parameter N_BIT = 16; +//-------------Input Ports----------------------------- +input clkin; +input enable; +input [N_BIT-1:0] N; + +//-------------Output Ports---------------------------- +output tick; + +//-------------Output Ports Data Type------------------ +// Output port can be a storage element (reg) or a wire +reg [N_BIT-1:0] count; +reg tick; + +initial tick = 1'b0; + +//------------ Main Body of the module ------------------------ + + always @ (posedge clkin) + if (enable == 1'b1) + if (count == 0) begin + tick <= 1'b1; + count <= N; + end + else begin + tick <= 1'b0; + count <= count - 1'b1; + end + +endmodule // End of Module clktick \ No newline at end of file diff --git a/part_4/ex16/delay_ram.v b/part_4/ex16/delay_ram.v new file mode 100644 index 0000000..23d49af --- /dev/null +++ b/part_4/ex16/delay_ram.v @@ -0,0 +1,220 @@ +// megafunction wizard: %RAM: 2-PORT% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altsyncram + +// ============================================================ +// File Name: delay_ram.v +// Megafunction Name(s): +// altsyncram +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 13.1.0 Build 162 10/23/2013 SJ Web Edition +// ************************************************************ + + +//Copyright (C) 1991-2013 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module delay_ram ( + clock, + data, + rdaddress, + rden, + wraddress, + wren, + q); + + input clock; + input [8:0] data; + input [12:0] rdaddress; + input rden; + input [12:0] wraddress; + input wren; + output [8:0] q; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_off +`endif + tri1 clock; + tri1 rden; + tri0 wren; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_on +`endif + + wire [8:0] sub_wire0; + wire [8:0] q = sub_wire0[8:0]; + + altsyncram altsyncram_component ( + .address_a (wraddress), + .clock0 (clock), + .data_a (data), + .rden_b (rden), + .wren_a (wren), + .address_b (rdaddress), + .q_b (sub_wire0), + .aclr0 (1'b0), + .aclr1 (1'b0), + .addressstall_a (1'b0), + .addressstall_b (1'b0), + .byteena_a (1'b1), + .byteena_b (1'b1), + .clock1 (1'b1), + .clocken0 (1'b1), + .clocken1 (1'b1), + .clocken2 (1'b1), + .clocken3 (1'b1), + .data_b ({9{1'b1}}), + .eccstatus (), + .q_a (), + .rden_a (1'b1), + .wren_b (1'b0)); + defparam + altsyncram_component.address_aclr_b = "NONE", + altsyncram_component.address_reg_b = "CLOCK0", + altsyncram_component.clock_enable_input_a = "BYPASS", + altsyncram_component.clock_enable_input_b = "BYPASS", + altsyncram_component.clock_enable_output_b = "BYPASS", + altsyncram_component.intended_device_family = "Cyclone III", + altsyncram_component.lpm_type = "altsyncram", + altsyncram_component.numwords_a = 8192, + altsyncram_component.numwords_b = 8192, + altsyncram_component.operation_mode = "DUAL_PORT", + altsyncram_component.outdata_aclr_b = "NONE", + altsyncram_component.outdata_reg_b = "CLOCK0", + altsyncram_component.power_up_uninitialized = "FALSE", + altsyncram_component.rdcontrol_reg_b = "CLOCK0", + altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE", + altsyncram_component.widthad_a = 13, + altsyncram_component.widthad_b = 13, + altsyncram_component.width_a = 9, + altsyncram_component.width_b = 9, + altsyncram_component.width_byteena_a = 1; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" +// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0" +// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0" +// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0" +// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0" +// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0" +// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "9" +// Retrieval info: PRIVATE: BlankMemory NUMERIC "1" +// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" +// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0" +// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" +// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0" +// Retrieval info: PRIVATE: CLRdata NUMERIC "0" +// Retrieval info: PRIVATE: CLRq NUMERIC "0" +// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0" +// Retrieval info: PRIVATE: CLRrren NUMERIC "0" +// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0" +// Retrieval info: PRIVATE: CLRwren NUMERIC "0" +// Retrieval info: PRIVATE: Clock NUMERIC "0" +// Retrieval info: PRIVATE: Clock_A NUMERIC "0" +// Retrieval info: PRIVATE: Clock_B NUMERIC "0" +// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" +// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0" +// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0" +// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B" +// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" +// Retrieval info: PRIVATE: JTAG_ID STRING "NONE" +// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" +// Retrieval info: PRIVATE: MEMSIZE NUMERIC "73728" +// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0" +// Retrieval info: PRIVATE: MIFfilename STRING "" +// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2" +// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0" +// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1" +// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" +// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2" +// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3" +// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3" +// Retrieval info: PRIVATE: REGdata NUMERIC "1" +// Retrieval info: PRIVATE: REGq NUMERIC "1" +// Retrieval info: PRIVATE: REGrdaddress NUMERIC "1" +// Retrieval info: PRIVATE: REGrren NUMERIC "1" +// Retrieval info: PRIVATE: REGwraddress NUMERIC "1" +// Retrieval info: PRIVATE: REGwren NUMERIC "1" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0" +// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1" +// Retrieval info: PRIVATE: VarWidth NUMERIC "0" +// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "9" +// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "9" +// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "9" +// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "9" +// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0" +// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0" +// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0" +// Retrieval info: PRIVATE: enable NUMERIC "0" +// Retrieval info: PRIVATE: rden NUMERIC "1" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE" +// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0" +// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" +// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS" +// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" +// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "8192" +// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "8192" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT" +// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE" +// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK0" +// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" +// Retrieval info: CONSTANT: RDCONTROL_REG_B STRING "CLOCK0" +// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE" +// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "13" +// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "13" +// Retrieval info: CONSTANT: WIDTH_A NUMERIC "9" +// Retrieval info: CONSTANT: WIDTH_B NUMERIC "9" +// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" +// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" +// Retrieval info: USED_PORT: data 0 0 9 0 INPUT NODEFVAL "data[8..0]" +// Retrieval info: USED_PORT: q 0 0 9 0 OUTPUT NODEFVAL "q[8..0]" +// Retrieval info: USED_PORT: rdaddress 0 0 13 0 INPUT NODEFVAL "rdaddress[12..0]" +// Retrieval info: USED_PORT: rden 0 0 0 0 INPUT VCC "rden" +// Retrieval info: USED_PORT: wraddress 0 0 13 0 INPUT NODEFVAL "wraddress[12..0]" +// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren" +// Retrieval info: CONNECT: @address_a 0 0 13 0 wraddress 0 0 13 0 +// Retrieval info: CONNECT: @address_b 0 0 13 0 rdaddress 0 0 13 0 +// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 +// Retrieval info: CONNECT: @data_a 0 0 9 0 data 0 0 9 0 +// Retrieval info: CONNECT: @rden_b 0 0 0 0 rden 0 0 0 0 +// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0 +// Retrieval info: CONNECT: q 0 0 9 0 @q_b 0 0 9 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL delay_ram.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL delay_ram.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL delay_ram.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL delay_ram.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL delay_ram_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL delay_ram_bb.v TRUE +// Retrieval info: LIB_FILE: altera_mf diff --git a/part_4/ex16/ex16_top.asm.rpt b/part_4/ex16/ex16_top.asm.rpt new file mode 100644 index 0000000..4cfbfba --- /dev/null +++ b/part_4/ex16/ex16_top.asm.rpt @@ -0,0 +1,92 @@ +Assembler report for ex16_top +Sat Dec 10 18:29:00 2016 +Quartus Prime Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Assembler Summary + 3. Assembler Settings + 4. Assembler Generated Files + 5. Assembler Device Options: H:/Year 2/VERI/part_4/ex16/ex16_top.sof + 6. Assembler Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2016 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel MegaCore Function License Agreement, or other +applicable license agreement, including, without limitation, +that your use is for the sole purpose of programming logic +devices manufactured by Intel and sold by Intel or its +authorized distributors. Please refer to the applicable +agreement for further details. + + + ++---------------------------------------------------------------+ +; Assembler Summary ; ++-----------------------+---------------------------------------+ +; Assembler Status ; Successful - Sat Dec 10 18:28:59 2016 ; +; Revision Name ; ex16_top ; +; Top-level Entity Name ; ex16_top ; +; Family ; Cyclone V ; +; Device ; 5CSEMA5F31C6 ; ++-----------------------+---------------------------------------+ + + ++----------------------------------+ +; Assembler Settings ; ++--------+---------+---------------+ +; Option ; Setting ; Default Value ; ++--------+---------+---------------+ + + ++-----------------------------------------+ +; Assembler Generated Files ; ++-----------------------------------------+ +; File Name ; ++-----------------------------------------+ +; H:/Year 2/VERI/part_4/ex16/ex16_top.sof ; ++-----------------------------------------+ + + ++-------------------------------------------------------------------+ +; Assembler Device Options: H:/Year 2/VERI/part_4/ex16/ex16_top.sof ; ++----------------+--------------------------------------------------+ +; Option ; Setting ; ++----------------+--------------------------------------------------+ +; Device ; 5CSEMA5F31C6 ; +; JTAG usercode ; 0x00B15ABD ; +; Checksum ; 0x00B15ABD ; ++----------------+--------------------------------------------------+ + + ++--------------------+ +; Assembler Messages ; ++--------------------+ +Info: ******************************************************************* +Info: Running Quartus Prime Assembler + Info: Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition + Info: Processing started: Sat Dec 10 18:27:22 2016 +Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off ex16 -c ex16_top +Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. +Info (115030): Assembler is generating device programming files +Info: Quartus Prime Assembler was successful. 0 errors, 1 warning + Info: Peak virtual memory: 728 megabytes + Info: Processing ended: Sat Dec 10 18:29:02 2016 + Info: Elapsed time: 00:01:40 + Info: Total CPU time (on all processors): 00:00:19 + + diff --git a/part_4/ex16/ex16_top.eda.rpt b/part_4/ex16/ex16_top.eda.rpt new file mode 100644 index 0000000..1421f53 --- /dev/null +++ b/part_4/ex16/ex16_top.eda.rpt @@ -0,0 +1,96 @@ +EDA Netlist Writer report for ex16_top +Sat Dec 10 18:30:59 2016 +Quartus Prime Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. EDA Netlist Writer Summary + 3. Simulation Settings + 4. Simulation Generated Files + 5. EDA Netlist Writer Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2016 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel MegaCore Function License Agreement, or other +applicable license agreement, including, without limitation, +that your use is for the sole purpose of programming logic +devices manufactured by Intel and sold by Intel or its +authorized distributors. Please refer to the applicable +agreement for further details. + + + ++-------------------------------------------------------------------+ +; EDA Netlist Writer Summary ; ++---------------------------+---------------------------------------+ +; EDA Netlist Writer Status ; Successful - Sat Dec 10 18:30:59 2016 ; +; Revision Name ; ex16_top ; +; Top-level Entity Name ; ex16_top ; +; Family ; Cyclone V ; +; Simulation Files Creation ; Successful ; ++---------------------------+---------------------------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------+ +; Simulation Settings ; ++---------------------------------------------------------------------------------------------------+---------------------------+ +; Option ; Setting ; ++---------------------------------------------------------------------------------------------------+---------------------------+ +; Tool Name ; ModelSim-Altera (Verilog) ; +; Generate functional simulation netlist ; Off ; +; Time scale ; 1 ps ; +; Truncate long hierarchy paths ; Off ; +; Map illegal HDL characters ; Off ; +; Flatten buses into individual nodes ; Off ; +; Maintain hierarchy ; Off ; +; Bring out device-wide set/reset signals as ports ; Off ; +; Enable glitch filtering ; Off ; +; Do not write top level VHDL entity ; Off ; +; Disable detection of setup and hold time violations in the input registers of bi-directional pins ; Off ; +; Architecture name in VHDL output netlist ; structure ; +; Generate third-party EDA tool command script for RTL functional simulation ; Off ; +; Generate third-party EDA tool command script for gate-level simulation ; Off ; ++---------------------------------------------------------------------------------------------------+---------------------------+ + + ++------------------------------------------------------------+ +; Simulation Generated Files ; ++------------------------------------------------------------+ +; Generated Files ; ++------------------------------------------------------------+ +; H:/Year 2/VERI/part_4/ex16/simulation/modelsim/ex16_top.vo ; ++------------------------------------------------------------+ + + ++-----------------------------+ +; EDA Netlist Writer Messages ; ++-----------------------------+ +Info: ******************************************************************* +Info: Running Quartus Prime EDA Netlist Writer + Info: Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition + Info: Processing started: Sat Dec 10 18:30:46 2016 +Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off ex16 -c ex16_top +Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. +Warning (10905): Generated the EDA functional simulation netlist because it is the only supported netlist type for this device. +Info (204019): Generated file ex16_top.vo in folder "H:/Year 2/VERI/part_4/ex16/simulation/modelsim/" for EDA simulation tool +Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 2 warnings + Info: Peak virtual memory: 628 megabytes + Info: Processing ended: Sat Dec 10 18:31:01 2016 + Info: Elapsed time: 00:00:15 + Info: Total CPU time (on all processors): 00:00:03 + + diff --git a/part_4/ex16/ex16_top.fit.rpt b/part_4/ex16/ex16_top.fit.rpt new file mode 100644 index 0000000..df6fbe0 --- /dev/null +++ b/part_4/ex16/ex16_top.fit.rpt @@ -0,0 +1,2026 @@ +Fitter report for ex16_top +Sat Dec 10 18:26:11 2016 +Quartus Prime Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Fitter Summary + 3. Fitter Settings + 4. Parallel Compilation + 5. Fitter Netlist Optimizations + 6. Ignored Assignments + 7. Incremental Compilation Preservation Summary + 8. Incremental Compilation Partition Settings + 9. Incremental Compilation Placement Preservation + 10. Pin-Out File + 11. Fitter Resource Usage Summary + 12. Fitter Partition Statistics + 13. Input Pins + 14. Output Pins + 15. I/O Bank Usage + 16. All Package Pins + 17. I/O Assignment Warnings + 18. Fitter Resource Utilization by Entity + 19. Delay Chain Summary + 20. Pad To Core Delay Chain Fanout + 21. Control Signals + 22. Global & Other Fast Signals + 23. Routing Usage Summary + 24. I/O Rules Summary + 25. I/O Rules Details + 26. I/O Rules Matrix + 27. Fitter Device Options + 28. Operating Settings and Conditions + 29. Estimated Delay Added for Hold Timing Summary + 30. Estimated Delay Added for Hold Timing Details + 31. Fitter Messages + 32. Fitter Suppressed Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2016 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel MegaCore Function License Agreement, or other +applicable license agreement, including, without limitation, +that your use is for the sole purpose of programming logic +devices manufactured by Intel and sold by Intel or its +authorized distributors. Please refer to the applicable +agreement for further details. + + + ++-------------------------------------------------------------------------------+ +; Fitter Summary ; ++---------------------------------+---------------------------------------------+ +; Fitter Status ; Successful - Sat Dec 10 18:26:11 2016 ; +; Quartus Prime Version ; 16.1.0 Build 196 10/24/2016 SJ Lite Edition ; +; Revision Name ; ex16_top ; +; Top-level Entity Name ; ex16_top ; +; Family ; Cyclone V ; +; Device ; 5CSEMA5F31C6 ; +; Timing Models ; Final ; +; Logic utilization (in ALMs) ; 62 / 32,070 ( < 1 % ) ; +; Total registers ; 113 ; +; Total pins ; 41 / 457 ( 9 % ) ; +; Total virtual pins ; 0 ; +; Total block memory bits ; 0 / 4,065,280 ( 0 % ) ; +; Total RAM Blocks ; 0 / 397 ( 0 % ) ; +; Total DSP Blocks ; 0 / 87 ( 0 % ) ; +; Total HSSI RX PCSs ; 0 ; +; Total HSSI PMA RX Deserializers ; 0 ; +; Total HSSI TX PCSs ; 0 ; +; Total HSSI PMA TX Serializers ; 0 ; +; Total PLLs ; 0 / 6 ( 0 % ) ; +; Total DLLs ; 0 / 4 ( 0 % ) ; ++---------------------------------+---------------------------------------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fitter Settings ; ++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+ +; Option ; Setting ; Default Value ; ++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+ +; Device ; 5CSEMA5F31C6 ; ; +; Minimum Core Junction Temperature ; 0 ; ; +; Maximum Core Junction Temperature ; 85 ; ; +; Use smart compilation ; Off ; Off ; +; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ; +; Enable compact report table ; Off ; Off ; +; Router Timing Optimization Level ; Normal ; Normal ; +; Perform Clocking Topology Analysis During Routing ; Off ; Off ; +; Placement Effort Multiplier ; 1.0 ; 1.0 ; +; Device initialization clock source ; INIT_INTOSC ; INIT_INTOSC ; +; Optimize Hold Timing ; All Paths ; All Paths ; +; Optimize Multi-Corner Timing ; On ; On ; +; Auto RAM to MLAB Conversion ; On ; On ; +; Equivalent RAM and MLAB Power Up ; Auto ; Auto ; +; Equivalent RAM and MLAB Paused Read Capabilities ; Care ; Care ; +; PowerPlay Power Optimization During Fitting ; Normal compilation ; Normal compilation ; +; SSN Optimization ; Off ; Off ; +; Optimize Timing ; Normal compilation ; Normal compilation ; +; Optimize Timing for ECOs ; Off ; Off ; +; Regenerate Full Fit Report During ECO Compiles ; Off ; Off ; +; Optimize IOC Register Placement for Timing ; Normal ; Normal ; +; Final Placement Optimizations ; Automatically ; Automatically ; +; Fitter Aggressive Routability Optimizations ; Automatically ; Automatically ; +; Fitter Initial Placement Seed ; 1 ; 1 ; +; Periphery to Core Placement and Routing Optimization ; Off ; Off ; +; Weak Pull-Up Resistor ; Off ; Off ; +; Enable Bus-Hold Circuitry ; Off ; Off ; +; Auto Packed Registers ; Auto ; Auto ; +; Auto Delay Chains ; On ; On ; +; Auto Delay Chains for High Fanout Input Pins ; Off ; Off ; +; Treat Bidirectional Pin as Output Pin ; Off ; Off ; +; Perform Physical Synthesis for Combinational Logic for Fitting ; Off ; Off ; +; Perform Physical Synthesis for Combinational Logic for Performance ; Off ; Off ; +; Perform Register Duplication for Performance ; Off ; Off ; +; Perform Register Retiming for Performance ; Off ; Off ; +; Perform Asynchronous Signal Pipelining ; Off ; Off ; +; Fitter Effort ; Auto Fit ; Auto Fit ; +; Physical Synthesis Effort Level ; Normal ; Normal ; +; Logic Cell Insertion - Logic Duplication ; Auto ; Auto ; +; Auto Register Duplication ; Auto ; Auto ; +; Auto Global Clock ; On ; On ; +; Auto Global Register Control Signals ; On ; On ; +; Reserve all unused pins ; As input tri-stated with weak pull-up ; As input tri-stated with weak pull-up ; +; Synchronizer Identification ; Auto ; Auto ; +; Enable Beneficial Skew Optimization ; On ; On ; +; Optimize Design for Metastability ; On ; On ; +; Active Serial clock source ; FREQ_100MHz ; FREQ_100MHz ; +; Force Fitter to Avoid Periphery Placement Warnings ; Off ; Off ; +; Clamping Diode ; Off ; Off ; +; Enable input tri-state on active configuration pins in user mode ; Off ; Off ; +; Advanced Physical Optimization ; On ; On ; ++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+ + + ++------------------------------------------+ +; Parallel Compilation ; ++----------------------------+-------------+ +; Processors ; Number ; ++----------------------------+-------------+ +; Number detected on machine ; 2 ; +; Maximum allowed ; 2 ; +; ; ; +; Average used ; 1.01 ; +; Maximum used ; 2 ; +; ; ; +; Usage by Processor ; % Time Used ; +; Processor 1 ; 100.0% ; +; Processor 2 ; 0.6% ; ++----------------------------+-------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fitter Netlist Optimizations ; ++----------------------------------+------------+---------------------------------------------------+----------------------------+-----------+----------------+--------------------------------------------+------------------+-----------------------+ +; Node ; Action ; Operation ; Reason ; Node Port ; Node Port Name ; Destination Node ; Destination Port ; Destination Port Name ; ++----------------------------------+------------+---------------------------------------------------+----------------------------+-----------+----------------+--------------------------------------------+------------------+-----------------------+ +; CLOCK_50~inputCLKENA0 ; Created ; Placement ; Fitter Periphery Placement ; ; ; ; ; ; +; spi2adc:SPI_ADC|ctr[1] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; spi2adc:SPI_ADC|ctr[1]~DUPLICATE ; ; ; +; spi2adc:SPI_ADC|ctr[2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; spi2adc:SPI_ADC|ctr[2]~DUPLICATE ; ; ; +; spi2adc:SPI_ADC|ctr[4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; spi2adc:SPI_ADC|ctr[4]~DUPLICATE ; ; ; +; spi2adc:SPI_ADC|data_from_adc[6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; spi2adc:SPI_ADC|data_from_adc[6]~DUPLICATE ; ; ; +; spi2adc:SPI_ADC|state[4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; spi2adc:SPI_ADC|state[4]~DUPLICATE ; ; ; +; spi2dac:SPI_DAC|state[1] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; spi2dac:SPI_DAC|state[1]~DUPLICATE ; ; ; ++----------------------------------+------------+---------------------------------------------------+----------------------------+-----------+----------------+--------------------------------------------+------------------+-----------------------+ + + ++--------------------------------------------------------------------------------------------+ +; Ignored Assignments ; ++--------------+----------------+--------------+------------+---------------+----------------+ +; Name ; Ignored Entity ; Ignored From ; Ignored To ; Ignored Value ; Ignored Source ; ++--------------+----------------+--------------+------------+---------------+----------------+ +; Location ; ; ; HEX3[0] ; PIN_AD26 ; QSF Assignment ; +; Location ; ; ; HEX3[1] ; PIN_AC27 ; QSF Assignment ; +; Location ; ; ; HEX3[2] ; PIN_AD25 ; QSF Assignment ; +; Location ; ; ; HEX3[3] ; PIN_AC25 ; QSF Assignment ; +; Location ; ; ; HEX3[4] ; PIN_AB28 ; QSF Assignment ; +; Location ; ; ; HEX3[5] ; PIN_AB25 ; QSF Assignment ; +; Location ; ; ; HEX3[6] ; PIN_AB22 ; QSF Assignment ; +; Location ; ; ; HEX4[0] ; PIN_AA24 ; QSF Assignment ; +; Location ; ; ; HEX4[1] ; PIN_Y23 ; QSF Assignment ; +; Location ; ; ; HEX4[2] ; PIN_Y24 ; QSF Assignment ; +; Location ; ; ; HEX4[3] ; PIN_W22 ; QSF Assignment ; +; Location ; ; ; HEX4[4] ; PIN_W24 ; QSF Assignment ; +; Location ; ; ; HEX4[5] ; PIN_V23 ; QSF Assignment ; +; Location ; ; ; HEX4[6] ; PIN_W25 ; QSF Assignment ; +; Location ; ; ; HEX5[0] ; PIN_V25 ; QSF Assignment ; +; Location ; ; ; HEX5[1] ; PIN_AA28 ; QSF Assignment ; +; Location ; ; ; HEX5[2] ; PIN_Y27 ; QSF Assignment ; +; Location ; ; ; HEX5[3] ; PIN_AB27 ; QSF Assignment ; +; Location ; ; ; HEX5[4] ; PIN_AB26 ; QSF Assignment ; +; Location ; ; ; HEX5[5] ; PIN_AA26 ; QSF Assignment ; +; Location ; ; ; HEX5[6] ; PIN_AA25 ; QSF Assignment ; +; Location ; ; ; KEY[0] ; PIN_AA14 ; QSF Assignment ; +; Location ; ; ; KEY[1] ; PIN_AA15 ; QSF Assignment ; +; Location ; ; ; KEY[2] ; PIN_W15 ; QSF Assignment ; +; Location ; ; ; KEY[3] ; PIN_Y16 ; QSF Assignment ; +; Location ; ; ; LEDR[0] ; PIN_V16 ; QSF Assignment ; +; Location ; ; ; LEDR[1] ; PIN_W16 ; QSF Assignment ; +; Location ; ; ; LEDR[2] ; PIN_V17 ; QSF Assignment ; +; Location ; ; ; LEDR[3] ; PIN_V18 ; QSF Assignment ; +; Location ; ; ; LEDR[4] ; PIN_W17 ; QSF Assignment ; +; Location ; ; ; LEDR[5] ; PIN_W19 ; QSF Assignment ; +; Location ; ; ; LEDR[6] ; PIN_Y19 ; QSF Assignment ; +; Location ; ; ; LEDR[7] ; PIN_W20 ; QSF Assignment ; +; Location ; ; ; LEDR[8] ; PIN_W21 ; QSF Assignment ; +; Location ; ; ; LEDR[9] ; PIN_Y21 ; QSF Assignment ; +; Location ; ; ; OLED_CLK ; PIN_AJ19 ; QSF Assignment ; +; Location ; ; ; OLED_CS ; PIN_Y17 ; QSF Assignment ; +; Location ; ; ; OLED_DATA ; PIN_AJ16 ; QSF Assignment ; +; Location ; ; ; OLED_DC ; PIN_AK18 ; QSF Assignment ; +; Location ; ; ; OLED_RST ; PIN_Y18 ; QSF Assignment ; +; I/O Standard ; ex16_top ; ; HEX3[0] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ex16_top ; ; HEX3[1] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ex16_top ; ; HEX3[2] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ex16_top ; ; HEX3[3] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ex16_top ; ; HEX3[4] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ex16_top ; ; HEX3[5] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ex16_top ; ; HEX3[6] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ex16_top ; ; HEX4[0] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ex16_top ; ; HEX4[1] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ex16_top ; ; HEX4[2] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ex16_top ; ; HEX4[3] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ex16_top ; ; HEX4[4] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ex16_top ; ; HEX4[5] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ex16_top ; ; HEX4[6] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ex16_top ; ; HEX5[0] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ex16_top ; ; HEX5[1] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ex16_top ; ; HEX5[2] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ex16_top ; ; HEX5[3] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ex16_top ; ; HEX5[4] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ex16_top ; ; HEX5[5] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ex16_top ; ; HEX5[6] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ex16_top ; ; KEY[0] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ex16_top ; ; KEY[1] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ex16_top ; ; KEY[2] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ex16_top ; ; KEY[3] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ex16_top ; ; LEDR[0] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ex16_top ; ; LEDR[1] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ex16_top ; ; LEDR[2] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ex16_top ; ; LEDR[3] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ex16_top ; ; LEDR[4] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ex16_top ; ; LEDR[5] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ex16_top ; ; LEDR[6] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ex16_top ; ; LEDR[7] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ex16_top ; ; LEDR[8] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ex16_top ; ; LEDR[9] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ex16_top ; ; OLED_CLK ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ex16_top ; ; OLED_CS ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ex16_top ; ; OLED_DATA ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ex16_top ; ; OLED_DC ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ex16_top ; ; OLED_RST ; 3.3-V LVTTL ; QSF Assignment ; ++--------------+----------------+--------------+------------+---------------+----------------+ + + ++--------------------------------------------------------------------------------------------------+ +; Incremental Compilation Preservation Summary ; ++---------------------+--------------------+----------------------------+--------------------------+ +; Type ; Total [A + B] ; From Design Partitions [A] ; From Rapid Recompile [B] ; ++---------------------+--------------------+----------------------------+--------------------------+ +; Placement (by node) ; ; ; ; +; -- Requested ; 0.00 % ( 0 / 299 ) ; 0.00 % ( 0 / 299 ) ; 0.00 % ( 0 / 299 ) ; +; -- Achieved ; 0.00 % ( 0 / 299 ) ; 0.00 % ( 0 / 299 ) ; 0.00 % ( 0 / 299 ) ; +; ; ; ; ; +; Routing (by net) ; ; ; ; +; -- Requested ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; +; -- Achieved ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; ++---------------------+--------------------+----------------------------+--------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Incremental Compilation Partition Settings ; ++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+ +; Partition Name ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents ; ++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+ +; Top ; User-created ; Source File ; N/A ; Source File ; N/A ; ; +; hard_block:auto_generated_inst ; Auto-generated ; Source File ; N/A ; Source File ; N/A ; hard_block:auto_generated_inst ; ++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------+ +; Incremental Compilation Placement Preservation ; ++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+ +; Partition Name ; Preservation Achieved ; Preservation Level Used ; Netlist Type Used ; Preservation Method ; Notes ; ++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+ +; Top ; 0.00 % ( 0 / 299 ) ; N/A ; Source File ; N/A ; ; +; hard_block:auto_generated_inst ; 0.00 % ( 0 / 0 ) ; N/A ; Source File ; N/A ; ; ++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+ + + ++--------------+ +; Pin-Out File ; ++--------------+ +The pin-out file can be found in H:/Year 2/VERI/part_4/ex16/ex16_top.pin. + + ++------------------------------------------------------------------------------------------+ +; Fitter Resource Usage Summary ; ++-------------------------------------------------------------+--------------------+-------+ +; Resource ; Usage ; % ; ++-------------------------------------------------------------+--------------------+-------+ +; Logic utilization (ALMs needed / total ALMs on device) ; 62 / 32,070 ; < 1 % ; +; ALMs needed [=A-B+C] ; 62 ; ; +; [A] ALMs used in final placement [=a+b+c+d] ; 72 / 32,070 ; < 1 % ; +; [a] ALMs used for LUT logic and registers ; 40 ; ; +; [b] ALMs used for LUT logic ; 18 ; ; +; [c] ALMs used for registers ; 14 ; ; +; [d] ALMs used for memory (up to half of total ALMs) ; 0 ; ; +; [B] Estimate of ALMs recoverable by dense packing ; 10 / 32,070 ; < 1 % ; +; [C] Estimate of ALMs unavailable [=a+b+c+d] ; 0 / 32,070 ; 0 % ; +; [a] Due to location constrained logic ; 0 ; ; +; [b] Due to LAB-wide signal conflicts ; 0 ; ; +; [c] Due to LAB input limits ; 0 ; ; +; [d] Due to virtual I/Os ; 0 ; ; +; ; ; ; +; Difficulty packing design ; Low ; ; +; ; ; ; +; Total LABs: partially or completely used ; 13 / 3,207 ; < 1 % ; +; -- Logic LABs ; 13 ; ; +; -- Memory LABs (up to half of total LABs) ; 0 ; ; +; ; ; ; +; Combinational ALUT usage for logic ; 109 ; ; +; -- 7 input functions ; 0 ; ; +; -- 6 input functions ; 9 ; ; +; -- 5 input functions ; 15 ; ; +; -- 4 input functions ; 30 ; ; +; -- <=3 input functions ; 55 ; ; +; Combinational ALUT usage for route-throughs ; 12 ; ; +; ; ; ; +; Dedicated logic registers ; 113 ; ; +; -- By type: ; ; ; +; -- Primary logic registers ; 107 / 64,140 ; < 1 % ; +; -- Secondary logic registers ; 6 / 64,140 ; < 1 % ; +; -- By function: ; ; ; +; -- Design implementation registers ; 107 ; ; +; -- Routing optimization registers ; 6 ; ; +; ; ; ; +; Virtual pins ; 0 ; ; +; I/O pins ; 41 / 457 ; 9 % ; +; -- Clock pins ; 1 / 8 ; 13 % ; +; -- Dedicated input pins ; 0 / 21 ; 0 % ; +; ; ; ; +; Hard processor system peripheral utilization ; ; ; +; -- Boot from FPGA ; 0 / 1 ( 0 % ) ; ; +; -- Clock resets ; 0 / 1 ( 0 % ) ; ; +; -- Cross trigger ; 0 / 1 ( 0 % ) ; ; +; -- S2F AXI ; 0 / 1 ( 0 % ) ; ; +; -- F2S AXI ; 0 / 1 ( 0 % ) ; ; +; -- AXI Lightweight ; 0 / 1 ( 0 % ) ; ; +; -- SDRAM ; 0 / 1 ( 0 % ) ; ; +; -- Interrupts ; 0 / 1 ( 0 % ) ; ; +; -- JTAG ; 0 / 1 ( 0 % ) ; ; +; -- Loan I/O ; 0 / 1 ( 0 % ) ; ; +; -- MPU event standby ; 0 / 1 ( 0 % ) ; ; +; -- MPU general purpose ; 0 / 1 ( 0 % ) ; ; +; -- STM event ; 0 / 1 ( 0 % ) ; ; +; -- TPIU trace ; 0 / 1 ( 0 % ) ; ; +; -- DMA ; 0 / 1 ( 0 % ) ; ; +; -- CAN ; 0 / 2 ( 0 % ) ; ; +; -- EMAC ; 0 / 2 ( 0 % ) ; ; +; -- I2C ; 0 / 4 ( 0 % ) ; ; +; -- NAND Flash ; 0 / 1 ( 0 % ) ; ; +; -- QSPI ; 0 / 1 ( 0 % ) ; ; +; -- SDMMC ; 0 / 1 ( 0 % ) ; ; +; -- SPI Master ; 0 / 2 ( 0 % ) ; ; +; -- SPI Slave ; 0 / 2 ( 0 % ) ; ; +; -- UART ; 0 / 2 ( 0 % ) ; ; +; -- USB ; 0 / 2 ( 0 % ) ; ; +; ; ; ; +; M10K blocks ; 0 / 397 ; 0 % ; +; Total MLAB memory bits ; 0 ; ; +; Total block memory bits ; 0 / 4,065,280 ; 0 % ; +; Total block memory implementation bits ; 0 / 4,065,280 ; 0 % ; +; ; ; ; +; Total DSP Blocks ; 0 / 87 ; 0 % ; +; ; ; ; +; Fractional PLLs ; 0 / 6 ; 0 % ; +; Global signals ; 1 ; ; +; -- Global clocks ; 1 / 16 ; 6 % ; +; -- Quadrant clocks ; 0 / 66 ; 0 % ; +; -- Horizontal periphery clocks ; 0 / 18 ; 0 % ; +; SERDES Transmitters ; 0 / 100 ; 0 % ; +; SERDES Receivers ; 0 / 100 ; 0 % ; +; JTAGs ; 0 / 1 ; 0 % ; +; ASMI blocks ; 0 / 1 ; 0 % ; +; CRC blocks ; 0 / 1 ; 0 % ; +; Remote update blocks ; 0 / 1 ; 0 % ; +; Oscillator blocks ; 0 / 1 ; 0 % ; +; Impedance control blocks ; 0 / 4 ; 0 % ; +; Hard Memory Controllers ; 0 / 2 ; 0 % ; +; Average interconnect usage (total/H/V) ; 0.0% / 0.0% / 0.0% ; ; +; Peak interconnect usage (total/H/V) ; 0.8% / 0.8% / 0.9% ; ; +; Maximum fan-out ; 60 ; ; +; Highest non-global fan-out ; 33 ; ; +; Total fan-out ; 706 ; ; +; Average fan-out ; 2.23 ; ; ++-------------------------------------------------------------+--------------------+-------+ + + ++----------------------------------------------------------------------------------------------------------------------+ +; Fitter Partition Statistics ; ++-------------------------------------------------------------+-----------------------+--------------------------------+ +; Statistic ; Top ; hard_block:auto_generated_inst ; ++-------------------------------------------------------------+-----------------------+--------------------------------+ +; Logic utilization (ALMs needed / total ALMs on device) ; 62 / 32070 ( < 1 % ) ; 0 / 32070 ( 0 % ) ; +; ALMs needed [=A-B+C] ; 62 ; 0 ; +; [A] ALMs used in final placement [=a+b+c+d] ; 72 / 32070 ( < 1 % ) ; 0 / 32070 ( 0 % ) ; +; [a] ALMs used for LUT logic and registers ; 40 ; 0 ; +; [b] ALMs used for LUT logic ; 18 ; 0 ; +; [c] ALMs used for registers ; 14 ; 0 ; +; [d] ALMs used for memory (up to half of total ALMs) ; 0 ; 0 ; +; [B] Estimate of ALMs recoverable by dense packing ; 10 / 32070 ( < 1 % ) ; 0 / 32070 ( 0 % ) ; +; [C] Estimate of ALMs unavailable [=a+b+c+d] ; 0 / 32070 ( 0 % ) ; 0 / 32070 ( 0 % ) ; +; [a] Due to location constrained logic ; 0 ; 0 ; +; [b] Due to LAB-wide signal conflicts ; 0 ; 0 ; +; [c] Due to LAB input limits ; 0 ; 0 ; +; [d] Due to virtual I/Os ; 0 ; 0 ; +; ; ; ; +; Difficulty packing design ; Low ; Low ; +; ; ; ; +; Total LABs: partially or completely used ; 13 / 3207 ( < 1 % ) ; 0 / 3207 ( 0 % ) ; +; -- Logic LABs ; 13 ; 0 ; +; -- Memory LABs (up to half of total LABs) ; 0 ; 0 ; +; ; ; ; +; Combinational ALUT usage for logic ; 109 ; 0 ; +; -- 7 input functions ; 0 ; 0 ; +; -- 6 input functions ; 9 ; 0 ; +; -- 5 input functions ; 15 ; 0 ; +; -- 4 input functions ; 30 ; 0 ; +; -- <=3 input functions ; 55 ; 0 ; +; Combinational ALUT usage for route-throughs ; 12 ; 0 ; +; Memory ALUT usage ; 0 ; 0 ; +; -- 64-address deep ; 0 ; 0 ; +; -- 32-address deep ; 0 ; 0 ; +; ; ; ; +; Dedicated logic registers ; 0 ; 0 ; +; -- By type: ; ; ; +; -- Primary logic registers ; 107 / 64140 ( < 1 % ) ; 0 / 64140 ( 0 % ) ; +; -- Secondary logic registers ; 6 / 64140 ( < 1 % ) ; 0 / 64140 ( 0 % ) ; +; -- By function: ; ; ; +; -- Design implementation registers ; 107 ; 0 ; +; -- Routing optimization registers ; 6 ; 0 ; +; ; ; ; +; ; ; ; +; Virtual pins ; 0 ; 0 ; +; I/O pins ; 41 ; 0 ; +; I/O registers ; 0 ; 0 ; +; Total block memory bits ; 0 ; 0 ; +; Total block memory implementation bits ; 0 ; 0 ; +; Clock enable block ; 1 / 116 ( < 1 % ) ; 0 / 116 ( 0 % ) ; +; ; ; ; +; Connections ; ; ; +; -- Input Connections ; 0 ; 0 ; +; -- Registered Input Connections ; 0 ; 0 ; +; -- Output Connections ; 0 ; 0 ; +; -- Registered Output Connections ; 0 ; 0 ; +; ; ; ; +; Internal Connections ; ; ; +; -- Total Connections ; 706 ; 0 ; +; -- Registered Connections ; 425 ; 0 ; +; ; ; ; +; External Connections ; ; ; +; -- Top ; 0 ; 0 ; +; -- hard_block:auto_generated_inst ; 0 ; 0 ; +; ; ; ; +; Partition Interface ; ; ; +; -- Input Ports ; 12 ; 0 ; +; -- Output Ports ; 29 ; 0 ; +; -- Bidir Ports ; 0 ; 0 ; +; ; ; ; +; Registered Ports ; ; ; +; -- Registered Input Ports ; 0 ; 0 ; +; -- Registered Output Ports ; 0 ; 0 ; +; ; ; ; +; Port Connectivity ; ; ; +; -- Input Ports driven by GND ; 0 ; 0 ; +; -- Output Ports driven by GND ; 0 ; 0 ; +; -- Input Ports driven by VCC ; 0 ; 0 ; +; -- Output Ports driven by VCC ; 0 ; 0 ; +; -- Input Ports with no Source ; 0 ; 0 ; +; -- Output Ports with no Source ; 0 ; 0 ; +; -- Input Ports with no Fanout ; 0 ; 0 ; +; -- Output Ports with no Fanout ; 0 ; 0 ; ++-------------------------------------------------------------+-----------------------+--------------------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Input Pins ; ++----------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+ +; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Termination Control Block ; Location assigned by ; Slew Rate ; ++----------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+ +; ADC_SDO ; AJ21 ; 4A ; 62 ; 0 ; 51 ; 1 ; 0 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ; no ; +; CLOCK_50 ; AF14 ; 3B ; 32 ; 0 ; 0 ; 62 ; 0 ; yes ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ; no ; +; SW[0] ; AB12 ; 3A ; 12 ; 0 ; 17 ; 0 ; 0 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ; no ; +; SW[1] ; AC12 ; 3A ; 16 ; 0 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ; no ; +; SW[2] ; AF9 ; 3A ; 8 ; 0 ; 34 ; 0 ; 0 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ; no ; +; SW[3] ; AF10 ; 3A ; 4 ; 0 ; 51 ; 0 ; 0 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ; no ; +; SW[4] ; AD11 ; 3A ; 2 ; 0 ; 40 ; 0 ; 0 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ; no ; +; SW[5] ; AD12 ; 3A ; 16 ; 0 ; 17 ; 0 ; 0 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ; no ; +; SW[6] ; AE11 ; 3A ; 4 ; 0 ; 34 ; 0 ; 0 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ; no ; +; SW[7] ; AC9 ; 3A ; 4 ; 0 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ; no ; +; SW[8] ; AD10 ; 3A ; 4 ; 0 ; 17 ; 0 ; 0 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ; no ; +; SW[9] ; AE12 ; 3A ; 2 ; 0 ; 57 ; 0 ; 0 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ; no ; ++----------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Output Pins ; ++---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+ +; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Output Buffer Delay ; Output Buffer Delay Control ; Location assigned by ; Output Enable Source ; Output Enable Group ; ++---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+ +; ADC_CS ; AG20 ; 4A ; 62 ; 0 ; 17 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; +; ADC_SCK ; AF21 ; 4A ; 70 ; 0 ; 17 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; +; ADC_SDI ; AG21 ; 4A ; 54 ; 0 ; 0 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; +; DAC_CS ; AD20 ; 4A ; 82 ; 0 ; 40 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; +; DAC_LD ; AK21 ; 4A ; 68 ; 0 ; 34 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; +; DAC_SCK ; AF20 ; 4A ; 70 ; 0 ; 0 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; +; DAC_SDI ; AG18 ; 4A ; 58 ; 0 ; 74 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; +; HEX0[0] ; AE26 ; 5A ; 89 ; 8 ; 37 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; +; HEX0[1] ; AE27 ; 5A ; 89 ; 11 ; 77 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; +; HEX0[2] ; AE28 ; 5A ; 89 ; 11 ; 94 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; +; HEX0[3] ; AG27 ; 5A ; 89 ; 4 ; 77 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; +; HEX0[4] ; AF28 ; 5A ; 89 ; 13 ; 54 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; +; HEX0[5] ; AG28 ; 5A ; 89 ; 13 ; 37 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; +; HEX0[6] ; AH28 ; 5A ; 89 ; 4 ; 94 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; +; HEX1[0] ; AJ29 ; 5A ; 89 ; 6 ; 37 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; +; HEX1[1] ; AH29 ; 5A ; 89 ; 6 ; 54 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; +; HEX1[2] ; AH30 ; 5A ; 89 ; 16 ; 37 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; +; HEX1[3] ; AG30 ; 5A ; 89 ; 16 ; 54 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; +; HEX1[4] ; AF29 ; 5A ; 89 ; 15 ; 37 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; +; HEX1[5] ; AF30 ; 5A ; 89 ; 15 ; 54 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; +; HEX1[6] ; AD27 ; 5A ; 89 ; 8 ; 54 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; +; HEX2[0] ; AB23 ; 5A ; 89 ; 9 ; 20 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; +; HEX2[1] ; AE29 ; 5B ; 89 ; 23 ; 37 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; +; HEX2[2] ; AD29 ; 5B ; 89 ; 23 ; 54 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; +; HEX2[3] ; AC28 ; 5B ; 89 ; 20 ; 77 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; +; HEX2[4] ; AD30 ; 5B ; 89 ; 25 ; 37 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; +; HEX2[5] ; AC29 ; 5B ; 89 ; 20 ; 94 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; +; HEX2[6] ; AC30 ; 5B ; 89 ; 25 ; 54 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; +; PWM_OUT ; AJ20 ; 4A ; 62 ; 0 ; 34 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; ++---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+ + + ++----------------------------------------------------------------------------+ +; I/O Bank Usage ; ++----------+------------------+---------------+--------------+---------------+ +; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ; VCCPD Voltage ; ++----------+------------------+---------------+--------------+---------------+ +; B2L ; 0 / 0 ( -- ) ; -- ; -- ; -- ; +; B1L ; 0 / 0 ( -- ) ; -- ; -- ; -- ; +; 3A ; 10 / 32 ( 31 % ) ; 3.3V ; -- ; 3.3V ; +; 3B ; 1 / 48 ( 2 % ) ; 3.3V ; -- ; 3.3V ; +; 4A ; 9 / 80 ( 11 % ) ; 3.3V ; -- ; 3.3V ; +; 5A ; 15 / 32 ( 47 % ) ; 3.3V ; -- ; 3.3V ; +; 5B ; 6 / 16 ( 38 % ) ; 3.3V ; -- ; 3.3V ; +; 6B ; 0 / 44 ( 0 % ) ; 2.5V ; -- ; 2.5V ; +; 6A ; 0 / 56 ( 0 % ) ; 2.5V ; -- ; 2.5V ; +; 7A ; 0 / 19 ( 0 % ) ; 2.5V ; -- ; 2.5V ; +; 7B ; 0 / 22 ( 0 % ) ; 2.5V ; -- ; 2.5V ; +; 7C ; 0 / 12 ( 0 % ) ; 2.5V ; -- ; 2.5V ; +; 7D ; 0 / 14 ( 0 % ) ; 2.5V ; -- ; 2.5V ; +; 8A ; 0 / 80 ( 0 % ) ; 2.5V ; -- ; 2.5V ; ++----------+------------------+---------------+--------------+---------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; All Package Pins ; ++----------+------------+----------------+---------------------------------+--------+--------------+---------------------+--------------+-----------------+----------+--------------+ +; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; I/O Type ; User Assignment ; Bus Hold ; Weak Pull Up ; ++----------+------------+----------------+---------------------------------+--------+--------------+---------------------+--------------+-----------------+----------+--------------+ +; A2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; A3 ; 493 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A4 ; 491 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A5 ; 489 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A6 ; 487 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A7 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; A8 ; 473 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A9 ; 471 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A10 ; 465 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A11 ; 463 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; A13 ; 461 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A14 ; 455 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A15 ; 447 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A16 ; 439 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; A18 ; 425 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A19 ; 423 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A20 ; 415 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A21 ; 411 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; A23 ; 395 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A24 ; 391 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A25 ; 389 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A26 ; 382 ; 7A ; ^GND ; ; ; ; -- ; ; -- ; -- ; +; A27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; A28 ; 380 ; 7A ; ^HPS_TRST ; ; ; ; -- ; ; -- ; -- ; +; A29 ; 378 ; 7A ; ^HPS_TMS ; ; ; ; -- ; ; -- ; -- ; +; AA1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AA2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AA3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AA4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AA5 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; AA6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AA7 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; +; AA8 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AA9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AA10 ; ; 3A ; VCCPD3A ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AA11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AA12 ; 74 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA13 ; 90 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA14 ; 122 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA15 ; 120 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA16 ; 146 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA17 ; ; 4A ; VCCIO4A ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AA18 ; 168 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA19 ; 176 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA20 ; 200 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA21 ; 210 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AA23 ; ; -- ; VCCPGM ; power ; ; 1.8V/2.5V/3.0V/3.3V ; -- ; ; -- ; -- ; +; AA24 ; 228 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AA25 ; 224 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AA26 ; 252 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AA27 ; ; 5B ; VCCIO5B ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AA28 ; 251 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AA29 ; ; 5B ; VREFB5BN0 ; power ; ; ; -- ; ; -- ; -- ; +; AA30 ; 250 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AB1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AB2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AB3 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; +; AB4 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; +; AB5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AB6 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AB7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AB8 ; 43 ; 3A ; ^nCSO, DATA4 ; ; ; ; Weak Pull Up ; ; -- ; On ; +; AB9 ; 42 ; 3A ; #TDO ; output ; ; ; -- ; ; -- ; -- ; +; AB10 ; ; -- ; VCCPGM ; power ; ; 1.8V/2.5V/3.0V/3.3V ; -- ; ; -- ; -- ; +; AB11 ; ; -- ; VCC_AUX ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AB12 ; 72 ; 3A ; SW[0] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; AB13 ; 88 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB14 ; ; 3B ; VCCIO3B ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AB15 ; 106 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB16 ; ; -- ; VCC_AUX ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AB17 ; 144 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB18 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AB19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AB20 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AB21 ; 208 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB22 ; 225 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AB23 ; 227 ; 5A ; HEX2[0] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; AB24 ; ; 5A ; VCCIO5A ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AB25 ; 230 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AB26 ; 226 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AB27 ; 254 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AB28 ; 249 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AB29 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AB30 ; 248 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AC1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AC2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AC3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AC4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AC5 ; 46 ; 3A ; #TCK ; input ; ; ; -- ; ; -- ; -- ; +; AC6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AC7 ; 45 ; 3A ; ^AS_DATA3, DATA3 ; ; ; ; Weak Pull Up ; ; -- ; On ; +; AC8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AC9 ; 58 ; 3A ; SW[7] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; AC10 ; ; 3A ; VCCPD3A ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AC11 ; ; 3A ; VCCIO3A ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AC12 ; 82 ; 3A ; SW[1] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; AC13 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AC14 ; 104 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AC15 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AC16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AC17 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AC18 ; 162 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AC19 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AC20 ; 186 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AC21 ; ; 4A ; VCCIO4A ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AC22 ; 207 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AC23 ; 205 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AC24 ; ; 5A ; VREFB5AN0 ; power ; ; ; -- ; ; -- ; -- ; +; AC25 ; 215 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AC26 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AC27 ; 242 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AC28 ; 245 ; 5B ; HEX2[3] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; AC29 ; 247 ; 5B ; HEX2[5] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; AC30 ; 259 ; 5B ; HEX2[6] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; AD1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AD2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AD3 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; +; AD4 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; +; AD5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AD6 ; ; 3A ; VREFB3AN0 ; power ; ; ; -- ; ; -- ; -- ; +; AD7 ; 62 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AD8 ; ; 3A ; VCCIO3A ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AD9 ; 55 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AD10 ; 56 ; 3A ; SW[8] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; AD11 ; 54 ; 3A ; SW[4] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; AD12 ; 80 ; 3A ; SW[5] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; AD13 ; ; 3B ; VCCIO3B ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AD14 ; 98 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AD15 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; +; AD16 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AD17 ; 160 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AD18 ; ; 4A ; VCCIO4A ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AD19 ; 184 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AD20 ; 199 ; 4A ; DAC_CS ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; AD21 ; 197 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AD22 ; ; -- ; VCC_AUX ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AD23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AD24 ; 211 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AD25 ; 213 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AD26 ; 240 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AD27 ; 222 ; 5A ; HEX1[6] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; AD28 ; ; 5A ; VCCIO5A ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AD29 ; 255 ; 5B ; HEX2[2] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; AD30 ; 257 ; 5B ; HEX2[4] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; AE1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AE2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AE3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AE4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AE5 ; 49 ; 3A ; ^AS_DATA1, DATA1 ; ; ; ; Weak Pull Up ; ; -- ; On ; +; AE6 ; 51 ; 3A ; ^AS_DATA0, ASDO, DATA0 ; ; ; ; Weak Pull Up ; ; -- ; On ; +; AE7 ; 60 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AE8 ; 47 ; 3A ; ^AS_DATA2, DATA2 ; ; ; ; Weak Pull Up ; ; -- ; On ; +; AE9 ; 53 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AE10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AE11 ; 59 ; 3A ; SW[6] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; AE12 ; 52 ; 3A ; SW[9] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; AE13 ; 95 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AE14 ; 96 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AE15 ; ; 3B ; VCCIO3B ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AE16 ; 139 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AE17 ; 135 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AE18 ; 167 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AE19 ; 165 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AE20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AE21 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AE22 ; 191 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AE23 ; 189 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AE24 ; 209 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AE25 ; ; 4A ; VCCIO4A ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AE26 ; 220 ; 5A ; HEX0[0] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; AE27 ; 229 ; 5A ; HEX0[1] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; AE28 ; 231 ; 5A ; HEX0[2] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; AE29 ; 253 ; 5B ; HEX2[1] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; AE30 ; ; 5B ; VCCIO5B ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AF1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AF2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AF3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AF4 ; 66 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF5 ; 64 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF6 ; 75 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF7 ; ; 3A ; VCCIO3A ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AF8 ; 70 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF9 ; 67 ; 3A ; SW[2] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; AF10 ; 57 ; 3A ; SW[3] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; AF11 ; 87 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AF13 ; 93 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF14 ; 114 ; 3B ; CLOCK_50 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; AF15 ; 112 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF16 ; 137 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AF18 ; 133 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF19 ; 159 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF20 ; 175 ; 4A ; DAC_SCK ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; AF21 ; 173 ; 4A ; ADC_SCK ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; AF22 ; ; 4A ; VCCIO4A ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AF23 ; 183 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF24 ; 181 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF25 ; 206 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF26 ; 204 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AF28 ; 235 ; 5A ; HEX0[4] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; AF29 ; 237 ; 5A ; HEX1[4] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; AF30 ; 239 ; 5A ; HEX1[5] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; AG1 ; 71 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AG2 ; 83 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AG3 ; 63 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AG4 ; ; 3A ; VCCIO3A ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AG5 ; 78 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AG6 ; 73 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AG7 ; 68 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AG8 ; 65 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AG9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AG10 ; 86 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AG11 ; 85 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AG12 ; 103 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AG13 ; 101 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AG14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AG15 ; 127 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AG16 ; 134 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AG17 ; 132 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AG18 ; 150 ; 4A ; DAC_SDI ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; AG19 ; ; 4A ; VCCIO4A ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AG20 ; 157 ; 4A ; ADC_CS ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; AG21 ; 143 ; 4A ; ADC_SDI ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; AG22 ; 166 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AG23 ; 163 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AG24 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AG25 ; 190 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AG26 ; 203 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AG27 ; 212 ; 5A ; HEX0[3] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; AG28 ; 233 ; 5A ; HEX0[5] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; AG29 ; ; 5A ; VCCIO5A ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AG30 ; 243 ; 5A ; HEX1[3] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; AH1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AH2 ; 69 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AH3 ; 81 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AH4 ; 61 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AH5 ; 76 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AH6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AH7 ; 115 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AH8 ; 113 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AH9 ; 84 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AH10 ; 118 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AH11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AH12 ; 126 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AH13 ; 111 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AH14 ; 109 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AH15 ; 125 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AH16 ; ; 4A ; VCCIO4A ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AH17 ; 147 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AH18 ; 145 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AH19 ; 148 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AH20 ; 141 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AH21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AH22 ; 164 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AH23 ; 174 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AH24 ; 161 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AH25 ; 188 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AH26 ; ; 4A ; VCCIO4A ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AH27 ; 201 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AH28 ; 214 ; 5A ; HEX0[6] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; AH29 ; 218 ; 5A ; HEX1[1] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; AH30 ; 241 ; 5A ; HEX1[2] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; AJ1 ; 79 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AJ2 ; 77 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AJ3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AJ4 ; 94 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AJ5 ; 99 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AJ6 ; 102 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AJ7 ; 100 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AJ8 ; ; 3B ; VCCIO3B ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AJ9 ; 110 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AJ10 ; 116 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AJ11 ; 119 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AJ12 ; 124 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AJ13 ; ; 3B ; VCCIO3B ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AJ14 ; 131 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AJ15 ; ; 3B ; VREFB3BN0 ; power ; ; ; -- ; ; -- ; -- ; +; AJ16 ; 142 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AJ17 ; 151 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AJ18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AJ19 ; 155 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AJ20 ; 158 ; 4A ; PWM_OUT ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; AJ21 ; 156 ; 4A ; ADC_SDO ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; AJ22 ; 172 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AJ23 ; ; 4A ; VCCIO4A ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AJ24 ; 182 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AJ25 ; 180 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AJ26 ; 187 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AJ27 ; 195 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AJ28 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AJ29 ; 216 ; 5A ; HEX1[0] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; AJ30 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AK2 ; 91 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AK3 ; 89 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AK4 ; 92 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AK5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AK6 ; 97 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AK7 ; 107 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AK8 ; 105 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AK9 ; 108 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AK10 ; ; 3B ; VCCIO3B ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AK11 ; 117 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AK12 ; 123 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AK13 ; 121 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AK14 ; 129 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AK15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AK16 ; 140 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AK17 ; ; 4A ; VREFB4AN0 ; power ; ; ; -- ; ; -- ; -- ; +; AK18 ; 149 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AK19 ; 153 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AK20 ; ; 4A ; VCCIO4A ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AK21 ; 171 ; 4A ; DAC_LD ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; AK22 ; 169 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AK23 ; 179 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AK24 ; 177 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AK25 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AK26 ; 185 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AK27 ; 193 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AK28 ; 198 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AK29 ; 196 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B1 ; 509 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B2 ; 507 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B3 ; 513 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B4 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; B5 ; 512 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B6 ; 510 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B7 ; 477 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B8 ; 481 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B10 ; ; 8A ; VREFB8AN0 ; power ; ; ; -- ; ; -- ; -- ; +; B11 ; 469 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B12 ; 464 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B13 ; 459 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B15 ; 451 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B16 ; 441 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B17 ; 431 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B18 ; 418 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B20 ; 417 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B21 ; 413 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B22 ; 399 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B23 ; 397 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B24 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B25 ; 387 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B26 ; 386 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B27 ; 381 ; 7A ; ^HPS_TDI ; ; ; ; -- ; ; -- ; -- ; +; B28 ; 376 ; 7A ; ^HPS_TDO ; ; ; ; -- ; ; -- ; -- ; +; B29 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B30 ; 365 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; C1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; C2 ; 517 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C3 ; 511 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C4 ; 501 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C5 ; 497 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; C7 ; 475 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C8 ; 479 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C9 ; 485 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C10 ; 483 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C11 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; C12 ; 467 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C13 ; 462 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C14 ; 448 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C15 ; 453 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; C17 ; 433 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C18 ; 435 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C19 ; 427 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C20 ; 421 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; C22 ; 396 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C23 ; 401 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C24 ; 393 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C25 ; 388 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C26 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; C27 ; 374 ; 7A ; ^HPS_nRST ; ; ; ; -- ; ; -- ; -- ; +; C28 ; 369 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; C29 ; 367 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; C30 ; 363 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; D1 ; 529 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D2 ; 515 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; D4 ; 521 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D5 ; 499 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D6 ; 495 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D7 ; 505 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D8 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; D9 ; 480 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D10 ; 472 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D11 ; 470 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D12 ; 496 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; D14 ; 446 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D15 ; 449 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D16 ; 445 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D17 ; 440 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D18 ; ; 7C ; VCCIO7C_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; D19 ; 426 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D20 ; 420 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D21 ; 419 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D22 ; 402 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; D24 ; 404 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D25 ; 384 ; 7A ; ^HPS_CLK1 ; ; ; ; -- ; ; -- ; -- ; +; D26 ; 373 ; 7A ; ^GND ; ; ; ; -- ; ; -- ; -- ; +; D27 ; 371 ; 6A ; HPS_RZQ_0 ; ; ; ; -- ; ; no ; On ; +; D28 ; ; 6A ; VCCIO6A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; D29 ; 361 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; D30 ; 359 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E1 ; 527 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E2 ; 525 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E3 ; 523 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E4 ; 519 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E5 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; E6 ; 533 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E7 ; 531 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E8 ; 503 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E9 ; 478 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; E11 ; 504 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E12 ; 494 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E13 ; 488 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E14 ; 454 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E15 ; ; 7D ; VCCIO7D_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; E16 ; 443 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E17 ; 438 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E18 ; 437 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E19 ; 424 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E20 ; ; 7B ; VCCIO7B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; E21 ; 412 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E22 ; ; 7A, 7B, 7C, 7D ; VREFB7A7B7C7DN0_HPS ; power ; ; ; -- ; ; -- ; -- ; +; E23 ; 394 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E24 ; 403 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E25 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; E26 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; +; E27 ; 357 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E28 ; 351 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E29 ; 353 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E30 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; F1 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; +; F2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; F3 ; 539 ; 9A ; ^CONF_DONE ; ; ; ; -- ; ; -- ; -- ; +; F4 ; 541 ; 9A ; ^nSTATUS ; ; ; ; -- ; ; -- ; -- ; +; F5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; F6 ; 537 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; F8 ; 536 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F9 ; 534 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F10 ; 528 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F11 ; 502 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F12 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; F13 ; 486 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F14 ; 468 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F15 ; 466 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F16 ; 442 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; F18 ; 430 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F19 ; 410 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F20 ; 407 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F21 ; 409 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F22 ; ; 7A ; VCCIO7A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; F23 ; 375 ; 7A ; ^HPS_nPOR ; ; ; ; -- ; ; -- ; -- ; +; F24 ; 383 ; 7A ; ^HPS_PORSEL ; ; ; ; -- ; ; -- ; -- ; +; F25 ; 385 ; 7A ; ^HPS_CLK2 ; ; ; ; -- ; ; -- ; -- ; +; F26 ; 341 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; F28 ; 345 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F29 ; 349 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F30 ; 347 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G1 ; ; ; GND ; ; ; ; -- ; ; -- ; -- ; +; G2 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; +; G3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; G4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; G5 ; 542 ; 9A ; ^nCE ; ; ; ; -- ; ; -- ; -- ; +; G6 ; 543 ; 9A ; ^MSEL2 ; ; ; ; -- ; ; -- ; -- ; +; G7 ; 535 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; G8 ; 492 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; G9 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; G10 ; 526 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; G11 ; 520 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; G12 ; 518 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; G13 ; 484 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; G14 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; G15 ; 460 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; G16 ; 444 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; G17 ; 436 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; G18 ; 432 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; G19 ; ; 7B ; VCCIO7B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; G20 ; 416 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; G21 ; 392 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; G22 ; 400 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; G23 ; 377 ; 7A ; ^VCCRSTCLK_HPS ; ; ; ; -- ; ; -- ; -- ; +; G24 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; G25 ; 370 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G26 ; 362 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G27 ; 339 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ; +; G28 ; 335 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G29 ; ; 6A ; VCCIO6A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; G30 ; 343 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; H2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; H3 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; +; H4 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; +; H5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; H6 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; H7 ; 508 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H8 ; 490 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H9 ; ; -- ; VCCBAT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; H10 ; ; -- ; VCC_AUX ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; H11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; H12 ; 500 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H13 ; 498 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H14 ; 482 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H15 ; 458 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H16 ; ; 7D ; VCCIO7D_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; H17 ; 434 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H18 ; 422 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H19 ; 406 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H20 ; 398 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H21 ; ; 7A ; VCCIO7A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; H22 ; 379 ; 7A ; ^HPS_TCK ; ; ; ; -- ; ; -- ; -- ; +; H23 ; 390 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H24 ; 364 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H25 ; 368 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H26 ; ; 6A ; VCCIO6A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; H27 ; 360 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H28 ; 333 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H29 ; 331 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H30 ; 337 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J5 ; 545 ; 9A ; ^nCONFIG ; ; ; ; -- ; ; -- ; -- ; +; J6 ; 547 ; 9A ; ^GND ; ; ; ; -- ; ; -- ; -- ; +; J7 ; 506 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; J8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J9 ; 532 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; J10 ; 530 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; J11 ; ; -- ; VCCPGM ; power ; ; 1.8V/2.5V/3.0V/3.3V ; -- ; ; -- ; -- ; +; J12 ; 516 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; J13 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; J14 ; 476 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; J15 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; +; J16 ; ; -- ; VCC_AUX ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; J17 ; ; 7C ; VCCPD7C_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; J18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J19 ; 408 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; J20 ; ; -- ; VCCRSTCLK_HPS ; power ; ; 1.8V/2.5V/3.0V/3.3V ; -- ; ; -- ; -- ; +; J21 ; ; -- ; VCC_AUX_SHARED ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; J22 ; 372 ; 7A ; ^GND ; ; ; ; -- ; ; -- ; -- ; +; J23 ; 354 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J24 ; 352 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J25 ; 344 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J26 ; 323 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J27 ; 346 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J28 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J29 ; 327 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J30 ; 329 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K3 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; +; K4 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; +; K5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K6 ; 540 ; 9A ; ^MSEL1 ; ; ; ; -- ; ; -- ; -- ; +; K7 ; 522 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; K8 ; 524 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; K9 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; K10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K11 ; ; 8A ; VCCPD8A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; K12 ; 514 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; K13 ; ; 8A ; VCCPD8A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; K14 ; 474 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; K15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K16 ; ; 7D ; VCCPD7D_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; K17 ; 414 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; K18 ; ; 7B ; VCCPD7B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; K19 ; ; 7A ; VCCPD7A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; K20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K21 ; 366 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K22 ; 336 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K23 ; 338 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K24 ; ; 6A ; VCCIO6A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; K25 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K26 ; 322 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K27 ; 319 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K28 ; 325 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K29 ; 321 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K30 ; ; 6A ; VCCIO6A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; L1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L5 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; L6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L7 ; 544 ; 9A ; ^MSEL3 ; ; ; ; -- ; ; -- ; -- ; +; L8 ; 538 ; 9A ; ^MSEL0 ; ; ; ; -- ; ; -- ; -- ; +; L9 ; 546 ; 9A ; ^MSEL4 ; ; ; ; -- ; ; -- ; -- ; +; L10 ; ; 8A ; VCCPD8A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; L11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L12 ; ; 8A ; VCCPD8A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; L13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L14 ; ; 8A ; VCCPD8A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; L15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L16 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; L17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L18 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; L19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L20 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; L21 ; ; -- ; VCCPLL_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; L22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L23 ; 350 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L24 ; 328 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L25 ; 330 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L26 ; 320 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L27 ; ; 6A ; VCCIO6A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; L28 ; 313 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L29 ; 315 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L30 ; 317 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M3 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; +; M4 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; +; M5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M6 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; M7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M9 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; M10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M11 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; M12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M13 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; M14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M15 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; M16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M17 ; 450 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; M18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M19 ; 334 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M21 ; ; 6A, 6B ; VCCPD6A6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; M22 ; 308 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M23 ; 348 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M24 ; ; 6A ; VCCIO6A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; M25 ; 324 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M26 ; 314 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M27 ; 312 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M28 ; 309 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M29 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M30 ; 311 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N5 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; N6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N7 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; N8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N10 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; N11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N12 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; N13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N14 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; N15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N16 ; 452 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; N17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N18 ; 332 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N20 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; N21 ; ; 6A ; VCCIO6A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; N22 ; ; 6A, 6B ; VCCPD6A6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; N23 ; 310 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N24 ; 318 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N25 ; 316 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N26 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N27 ; 297 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N28 ; 303 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N29 ; 305 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N30 ; 307 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P3 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; +; P4 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; +; P5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P6 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; P7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P11 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; P12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P13 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; P14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P15 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; P16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P17 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; P18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P19 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; P20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P21 ; ; 6A, 6B ; VCCPD6A6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; P22 ; 294 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P23 ; ; 6B ; VCCIO6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; P24 ; 290 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P25 ; 288 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P26 ; 298 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P27 ; 296 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P28 ; ; 6B ; VCCIO6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; P29 ; 299 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P30 ; 301 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; R2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; R3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; R4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; R5 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; R6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; R7 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; R8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; R9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; R10 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; R11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; R12 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; R13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; R14 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; R15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; R16 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; R17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; R18 ; 302 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R19 ; 300 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R20 ; ; 6A, 6B ; VCCPD6A6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; R21 ; 286 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R22 ; 284 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R23 ; ; 6A, 6B ; VCCPD6A6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; R24 ; 272 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R25 ; ; 6B ; VCCIO6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; R26 ; 280 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R27 ; 282 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R28 ; 293 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R29 ; 295 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R30 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T3 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; +; T4 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; +; T5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T6 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; T7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T11 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; T12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T13 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; T14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T17 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; T18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T19 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; T20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T21 ; 278 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T22 ; ; 6B ; VCCIO6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; T23 ; 270 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T24 ; 268 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T25 ; 266 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T26 ; 304 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T28 ; 287 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T29 ; 289 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T30 ; 291 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; U2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; U3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; U4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; U5 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; U6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; U7 ; 50 ; 3A ; ^DCLK ; ; ; ; Weak Pull Up ; ; -- ; On ; +; U8 ; 48 ; 3A ; #TDI ; input ; ; ; -- ; ; -- ; -- ; +; U9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; U10 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; U11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; U12 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; U13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; U14 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; U15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; U16 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; U17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; U18 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; U19 ; ; 6B ; VCCIO6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; U20 ; 276 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U21 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; U22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; U23 ; ; 5B ; VCCPD5B ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; U24 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; U25 ; 264 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U26 ; 306 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U27 ; 273 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U28 ; 285 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U29 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; U30 ; 283 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ; +; V1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; V2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; V3 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; +; V4 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; +; V5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; V6 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; V7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; V8 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; V9 ; 44 ; 3A ; #TMS ; input ; ; ; -- ; ; -- ; -- ; +; V10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; V11 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; V12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; V13 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; V14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; V15 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; V16 ; 138 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V17 ; 154 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V18 ; 194 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; V20 ; 292 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; V22 ; ; 5A ; VCCPD5A ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; V23 ; 236 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V24 ; ; 5A ; VCCPD5A ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; V25 ; 246 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V26 ; ; 6B ; VCCIO6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; V27 ; 265 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V28 ; 271 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V29 ; 275 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V30 ; 281 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; W1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; W2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; W3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; W4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; W5 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; W6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; W7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; W8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; W9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; W10 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; W11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; W12 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; W13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; W14 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; W15 ; 130 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W16 ; 136 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W17 ; 152 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; W19 ; 192 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W20 ; 217 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; W21 ; 221 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; W22 ; 223 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; W23 ; ; 5A ; VCCIO5A ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; W24 ; 238 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; W25 ; 244 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; W26 ; 274 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; W27 ; 261 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; W28 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; W29 ; 279 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; W30 ; 277 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; Y1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y3 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; +; Y4 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; +; Y5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y6 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; Y7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y9 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; Y10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y11 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; Y12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y13 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; Y14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y16 ; 128 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y17 ; 170 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y18 ; 178 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y19 ; 202 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y21 ; 219 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; Y22 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; Y23 ; 232 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; Y24 ; 234 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; Y25 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y26 ; 256 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; Y27 ; 258 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; Y28 ; 269 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; Y29 ; 263 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; Y30 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ++----------+------------+----------------+---------------------------------+--------+--------------+---------------------+--------------+-----------------+----------+--------------+ +Note: Pin directions (input, output or bidir) are based on device operating in user mode. + + ++-------------------------------------------------+ +; I/O Assignment Warnings ; ++----------+--------------------------------------+ +; Pin Name ; Reason ; ++----------+--------------------------------------+ +; HEX0[0] ; Missing drive strength and slew rate ; +; HEX0[1] ; Missing drive strength and slew rate ; +; HEX0[2] ; Missing drive strength and slew rate ; +; HEX0[3] ; Missing drive strength and slew rate ; +; HEX0[4] ; Missing drive strength and slew rate ; +; HEX0[5] ; Missing drive strength and slew rate ; +; HEX0[6] ; Missing drive strength and slew rate ; +; HEX1[0] ; Missing drive strength and slew rate ; +; HEX1[1] ; Missing drive strength and slew rate ; +; HEX1[2] ; Missing drive strength and slew rate ; +; HEX1[3] ; Missing drive strength and slew rate ; +; HEX1[4] ; Missing drive strength and slew rate ; +; HEX1[5] ; Missing drive strength and slew rate ; +; HEX1[6] ; Missing drive strength and slew rate ; +; HEX2[0] ; Missing drive strength and slew rate ; +; HEX2[1] ; Missing drive strength and slew rate ; +; HEX2[2] ; Missing drive strength and slew rate ; +; HEX2[3] ; Missing drive strength and slew rate ; +; HEX2[4] ; Missing drive strength and slew rate ; +; HEX2[5] ; Missing drive strength and slew rate ; +; HEX2[6] ; Missing drive strength and slew rate ; +; DAC_SDI ; Missing drive strength and slew rate ; +; DAC_SCK ; Missing drive strength and slew rate ; +; DAC_CS ; Missing drive strength and slew rate ; +; DAC_LD ; Missing drive strength and slew rate ; +; ADC_SDI ; Missing drive strength and slew rate ; +; ADC_SCK ; Missing drive strength and slew rate ; +; ADC_CS ; Missing drive strength and slew rate ; +; PWM_OUT ; Missing drive strength and slew rate ; ++----------+--------------------------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fitter Resource Utilization by Entity ; ++----------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+------------------------------+-------------+--------------+ +; Compilation Hierarchy Node ; ALMs needed [=A-B+C] ; [A] ALMs used in final placement ; [B] Estimate of ALMs recoverable by dense packing ; [C] Estimate of ALMs unavailable ; ALMs used for memory ; Combinational ALUTs ; Dedicated Logic Registers ; I/O Registers ; Block Memory Bits ; M10Ks ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name ; Entity Name ; Library Name ; ++----------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+------------------------------+-------------+--------------+ +; |ex16_top ; 61.5 (0.5) ; 71.0 (0.5) ; 9.5 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 109 (1) ; 113 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 41 ; 0 ; |ex16_top ; ex16_top ; work ; +; |clktick_16:GEN_10K| ; 11.5 (11.5) ; 11.5 (11.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 20 (20) ; 17 (17) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex16_top|clktick_16:GEN_10K ; clktick_16 ; work ; +; |hex_to_7seg:SEG0| ; 2.5 (2.5) ; 2.7 (2.7) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 7 (7) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex16_top|hex_to_7seg:SEG0 ; hex_to_7seg ; work ; +; |hex_to_7seg:SEG1| ; 2.2 (2.2) ; 2.8 (2.8) ; 0.7 (0.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 7 (7) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex16_top|hex_to_7seg:SEG1 ; hex_to_7seg ; work ; +; |hex_to_7seg:SEG2| ; 1.0 (1.0) ; 1.5 (1.5) ; 0.5 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 3 (3) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex16_top|hex_to_7seg:SEG2 ; hex_to_7seg ; work ; +; |processor:ALLPASS| ; 4.5 (4.5) ; 4.5 (4.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 9 (9) ; 8 (8) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex16_top|processor:ALLPASS ; processor ; work ; +; |pwm:PWM_DC| ; 9.5 (9.5) ; 10.5 (10.5) ; 1.0 (1.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 15 (15) ; 19 (19) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex16_top|pwm:PWM_DC ; pwm ; work ; +; |spi2adc:SPI_ADC| ; 15.3 (15.3) ; 22.3 (22.3) ; 7.0 (7.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 21 (21) ; 44 (44) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex16_top|spi2adc:SPI_ADC ; spi2adc ; work ; +; |spi2dac:SPI_DAC| ; 14.5 (14.5) ; 14.7 (14.7) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 26 (26) ; 25 (25) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex16_top|spi2dac:SPI_DAC ; spi2dac ; work ; ++----------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+------------------------------+-------------+--------------+ +Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. + + ++-------------------------------------------------------------------------------------------------------------------------+ +; Delay Chain Summary ; ++----------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+ +; Name ; Pin Type ; D1 ; D3_0 ; D3_1 ; D4 ; D5 ; D5 OE ; D5 OCT ; T11 (Postamble Gating) ; T11 (Postamble Ungating) ; ++----------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+ +; SW[0] ; Input ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; +; SW[1] ; Input ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; +; SW[2] ; Input ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; +; SW[3] ; Input ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; +; SW[4] ; Input ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; +; SW[5] ; Input ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; +; SW[6] ; Input ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; +; SW[7] ; Input ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; +; SW[8] ; Input ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; +; SW[9] ; Input ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; +; HEX0[0] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; HEX0[1] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; HEX0[2] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; HEX0[3] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; HEX0[4] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; HEX0[5] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; HEX0[6] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; HEX1[0] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; HEX1[1] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; HEX1[2] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; HEX1[3] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; HEX1[4] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; HEX1[5] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; HEX1[6] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; HEX2[0] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; HEX2[1] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; HEX2[2] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; HEX2[3] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; HEX2[4] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; HEX2[5] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; HEX2[6] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; DAC_SDI ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; DAC_SCK ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; DAC_CS ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; DAC_LD ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; ADC_SDI ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; ADC_SCK ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; ADC_CS ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; PWM_OUT ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; CLOCK_50 ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; +; ADC_SDO ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; ++----------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+ + + ++--------------------------------------------------------------------------+ +; Pad To Core Delay Chain Fanout ; ++--------------------------------------------+-------------------+---------+ +; Source Pin / Fanout ; Pad To Core Index ; Setting ; ++--------------------------------------------+-------------------+---------+ +; SW[0] ; ; ; +; SW[1] ; ; ; +; SW[2] ; ; ; +; SW[3] ; ; ; +; SW[4] ; ; ; +; SW[5] ; ; ; +; SW[6] ; ; ; +; SW[7] ; ; ; +; SW[8] ; ; ; +; SW[9] ; ; ; +; CLOCK_50 ; ; ; +; - spi2dac:SPI_DAC|clk_1MHz ; 0 ; 0 ; +; - spi2adc:SPI_ADC|clk_1MHz ; 0 ; 0 ; +; ADC_SDO ; ; ; +; - spi2adc:SPI_ADC|shift_reg[0]~feeder ; 1 ; 0 ; ++--------------------------------------------+-------------------+---------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Control Signals ; ++-----------------------------+--------------------+---------+--------------+--------+----------------------+------------------+---------------------------+ +; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ; ++-----------------------------+--------------------+---------+--------------+--------+----------------------+------------------+---------------------------+ +; CLOCK_50 ; PIN_AF14 ; 3 ; Clock ; no ; -- ; -- ; -- ; +; CLOCK_50 ; PIN_AF14 ; 60 ; Clock ; yes ; Global Clock ; GCLK6 ; -- ; +; clktick_16:GEN_10K|Equal0~3 ; LABCELL_X71_Y7_N33 ; 10 ; Sync. clear ; no ; -- ; -- ; -- ; +; clktick_16:GEN_10K|tick ; FF_X71_Y7_N32 ; 14 ; Clock enable ; no ; -- ; -- ; -- ; +; spi2adc:SPI_ADC|adc_done ; FF_X66_Y4_N20 ; 11 ; Clock enable ; no ; -- ; -- ; -- ; +; spi2adc:SPI_ADC|always3~0 ; LABCELL_X66_Y4_N51 ; 10 ; Clock enable ; no ; -- ; -- ; -- ; +; spi2adc:SPI_ADC|clk_1MHz ; FF_X67_Y4_N11 ; 33 ; Clock ; no ; -- ; -- ; -- ; +; spi2dac:SPI_DAC|Equal0~0 ; LABCELL_X68_Y4_N57 ; 2 ; Clock enable ; no ; -- ; -- ; -- ; +; spi2dac:SPI_DAC|clk_1MHz ; FF_X67_Y4_N8 ; 22 ; Clock ; no ; -- ; -- ; -- ; ++-----------------------------+--------------------+---------+--------------+--------+----------------------+------------------+---------------------------+ + + ++-----------------------------------------------------------------------------------------------------+ +; Global & Other Fast Signals ; ++----------+----------+---------+----------------------+------------------+---------------------------+ +; Name ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ; ++----------+----------+---------+----------------------+------------------+---------------------------+ +; CLOCK_50 ; PIN_AF14 ; 60 ; Global Clock ; GCLK6 ; -- ; ++----------+----------+---------+----------------------+------------------+---------------------------+ + + ++-----------------------------------------------------------------------+ +; Routing Usage Summary ; ++---------------------------------------------+-------------------------+ +; Routing Resource Type ; Usage ; ++---------------------------------------------+-------------------------+ +; Block interconnects ; 151 / 289,320 ( < 1 % ) ; +; C12 interconnects ; 6 / 13,420 ( < 1 % ) ; +; C2 interconnects ; 24 / 119,108 ( < 1 % ) ; +; C4 interconnects ; 38 / 56,300 ( < 1 % ) ; +; DQS bus muxes ; 0 / 25 ( 0 % ) ; +; DQS-18 I/O buses ; 0 / 25 ( 0 % ) ; +; DQS-9 I/O buses ; 0 / 25 ( 0 % ) ; +; Direct links ; 43 / 289,320 ( < 1 % ) ; +; Global clocks ; 1 / 16 ( 6 % ) ; +; HPS SDRAM PLL inputs ; 0 / 1 ( 0 % ) ; +; HPS SDRAM PLL outputs ; 0 / 1 ( 0 % ) ; +; HPS_INTERFACE_BOOT_FROM_FPGA_INPUTs ; 0 / 9 ( 0 % ) ; +; HPS_INTERFACE_CLOCKS_RESETS_INPUTs ; 0 / 7 ( 0 % ) ; +; HPS_INTERFACE_CLOCKS_RESETS_OUTPUTs ; 0 / 6 ( 0 % ) ; +; HPS_INTERFACE_CROSS_TRIGGER_INPUTs ; 0 / 18 ( 0 % ) ; +; HPS_INTERFACE_CROSS_TRIGGER_OUTPUTs ; 0 / 24 ( 0 % ) ; +; HPS_INTERFACE_DBG_APB_INPUTs ; 0 / 37 ( 0 % ) ; +; HPS_INTERFACE_DBG_APB_OUTPUTs ; 0 / 55 ( 0 % ) ; +; HPS_INTERFACE_DMA_INPUTs ; 0 / 16 ( 0 % ) ; +; HPS_INTERFACE_DMA_OUTPUTs ; 0 / 8 ( 0 % ) ; +; HPS_INTERFACE_FPGA2HPS_INPUTs ; 0 / 287 ( 0 % ) ; +; HPS_INTERFACE_FPGA2HPS_OUTPUTs ; 0 / 154 ( 0 % ) ; +; HPS_INTERFACE_FPGA2SDRAM_INPUTs ; 0 / 852 ( 0 % ) ; +; HPS_INTERFACE_FPGA2SDRAM_OUTPUTs ; 0 / 408 ( 0 % ) ; +; HPS_INTERFACE_HPS2FPGA_INPUTs ; 0 / 165 ( 0 % ) ; +; HPS_INTERFACE_HPS2FPGA_LIGHT_WEIGHT_INPUTs ; 0 / 67 ( 0 % ) ; +; HPS_INTERFACE_HPS2FPGA_LIGHT_WEIGHT_OUTPUTs ; 0 / 156 ( 0 % ) ; +; HPS_INTERFACE_HPS2FPGA_OUTPUTs ; 0 / 282 ( 0 % ) ; +; HPS_INTERFACE_INTERRUPTS_INPUTs ; 0 / 64 ( 0 % ) ; +; HPS_INTERFACE_INTERRUPTS_OUTPUTs ; 0 / 42 ( 0 % ) ; +; HPS_INTERFACE_JTAG_OUTPUTs ; 0 / 5 ( 0 % ) ; +; HPS_INTERFACE_LOAN_IO_INPUTs ; 0 / 142 ( 0 % ) ; +; HPS_INTERFACE_LOAN_IO_OUTPUTs ; 0 / 85 ( 0 % ) ; +; HPS_INTERFACE_MPU_EVENT_STANDBY_INPUTs ; 0 / 1 ( 0 % ) ; +; HPS_INTERFACE_MPU_EVENT_STANDBY_OUTPUTs ; 0 / 5 ( 0 % ) ; +; HPS_INTERFACE_MPU_GENERAL_PURPOSE_INPUTs ; 0 / 32 ( 0 % ) ; +; HPS_INTERFACE_MPU_GENERAL_PURPOSE_OUTPUTs ; 0 / 32 ( 0 % ) ; +; HPS_INTERFACE_PERIPHERAL_CAN_INPUTs ; 0 / 2 ( 0 % ) ; +; HPS_INTERFACE_PERIPHERAL_CAN_OUTPUTs ; 0 / 2 ( 0 % ) ; +; HPS_INTERFACE_PERIPHERAL_EMAC_INPUTs ; 0 / 32 ( 0 % ) ; +; HPS_INTERFACE_PERIPHERAL_EMAC_OUTPUTs ; 0 / 34 ( 0 % ) ; +; HPS_INTERFACE_PERIPHERAL_I2C_INPUTs ; 0 / 8 ( 0 % ) ; +; HPS_INTERFACE_PERIPHERAL_I2C_OUTPUTs ; 0 / 8 ( 0 % ) ; +; HPS_INTERFACE_PERIPHERAL_NAND_INPUTs ; 0 / 12 ( 0 % ) ; +; HPS_INTERFACE_PERIPHERAL_NAND_OUTPUTs ; 0 / 18 ( 0 % ) ; +; HPS_INTERFACE_PERIPHERAL_QSPI_INPUTs ; 0 / 4 ( 0 % ) ; +; HPS_INTERFACE_PERIPHERAL_QSPI_OUTPUTs ; 0 / 13 ( 0 % ) ; +; HPS_INTERFACE_PERIPHERAL_SDMMC_INPUTs ; 0 / 13 ( 0 % ) ; +; HPS_INTERFACE_PERIPHERAL_SDMMC_OUTPUTs ; 0 / 22 ( 0 % ) ; +; HPS_INTERFACE_PERIPHERAL_SPI_MASTER_INPUTs ; 0 / 4 ( 0 % ) ; +; HPS_INTERFACE_PERIPHERAL_SPI_MASTER_OUTPUTs ; 0 / 14 ( 0 % ) ; +; HPS_INTERFACE_PERIPHERAL_SPI_SLAVE_INPUTs ; 0 / 6 ( 0 % ) ; +; HPS_INTERFACE_PERIPHERAL_SPI_SLAVE_OUTPUTs ; 0 / 4 ( 0 % ) ; +; HPS_INTERFACE_PERIPHERAL_UART_INPUTs ; 0 / 10 ( 0 % ) ; +; HPS_INTERFACE_PERIPHERAL_UART_OUTPUTs ; 0 / 10 ( 0 % ) ; +; HPS_INTERFACE_PERIPHERAL_USB_INPUTs ; 0 / 22 ( 0 % ) ; +; HPS_INTERFACE_PERIPHERAL_USB_OUTPUTs ; 0 / 34 ( 0 % ) ; +; HPS_INTERFACE_STM_EVENT_INPUTs ; 0 / 28 ( 0 % ) ; +; HPS_INTERFACE_TEST_INPUTs ; 0 / 610 ( 0 % ) ; +; HPS_INTERFACE_TEST_OUTPUTs ; 0 / 513 ( 0 % ) ; +; HPS_INTERFACE_TPIU_TRACE_INPUTs ; 0 / 2 ( 0 % ) ; +; HPS_INTERFACE_TPIU_TRACE_OUTPUTs ; 0 / 33 ( 0 % ) ; +; Horizontal periphery clocks ; 0 / 72 ( 0 % ) ; +; Local interconnects ; 72 / 84,580 ( < 1 % ) ; +; Quadrant clocks ; 0 / 66 ( 0 % ) ; +; R14 interconnects ; 11 / 12,676 ( < 1 % ) ; +; R14/C12 interconnect drivers ; 16 / 20,720 ( < 1 % ) ; +; R3 interconnects ; 62 / 130,992 ( < 1 % ) ; +; R6 interconnects ; 92 / 266,960 ( < 1 % ) ; +; Spine clocks ; 2 / 360 ( < 1 % ) ; +; Wire stub REs ; 0 / 15,858 ( 0 % ) ; ++---------------------------------------------+-------------------------+ + + ++------------------------------------------+ +; I/O Rules Summary ; ++----------------------------------+-------+ +; I/O Rules Statistic ; Total ; ++----------------------------------+-------+ +; Total I/O Rules ; 28 ; +; Number of I/O Rules Passed ; 6 ; +; Number of I/O Rules Failed ; 0 ; +; Number of I/O Rules Unchecked ; 0 ; +; Number of I/O Rules Inapplicable ; 22 ; ++----------------------------------+-------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; I/O Rules Details ; ++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+------+-------------------+ +; Status ; ID ; Category ; Rule Description ; Severity ; Information ; Area ; Extra Information ; ++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+------+-------------------+ +; Pass ; IO_000001 ; Capacity Checks ; Number of pins in an I/O bank should not exceed the number of locations available. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000002 ; Capacity Checks ; Number of clocks in an I/O bank should not exceed the number of clocks available. ; Critical ; No Global Signal assignments found. ; I/O ; ; +; Pass ; IO_000003 ; Capacity Checks ; Number of pins in a Vrefgroup should not exceed the number of locations available. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000004 ; Voltage Compatibility Checks ; The I/O bank should support the requested VCCIO. ; Critical ; No IOBANK_VCCIO assignments found. ; I/O ; ; +; Inapplicable ; IO_000005 ; Voltage Compatibility Checks ; The I/O bank should not have competing VREF values. ; Critical ; No VREF I/O Standard assignments found. ; I/O ; ; +; Pass ; IO_000006 ; Voltage Compatibility Checks ; The I/O bank should not have competing VCCIO values. ; Critical ; 0 such failures found. ; I/O ; ; +; Pass ; IO_000007 ; Valid Location Checks ; Checks for unavailable locations. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000008 ; Valid Location Checks ; Checks for reserved locations. ; Critical ; No reserved LogicLock region found. ; I/O ; ; +; Pass ; IO_000009 ; I/O Properties Checks for One I/O ; The location should support the requested I/O standard. ; Critical ; 0 such failures found. ; I/O ; ; +; Pass ; IO_000010 ; I/O Properties Checks for One I/O ; The location should support the requested I/O direction. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000011 ; I/O Properties Checks for One I/O ; The location should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ; +; Inapplicable ; IO_000012 ; I/O Properties Checks for One I/O ; The location should support the requested On Chip Termination value. ; Critical ; No Termination assignments found. ; I/O ; ; +; Inapplicable ; IO_000013 ; I/O Properties Checks for One I/O ; The location should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ; +; Inapplicable ; IO_000014 ; I/O Properties Checks for One I/O ; The location should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ; +; Inapplicable ; IO_000015 ; I/O Properties Checks for One I/O ; The location should support the requested PCI Clamp Diode. ; Critical ; No Clamping Diode assignments found. ; I/O ; ; +; Inapplicable ; IO_000018 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ; +; Inapplicable ; IO_000019 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested On Chip Termination value. ; Critical ; No Termination assignments found. ; I/O ; ; +; Inapplicable ; IO_000020 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested PCI Clamp Diode. ; Critical ; No Clamping Diode assignments found. ; I/O ; ; +; Inapplicable ; IO_000021 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ; +; Inapplicable ; IO_000022 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ; +; Inapplicable ; IO_000023 ; I/O Properties Checks for One I/O ; The I/O standard should support the Open Drain value. ; Critical ; No open drain assignments found. ; I/O ; ; +; Inapplicable ; IO_000024 ; I/O Properties Checks for One I/O ; The I/O direction should support the On Chip Termination value. ; Critical ; No Termination assignments found. ; I/O ; ; +; Inapplicable ; IO_000026 ; I/O Properties Checks for One I/O ; On Chip Termination and Current Strength should not be used at the same time. ; Critical ; No Current Strength or Termination assignments found. ; I/O ; ; +; Inapplicable ; IO_000027 ; I/O Properties Checks for One I/O ; Weak Pull Up and Bus Hold should not be used at the same time. ; Critical ; No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found. ; I/O ; ; +; Inapplicable ; IO_000045 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ; +; Inapplicable ; IO_000046 ; I/O Properties Checks for One I/O ; The location should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ; +; Inapplicable ; IO_000047 ; I/O Properties Checks for One I/O ; On Chip Termination and Slew Rate should not be used at the same time. ; Critical ; No Slew Rate assignments found. ; I/O ; ; +; Inapplicable ; IO_000034 ; SI Related Distance Checks ; Single-ended outputs should be 0 LAB row(s) away from a differential I/O. ; High ; No Differential I/O Standard assignments found. ; I/O ; ; ++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+------+-------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; I/O Rules Matrix ; ++--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+ +; Pin/Rules ; IO_000001 ; IO_000002 ; IO_000003 ; IO_000004 ; IO_000005 ; IO_000006 ; IO_000007 ; IO_000008 ; IO_000009 ; IO_000010 ; IO_000011 ; IO_000012 ; IO_000013 ; IO_000014 ; IO_000015 ; IO_000018 ; IO_000019 ; IO_000020 ; IO_000021 ; IO_000022 ; IO_000023 ; IO_000024 ; IO_000026 ; IO_000027 ; IO_000045 ; IO_000046 ; IO_000047 ; IO_000034 ; ++--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+ +; Total Pass ; 41 ; 0 ; 41 ; 0 ; 0 ; 41 ; 41 ; 0 ; 41 ; 41 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; Total Unchecked ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; Total Inapplicable ; 0 ; 41 ; 0 ; 41 ; 41 ; 0 ; 0 ; 41 ; 0 ; 0 ; 41 ; 41 ; 41 ; 41 ; 41 ; 41 ; 41 ; 41 ; 41 ; 41 ; 41 ; 41 ; 41 ; 41 ; 41 ; 41 ; 41 ; 41 ; +; Total Fail ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; SW[0] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; SW[1] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; SW[2] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; SW[3] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; SW[4] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; SW[5] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; SW[6] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; SW[7] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; SW[8] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; SW[9] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; HEX0[0] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; HEX0[1] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; HEX0[2] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; HEX0[3] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; HEX0[4] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; HEX0[5] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; HEX0[6] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; HEX1[0] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; HEX1[1] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; HEX1[2] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; HEX1[3] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; HEX1[4] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; HEX1[5] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; HEX1[6] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; HEX2[0] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; HEX2[1] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; HEX2[2] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; HEX2[3] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; HEX2[4] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; HEX2[5] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; HEX2[6] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; DAC_SDI ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; DAC_SCK ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; DAC_CS ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; DAC_LD ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; ADC_SDI ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; ADC_SCK ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; ADC_CS ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; PWM_OUT ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; CLOCK_50 ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; ADC_SDO ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; ++--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+ + + ++------------------------------------------------------------------------------------------------+ +; Fitter Device Options ; ++------------------------------------------------------------------+-----------------------------+ +; Option ; Setting ; ++------------------------------------------------------------------+-----------------------------+ +; Enable user-supplied start-up clock (CLKUSR) ; Off ; +; Enable device-wide reset (DEV_CLRn) ; Off ; +; Enable device-wide output enable (DEV_OE) ; Off ; +; Enable INIT_DONE output ; Off ; +; Configuration scheme ; Passive Serial ; +; Enable Error Detection CRC_ERROR pin ; Off ; +; Enable CvP_CONFDONE pin ; Off ; +; Enable open drain on CRC_ERROR pin ; On ; +; Enable open drain on CvP_CONFDONE pin ; On ; +; Enable open drain on INIT_DONE pin ; On ; +; Enable open drain on Partial Reconfiguration pins ; Off ; +; Enable open drain on nCEO pin ; On ; +; Enable Partial Reconfiguration pins ; Off ; +; Enable input tri-state on active configuration pins in user mode ; Off ; +; Enable internal scrubbing ; Off ; +; Active Serial clock source ; 100 MHz Internal Oscillator ; +; Device initialization clock source ; Internal Oscillator ; +; Configuration via Protocol ; Off ; +; Configuration Voltage Level ; Auto ; +; Force Configuration Voltage Level ; Off ; +; Enable nCEO output ; Off ; +; Data[15..8] ; Unreserved ; +; Data[7..5] ; Unreserved ; +; Base pin-out file on sameframe device ; Off ; ++------------------------------------------------------------------+-----------------------------+ + + ++------------------------------------+ +; Operating Settings and Conditions ; ++---------------------------+--------+ +; Setting ; Value ; ++---------------------------+--------+ +; Nominal Core Voltage ; 1.10 V ; +; Low Junction Temperature ; 0 °C ; +; High Junction Temperature ; 85 °C ; ++---------------------------+--------+ + + ++------------------------------------------------------------+ +; Estimated Delay Added for Hold Timing Summary ; ++-----------------+----------------------+-------------------+ +; Source Clock(s) ; Destination Clock(s) ; Delay Added in ns ; ++-----------------+----------------------+-------------------+ +; CLOCK_50 ; CLOCK_50 ; 16.3 ; ++-----------------+----------------------+-------------------+ +Note: For more information on problematic transfers, consider running the Fitter again with the Optimize hold timing option (Settings Menu) turned off. +This will disable optimization of problematic paths and expose them for further analysis using the TimeQuest Timing Analyzer. + + ++-----------------------------------------------------------------------------------------------------+ +; Estimated Delay Added for Hold Timing Details ; ++----------------------------------------+----------------------------------------+-------------------+ +; Source Register ; Destination Register ; Delay Added in ns ; ++----------------------------------------+----------------------------------------+-------------------+ +; spi2adc:SPI_ADC|ctr[4] ; spi2adc:SPI_ADC|clk_1MHz ; 1.536 ; +; spi2adc:SPI_ADC|ctr[2] ; spi2adc:SPI_ADC|clk_1MHz ; 1.515 ; +; spi2adc:SPI_ADC|ctr[0] ; spi2adc:SPI_ADC|clk_1MHz ; 1.488 ; +; spi2adc:SPI_ADC|ctr[1] ; spi2adc:SPI_ADC|clk_1MHz ; 1.473 ; +; spi2adc:SPI_ADC|ctr[3] ; spi2adc:SPI_ADC|clk_1MHz ; 1.219 ; +; pwm:PWM_DC|d[8] ; pwm:PWM_DC|pwm_out ; 0.430 ; +; pwm:PWM_DC|count[9] ; pwm:PWM_DC|pwm_out ; 0.417 ; +; pwm:PWM_DC|count[0] ; pwm:PWM_DC|count[9] ; 0.410 ; +; spi2dac:SPI_DAC|sr_state.IDLE ; spi2dac:SPI_DAC|sr_state.WAIT_CSB_FALL ; 0.375 ; +; spi2adc:SPI_ADC|sr_state.IDLE ; spi2adc:SPI_ADC|sr_state.WAIT_CSB_FALL ; 0.365 ; +; pwm:PWM_DC|d[9] ; pwm:PWM_DC|pwm_out ; 0.364 ; +; spi2dac:SPI_DAC|sr_state.WAIT_CSB_HIGH ; spi2dac:SPI_DAC|sr_state.IDLE ; 0.344 ; +; spi2adc:SPI_ADC|sr_state.WAIT_CSB_HIGH ; spi2adc:SPI_ADC|sr_state.IDLE ; 0.339 ; +; pwm:PWM_DC|d[4] ; pwm:PWM_DC|pwm_out ; 0.324 ; +; pwm:PWM_DC|d[3] ; pwm:PWM_DC|pwm_out ; 0.324 ; +; pwm:PWM_DC|d[2] ; pwm:PWM_DC|pwm_out ; 0.324 ; +; pwm:PWM_DC|d[7] ; pwm:PWM_DC|pwm_out ; 0.324 ; +; pwm:PWM_DC|d[6] ; pwm:PWM_DC|pwm_out ; 0.324 ; +; pwm:PWM_DC|d[5] ; pwm:PWM_DC|pwm_out ; 0.324 ; +; pwm:PWM_DC|count[7] ; pwm:PWM_DC|pwm_out ; 0.324 ; +; pwm:PWM_DC|count[6] ; pwm:PWM_DC|pwm_out ; 0.324 ; +; pwm:PWM_DC|count[5] ; pwm:PWM_DC|pwm_out ; 0.324 ; +; pwm:PWM_DC|count[4] ; pwm:PWM_DC|pwm_out ; 0.324 ; +; pwm:PWM_DC|count[3] ; pwm:PWM_DC|pwm_out ; 0.324 ; +; pwm:PWM_DC|count[2] ; pwm:PWM_DC|pwm_out ; 0.324 ; +; pwm:PWM_DC|count[1] ; pwm:PWM_DC|pwm_out ; 0.324 ; +; spi2adc:SPI_ADC|sr_state.WAIT_CSB_FALL ; spi2adc:SPI_ADC|adc_start ; 0.319 ; +; spi2dac:SPI_DAC|sr_state.WAIT_CSB_FALL ; spi2dac:SPI_DAC|dac_start ; 0.307 ; +; pwm:PWM_DC|count[8] ; pwm:PWM_DC|pwm_out ; 0.262 ; +; clktick_16:GEN_10K|count[7] ; clktick_16:GEN_10K|count[15] ; 0.060 ; +; clktick_16:GEN_10K|count[9] ; clktick_16:GEN_10K|count[15] ; 0.057 ; +; clktick_16:GEN_10K|count[15] ; clktick_16:GEN_10K|count[15] ; 0.056 ; +; clktick_16:GEN_10K|count[1] ; clktick_16:GEN_10K|count[15] ; 0.055 ; +; clktick_16:GEN_10K|count[12] ; clktick_16:GEN_10K|count[15] ; 0.053 ; +; clktick_16:GEN_10K|count[8] ; clktick_16:GEN_10K|count[15] ; 0.051 ; +; clktick_16:GEN_10K|count[5] ; clktick_16:GEN_10K|count[15] ; 0.046 ; +; clktick_16:GEN_10K|count[13] ; clktick_16:GEN_10K|count[15] ; 0.043 ; +; clktick_16:GEN_10K|count[3] ; clktick_16:GEN_10K|count[15] ; 0.042 ; +; clktick_16:GEN_10K|count[6] ; clktick_16:GEN_10K|count[15] ; 0.040 ; +; clktick_16:GEN_10K|count[0] ; clktick_16:GEN_10K|count[15] ; 0.031 ; ++----------------------------------------+----------------------------------------+-------------------+ +Note: This table only shows the top 40 path(s) that have the largest delay added for hold. + + ++-----------------+ +; Fitter Messages ; ++-----------------+ +Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. +Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected +Info (119006): Selected device 5CSEMA5F31C6 for design "ex16_top" +Info (21077): Low junction temperature is 0 degrees C +Info (21077): High junction temperature is 85 degrees C +Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time +Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature. +Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details +Info (184020): Starting Fitter periphery placement operations +Info (11191): Automatically promoted 1 clock (1 global) + Info (11162): CLOCK_50~inputCLKENA0 with 57 fanout uses global clock CLKCTRL_G6 +Info (184021): Fitter periphery placement operations ending: elapsed time is 00:00:01 +Info (176233): Starting register packing +Info (332104): Reading SDC File: 'ex16_top.sdc' +Warning (332060): Node: spi2adc:SPI_ADC|clk_1MHz was determined to be a clock but was found without an associated clock assignment. + Info (13166): Register spi2adc:SPI_ADC|data_from_adc[0] is being clocked by spi2adc:SPI_ADC|clk_1MHz +Warning (332060): Node: spi2dac:SPI_DAC|clk_1MHz was determined to be a clock but was found without an associated clock assignment. + Info (13166): Register spi2dac:SPI_DAC|shift_reg[15] is being clocked by spi2dac:SPI_DAC|clk_1MHz +Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty" +Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. +Info (332129): Detected timing requirements -- optimizing circuit to achieve only the specified requirements +Info (332111): Found 1 clocks + Info (332111): Period Clock Name + Info (332111): ======== ============ + Info (332111): 20.000 CLOCK_50 +Info (176235): Finished register packing + Extra Info (176219): No registers were packed into other blocks +Warning (15705): Ignored locations or region assignments to the following nodes + Warning (15706): Node "HEX3[0]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HEX3[1]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HEX3[2]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HEX3[3]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HEX3[4]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HEX3[5]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HEX3[6]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HEX4[0]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HEX4[1]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HEX4[2]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HEX4[3]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HEX4[4]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HEX4[5]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HEX4[6]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HEX5[0]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HEX5[1]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HEX5[2]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HEX5[3]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HEX5[4]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HEX5[5]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HEX5[6]" is assigned to location or region, but does not exist in design + Warning (15706): Node "KEY[0]" is assigned to location or region, but does not exist in design + Warning (15706): Node "KEY[1]" is assigned to location or region, but does not exist in design + Warning (15706): Node "KEY[2]" is assigned to location or region, but does not exist in design + Warning (15706): Node "KEY[3]" is assigned to location or region, but does not exist in design + Warning (15706): Node "LEDR[0]" is assigned to location or region, but does not exist in design + Warning (15706): Node "LEDR[1]" is assigned to location or region, but does not exist in design + Warning (15706): Node "LEDR[2]" is assigned to location or region, but does not exist in design + Warning (15706): Node "LEDR[3]" is assigned to location or region, but does not exist in design + Warning (15706): Node "LEDR[4]" is assigned to location or region, but does not exist in design + Warning (15706): Node "LEDR[5]" is assigned to location or region, but does not exist in design + Warning (15706): Node "LEDR[6]" is assigned to location or region, but does not exist in design + Warning (15706): Node "LEDR[7]" is assigned to location or region, but does not exist in design + Warning (15706): Node "LEDR[8]" is assigned to location or region, but does not exist in design + Warning (15706): Node "LEDR[9]" is assigned to location or region, but does not exist in design + Warning (15706): Node "OLED_CLK" is assigned to location or region, but does not exist in design + Warning (15706): Node "OLED_CS" is assigned to location or region, but does not exist in design + Warning (15706): Node "OLED_DATA" is assigned to location or region, but does not exist in design + Warning (15706): Node "OLED_DC" is assigned to location or region, but does not exist in design + Warning (15706): Node "OLED_RST" is assigned to location or region, but does not exist in design +Info (11798): Fitter preparation operations ending: elapsed time is 00:01:18 +Info (170189): Fitter placement preparation operations beginning +Info (14951): The Fitter is using Advanced Physical Optimization. +Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:15 +Info (170191): Fitter placement operations beginning +Info (170137): Fitter placement was successful +Info (170192): Fitter placement operations ending: elapsed time is 00:00:02 +Info (170193): Fitter routing operations beginning +Info (170195): Router estimated average interconnect usage is 0% of the available device resources + Info (170196): Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X67_Y0 to location X77_Y10 +Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time. + Info (170201): Optimizations that may affect the design's routability were skipped + Info (170200): Optimizations that may affect the design's timing were skipped +Info (170194): Fitter routing operations ending: elapsed time is 00:00:13 +Info (11888): Total time spent on timing analysis during the Fitter is 2.13 seconds. +Info (334003): Started post-fitting delay annotation +Info (334004): Delay annotation completed successfully +Info (334003): Started post-fitting delay annotation +Info (334004): Delay annotation completed successfully +Info (11801): Fitter post-fit operations ending: elapsed time is 00:00:16 +Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information. +Info (144001): Generated suppressed messages file H:/Year 2/VERI/part_4/ex16/ex16_top.fit.smsg +Info: Quartus Prime Fitter was successful. 0 errors, 47 warnings + Info: Peak virtual memory: 2147 megabytes + Info: Processing ended: Sat Dec 10 18:26:33 2016 + Info: Elapsed time: 00:04:40 + Info: Total CPU time (on all processors): 00:01:47 + + ++----------------------------+ +; Fitter Suppressed Messages ; ++----------------------------+ +The suppressed messages can be found in H:/Year 2/VERI/part_4/ex16/ex16_top.fit.smsg. + + diff --git a/part_4/ex16/ex16_top.flow.rpt b/part_4/ex16/ex16_top.flow.rpt new file mode 100644 index 0000000..d75192e --- /dev/null +++ b/part_4/ex16/ex16_top.flow.rpt @@ -0,0 +1,131 @@ +Flow report for ex16_top +Sat Dec 10 18:30:59 2016 +Quartus Prime Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Flow Summary + 3. Flow Settings + 4. Flow Non-Default Global Settings + 5. Flow Elapsed Time + 6. Flow OS Summary + 7. Flow Log + 8. Flow Messages + 9. Flow Suppressed Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2016 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel MegaCore Function License Agreement, or other +applicable license agreement, including, without limitation, +that your use is for the sole purpose of programming logic +devices manufactured by Intel and sold by Intel or its +authorized distributors. Please refer to the applicable +agreement for further details. + + + ++-------------------------------------------------------------------------------+ +; Flow Summary ; ++---------------------------------+---------------------------------------------+ +; Flow Status ; Successful - Sat Dec 10 18:30:59 2016 ; +; Quartus Prime Version ; 16.1.0 Build 196 10/24/2016 SJ Lite Edition ; +; Revision Name ; ex16_top ; +; Top-level Entity Name ; ex16_top ; +; Family ; Cyclone V ; +; Device ; 5CSEMA5F31C6 ; +; Timing Models ; Final ; +; Logic utilization (in ALMs) ; 62 / 32,070 ( < 1 % ) ; +; Total registers ; 113 ; +; Total pins ; 41 / 457 ( 9 % ) ; +; Total virtual pins ; 0 ; +; Total block memory bits ; 0 / 4,065,280 ( 0 % ) ; +; Total DSP Blocks ; 0 / 87 ( 0 % ) ; +; Total HSSI RX PCSs ; 0 ; +; Total HSSI PMA RX Deserializers ; 0 ; +; Total HSSI TX PCSs ; 0 ; +; Total HSSI PMA TX Serializers ; 0 ; +; Total PLLs ; 0 / 6 ( 0 % ) ; +; Total DLLs ; 0 / 4 ( 0 % ) ; ++---------------------------------+---------------------------------------------+ + + ++-----------------------------------------+ +; Flow Settings ; ++-------------------+---------------------+ +; Option ; Setting ; ++-------------------+---------------------+ +; Start date & time ; 12/10/2016 18:19:09 ; +; Main task ; Compilation ; +; Revision Name ; ex16_top ; ++-------------------+---------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------+ +; Flow Non-Default Global Settings ; ++-------------------------------------+----------------------------------------+---------------+-------------+------------+ +; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ; ++-------------------------------------+----------------------------------------+---------------+-------------+------------+ +; COMPILER_SIGNATURE_ID ; 147774608559.148139394706592 ; -- ; -- ; -- ; +; EDA_SIMULATION_TOOL ; ModelSim-Altera (Verilog) ; ; -- ; -- ; +; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ; +; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ; +; PARTITION_COLOR ; -- (Not supported for targeted family) ; -- ; -- ; Top ; +; PARTITION_FITTER_PRESERVATION_LEVEL ; -- (Not supported for targeted family) ; -- ; -- ; Top ; +; PARTITION_NETLIST_TYPE ; -- (Not supported for targeted family) ; -- ; -- ; Top ; +; POWER_BOARD_THERMAL_MODEL ; None (CONSERVATIVE) ; -- ; -- ; -- ; +; POWER_PRESET_COOLING_SOLUTION ; 23 MM HEAT SINK WITH 200 LFPM AIRFLOW ; -- ; -- ; -- ; ++-------------------------------------+----------------------------------------+---------------+-------------+------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------+ +; Flow Elapsed Time ; ++---------------------------+--------------+-------------------------+---------------------+------------------------------------+ +; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; ++---------------------------+--------------+-------------------------+---------------------+------------------------------------+ +; Analysis & Synthesis ; 00:02:10 ; 1.0 ; 698 MB ; 00:00:40 ; +; Fitter ; 00:04:17 ; 1.0 ; 2147 MB ; 00:01:46 ; +; Assembler ; 00:01:37 ; 1.0 ; 727 MB ; 00:00:19 ; +; TimeQuest Timing Analyzer ; 00:01:18 ; 1.0 ; 1006 MB ; 00:00:12 ; +; EDA Netlist Writer ; 00:00:13 ; 1.0 ; 628 MB ; 00:00:03 ; +; Total ; 00:09:35 ; -- ; -- ; 00:03:00 ; ++---------------------------+--------------+-------------------------+---------------------+------------------------------------+ + + ++-----------------------------------------------------------------------------------------+ +; Flow OS Summary ; ++---------------------------+------------------+------------+------------+----------------+ +; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ; ++---------------------------+------------------+------------+------------+----------------+ +; Analysis & Synthesis ; Xav-Laptop ; Windows 10 ; 10.0 ; x86_64 ; +; Fitter ; Xav-Laptop ; Windows 10 ; 10.0 ; x86_64 ; +; Assembler ; Xav-Laptop ; Windows 10 ; 10.0 ; x86_64 ; +; TimeQuest Timing Analyzer ; Xav-Laptop ; Windows 10 ; 10.0 ; x86_64 ; +; EDA Netlist Writer ; Xav-Laptop ; Windows 10 ; 10.0 ; x86_64 ; ++---------------------------+------------------+------------+------------+----------------+ + + +------------ +; Flow Log ; +------------ +quartus_map --read_settings_files=on --write_settings_files=off ex16 -c ex16_top +quartus_fit --read_settings_files=off --write_settings_files=off ex16 -c ex16_top +quartus_asm --read_settings_files=off --write_settings_files=off ex16 -c ex16_top +quartus_sta ex16 -c ex16_top +quartus_eda --read_settings_files=off --write_settings_files=off ex16 -c ex16_top + + + diff --git a/part_4/ex16/ex16_top.map.rpt b/part_4/ex16/ex16_top.map.rpt new file mode 100644 index 0000000..591567f --- /dev/null +++ b/part_4/ex16/ex16_top.map.rpt @@ -0,0 +1,629 @@ +Analysis & Synthesis report for ex16_top +Sat Dec 10 18:21:36 2016 +Quartus Prime Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Analysis & Synthesis Summary + 3. Analysis & Synthesis Settings + 4. Parallel Compilation + 5. Analysis & Synthesis Source Files Read + 6. Analysis & Synthesis Resource Usage Summary + 7. Analysis & Synthesis Resource Utilization by Entity + 8. State Machine - |ex16_top|spi2adc:SPI_ADC|sr_state + 9. State Machine - |ex16_top|spi2dac:SPI_DAC|sr_state + 10. Registers Removed During Synthesis + 11. Removed Registers Triggering Further Register Optimizations + 12. General Register Statistics + 13. Inverted Register Statistics + 14. Parameter Settings for User Entity Instance: clktick_16:GEN_10K + 15. Parameter Settings for User Entity Instance: spi2dac:SPI_DAC + 16. Parameter Settings for User Entity Instance: spi2adc:SPI_ADC + 17. Parameter Settings for User Entity Instance: processor:ALLPASS + 18. Parameter Settings for User Entity Instance: processor:ALLPASS|multiply_4:MULT4|lpm_mult:lpm_mult_component + 19. lpm_mult Parameter Settings by Entity Instance + 20. Port Connectivity Checks: "hex_to_7seg:SEG2" + 21. Port Connectivity Checks: "processor:ALLPASS|multiply_4:MULT4" + 22. Port Connectivity Checks: "spi2adc:SPI_ADC" + 23. Port Connectivity Checks: "clktick_16:GEN_10K" + 24. Post-Synthesis Netlist Statistics for Top Partition + 25. Elapsed Time Per Partition + 26. Analysis & Synthesis Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2016 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel MegaCore Function License Agreement, or other +applicable license agreement, including, without limitation, +that your use is for the sole purpose of programming logic +devices manufactured by Intel and sold by Intel or its +authorized distributors. Please refer to the applicable +agreement for further details. + + + ++-------------------------------------------------------------------------------+ +; Analysis & Synthesis Summary ; ++---------------------------------+---------------------------------------------+ +; Analysis & Synthesis Status ; Successful - Sat Dec 10 18:21:34 2016 ; +; Quartus Prime Version ; 16.1.0 Build 196 10/24/2016 SJ Lite Edition ; +; Revision Name ; ex16_top ; +; Top-level Entity Name ; ex16_top ; +; Family ; Cyclone V ; +; Logic utilization (in ALMs) ; N/A ; +; Total registers ; 107 ; +; Total pins ; 41 ; +; Total virtual pins ; 0 ; +; Total block memory bits ; 0 ; +; Total DSP Blocks ; 0 ; +; Total HSSI RX PCSs ; 0 ; +; Total HSSI PMA RX Deserializers ; 0 ; +; Total HSSI TX PCSs ; 0 ; +; Total HSSI PMA TX Serializers ; 0 ; +; Total PLLs ; 0 ; +; Total DLLs ; 0 ; ++---------------------------------+---------------------------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Settings ; ++---------------------------------------------------------------------------------+--------------------+--------------------+ +; Option ; Setting ; Default Value ; ++---------------------------------------------------------------------------------+--------------------+--------------------+ +; Device ; 5CSEMA5F31C6 ; ; +; Top-level entity name ; ex16_top ; ex16_top ; +; Family name ; Cyclone V ; Cyclone V ; +; Use smart compilation ; Off ; Off ; +; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ; +; Enable compact report table ; Off ; Off ; +; Restructure Multiplexers ; Auto ; Auto ; +; MLAB Add Timing Constraints For Mixed-Port Feed-Through Mode Setting Don't Care ; Off ; Off ; +; Create Debugging Nodes for IP Cores ; Off ; Off ; +; Preserve fewer node names ; On ; On ; +; OpenCore Plus hardware evaluation ; Enable ; Enable ; +; Verilog Version ; Verilog_2001 ; Verilog_2001 ; +; VHDL Version ; VHDL_1993 ; VHDL_1993 ; +; State Machine Processing ; Auto ; Auto ; +; Safe State Machine ; Off ; Off ; +; Extract Verilog State Machines ; On ; On ; +; Extract VHDL State Machines ; On ; On ; +; Ignore Verilog initial constructs ; Off ; Off ; +; Iteration limit for constant Verilog loops ; 5000 ; 5000 ; +; Iteration limit for non-constant Verilog loops ; 250 ; 250 ; +; Add Pass-Through Logic to Inferred RAMs ; On ; On ; +; Infer RAMs from Raw Logic ; On ; On ; +; Parallel Synthesis ; On ; On ; +; DSP Block Balancing ; Auto ; Auto ; +; NOT Gate Push-Back ; On ; On ; +; Power-Up Don't Care ; On ; On ; +; Remove Redundant Logic Cells ; Off ; Off ; +; Remove Duplicate Registers ; On ; On ; +; Ignore CARRY Buffers ; Off ; Off ; +; Ignore CASCADE Buffers ; Off ; Off ; +; Ignore GLOBAL Buffers ; Off ; Off ; +; Ignore ROW GLOBAL Buffers ; Off ; Off ; +; Ignore LCELL Buffers ; Off ; Off ; +; Ignore SOFT Buffers ; On ; On ; +; Limit AHDL Integers to 32 Bits ; Off ; Off ; +; Optimization Technique ; Balanced ; Balanced ; +; Carry Chain Length ; 70 ; 70 ; +; Auto Carry Chains ; On ; On ; +; Auto Open-Drain Pins ; On ; On ; +; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ; +; Auto ROM Replacement ; On ; On ; +; Auto RAM Replacement ; On ; On ; +; Auto DSP Block Replacement ; On ; On ; +; Auto Shift Register Replacement ; Auto ; Auto ; +; Allow Shift Register Merging across Hierarchies ; Auto ; Auto ; +; Auto Clock Enable Replacement ; On ; On ; +; Strict RAM Replacement ; Off ; Off ; +; Allow Synchronous Control Signals ; On ; On ; +; Force Use of Synchronous Clear Signals ; Off ; Off ; +; Auto Resource Sharing ; Off ; Off ; +; Allow Any RAM Size For Recognition ; Off ; Off ; +; Allow Any ROM Size For Recognition ; Off ; Off ; +; Allow Any Shift Register Size For Recognition ; Off ; Off ; +; Use LogicLock Constraints during Resource Balancing ; On ; On ; +; Ignore translate_off and synthesis_off directives ; Off ; Off ; +; Timing-Driven Synthesis ; On ; On ; +; Report Parameter Settings ; On ; On ; +; Report Source Assignments ; On ; On ; +; Report Connectivity Checks ; On ; On ; +; Ignore Maximum Fan-Out Assignments ; Off ; Off ; +; Synchronization Register Chain Length ; 3 ; 3 ; +; PowerPlay Power Optimization During Synthesis ; Normal compilation ; Normal compilation ; +; HDL message level ; Level2 ; Level2 ; +; Suppress Register Optimization Related Messages ; Off ; Off ; +; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ; +; Number of Swept Nodes Reported in Synthesis Report ; 5000 ; 5000 ; +; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ; +; Clock MUX Protection ; On ; On ; +; Auto Gated Clock Conversion ; Off ; Off ; +; Block Design Naming ; Auto ; Auto ; +; SDC constraint protection ; Off ; Off ; +; Synthesis Effort ; Auto ; Auto ; +; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ; +; Pre-Mapping Resynthesis Optimization ; Off ; Off ; +; Analysis & Synthesis Message Level ; Medium ; Medium ; +; Disable Register Merging Across Hierarchies ; Auto ; Auto ; +; Resource Aware Inference For Block RAM ; On ; On ; +; Automatic Parallel Synthesis ; On ; On ; +; Partial Reconfiguration Bitstream ID ; Off ; Off ; ++---------------------------------------------------------------------------------+--------------------+--------------------+ + + ++------------------------------------------+ +; Parallel Compilation ; ++----------------------------+-------------+ +; Processors ; Number ; ++----------------------------+-------------+ +; Number detected on machine ; 2 ; +; Maximum allowed ; 2 ; +; ; ; +; Average used ; 1.00 ; +; Maximum used ; 2 ; +; ; ; +; Usage by Processor ; % Time Used ; +; Processor 1 ; 100.0% ; +; Processor 2 ; 0.1% ; ++----------------------------+-------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Source Files Read ; ++----------------------------------+-----------------+------------------------------+--------------------------------------------------------------------------------+---------+ +; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ; ++----------------------------------+-----------------+------------------------------+--------------------------------------------------------------------------------+---------+ +; ../mylib/multiply_4.v ; yes ; User Wizard-Generated File ; H:/Year 2/VERI/part_4/mylib/multiply_4.v ; ; +; mult4.v ; yes ; User Verilog HDL File ; H:/Year 2/VERI/part_4/ex16/mult4.v ; ; +; hex_to_7seg.v ; yes ; User Verilog HDL File ; H:/Year 2/VERI/part_4/ex16/hex_to_7seg.v ; ; +; clktick_16.v ; yes ; User Verilog HDL File ; H:/Year 2/VERI/part_4/ex16/clktick_16.v ; ; +; spi2dac.v ; yes ; User Verilog HDL File ; H:/Year 2/VERI/part_4/ex16/spi2dac.v ; ; +; spi2adc.v ; yes ; User Verilog HDL File ; H:/Year 2/VERI/part_4/ex16/spi2adc.v ; ; +; pwm.v ; yes ; User Verilog HDL File ; H:/Year 2/VERI/part_4/ex16/pwm.v ; ; +; ex16_top.v ; yes ; User Verilog HDL File ; H:/Year 2/VERI/part_4/ex16/ex16_top.v ; ; +; lpm_mult.tdf ; yes ; Megafunction ; c:/intelfpga_lite/16.1/quartus/libraries/megafunctions/lpm_mult.tdf ; ; +; aglobal161.inc ; yes ; Megafunction ; c:/intelfpga_lite/16.1/quartus/libraries/megafunctions/aglobal161.inc ; ; +; lpm_add_sub.inc ; yes ; Megafunction ; c:/intelfpga_lite/16.1/quartus/libraries/megafunctions/lpm_add_sub.inc ; ; +; multcore.inc ; yes ; Megafunction ; c:/intelfpga_lite/16.1/quartus/libraries/megafunctions/multcore.inc ; ; +; bypassff.inc ; yes ; Megafunction ; c:/intelfpga_lite/16.1/quartus/libraries/megafunctions/bypassff.inc ; ; +; altshift.inc ; yes ; Megafunction ; c:/intelfpga_lite/16.1/quartus/libraries/megafunctions/altshift.inc ; ; +; multcore.tdf ; yes ; Megafunction ; c:/intelfpga_lite/16.1/quartus/libraries/megafunctions/multcore.tdf ; ; +; csa_add.inc ; yes ; Megafunction ; c:/intelfpga_lite/16.1/quartus/libraries/megafunctions/csa_add.inc ; ; +; mpar_add.inc ; yes ; Megafunction ; c:/intelfpga_lite/16.1/quartus/libraries/megafunctions/mpar_add.inc ; ; +; muleabz.inc ; yes ; Megafunction ; c:/intelfpga_lite/16.1/quartus/libraries/megafunctions/muleabz.inc ; ; +; mul_lfrg.inc ; yes ; Megafunction ; c:/intelfpga_lite/16.1/quartus/libraries/megafunctions/mul_lfrg.inc ; ; +; mul_boothc.inc ; yes ; Megafunction ; c:/intelfpga_lite/16.1/quartus/libraries/megafunctions/mul_boothc.inc ; ; +; alt_ded_mult.inc ; yes ; Megafunction ; c:/intelfpga_lite/16.1/quartus/libraries/megafunctions/alt_ded_mult.inc ; ; +; alt_ded_mult_y.inc ; yes ; Megafunction ; c:/intelfpga_lite/16.1/quartus/libraries/megafunctions/alt_ded_mult_y.inc ; ; +; dffpipe.inc ; yes ; Megafunction ; c:/intelfpga_lite/16.1/quartus/libraries/megafunctions/dffpipe.inc ; ; +; mpar_add.tdf ; yes ; Megafunction ; c:/intelfpga_lite/16.1/quartus/libraries/megafunctions/mpar_add.tdf ; ; +; lpm_add_sub.tdf ; yes ; Megafunction ; c:/intelfpga_lite/16.1/quartus/libraries/megafunctions/lpm_add_sub.tdf ; ; +; addcore.inc ; yes ; Megafunction ; c:/intelfpga_lite/16.1/quartus/libraries/megafunctions/addcore.inc ; ; +; look_add.inc ; yes ; Megafunction ; c:/intelfpga_lite/16.1/quartus/libraries/megafunctions/look_add.inc ; ; +; alt_stratix_add_sub.inc ; yes ; Megafunction ; c:/intelfpga_lite/16.1/quartus/libraries/megafunctions/alt_stratix_add_sub.inc ; ; +; db/add_sub_a9h.tdf ; yes ; Auto-Generated Megafunction ; H:/Year 2/VERI/part_4/ex16/db/add_sub_a9h.tdf ; ; +; db/add_sub_e9h.tdf ; yes ; Auto-Generated Megafunction ; H:/Year 2/VERI/part_4/ex16/db/add_sub_e9h.tdf ; ; +; altshift.tdf ; yes ; Megafunction ; c:/intelfpga_lite/16.1/quartus/libraries/megafunctions/altshift.tdf ; ; ++----------------------------------+-----------------+------------------------------+--------------------------------------------------------------------------------+---------+ + + ++--------------------------------------------------------------+ +; Analysis & Synthesis Resource Usage Summary ; ++---------------------------------------------+----------------+ +; Resource ; Usage ; ++---------------------------------------------+----------------+ +; Estimate of Logic utilization (ALMs needed) ; 62 ; +; ; ; +; Combinational ALUT usage for logic ; 108 ; +; -- 7 input functions ; 0 ; +; -- 6 input functions ; 9 ; +; -- 5 input functions ; 15 ; +; -- 4 input functions ; 30 ; +; -- <=3 input functions ; 54 ; +; ; ; +; Dedicated logic registers ; 107 ; +; ; ; +; I/O pins ; 41 ; +; ; ; +; Total DSP Blocks ; 0 ; +; ; ; +; Maximum fan-out node ; CLOCK_50~input ; +; Maximum fan-out ; 59 ; +; Total fan-out ; 680 ; +; Average fan-out ; 2.29 ; ++---------------------------------------------+----------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Resource Utilization by Entity ; ++----------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+------------------------------+-------------+--------------+ +; Compilation Hierarchy Node ; Combinational ALUTs ; Dedicated Logic Registers ; Block Memory Bits ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name ; Entity Name ; Library Name ; ++----------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+------------------------------+-------------+--------------+ +; |ex16_top ; 108 (0) ; 107 (0) ; 0 ; 0 ; 41 ; 0 ; |ex16_top ; ex16_top ; work ; +; |clktick_16:GEN_10K| ; 20 (20) ; 17 (17) ; 0 ; 0 ; 0 ; 0 ; |ex16_top|clktick_16:GEN_10K ; clktick_16 ; work ; +; |hex_to_7seg:SEG0| ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex16_top|hex_to_7seg:SEG0 ; hex_to_7seg ; work ; +; |hex_to_7seg:SEG1| ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex16_top|hex_to_7seg:SEG1 ; hex_to_7seg ; work ; +; |hex_to_7seg:SEG2| ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex16_top|hex_to_7seg:SEG2 ; hex_to_7seg ; work ; +; |processor:ALLPASS| ; 9 (9) ; 8 (8) ; 0 ; 0 ; 0 ; 0 ; |ex16_top|processor:ALLPASS ; processor ; work ; +; |pwm:PWM_DC| ; 15 (15) ; 19 (19) ; 0 ; 0 ; 0 ; 0 ; |ex16_top|pwm:PWM_DC ; pwm ; work ; +; |spi2adc:SPI_ADC| ; 21 (21) ; 39 (39) ; 0 ; 0 ; 0 ; 0 ; |ex16_top|spi2adc:SPI_ADC ; spi2adc ; work ; +; |spi2dac:SPI_DAC| ; 26 (26) ; 24 (24) ; 0 ; 0 ; 0 ; 0 ; |ex16_top|spi2dac:SPI_DAC ; spi2dac ; work ; ++----------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+------------------------------+-------------+--------------+ +Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. + + +Encoding Type: One-Hot ++------------------------------------------------------------------------------------------+ +; State Machine - |ex16_top|spi2adc:SPI_ADC|sr_state ; ++------------------------+---------------+------------------------+------------------------+ +; Name ; sr_state.IDLE ; sr_state.WAIT_CSB_HIGH ; sr_state.WAIT_CSB_FALL ; ++------------------------+---------------+------------------------+------------------------+ +; sr_state.IDLE ; 0 ; 0 ; 0 ; +; sr_state.WAIT_CSB_FALL ; 1 ; 0 ; 1 ; +; sr_state.WAIT_CSB_HIGH ; 1 ; 1 ; 0 ; ++------------------------+---------------+------------------------+------------------------+ + + +Encoding Type: One-Hot ++------------------------------------------------------------------------------------------+ +; State Machine - |ex16_top|spi2dac:SPI_DAC|sr_state ; ++------------------------+---------------+------------------------+------------------------+ +; Name ; sr_state.IDLE ; sr_state.WAIT_CSB_HIGH ; sr_state.WAIT_CSB_FALL ; ++------------------------+---------------+------------------------+------------------------+ +; sr_state.IDLE ; 0 ; 0 ; 0 ; +; sr_state.WAIT_CSB_FALL ; 1 ; 0 ; 1 ; +; sr_state.WAIT_CSB_HIGH ; 1 ; 1 ; 0 ; ++------------------------+---------------+------------------------+------------------------+ + + ++---------------------------------------------------------------------------------+ +; Registers Removed During Synthesis ; ++----------------------------------------+----------------------------------------+ +; Register name ; Reason for Removal ; ++----------------------------------------+----------------------------------------+ +; spi2dac:SPI_DAC|shift_reg[0,1] ; Stuck at GND due to stuck port data_in ; +; processor:ALLPASS|data_out[0,1] ; Stuck at GND due to stuck port data_in ; +; pwm:PWM_DC|d[0,1] ; Stuck at GND due to stuck port data_in ; +; spi2dac:SPI_DAC|shift_reg[2,3] ; Stuck at GND due to stuck port data_in ; +; spi2dac:SPI_DAC|ctr[4] ; Merged with spi2adc:SPI_ADC|ctr[4] ; +; spi2dac:SPI_DAC|ctr[3] ; Merged with spi2adc:SPI_ADC|ctr[3] ; +; spi2dac:SPI_DAC|ctr[2] ; Merged with spi2adc:SPI_ADC|ctr[2] ; +; spi2dac:SPI_DAC|ctr[1] ; Merged with spi2adc:SPI_ADC|ctr[1] ; +; spi2dac:SPI_DAC|ctr[0] ; Merged with spi2adc:SPI_ADC|ctr[0] ; +; Total Number of Removed Registers = 13 ; ; ++----------------------------------------+----------------------------------------+ + + ++------------------------------------------------------------------------------------------------------------------------+ +; Removed Registers Triggering Further Register Optimizations ; ++-------------------------------+---------------------------+------------------------------------------------------------+ +; Register name ; Reason for Removal ; Registers Removed due to This Register ; ++-------------------------------+---------------------------+------------------------------------------------------------+ +; spi2dac:SPI_DAC|shift_reg[0] ; Stuck at GND ; spi2dac:SPI_DAC|shift_reg[1], spi2dac:SPI_DAC|shift_reg[2] ; +; ; due to stuck port data_in ; ; +; processor:ALLPASS|data_out[1] ; Stuck at GND ; pwm:PWM_DC|d[1], spi2dac:SPI_DAC|shift_reg[3] ; +; ; due to stuck port data_in ; ; +; processor:ALLPASS|data_out[0] ; Stuck at GND ; pwm:PWM_DC|d[0] ; +; ; due to stuck port data_in ; ; ++-------------------------------+---------------------------+------------------------------------------------------------+ + + ++------------------------------------------------------+ +; General Register Statistics ; ++----------------------------------------------+-------+ +; Statistic ; Value ; ++----------------------------------------------+-------+ +; Total registers ; 107 ; +; Number of registers using Synchronous Clear ; 9 ; +; Number of registers using Synchronous Load ; 0 ; +; Number of registers using Asynchronous Clear ; 0 ; +; Number of registers using Asynchronous Load ; 0 ; +; Number of registers using Clock Enable ; 30 ; +; Number of registers using Preset ; 0 ; ++----------------------------------------------+-------+ + + ++--------------------------------------------------+ +; Inverted Register Statistics ; ++----------------------------------------+---------+ +; Inverted Register ; Fan out ; ++----------------------------------------+---------+ +; spi2dac:SPI_DAC|dac_cs ; 18 ; +; spi2adc:SPI_ADC|adc_cs ; 7 ; +; Total number of inverted registers = 2 ; ; ++----------------------------------------+---------+ + + ++-----------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: clktick_16:GEN_10K ; ++----------------+-------+----------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+-------+----------------------------------------+ +; N_BIT ; 16 ; Signed Integer ; ++----------------+-------+----------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++--------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: spi2dac:SPI_DAC ; ++----------------+-------+-------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+-------+-------------------------------------+ +; BUF ; 1 ; Unsigned Binary ; +; GA_N ; 1 ; Unsigned Binary ; +; SHDN_N ; 1 ; Unsigned Binary ; +; TIME_CONSTANT ; 11000 ; Unsigned Binary ; +; IDLE ; 00 ; Unsigned Binary ; +; WAIT_CSB_FALL ; 01 ; Unsigned Binary ; +; WAIT_CSB_HIGH ; 10 ; Unsigned Binary ; ++----------------+-------+-------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++--------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: spi2adc:SPI_ADC ; ++----------------+-------+-------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+-------+-------------------------------------+ +; SGL ; 1 ; Unsigned Binary ; +; MSBF ; 1 ; Unsigned Binary ; +; TIME_CONSTANT ; 11000 ; Unsigned Binary ; +; IDLE ; 00 ; Unsigned Binary ; +; WAIT_CSB_FALL ; 01 ; Unsigned Binary ; +; WAIT_CSB_HIGH ; 10 ; Unsigned Binary ; ++----------------+-------+-------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++----------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: processor:ALLPASS ; ++----------------+------------+----------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+------------+----------------------------------+ +; ADC_OFFSET ; 0110000001 ; Unsigned Binary ; +; DAC_OFFSET ; 1000000000 ; Unsigned Binary ; ++----------------+------------+----------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++-------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: processor:ALLPASS|multiply_4:MULT4|lpm_mult:lpm_mult_component ; ++------------------------------------------------+-----------+------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------------------------------+-----------+------------------------------------------------+ +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; +; LPM_WIDTHA ; 9 ; Signed Integer ; +; LPM_WIDTHB ; 11 ; Signed Integer ; +; LPM_WIDTHP ; 20 ; Signed Integer ; +; LPM_WIDTHR ; 0 ; Untyped ; +; LPM_WIDTHS ; 1 ; Untyped ; +; LPM_REPRESENTATION ; UNSIGNED ; Untyped ; +; LPM_PIPELINE ; 0 ; Untyped ; +; LATENCY ; 0 ; Untyped ; +; INPUT_A_IS_CONSTANT ; NO ; Untyped ; +; INPUT_B_IS_CONSTANT ; YES ; Untyped ; +; USE_EAB ; OFF ; Untyped ; +; MAXIMIZE_SPEED ; 5 ; Untyped ; +; DEVICE_FAMILY ; Cyclone V ; Untyped ; +; CARRY_CHAIN ; MANUAL ; Untyped ; +; APEX20K_TECHNOLOGY_MAPPER ; LUT ; TECH_MAPPER_APEX20K ; +; DEDICATED_MULTIPLIER_CIRCUITRY ; AUTO ; Untyped ; +; DEDICATED_MULTIPLIER_MIN_INPUT_WIDTH_FOR_AUTO ; 0 ; Untyped ; +; DEDICATED_MULTIPLIER_MIN_OUTPUT_WIDTH_FOR_AUTO ; 0 ; Untyped ; +; CBXI_PARAMETER ; NOTHING ; Untyped ; +; INPUT_A_FIXED_VALUE ; Bx ; Untyped ; +; INPUT_B_FIXED_VALUE ; Bx ; Untyped ; +; USE_AHDL_IMPLEMENTATION ; OFF ; Untyped ; ++------------------------------------------------+-----------+------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++--------------------------------------------------------------------------------------------------------+ +; lpm_mult Parameter Settings by Entity Instance ; ++---------------------------------------+----------------------------------------------------------------+ +; Name ; Value ; ++---------------------------------------+----------------------------------------------------------------+ +; Number of entity instances ; 1 ; +; Entity Instance ; processor:ALLPASS|multiply_4:MULT4|lpm_mult:lpm_mult_component ; +; -- LPM_WIDTHA ; 9 ; +; -- LPM_WIDTHB ; 11 ; +; -- LPM_WIDTHP ; 20 ; +; -- LPM_REPRESENTATION ; UNSIGNED ; +; -- INPUT_A_IS_CONSTANT ; NO ; +; -- INPUT_B_IS_CONSTANT ; YES ; +; -- USE_EAB ; OFF ; +; -- DEDICATED_MULTIPLIER_CIRCUITRY ; AUTO ; +; -- INPUT_A_FIXED_VALUE ; Bx ; +; -- INPUT_B_FIXED_VALUE ; Bx ; ++---------------------------------------+----------------------------------------------------------------+ + + ++----------------------------------------------+ +; Port Connectivity Checks: "hex_to_7seg:SEG2" ; ++----------+-------+----------+----------------+ +; Port ; Type ; Severity ; Details ; ++----------+-------+----------+----------------+ +; in[3..2] ; Input ; Info ; Stuck at GND ; ++----------+-------+----------+----------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "processor:ALLPASS|multiply_4:MULT4" ; ++--------+--------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++--------+--------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; dataa ; Input ; Warning ; Input port expression (10 bits) is wider than the input port (9 bits) it drives. The 1 most-significant bit(s) in the expression will be dangling if they have no other fanouts. ; +; result ; Output ; Warning ; Output or bidir port (20 bits) is wider than the port expression (10 bits) it drives; bit(s) "result[19..10]" have no fanouts ; ++--------+--------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "spi2adc:SPI_ADC" ; ++------------+--------+----------+-------------------------------------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++------------+--------+----------+-------------------------------------------------------------------------------------+ +; channel ; Input ; Info ; Stuck at VCC ; +; data_valid ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; ++------------+--------+----------+-------------------------------------------------------------------------------------+ + + ++------------------------------------------------+ +; Port Connectivity Checks: "clktick_16:GEN_10K" ; ++-----------+-------+----------+-----------------+ +; Port ; Type ; Severity ; Details ; ++-----------+-------+----------+-----------------+ +; enable ; Input ; Info ; Stuck at VCC ; +; N[9..7] ; Input ; Info ; Stuck at VCC ; +; N[2..0] ; Input ; Info ; Stuck at VCC ; +; N[15..13] ; Input ; Info ; Stuck at GND ; +; N[11..10] ; Input ; Info ; Stuck at GND ; +; N[6..3] ; Input ; Info ; Stuck at GND ; +; N[12] ; Input ; Info ; Stuck at VCC ; ++-----------+-------+----------+-----------------+ + + ++-----------------------------------------------------+ +; Post-Synthesis Netlist Statistics for Top Partition ; ++-----------------------+-----------------------------+ +; Type ; Count ; ++-----------------------+-----------------------------+ +; arriav_ff ; 107 ; +; ENA ; 30 ; +; SCLR ; 9 ; +; plain ; 68 ; +; arriav_lcell_comb ; 116 ; +; arith ; 33 ; +; 1 data inputs ; 32 ; +; 2 data inputs ; 1 ; +; normal ; 83 ; +; 0 data inputs ; 1 ; +; 1 data inputs ; 11 ; +; 2 data inputs ; 10 ; +; 3 data inputs ; 7 ; +; 4 data inputs ; 30 ; +; 5 data inputs ; 15 ; +; 6 data inputs ; 9 ; +; boundary_port ; 41 ; +; ; ; +; Max LUT depth ; 3.00 ; +; Average LUT depth ; 1.47 ; ++-----------------------+-----------------------------+ + + ++-------------------------------+ +; Elapsed Time Per Partition ; ++----------------+--------------+ +; Partition Name ; Elapsed Time ; ++----------------+--------------+ +; Top ; 00:00:21 ; ++----------------+--------------+ + + ++-------------------------------+ +; Analysis & Synthesis Messages ; ++-------------------------------+ +Info: ******************************************************************* +Info: Running Quartus Prime Analysis & Synthesis + Info: Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition + Info: Processing started: Sat Dec 10 18:19:03 2016 +Info: Command: quartus_map --read_settings_files=on --write_settings_files=off ex16 -c ex16_top +Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. +Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected +Info (12021): Found 1 design units, including 1 entities, in source file /year 2/veri/part_4/mylib/multiply_4.v + Info (12023): Found entity 1: multiply_4 File: H:/Year 2/VERI/part_4/mylib/multiply_4.v Line: 39 +Info (12021): Found 1 design units, including 1 entities, in source file mult4.v + Info (12023): Found entity 1: processor File: H:/Year 2/VERI/part_4/ex16/mult4.v Line: 9 +Info (12021): Found 1 design units, including 1 entities, in source file hex_to_7seg.v + Info (12023): Found entity 1: hex_to_7seg File: H:/Year 2/VERI/part_4/ex16/hex_to_7seg.v Line: 10 +Info (12021): Found 1 design units, including 1 entities, in source file clktick_16.v + Info (12023): Found entity 1: clktick_16 File: H:/Year 2/VERI/part_4/ex16/clktick_16.v Line: 6 +Info (12021): Found 1 design units, including 1 entities, in source file spi2dac.v + Info (12023): Found entity 1: spi2dac File: H:/Year 2/VERI/part_4/ex16/spi2dac.v Line: 9 +Info (12021): Found 1 design units, including 1 entities, in source file spi2adc.v + Info (12023): Found entity 1: spi2adc File: H:/Year 2/VERI/part_4/ex16/spi2adc.v Line: 9 +Info (12021): Found 1 design units, including 1 entities, in source file pwm.v + Info (12023): Found entity 1: pwm File: H:/Year 2/VERI/part_4/ex16/pwm.v Line: 1 +Info (12021): Found 1 design units, including 1 entities, in source file delay_ram.v + Info (12023): Found entity 1: delay_ram File: H:/Year 2/VERI/part_4/ex16/delay_ram.v Line: 39 +Info (12021): Found 1 design units, including 1 entities, in source file ex16_top.v + Info (12023): Found entity 1: ex16_top File: H:/Year 2/VERI/part_4/ex16/ex16_top.v Line: 9 +Info (12127): Elaborating entity "ex16_top" for the top level hierarchy +Info (12128): Elaborating entity "clktick_16" for hierarchy "clktick_16:GEN_10K" File: H:/Year 2/VERI/part_4/ex16/ex16_top.v Line: 32 +Info (12128): Elaborating entity "spi2dac" for hierarchy "spi2dac:SPI_DAC" File: H:/Year 2/VERI/part_4/ex16/ex16_top.v Line: 34 +Info (12128): Elaborating entity "pwm" for hierarchy "pwm:PWM_DC" File: H:/Year 2/VERI/part_4/ex16/ex16_top.v Line: 35 +Info (12128): Elaborating entity "spi2adc" for hierarchy "spi2adc:SPI_ADC" File: H:/Year 2/VERI/part_4/ex16/ex16_top.v Line: 46 +Info (12128): Elaborating entity "processor" for hierarchy "processor:ALLPASS" File: H:/Year 2/VERI/part_4/ex16/ex16_top.v Line: 48 +Info (12128): Elaborating entity "multiply_4" for hierarchy "processor:ALLPASS|multiply_4:MULT4" File: H:/Year 2/VERI/part_4/ex16/mult4.v Line: 28 +Info (12128): Elaborating entity "lpm_mult" for hierarchy "processor:ALLPASS|multiply_4:MULT4|lpm_mult:lpm_mult_component" File: H:/Year 2/VERI/part_4/mylib/multiply_4.v Line: 57 +Info (12130): Elaborated megafunction instantiation "processor:ALLPASS|multiply_4:MULT4|lpm_mult:lpm_mult_component" File: H:/Year 2/VERI/part_4/mylib/multiply_4.v Line: 57 +Info (12133): Instantiated megafunction "processor:ALLPASS|multiply_4:MULT4|lpm_mult:lpm_mult_component" with the following parameter: File: H:/Year 2/VERI/part_4/mylib/multiply_4.v Line: 57 + Info (12134): Parameter "lpm_hint" = "INPUT_B_IS_CONSTANT=YES,MAXIMIZE_SPEED=5" + Info (12134): Parameter "lpm_representation" = "UNSIGNED" + Info (12134): Parameter "lpm_type" = "LPM_MULT" + Info (12134): Parameter "lpm_widtha" = "9" + Info (12134): Parameter "lpm_widthb" = "11" + Info (12134): Parameter "lpm_widthp" = "20" +Info (12128): Elaborating entity "multcore" for hierarchy "processor:ALLPASS|multiply_4:MULT4|lpm_mult:lpm_mult_component|multcore:mult_core" File: c:/intelfpga_lite/16.1/quartus/libraries/megafunctions/lpm_mult.tdf Line: 309 +Info (12131): Elaborated megafunction instantiation "processor:ALLPASS|multiply_4:MULT4|lpm_mult:lpm_mult_component|multcore:mult_core", which is child of megafunction instantiation "processor:ALLPASS|multiply_4:MULT4|lpm_mult:lpm_mult_component" File: c:/intelfpga_lite/16.1/quartus/libraries/megafunctions/lpm_mult.tdf Line: 309 +Info (12128): Elaborating entity "mpar_add" for hierarchy "processor:ALLPASS|multiply_4:MULT4|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder" File: c:/intelfpga_lite/16.1/quartus/libraries/megafunctions/multcore.tdf Line: 229 +Info (12131): Elaborated megafunction instantiation "processor:ALLPASS|multiply_4:MULT4|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder", which is child of megafunction instantiation "processor:ALLPASS|multiply_4:MULT4|lpm_mult:lpm_mult_component" File: c:/intelfpga_lite/16.1/quartus/libraries/megafunctions/multcore.tdf Line: 229 +Info (12128): Elaborating entity "lpm_add_sub" for hierarchy "processor:ALLPASS|multiply_4:MULT4|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]" File: c:/intelfpga_lite/16.1/quartus/libraries/megafunctions/mpar_add.tdf Line: 78 +Info (12131): Elaborated megafunction instantiation "processor:ALLPASS|multiply_4:MULT4|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]", which is child of megafunction instantiation "processor:ALLPASS|multiply_4:MULT4|lpm_mult:lpm_mult_component" File: c:/intelfpga_lite/16.1/quartus/libraries/megafunctions/mpar_add.tdf Line: 78 +Info (12021): Found 1 design units, including 1 entities, in source file db/add_sub_a9h.tdf + Info (12023): Found entity 1: add_sub_a9h File: H:/Year 2/VERI/part_4/ex16/db/add_sub_a9h.tdf Line: 23 +Info (12128): Elaborating entity "add_sub_a9h" for hierarchy "processor:ALLPASS|multiply_4:MULT4|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_a9h:auto_generated" File: c:/intelfpga_lite/16.1/quartus/libraries/megafunctions/lpm_add_sub.tdf Line: 119 +Info (12128): Elaborating entity "mpar_add" for hierarchy "processor:ALLPASS|multiply_4:MULT4|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add" File: c:/intelfpga_lite/16.1/quartus/libraries/megafunctions/mpar_add.tdf Line: 138 +Info (12131): Elaborated megafunction instantiation "processor:ALLPASS|multiply_4:MULT4|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add", which is child of megafunction instantiation "processor:ALLPASS|multiply_4:MULT4|lpm_mult:lpm_mult_component" File: c:/intelfpga_lite/16.1/quartus/libraries/megafunctions/mpar_add.tdf Line: 138 +Info (12128): Elaborating entity "lpm_add_sub" for hierarchy "processor:ALLPASS|multiply_4:MULT4|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]" File: c:/intelfpga_lite/16.1/quartus/libraries/megafunctions/mpar_add.tdf Line: 78 +Info (12131): Elaborated megafunction instantiation "processor:ALLPASS|multiply_4:MULT4|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]", which is child of megafunction instantiation "processor:ALLPASS|multiply_4:MULT4|lpm_mult:lpm_mult_component" File: c:/intelfpga_lite/16.1/quartus/libraries/megafunctions/mpar_add.tdf Line: 78 +Info (12021): Found 1 design units, including 1 entities, in source file db/add_sub_e9h.tdf + Info (12023): Found entity 1: add_sub_e9h File: H:/Year 2/VERI/part_4/ex16/db/add_sub_e9h.tdf Line: 23 +Info (12128): Elaborating entity "add_sub_e9h" for hierarchy "processor:ALLPASS|multiply_4:MULT4|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|add_sub_e9h:auto_generated" File: c:/intelfpga_lite/16.1/quartus/libraries/megafunctions/lpm_add_sub.tdf Line: 119 +Info (12128): Elaborating entity "altshift" for hierarchy "processor:ALLPASS|multiply_4:MULT4|lpm_mult:lpm_mult_component|altshift:external_latency_ffs" File: c:/intelfpga_lite/16.1/quartus/libraries/megafunctions/lpm_mult.tdf Line: 352 +Info (12131): Elaborated megafunction instantiation "processor:ALLPASS|multiply_4:MULT4|lpm_mult:lpm_mult_component|altshift:external_latency_ffs", which is child of megafunction instantiation "processor:ALLPASS|multiply_4:MULT4|lpm_mult:lpm_mult_component" File: c:/intelfpga_lite/16.1/quartus/libraries/megafunctions/lpm_mult.tdf Line: 352 +Info (12128): Elaborating entity "hex_to_7seg" for hierarchy "hex_to_7seg:SEG0" File: H:/Year 2/VERI/part_4/ex16/ex16_top.v Line: 50 +Warning (12241): 1 hierarchies have connectivity warnings - see the Connectivity Checks report folder +Warning (13024): Output pins are stuck at VCC or GND + Warning (13410): Pin "HEX2[1]" is stuck at GND File: H:/Year 2/VERI/part_4/ex16/ex16_top.v Line: 15 +Info (286030): Timing-Driven Synthesis is running +Info (16010): Generating hard_block partition "hard_block:auto_generated_inst" + Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL +Warning (21074): Design contains 10 input pin(s) that do not drive logic + Warning (15610): No output dependent on input pin "SW[0]" File: H:/Year 2/VERI/part_4/ex16/ex16_top.v Line: 14 + Warning (15610): No output dependent on input pin "SW[1]" File: H:/Year 2/VERI/part_4/ex16/ex16_top.v Line: 14 + Warning (15610): No output dependent on input pin "SW[2]" File: H:/Year 2/VERI/part_4/ex16/ex16_top.v Line: 14 + Warning (15610): No output dependent on input pin "SW[3]" File: H:/Year 2/VERI/part_4/ex16/ex16_top.v Line: 14 + Warning (15610): No output dependent on input pin "SW[4]" File: H:/Year 2/VERI/part_4/ex16/ex16_top.v Line: 14 + Warning (15610): No output dependent on input pin "SW[5]" File: H:/Year 2/VERI/part_4/ex16/ex16_top.v Line: 14 + Warning (15610): No output dependent on input pin "SW[6]" File: H:/Year 2/VERI/part_4/ex16/ex16_top.v Line: 14 + Warning (15610): No output dependent on input pin "SW[7]" File: H:/Year 2/VERI/part_4/ex16/ex16_top.v Line: 14 + Warning (15610): No output dependent on input pin "SW[8]" File: H:/Year 2/VERI/part_4/ex16/ex16_top.v Line: 14 + Warning (15610): No output dependent on input pin "SW[9]" File: H:/Year 2/VERI/part_4/ex16/ex16_top.v Line: 14 +Info (21057): Implemented 178 device resources after synthesis - the final resource count might be different + Info (21058): Implemented 12 input pins + Info (21059): Implemented 29 output pins + Info (21061): Implemented 137 logic cells +Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 15 warnings + Info: Peak virtual memory: 711 megabytes + Info: Processing ended: Sat Dec 10 18:21:37 2016 + Info: Elapsed time: 00:02:34 + Info: Total CPU time (on all processors): 00:00:40 + + diff --git a/part_4/ex16/ex16_top.sta.rpt b/part_4/ex16/ex16_top.sta.rpt new file mode 100644 index 0000000..297645b --- /dev/null +++ b/part_4/ex16/ex16_top.sta.rpt @@ -0,0 +1,809 @@ +TimeQuest Timing Analyzer report for ex16_top +Sat Dec 10 18:30:28 2016 +Quartus Prime Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. TimeQuest Timing Analyzer Summary + 3. Parallel Compilation + 4. SDC File List + 5. Clocks + 6. Slow 1100mV 85C Model Fmax Summary + 7. Timing Closure Recommendations + 8. Slow 1100mV 85C Model Setup Summary + 9. Slow 1100mV 85C Model Hold Summary + 10. Slow 1100mV 85C Model Recovery Summary + 11. Slow 1100mV 85C Model Removal Summary + 12. Slow 1100mV 85C Model Minimum Pulse Width Summary + 13. Slow 1100mV 85C Model Metastability Summary + 14. Slow 1100mV 0C Model Fmax Summary + 15. Slow 1100mV 0C Model Setup Summary + 16. Slow 1100mV 0C Model Hold Summary + 17. Slow 1100mV 0C Model Recovery Summary + 18. Slow 1100mV 0C Model Removal Summary + 19. Slow 1100mV 0C Model Minimum Pulse Width Summary + 20. Slow 1100mV 0C Model Metastability Summary + 21. Fast 1100mV 85C Model Setup Summary + 22. Fast 1100mV 85C Model Hold Summary + 23. Fast 1100mV 85C Model Recovery Summary + 24. Fast 1100mV 85C Model Removal Summary + 25. Fast 1100mV 85C Model Minimum Pulse Width Summary + 26. Fast 1100mV 85C Model Metastability Summary + 27. Fast 1100mV 0C Model Setup Summary + 28. Fast 1100mV 0C Model Hold Summary + 29. Fast 1100mV 0C Model Recovery Summary + 30. Fast 1100mV 0C Model Removal Summary + 31. Fast 1100mV 0C Model Minimum Pulse Width Summary + 32. Fast 1100mV 0C Model Metastability Summary + 33. Multicorner Timing Analysis Summary + 34. Board Trace Model Assignments + 35. Input Transition Times + 36. Signal Integrity Metrics (Slow 1100mv 0c Model) + 37. Signal Integrity Metrics (Slow 1100mv 85c Model) + 38. Signal Integrity Metrics (Fast 1100mv 0c Model) + 39. Signal Integrity Metrics (Fast 1100mv 85c Model) + 40. Setup Transfers + 41. Hold Transfers + 42. Report TCCS + 43. Report RSKM + 44. Unconstrained Paths Summary + 45. Clock Status Summary + 46. Unconstrained Input Ports + 47. Unconstrained Output Ports + 48. Unconstrained Input Ports + 49. Unconstrained Output Ports + 50. TimeQuest Timing Analyzer Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2016 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel MegaCore Function License Agreement, or other +applicable license agreement, including, without limitation, +that your use is for the sole purpose of programming logic +devices manufactured by Intel and sold by Intel or its +authorized distributors. Please refer to the applicable +agreement for further details. + + + ++-----------------------------------------------------------------------------+ +; TimeQuest Timing Analyzer Summary ; ++-----------------------+-----------------------------------------------------+ +; Quartus Prime Version ; Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition ; +; Timing Analyzer ; TimeQuest ; +; Revision Name ; ex16_top ; +; Device Family ; Cyclone V ; +; Device Name ; 5CSEMA5F31C6 ; +; Timing Models ; Final ; +; Delay Model ; Combined ; +; Rise/Fall Delays ; Enabled ; ++-----------------------+-----------------------------------------------------+ + + ++------------------------------------------+ +; Parallel Compilation ; ++----------------------------+-------------+ +; Processors ; Number ; ++----------------------------+-------------+ +; Number detected on machine ; 2 ; +; Maximum allowed ; 2 ; +; ; ; +; Average used ; 1.01 ; +; Maximum used ; 2 ; +; ; ; +; Usage by Processor ; % Time Used ; +; Processor 1 ; 100.0% ; +; Processor 2 ; 0.9% ; ++----------------------------+-------------+ + + ++---------------------------------------------------+ +; SDC File List ; ++---------------+--------+--------------------------+ +; SDC File Path ; Status ; Read at ; ++---------------+--------+--------------------------+ +; ex16_top.sdc ; OK ; Sat Dec 10 18:29:22 2016 ; ++---------------+--------+--------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Clocks ; ++------------+------+--------+-----------+-------+--------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+--------------+ +; Clock Name ; Type ; Period ; Frequency ; Rise ; Fall ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets ; ++------------+------+--------+-----------+-------+--------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+--------------+ +; CLOCK_50 ; Base ; 20.000 ; 50.0 MHz ; 0.000 ; 10.000 ; ; ; ; ; ; ; ; ; ; ; { CLOCK_50 } ; ++------------+------+--------+-----------+-------+--------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+--------------+ + + ++--------------------------------------------------+ +; Slow 1100mV 85C Model Fmax Summary ; ++------------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++------------+-----------------+------------+------+ +; 284.82 MHz ; 284.82 MHz ; CLOCK_50 ; ; ++------------+-----------------+------------+------+ +This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis. + + +---------------------------------- +; Timing Closure Recommendations ; +---------------------------------- +HTML report is unavailable in plain text report export. + + ++-------------------------------------+ +; Slow 1100mV 85C Model Setup Summary ; ++----------+--------+-----------------+ +; Clock ; Slack ; End Point TNS ; ++----------+--------+-----------------+ +; CLOCK_50 ; 16.489 ; 0.000 ; ++----------+--------+-----------------+ + + ++------------------------------------+ +; Slow 1100mV 85C Model Hold Summary ; ++----------+-------+-----------------+ +; Clock ; Slack ; End Point TNS ; ++----------+-------+-----------------+ +; CLOCK_50 ; 0.376 ; 0.000 ; ++----------+-------+-----------------+ + + +------------------------------------------ +; Slow 1100mV 85C Model Recovery Summary ; +------------------------------------------ +No paths to report. + + +----------------------------------------- +; Slow 1100mV 85C Model Removal Summary ; +----------------------------------------- +No paths to report. + + ++---------------------------------------------------+ +; Slow 1100mV 85C Model Minimum Pulse Width Summary ; ++----------+-------+--------------------------------+ +; Clock ; Slack ; End Point TNS ; ++----------+-------+--------------------------------+ +; CLOCK_50 ; 8.851 ; 0.000 ; ++----------+-------+--------------------------------+ + + +----------------------------------------------- +; Slow 1100mV 85C Model Metastability Summary ; +----------------------------------------------- +No synchronizer chains to report. + + ++--------------------------------------------------+ +; Slow 1100mV 0C Model Fmax Summary ; ++------------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++------------+-----------------+------------+------+ +; 278.24 MHz ; 278.24 MHz ; CLOCK_50 ; ; ++------------+-----------------+------------+------+ +This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis. + + ++------------------------------------+ +; Slow 1100mV 0C Model Setup Summary ; ++----------+--------+----------------+ +; Clock ; Slack ; End Point TNS ; ++----------+--------+----------------+ +; CLOCK_50 ; 16.406 ; 0.000 ; ++----------+--------+----------------+ + + ++-----------------------------------+ +; Slow 1100mV 0C Model Hold Summary ; ++----------+-------+----------------+ +; Clock ; Slack ; End Point TNS ; ++----------+-------+----------------+ +; CLOCK_50 ; 0.369 ; 0.000 ; ++----------+-------+----------------+ + + +----------------------------------------- +; Slow 1100mV 0C Model Recovery Summary ; +----------------------------------------- +No paths to report. + + +---------------------------------------- +; Slow 1100mV 0C Model Removal Summary ; +---------------------------------------- +No paths to report. + + ++--------------------------------------------------+ +; Slow 1100mV 0C Model Minimum Pulse Width Summary ; ++----------+-------+-------------------------------+ +; Clock ; Slack ; End Point TNS ; ++----------+-------+-------------------------------+ +; CLOCK_50 ; 8.802 ; 0.000 ; ++----------+-------+-------------------------------+ + + +---------------------------------------------- +; Slow 1100mV 0C Model Metastability Summary ; +---------------------------------------------- +No synchronizer chains to report. + + ++-------------------------------------+ +; Fast 1100mV 85C Model Setup Summary ; ++----------+--------+-----------------+ +; Clock ; Slack ; End Point TNS ; ++----------+--------+-----------------+ +; CLOCK_50 ; 17.733 ; 0.000 ; ++----------+--------+-----------------+ + + ++------------------------------------+ +; Fast 1100mV 85C Model Hold Summary ; ++----------+-------+-----------------+ +; Clock ; Slack ; End Point TNS ; ++----------+-------+-----------------+ +; CLOCK_50 ; 0.190 ; 0.000 ; ++----------+-------+-----------------+ + + +------------------------------------------ +; Fast 1100mV 85C Model Recovery Summary ; +------------------------------------------ +No paths to report. + + +----------------------------------------- +; Fast 1100mV 85C Model Removal Summary ; +----------------------------------------- +No paths to report. + + ++---------------------------------------------------+ +; Fast 1100mV 85C Model Minimum Pulse Width Summary ; ++----------+-------+--------------------------------+ +; Clock ; Slack ; End Point TNS ; ++----------+-------+--------------------------------+ +; CLOCK_50 ; 8.722 ; 0.000 ; ++----------+-------+--------------------------------+ + + +----------------------------------------------- +; Fast 1100mV 85C Model Metastability Summary ; +----------------------------------------------- +No synchronizer chains to report. + + ++------------------------------------+ +; Fast 1100mV 0C Model Setup Summary ; ++----------+--------+----------------+ +; Clock ; Slack ; End Point TNS ; ++----------+--------+----------------+ +; CLOCK_50 ; 17.844 ; 0.000 ; ++----------+--------+----------------+ + + ++-----------------------------------+ +; Fast 1100mV 0C Model Hold Summary ; ++----------+-------+----------------+ +; Clock ; Slack ; End Point TNS ; ++----------+-------+----------------+ +; CLOCK_50 ; 0.179 ; 0.000 ; ++----------+-------+----------------+ + + +----------------------------------------- +; Fast 1100mV 0C Model Recovery Summary ; +----------------------------------------- +No paths to report. + + +---------------------------------------- +; Fast 1100mV 0C Model Removal Summary ; +---------------------------------------- +No paths to report. + + ++--------------------------------------------------+ +; Fast 1100mV 0C Model Minimum Pulse Width Summary ; ++----------+-------+-------------------------------+ +; Clock ; Slack ; End Point TNS ; ++----------+-------+-------------------------------+ +; CLOCK_50 ; 8.680 ; 0.000 ; ++----------+-------+-------------------------------+ + + +---------------------------------------------- +; Fast 1100mV 0C Model Metastability Summary ; +---------------------------------------------- +No synchronizer chains to report. + + ++------------------------------------------------------------------------------+ +; Multicorner Timing Analysis Summary ; ++------------------+--------+-------+----------+---------+---------------------+ +; Clock ; Setup ; Hold ; Recovery ; Removal ; Minimum Pulse Width ; ++------------------+--------+-------+----------+---------+---------------------+ +; Worst-case Slack ; 16.406 ; 0.179 ; N/A ; N/A ; 8.680 ; +; CLOCK_50 ; 16.406 ; 0.179 ; N/A ; N/A ; 8.680 ; +; Design-wide TNS ; 0.0 ; 0.0 ; 0.0 ; 0.0 ; 0.0 ; +; CLOCK_50 ; 0.000 ; 0.000 ; N/A ; N/A ; 0.000 ; ++------------------+--------+-------+----------+---------+---------------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Board Trace Model Assignments ; ++---------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ +; Pin ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ; ++---------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ +; HEX0[0] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX0[1] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX0[2] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX0[3] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX0[4] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX0[5] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX0[6] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX1[0] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX1[1] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX1[2] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX1[3] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX1[4] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX1[5] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX1[6] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX2[0] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX2[1] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX2[2] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX2[3] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX2[4] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX2[5] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX2[6] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DAC_SDI ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DAC_SCK ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DAC_CS ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DAC_LD ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; ADC_SDI ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; ADC_SCK ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; ADC_CS ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; PWM_OUT ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; ++---------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ + + ++-------------------------------------------------------------+ +; Input Transition Times ; ++----------+--------------+-----------------+-----------------+ +; Pin ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ; ++----------+--------------+-----------------+-----------------+ +; SW[0] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; SW[1] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; SW[2] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; SW[3] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; SW[4] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; SW[5] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; SW[6] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; SW[7] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; SW[8] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; SW[9] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; CLOCK_50 ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; ADC_SDO ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; ++----------+--------------+-----------------+-----------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Signal Integrity Metrics (Slow 1100mv 0c Model) ; ++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; ++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; HEX0[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; +; HEX0[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; +; HEX0[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; +; HEX0[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; +; HEX0[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; +; HEX0[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; +; HEX0[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; +; HEX1[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; +; HEX1[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; +; HEX1[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; +; HEX1[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; +; HEX1[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; +; HEX1[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; +; HEX1[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; +; HEX2[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ; +; HEX2[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; +; HEX2[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; +; HEX2[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; +; HEX2[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; +; HEX2[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; +; HEX2[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; +; DAC_SDI ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; +; DAC_SCK ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ; +; DAC_CS ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ; +; DAC_LD ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; +; ADC_SDI ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ; +; ADC_SCK ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ; +; ADC_CS ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ; +; PWM_OUT ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; ++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Signal Integrity Metrics (Slow 1100mv 85c Model) ; ++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; ++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; HEX0[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; +; HEX0[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; +; HEX0[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; +; HEX0[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; +; HEX0[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; +; HEX0[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; +; HEX0[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; +; HEX1[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; +; HEX1[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; +; HEX1[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; +; HEX1[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; +; HEX1[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; +; HEX1[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; +; HEX1[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; +; HEX2[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ; +; HEX2[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; +; HEX2[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; +; HEX2[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; +; HEX2[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; +; HEX2[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; +; HEX2[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; +; DAC_SDI ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; +; DAC_SCK ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ; +; DAC_CS ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ; +; DAC_LD ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; +; ADC_SDI ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ; +; ADC_SCK ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ; +; ADC_CS ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ; +; PWM_OUT ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; ++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Signal Integrity Metrics (Fast 1100mv 0c Model) ; ++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; ++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; HEX0[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; +; HEX0[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; +; HEX0[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; +; HEX0[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; +; HEX0[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; +; HEX0[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; +; HEX0[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; +; HEX1[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; +; HEX1[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; +; HEX1[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; +; HEX1[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; +; HEX1[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; +; HEX1[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; +; HEX1[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; +; HEX2[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ; +; HEX2[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; +; HEX2[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; +; HEX2[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; +; HEX2[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; +; HEX2[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; +; HEX2[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; +; DAC_SDI ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; +; DAC_SCK ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ; +; DAC_CS ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ; +; DAC_LD ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; +; ADC_SDI ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ; +; ADC_SCK ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ; +; ADC_CS ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ; +; PWM_OUT ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; ++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Signal Integrity Metrics (Fast 1100mv 85c Model) ; ++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; ++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; HEX0[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; +; HEX0[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; +; HEX0[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; +; HEX0[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; +; HEX0[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; +; HEX0[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; +; HEX0[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; +; HEX1[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; +; HEX1[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; +; HEX1[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; +; HEX1[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; +; HEX1[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; +; HEX1[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; +; HEX1[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; +; HEX2[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ; +; HEX2[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; +; HEX2[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; +; HEX2[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; +; HEX2[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; +; HEX2[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; +; HEX2[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; +; DAC_SDI ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; +; DAC_SCK ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ; +; DAC_CS ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ; +; DAC_LD ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; +; ADC_SDI ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ; +; ADC_SCK ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ; +; ADC_CS ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ; +; PWM_OUT ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; ++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ + + ++-------------------------------------------------------------------+ +; Setup Transfers ; ++------------+----------+----------+----------+----------+----------+ +; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; ++------------+----------+----------+----------+----------+----------+ +; CLOCK_50 ; CLOCK_50 ; 464 ; 0 ; 0 ; 0 ; ++------------+----------+----------+----------+----------+----------+ +Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. + + ++-------------------------------------------------------------------+ +; Hold Transfers ; ++------------+----------+----------+----------+----------+----------+ +; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; ++------------+----------+----------+----------+----------+----------+ +; CLOCK_50 ; CLOCK_50 ; 464 ; 0 ; 0 ; 0 ; ++------------+----------+----------+----------+----------+----------+ +Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. + + +--------------- +; Report TCCS ; +--------------- +No dedicated SERDES Transmitter circuitry present in device or used in design + + +--------------- +; Report RSKM ; +--------------- +No non-DPA dedicated SERDES Receiver circuitry present in device or used in design + + ++------------------------------------------------+ +; Unconstrained Paths Summary ; ++---------------------------------+-------+------+ +; Property ; Setup ; Hold ; ++---------------------------------+-------+------+ +; Illegal Clocks ; 0 ; 0 ; +; Unconstrained Clocks ; 2 ; 2 ; +; Unconstrained Input Ports ; 1 ; 1 ; +; Unconstrained Input Port Paths ; 1 ; 1 ; +; Unconstrained Output Ports ; 28 ; 28 ; +; Unconstrained Output Port Paths ; 76 ; 76 ; ++---------------------------------+-------+------+ + + ++------------------------------------------------------------+ +; Clock Status Summary ; ++--------------------------+----------+------+---------------+ +; Target ; Clock ; Type ; Status ; ++--------------------------+----------+------+---------------+ +; CLOCK_50 ; CLOCK_50 ; Base ; Constrained ; +; spi2adc:SPI_ADC|clk_1MHz ; ; Base ; Unconstrained ; +; spi2dac:SPI_DAC|clk_1MHz ; ; Base ; Unconstrained ; ++--------------------------+----------+------+---------------+ + + ++---------------------------------------------------------------------------------------------------+ +; Unconstrained Input Ports ; ++------------+--------------------------------------------------------------------------------------+ +; Input Port ; Comment ; ++------------+--------------------------------------------------------------------------------------+ +; ADC_SDO ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ++------------+--------------------------------------------------------------------------------------+ + + ++-----------------------------------------------------------------------------------------------------+ +; Unconstrained Output Ports ; ++-------------+---------------------------------------------------------------------------------------+ +; Output Port ; Comment ; ++-------------+---------------------------------------------------------------------------------------+ +; ADC_CS ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; ADC_SCK ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; ADC_SDI ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; DAC_CS ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; DAC_LD ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; DAC_SCK ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; DAC_SDI ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX0[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX0[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX0[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX0[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX0[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX0[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX0[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX1[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX1[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX1[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX1[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX1[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX1[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX1[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX2[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX2[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX2[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX2[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX2[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX2[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; PWM_OUT ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ++-------------+---------------------------------------------------------------------------------------+ + + ++---------------------------------------------------------------------------------------------------+ +; Unconstrained Input Ports ; ++------------+--------------------------------------------------------------------------------------+ +; Input Port ; Comment ; ++------------+--------------------------------------------------------------------------------------+ +; ADC_SDO ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ++------------+--------------------------------------------------------------------------------------+ + + ++-----------------------------------------------------------------------------------------------------+ +; Unconstrained Output Ports ; ++-------------+---------------------------------------------------------------------------------------+ +; Output Port ; Comment ; ++-------------+---------------------------------------------------------------------------------------+ +; ADC_CS ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; ADC_SCK ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; ADC_SDI ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; DAC_CS ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; DAC_LD ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; DAC_SCK ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; DAC_SDI ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX0[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX0[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX0[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX0[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX0[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX0[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX0[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX1[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX1[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX1[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX1[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX1[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX1[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX1[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX2[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX2[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX2[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX2[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX2[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX2[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; PWM_OUT ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ++-------------+---------------------------------------------------------------------------------------+ + + ++------------------------------------+ +; TimeQuest Timing Analyzer Messages ; ++------------------------------------+ +Info: ******************************************************************* +Info: Running Quartus Prime TimeQuest Timing Analyzer + Info: Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition + Info: Processing started: Sat Dec 10 18:29:07 2016 +Info: Command: quartus_sta ex16 -c ex16_top +Info: qsta_default_script.tcl version: #1 +Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. +Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected +Info (21077): Low junction temperature is 0 degrees C +Info (21077): High junction temperature is 85 degrees C +Info (332104): Reading SDC File: 'ex16_top.sdc' +Warning (332060): Node: spi2adc:SPI_ADC|clk_1MHz was determined to be a clock but was found without an associated clock assignment. + Info (13166): Register spi2adc:SPI_ADC|data_from_adc[6] is being clocked by spi2adc:SPI_ADC|clk_1MHz +Warning (332060): Node: spi2dac:SPI_DAC|clk_1MHz was determined to be a clock but was found without an associated clock assignment. + Info (13166): Register spi2dac:SPI_DAC|shift_reg[15] is being clocked by spi2dac:SPI_DAC|clk_1MHz +Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty" +Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. +Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON +Info: Analyzing Slow 1100mV 85C Model +Info (332146): Worst-case setup slack is 16.489 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): 16.489 0.000 CLOCK_50 +Info (332146): Worst-case hold slack is 0.376 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): 0.376 0.000 CLOCK_50 +Info (332140): No Recovery paths to report +Info (332140): No Removal paths to report +Info (332146): Worst-case minimum pulse width slack is 8.851 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): 8.851 0.000 CLOCK_50 +Info: Analyzing Slow 1100mV 0C Model +Info (334003): Started post-fitting delay annotation +Info (334004): Delay annotation completed successfully +Warning (332060): Node: spi2adc:SPI_ADC|clk_1MHz was determined to be a clock but was found without an associated clock assignment. + Info (13166): Register spi2adc:SPI_ADC|data_from_adc[6] is being clocked by spi2adc:SPI_ADC|clk_1MHz +Warning (332060): Node: spi2dac:SPI_DAC|clk_1MHz was determined to be a clock but was found without an associated clock assignment. + Info (13166): Register spi2dac:SPI_DAC|shift_reg[15] is being clocked by spi2dac:SPI_DAC|clk_1MHz +Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. +Info (332146): Worst-case setup slack is 16.406 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): 16.406 0.000 CLOCK_50 +Info (332146): Worst-case hold slack is 0.369 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): 0.369 0.000 CLOCK_50 +Info (332140): No Recovery paths to report +Info (332140): No Removal paths to report +Info (332146): Worst-case minimum pulse width slack is 8.802 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): 8.802 0.000 CLOCK_50 +Info: Analyzing Fast 1100mV 85C Model +Info (334003): Started post-fitting delay annotation +Info (334004): Delay annotation completed successfully +Warning (332060): Node: spi2adc:SPI_ADC|clk_1MHz was determined to be a clock but was found without an associated clock assignment. + Info (13166): Register spi2adc:SPI_ADC|data_from_adc[6] is being clocked by spi2adc:SPI_ADC|clk_1MHz +Warning (332060): Node: spi2dac:SPI_DAC|clk_1MHz was determined to be a clock but was found without an associated clock assignment. + Info (13166): Register spi2dac:SPI_DAC|shift_reg[15] is being clocked by spi2dac:SPI_DAC|clk_1MHz +Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. +Info (332146): Worst-case setup slack is 17.733 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): 17.733 0.000 CLOCK_50 +Info (332146): Worst-case hold slack is 0.190 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): 0.190 0.000 CLOCK_50 +Info (332140): No Recovery paths to report +Info (332140): No Removal paths to report +Info (332146): Worst-case minimum pulse width slack is 8.722 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): 8.722 0.000 CLOCK_50 +Info: Analyzing Fast 1100mV 0C Model +Warning (332060): Node: spi2adc:SPI_ADC|clk_1MHz was determined to be a clock but was found without an associated clock assignment. + Info (13166): Register spi2adc:SPI_ADC|data_from_adc[6] is being clocked by spi2adc:SPI_ADC|clk_1MHz +Warning (332060): Node: spi2dac:SPI_DAC|clk_1MHz was determined to be a clock but was found without an associated clock assignment. + Info (13166): Register spi2dac:SPI_DAC|shift_reg[15] is being clocked by spi2dac:SPI_DAC|clk_1MHz +Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. +Info (332146): Worst-case setup slack is 17.844 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): 17.844 0.000 CLOCK_50 +Info (332146): Worst-case hold slack is 0.179 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): 0.179 0.000 CLOCK_50 +Info (332140): No Recovery paths to report +Info (332140): No Removal paths to report +Info (332146): Worst-case minimum pulse width slack is 8.680 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): 8.680 0.000 CLOCK_50 +Info (332102): Design is not fully constrained for setup requirements +Info (332102): Design is not fully constrained for hold requirements +Info: Quartus Prime TimeQuest Timing Analyzer was successful. 0 errors, 9 warnings + Info: Peak virtual memory: 1006 megabytes + Info: Processing ended: Sat Dec 10 18:30:28 2016 + Info: Elapsed time: 00:01:21 + Info: Total CPU time (on all processors): 00:00:12 + + diff --git a/part_4/ex16/ex16_top.v b/part_4/ex16/ex16_top.v new file mode 100644 index 0000000..047114c --- /dev/null +++ b/part_4/ex16/ex16_top.v @@ -0,0 +1,56 @@ +//------------------------------ +// Module name: ex16_top +// Function: top level module - pass audio input to output directly +// Creator: Peter Cheung +// Version: 2.0 +// Date: 10 Nov 2016 +//------------------------------ + +module ex16_top (CLOCK_50, SW, HEX0, HEX1, HEX2, + DAC_SDI, DAC_SCK, DAC_CS, DAC_LD, + ADC_SDI, ADC_SCK, ADC_CS, ADC_SDO, PWM_OUT); + + input CLOCK_50; // DE0 50MHz system clock + input [9:0] SW; // 10 slide switches to specify address to ROM + output [6:0] HEX0, HEX1, HEX2; + output DAC_SDI; //Serial data out to SDI of the DAC + output DAC_SCK; //Serial clock signal to both DAC and ADC + output DAC_CS; //Chip select to the DAC, low active + output DAC_LD; //Load new data to DAC, low active + output ADC_SDI; //Serial data out to SDI of the ADC + output ADC_SCK; // ADC Clock signal + output ADC_CS; //Chip select to the ADC, low active + input ADC_SDO; //Converted serial data from ADC + output PWM_OUT; // PWM output to R channel + + wire tick_10k; // internal clock at 10kHz + wire [9:0] data_in; // converted data from ADC + wire [9:0] data_out; // processed data to DAC + wire data_valid; + wire DAC_SCK, ADC_SCK; + + clktick_16 GEN_10K (CLOCK_50, 1'b1, 16'd4999, tick_10k); // generate 10KHz sampling clock ticks + spi2dac SPI_DAC (CLOCK_50, data_out, tick_10k, // send processed sample to DAC + DAC_SDI, DAC_CS, DAC_SCK, DAC_LD); // order of signals matter + pwm PWM_DC(CLOCK_50, data_out, tick_10k, PWM_OUT); // output via PWM - R-channel + + spi2adc SPI_ADC ( // perform a A-to-D conversion + .sysclk (CLOCK_50), // order of parameters do not matter + .channel (1'b1), // use only CH1 + .start (tick_10k), + .data_from_adc (data_in), + .data_valid (data_valid), + .sdata_to_adc (ADC_SDI), + .adc_cs (ADC_CS), + .adc_sck (ADC_SCK), + .sdata_from_adc (ADC_SDO)); + + processor ALLPASS (CLOCK_50, data_in, data_out); // do some processing on the data + + hex_to_7seg SEG0 (HEX0, data_in[3:0]); + hex_to_7seg SEG1 (HEX1, data_in[7:4]); + hex_to_7seg SEG2 (HEX2, {2'b0,data_in[9:8]}); + +endmodule + + diff --git a/part_4/ex16/hex_to_7seg.v b/part_4/ex16/hex_to_7seg.v new file mode 100644 index 0000000..1c39f02 --- /dev/null +++ b/part_4/ex16/hex_to_7seg.v @@ -0,0 +1,38 @@ +//------------------------------ +// Module name: hex_to_7seg +// Function: convert 4-bit hex value to drive 7 segment display +// output is low active - using case statement +// Creator: Peter Cheung +// Version: 1.1 +// Date: 23 Oct 2011 +//------------------------------ + +module hex_to_7seg (out,in); + + output [6:0] out; // low-active output to drive 7 segment display + input [3:0] in; // 4-bit binary input of a hexademical number + + reg [6:0] out; // make out a variable for use in procedural assignment + + always @ (in) + case (in) + 4'h0: out = 7'b1000000; + 4'h1: out = 7'b1111001; // -- 0 --- + 4'h2: out = 7'b0100100; // | | + 4'h3: out = 7'b0110000; // 5 1 + 4'h4: out = 7'b0011001; // | | + 4'h5: out = 7'b0010010; // -- 6 --- + 4'h6: out = 7'b0000010; // | | + 4'h7: out = 7'b1111000; // 4 2 + 4'h8: out = 7'b0000000; // | | + 4'h9: out = 7'b0011000; // -- 3 --- + 4'ha: out = 7'b0001000; + 4'hb: out = 7'b0000011; + 4'hc: out = 7'b1000110; + 4'hd: out = 7'b0100001; + 4'he: out = 7'b0000110; + 4'hf: out = 7'b0001110; + endcase +endmodule + + diff --git a/part_4/ex16/mult4.v b/part_4/ex16/mult4.v new file mode 100644 index 0000000..30a1798 --- /dev/null +++ b/part_4/ex16/mult4.v @@ -0,0 +1,35 @@ +//------------------------------ +// Module name: allpass processor +// Function: Simply to pass input to output +// Creator: Peter Cheung +// Version: 1.1 +// Date: 24 Jan 2014 +//------------------------------ + +module processor (sysclk, data_in, data_out); + + input sysclk; // system clock + input [9:0] data_in; // 10-bit input data + output [9:0] data_out; // 10-bit output data + + wire sysclk; + wire [9:0] data_in; + reg [9:0] data_out; + wire [9:0] x,y,z; + + parameter ADC_OFFSET = 10'h181; + parameter DAC_OFFSET = 10'h200; + + assign x = data_in[9:0] - ADC_OFFSET; // x is input in 2's complement + + // This part should include your own processing hardware + // ... that takes x to produce y + // ... In this case, it is ALL PASS. + multiply_4 MULT4 (x,y); + + // Now clock y output with system clock + always @(posedge sysclk) + data_out <= y + DAC_OFFSET; + +endmodule + \ No newline at end of file diff --git a/part_4/ex16/multiply_k.v b/part_4/ex16/multiply_k.v new file mode 100644 index 0000000..8292b58 --- /dev/null +++ b/part_4/ex16/multiply_k.v @@ -0,0 +1,107 @@ +// megafunction wizard: %LPM_MULT% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: lpm_mult + +// ============================================================ +// File Name: multiply_k.v +// Megafunction Name(s): +// lpm_mult +// +// Simulation Library Files(s): +// lpm +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 13.1.0 Build 162 10/23/2013 SJ Web Edition +// ************************************************************ + + +//Copyright (C) 1991-2013 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module multiply_k ( + dataa, + result); + + input [8:0] dataa; + output [19:0] result; + + wire [19:0] sub_wire0; + wire [10:0] sub_wire1 = 11'h666; + wire [19:0] result = sub_wire0[19:0]; + + lpm_mult lpm_mult_component ( + .dataa (dataa), + .datab (sub_wire1), + .result (sub_wire0), + .aclr (1'b0), + .clken (1'b1), + .clock (1'b0), + .sum (1'b0)); + defparam + lpm_mult_component.lpm_hint = "INPUT_B_IS_CONSTANT=YES,MAXIMIZE_SPEED=5", + lpm_mult_component.lpm_representation = "UNSIGNED", + lpm_mult_component.lpm_type = "LPM_MULT", + lpm_mult_component.lpm_widtha = 9, + lpm_mult_component.lpm_widthb = 11, + lpm_mult_component.lpm_widthp = 20; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: AutoSizeResult NUMERIC "1" +// Retrieval info: PRIVATE: B_isConstant NUMERIC "1" +// Retrieval info: PRIVATE: ConstantB NUMERIC "1638" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +// Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "0" +// Retrieval info: PRIVATE: Latency NUMERIC "0" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: SignedMult NUMERIC "0" +// Retrieval info: PRIVATE: USE_MULT NUMERIC "1" +// Retrieval info: PRIVATE: ValidConstant NUMERIC "1" +// Retrieval info: PRIVATE: WidthA NUMERIC "9" +// Retrieval info: PRIVATE: WidthB NUMERIC "11" +// Retrieval info: PRIVATE: WidthP NUMERIC "20" +// Retrieval info: PRIVATE: aclr NUMERIC "0" +// Retrieval info: PRIVATE: clken NUMERIC "0" +// Retrieval info: PRIVATE: new_diagram STRING "1" +// Retrieval info: PRIVATE: optimize NUMERIC "0" +// Retrieval info: LIBRARY: lpm lpm.lpm_components.all +// Retrieval info: CONSTANT: LPM_HINT STRING "INPUT_B_IS_CONSTANT=YES,MAXIMIZE_SPEED=5" +// Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "UNSIGNED" +// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MULT" +// Retrieval info: CONSTANT: LPM_WIDTHA NUMERIC "9" +// Retrieval info: CONSTANT: LPM_WIDTHB NUMERIC "11" +// Retrieval info: CONSTANT: LPM_WIDTHP NUMERIC "20" +// Retrieval info: USED_PORT: dataa 0 0 9 0 INPUT NODEFVAL "dataa[8..0]" +// Retrieval info: USED_PORT: result 0 0 20 0 OUTPUT NODEFVAL "result[19..0]" +// Retrieval info: CONNECT: @dataa 0 0 9 0 dataa 0 0 9 0 +// Retrieval info: CONNECT: @datab 0 0 11 0 1638 0 0 11 0 +// Retrieval info: CONNECT: result 0 0 20 0 @result 0 0 20 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL multiply_k.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL multiply_k.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL multiply_k.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL multiply_k.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL multiply_k_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL multiply_k_bb.v TRUE +// Retrieval info: LIB_FILE: lpm diff --git a/part_4/ex16/pulse_gen.v b/part_4/ex16/pulse_gen.v new file mode 100644 index 0000000..d82fe49 --- /dev/null +++ b/part_4/ex16/pulse_gen.v @@ -0,0 +1,43 @@ +//------------------------------ +// Module name: pulse_gen (Moore) +// Function: Generate one clock pulse on +ve edge of input +// Creator: Peter Cheung +// Version: 1.0 +// Date: 29 Jan 2014 +//------------------------------ + +module pulse_gen(pulse, in, clk); + + output pulse; // output pulse lasting one clk cycle + input in; // input, +ve edge to be detected + input clk; // clock signal + + reg [1:0] state; + reg pulse; + + parameter IDLE = 2'b0; // state coding for IDLE state + parameter IN_HIGH = 2'b01; + parameter WAIT_LOW = 2'b10; + + initial state = IDLE; + + always @ (posedge clk) + begin + pulse <= 0; // default output + case (state) + IDLE: if (in == 1'b1) begin + state <= IN_HIGH; pulse <= 1'b1; end + else + state <= IDLE; + IN_HIGH: if (in == 1'b1) + state <= WAIT_LOW; + else + state <= IDLE; + WAIT_LOW: if (in == 1'b1) + state <= WAIT_LOW; + else + state <= IDLE; + default: ; + endcase + end //... always +endmodule diff --git a/part_4/ex16/pwm.v b/part_4/ex16/pwm.v new file mode 100644 index 0000000..c3b34d9 --- /dev/null +++ b/part_4/ex16/pwm.v @@ -0,0 +1,25 @@ +module pwm (clk, data_in, load, pwm_out); + + input clk; // system clock + input [9:0] data_in; // input data for conversion + input load; // high pulse to load new data + output pwm_out; // PWM output + + reg [9:0] d; // internal register + reg [9:0] count; // internal 10-bit counter + reg pwm_out; + + always @ (posedge clk) + if (load == 1'b1) d <= data_in; + + initial count = 10'b0; + + always @ (posedge clk) begin + count <= count + 1'b1; + if (count > d) + pwm_out <= 1'b0; + else + pwm_out <= 1'b1; + end + +endmodule diff --git a/part_4/ex16/simulation/modelsim/init.do b/part_4/ex16/simulation/modelsim/init.do new file mode 100644 index 0000000..c39709a --- /dev/null +++ b/part_4/ex16/simulation/modelsim/init.do @@ -0,0 +1,20 @@ +add wave -position end sim:/top/CLOCK_50 +add wave -position end sim:/top/clock_25 +add wave -position end sim:/top/tone_1k +add wave -position end sim:/top/ld_pulse +add wave -position end sim:/top/reset +add wave -position end sim:/top/DAC_SDI +add wave -position end sim:/top/DAC_SCK +add wave -position end sim:/top/DAC_CS +add wave -position end sim:/top/DAC_LD +add wave -position end sim:/top/BUTTON0 +add wave -position end -hexadecimal sim:/top/mux_out +add wave -position end -hexadecimal sim:/top/SPI_1/state +add wave -position end sim:/top/SPI_1/sck_ena +add wave -position end sim:/top/SPI_1/clk_half +force CLOCK_50 1 0, 0 {10 ns} -r {20 ns} +alias ck "run 20ns" +force BUTTON0 0 +ck +force BUTTON0 1 +ck diff --git a/part_4/ex16/simulation/modelsim/init_adc.do b/part_4/ex16/simulation/modelsim/init_adc.do new file mode 100644 index 0000000..1269f00 --- /dev/null +++ b/part_4/ex16/simulation/modelsim/init_adc.do @@ -0,0 +1,23 @@ +add wave sysclk +add wave clk_1MHz +add wave start +add wave data_from_adc +add wave data_valid +add wave -hexadecimal data_out +add wave adc_cs +add wave adc_sck +add wave adc_done +add wave adc_din +add wave -hexadecimal shift_reg +add wave -hexadecimal state +add wave shift_ena +force sysclk 1 0, 0 {10 ns} -r 20 ns +force start 0 +run 200ns +force start 1 +run 200ns +force start 0 +force data_from_adc 0 @ 1us, 1 @ 6us, 0 @ 8us, 1 @ 10us, 0 @ 13us, 1 @ 15us + +run 20us + diff --git a/part_4/ex16/simulation/modelsim/init_cal.do b/part_4/ex16/simulation/modelsim/init_cal.do new file mode 100644 index 0000000..a6d14b9 --- /dev/null +++ b/part_4/ex16/simulation/modelsim/init_cal.do @@ -0,0 +1,17 @@ +add wave -position end sim:/top/CLOCK_50 +add wave -position end sim:/top/clk_10k +add wave -position end sim:/top/ld_pulse +add wave -position end -hexadecimal sim:/top/SW +add wave -position end -hexadecimal sim:/top/data +add wave -position end sim:/top/DAC_SDI +add wave -position end sim:/top/DAC_SCK +add wave -position end sim:/top/DAC_CS +add wave -position end sim:/top/DAC_LD +add wave -position end sim:/top/ADC_SDI +add wave -position end sim:/top/ADC_SCK +add wave -position end sim:/top/ADC_CS +add wave -position end sim:/top/ADC_SDO +force CLOCK_50 1 0, 0 10ns -r 20ns +force SW 10'h20f +force ADC_SDO 1 +run 400us diff --git a/part_4/ex16/simulation/modelsim/init_spi.do b/part_4/ex16/simulation/modelsim/init_spi.do new file mode 100644 index 0000000..b99ff7a --- /dev/null +++ b/part_4/ex16/simulation/modelsim/init_spi.do @@ -0,0 +1,25 @@ +add wave -position end sim:/spi2dac/sysclk +add wave -position end sim:/spi2dac/div2 +add wave -position end sim:/spi2dac/div4 +add wave -position end sim:/spi2dac/status_busy +add wave -position end -hexadecimal sim:/spi2dac/data_in +add wave -position end sim:/spi2dac/ld +add wave -position end -hexadecimal sim:/spi2dac/state +add wave -position end sim:/spi2dac/sck_ena +add wave -position end sim:/spi2dac/dac_ld +add wave -position end -hexadecimal sim:/spi2dac/shift_reg +add wave -position end sim:/spi2dac/spi_sdo +add wave -position end sim:/spi2dac/spi_cs +add wave -position end sim:/spi2dac/spi_sck +add wave -position end sim:/spi2dac/spi_ld +add wave -position end sim:/spi2dac/rs_state +force -freeze sim:/spi2dac/sysclk 1 0, 0 {10 ns} -r 20 ns +run 20ns +force data_in 10'h2c3 +force ld 0 +run 20ns +force ld 1 +run 20ns +force ld 0 +run 20ns + \ No newline at end of file diff --git a/part_4/ex16/simulation/modelsim/top_run_msim_rtl_verilog.do b/part_4/ex16/simulation/modelsim/top_run_msim_rtl_verilog.do new file mode 100644 index 0000000..377f3cd --- /dev/null +++ b/part_4/ex16/simulation/modelsim/top_run_msim_rtl_verilog.do @@ -0,0 +1,9 @@ +transcript on +if {[file exists rtl_work]} { + vdel -lib rtl_work -all +} +vlib rtl_work +vmap work rtl_work + +vlog -vlog01compat -work work +incdir+Z:/Dropbox/_My\ Documents/E2\ Digital/adc_dac {Z:/Dropbox/_My Documents/E2 Digital/adc_dac/spi2adc.v} + diff --git a/part_4/ex16/spi2adc.v b/part_4/ex16/spi2adc.v new file mode 100644 index 0000000..3878f71 --- /dev/null +++ b/part_4/ex16/spi2adc.v @@ -0,0 +1,150 @@ +//------------------------------ +// Module name: spi2adc +// Function: SPI interface for MCP3002 ADC +// Creator: Peter Cheung +// Version: 1.1 +// Date: 24 Jan 2014 +//------------------------------ + +module spi2adc (sysclk, start, channel, data_from_adc, data_valid, + sdata_to_adc, adc_cs, adc_sck, sdata_from_adc); + + input sysclk; // 50MHz system clock of DE0 + input start; // Pulse to start ADC, minimum wide = clock period + input channel; // channel 0 or 1 to be converted + output [9:0] data_from_adc; // 10-bit ADC result + output data_valid; // High indicates that converted data valid + output sdata_to_adc; // Serial commands send to adc chip + output adc_cs; // chip select - low when converting + output adc_sck; // SPI clock - active during conversion + input sdata_from_adc; // Converted serial data from ADC, MSB first + +//-------------Input Ports----------------------------- +// All the input ports should be wires + wire sysclk, start, sdata_from_adc; + +//-------------Output Ports----------------------------- +// Output port can be a storage element (reg) or a wire + reg [9:0] data_from_adc; + reg adc_cs; + wire sdata_to_adc, adc_sck, data_valid; + +//-------------Configuration parameters for ADC -------- + parameter SGL=1'b1; // 0:diff i/p, 1:single-ended + parameter MSBF=1'b1; // 0:LSB first, 1:MSB first + +// --- Submodule: Generate internal clock at 1 MHz ----- + reg clk_1MHz; // 1Mhz clock derived from 50MHz + reg [4:0] ctr; // internal counter + parameter TIME_CONSTANT = 5'd24; // change this for diff clk freq + initial begin + clk_1MHz = 0; // don't need to reset - don't care if it is 1 or 0 to start + ctr = 5'b0; // ... to start. Initialise to make simulation easier + end + + always @ (posedge sysclk) // + if (ctr==0) begin + ctr <= TIME_CONSTANT; + clk_1MHz <= ~clk_1MHz; // toggle the output clock for squarewave + end + else + ctr <= ctr - 1'b1; +// ---- end internal clock generator ---------- + +// ---- Detect start is asserted with a small state machine + // .... FF set on positive edge of start + // .... reset when adc_cs goes high again + reg [1:0] sr_state; + parameter IDLE = 2'b00,WAIT_CSB_FALL = 2'b01, WAIT_CSB_HIGH = 2'b10; + reg adc_start; + + initial begin + sr_state = IDLE; + adc_start = 1'b0; // set while sending data to ADC + end + + always @ (posedge sysclk) + case (sr_state) + IDLE: if (start==1'b0) sr_state <= IDLE; + else begin + sr_state <= WAIT_CSB_FALL; + adc_start <= 1'b1; + end + WAIT_CSB_FALL: if (adc_cs==1'b1) sr_state <= WAIT_CSB_FALL; + else sr_state <= WAIT_CSB_HIGH; + + WAIT_CSB_HIGH: if (adc_cs==1'b0) sr_state <= WAIT_CSB_HIGH; + else begin + sr_state <= IDLE; + adc_start <= 1'b0; + end + default: sr_state <= IDLE; + endcase +//------- End circuit to detect start and end of conversion + + +// spi controller designed as a state machine +// .... with 16 states (idle, and S1-S15 indicated by state value + + reg [4:0] state; + reg adc_done, adc_din, shift_ena; + + initial begin + state = 5'b0; adc_cs = 1'b1; adc_done = 1'b0; + adc_din = 1'b0; shift_ena <= 1'b0; + end + + always @(posedge clk_1MHz) begin + + // default outputs and state transition + adc_cs <= 1'b0; adc_done <= 1'b0; adc_din <= 1'b0; shift_ena <= 1'b0; + state <= state + 1'b1; + case (state) + 5'd0: begin + if (adc_start==1'b0) begin + state <= 5'd0; // still idle + adc_cs <= 1'b1; // chip select not active + end + else begin + state <= 5'd1; // start converting + adc_din <= 1'b1; // start bit is 1 + end + end + 5'd1: adc_din <= SGL; // SGL bit + 5'd2: adc_din <= channel; // CH bit + 5'd3: adc_din <= MSBF; // MSB first bit + 5'd4: shift_ena <= 1'b1; // start shifting data from adc + 5'd15: begin + shift_ena <= 1'b0; + adc_done <= 1'b1; + end + 5'd16: begin + adc_cs <= 1'b1; // last state - disable chip select + state <= 5'd0; // go back to idle state + end + default: + shift_ena <= 1'b1; // unspecified states are covered by default above + endcase + end // ... always + + // shift register for output data + reg [9:0] shift_reg; + initial begin + shift_reg = 10'b0; + data_from_adc = 10'b0; + end + + always @(negedge clk_1MHz) + if((adc_cs==1'b0)&&(shift_ena==1'b1)) // start shifting data_in + shift_reg <= {shift_reg[8:0],sdata_from_adc}; + + // Latch converted output data + always @(posedge clk_1MHz) + if(adc_done) + data_from_adc = shift_reg; + + // Assign outputs to drive SPI interface to DAC + assign adc_sck = !clk_1MHz & !adc_cs; + assign sdata_to_adc = adc_din; + assign data_valid = adc_cs; +endmodule \ No newline at end of file diff --git a/part_4/ex16/spi2dac.v b/part_4/ex16/spi2dac.v new file mode 100644 index 0000000..ccfb4e8 --- /dev/null +++ b/part_4/ex16/spi2dac.v @@ -0,0 +1,128 @@ +//------------------------------ +// Module name: spi2dac +// Function: SPI interface for MPC4911 DAC +// Creator: Peter Cheung +// Version: 1.3 +// Date: 8 Nov 2016 +//------------------------------ + +module spi2dac (clk, data_in, load, dac_sdi, dac_cs, dac_sck, dac_ld); + + input clk; // 50MHz system clock of DE0 + input [9:0] data_in; // input data to DAC + input load; // Pulse to load data to dac + output dac_sdi; // SPI serial data out + output dac_cs; // chip select - low when sending data to dac + output dac_sck; // SPI clock, 16 cycles at half clk freq + output dac_ld; + +//-------------Input Ports----------------------------- +// All the input ports should be wires + wire clk, load; + wire [9:0] data_in; + +//-------------Output Ports----------------------------- +// Output port can be a storage element (reg) or a wire + reg dac_cs, dac_ld; + wire dac_sck, dac_sdi; + + parameter BUF=1'b1; // 0:no buffer, 1:Vref buffered + parameter GA_N=1'b1; // 0:gain = 2x, 1:gain = 1x + parameter SHDN_N=1'b1; // 0:power down, 1:dac active + + wire [3:0] cmd = {1'b0,BUF,GA_N,SHDN_N}; // wire to VDD or GND + + // --- Submodule: Generate internal clock at 1 MHz ----- + reg clk_1MHz; // 1Mhz clock derived from 50MHz + reg [4:0] ctr; // internal counter + parameter TIME_CONSTANT = 5'd24; // change this for diff clk freq + initial begin + clk_1MHz = 0; // don't need to reset - don't care if it is 1 or 0 to start + ctr = 5'b0; // ... Initialise when FPGA is configured + end + + always @ (posedge clk) // + if (ctr==0) begin + ctr <= TIME_CONSTANT; + clk_1MHz <= ~clk_1MHz; // toggle the output clock for squarewave + end + else + ctr <= ctr - 1'b1; + // ---- end internal clock generator ---------- + + // ---- Detect posedge of load with a small state machine + // .... FF set on posedge of load + // .... reset when dac_cs goes high at the end of DAC output cycle + reg [1:0] sr_state; + parameter IDLE = 2'b00,WAIT_CSB_FALL = 2'b01, WAIT_CSB_HIGH = 2'b10; + reg dac_start; // set if a DAC write is detected + + initial begin + sr_state = IDLE; + dac_start = 1'b0; // set while sending data to DAC + end + + always @ (posedge clk) + case (sr_state) + IDLE: if (load==1'b0) sr_state <= IDLE; + else begin + sr_state <= WAIT_CSB_FALL; + dac_start <= 1'b1; + end + WAIT_CSB_FALL: if (dac_cs==1'b1) sr_state <= WAIT_CSB_FALL; + else sr_state <= WAIT_CSB_HIGH; + + WAIT_CSB_HIGH: if (dac_cs==1'b0) sr_state <= WAIT_CSB_HIGH; + else begin + sr_state <= IDLE; + dac_start <= 1'b0; + end + default: sr_state <= IDLE; + endcase + //------- End circuit to detect start and end of conversion + + //------- spi controller designed as a state machine + // .... with 17 states (idle, and S1-S16 + // .... for the 16 cycles each sending 1-bit to dac) + reg [4:0] state; + + initial begin + state = 5'b0; dac_ld = 1'b0; dac_cs = 1'b1; + end + + always @(posedge clk_1MHz) begin + // default outputs and state transition + dac_cs <= 1'b0; dac_ld <= 1'b1; + state <= state + 1'b1; // move to next state by default + case (state) + 5'd0: if (dac_start == 1'b0) begin + state <= 5'd0; // still waiting + dac_cs <= 1'b1; + end + 5'd16: begin + dac_cs <= 1'b1; dac_ld <= 1'b0; + state <= 5'd0; // go back to idle state + end + default: begin // all other states + dac_cs <= 1'b0; dac_ld <= 1'b1; + state <= state + 1'b1; // default state transition + end + endcase + end // ... always + + // shift register for output data + reg [15:0] shift_reg; + initial begin + shift_reg = 16'b0; + end + + always @(posedge clk_1MHz) + if((dac_start==1'b1)&&(dac_cs==1'b1)) // parallel load data to shift reg + shift_reg <= {cmd,data_in,2'b00}; + else // .. else start shifting + shift_reg <= {shift_reg[14:0],1'b0}; + + // Assign outputs to drive SPI interface to DAC + assign dac_sck = !clk_1MHz&!dac_cs; + assign dac_sdi = shift_reg[15]; +endmodule \ No newline at end of file diff --git a/part_4/ex17/FIFO.v b/part_4/ex17/FIFO.v new file mode 100644 index 0000000..34128f9 --- /dev/null +++ b/part_4/ex17/FIFO.v @@ -0,0 +1,159 @@ +// megafunction wizard: %FIFO% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: scfifo + +// ============================================================ +// File Name: FIFO.v +// Megafunction Name(s): +// scfifo +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 16.1.0 Build 196 10/24/2016 SJ Lite Edition +// ************************************************************ + + +//Copyright (C) 2016 Intel Corporation. All rights reserved. +//Your use of Intel Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Intel Program License +//Subscription Agreement, the Intel Quartus Prime License Agreement, +//the Intel MegaCore Function License Agreement, or other +//applicable license agreement, including, without limitation, +//that your use is for the sole purpose of programming logic +//devices manufactured by Intel and sold by Intel or its +//authorized distributors. Please refer to the applicable +//agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module FIFO ( + clock, + data, + rdreq, + wrreq, + empty, + full, + q); + + input clock; + input [9:0] data; + input rdreq; + input wrreq; + output empty; + output full; + output [9:0] q; + + wire sub_wire0; + wire sub_wire1; + wire [9:0] sub_wire2; + wire empty = sub_wire0; + wire full = sub_wire1; + wire [9:0] q = sub_wire2[9:0]; + + scfifo scfifo_component ( + .clock (clock), + .data (data), + .rdreq (rdreq), + .wrreq (wrreq), + .empty (sub_wire0), + .full (sub_wire1), + .q (sub_wire2), + .aclr (), + .almost_empty (), + .almost_full (), + .eccstatus (), + .sclr (), + .usedw ()); + defparam + scfifo_component.add_ram_output_register = "OFF", + scfifo_component.intended_device_family = "Cyclone V", + scfifo_component.lpm_numwords = 8192, + scfifo_component.lpm_showahead = "OFF", + scfifo_component.lpm_type = "scfifo", + scfifo_component.lpm_width = 10, + scfifo_component.lpm_widthu = 13, + scfifo_component.overflow_checking = "ON", + scfifo_component.underflow_checking = "ON", + scfifo_component.use_eab = "ON"; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0" +// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1" +// Retrieval info: PRIVATE: AlmostFull NUMERIC "0" +// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1" +// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0" +// Retrieval info: PRIVATE: Clock NUMERIC "0" +// Retrieval info: PRIVATE: Depth NUMERIC "8192" +// Retrieval info: PRIVATE: Empty NUMERIC "1" +// Retrieval info: PRIVATE: Full NUMERIC "1" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V" +// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0" +// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1" +// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0" +// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0" +// Retrieval info: PRIVATE: Optimize NUMERIC "0" +// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0" +// Retrieval info: PRIVATE: UsedW NUMERIC "0" +// Retrieval info: PRIVATE: Width NUMERIC "10" +// Retrieval info: PRIVATE: dc_aclr NUMERIC "0" +// Retrieval info: PRIVATE: diff_widths NUMERIC "0" +// Retrieval info: PRIVATE: msb_usedw NUMERIC "0" +// Retrieval info: PRIVATE: output_width NUMERIC "10" +// Retrieval info: PRIVATE: rsEmpty NUMERIC "1" +// Retrieval info: PRIVATE: rsFull NUMERIC "0" +// Retrieval info: PRIVATE: rsUsedW NUMERIC "0" +// Retrieval info: PRIVATE: sc_aclr NUMERIC "0" +// Retrieval info: PRIVATE: sc_sclr NUMERIC "0" +// Retrieval info: PRIVATE: wsEmpty NUMERIC "0" +// Retrieval info: PRIVATE: wsFull NUMERIC "1" +// Retrieval info: PRIVATE: wsUsedW NUMERIC "0" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V" +// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "8192" +// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF" +// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo" +// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "10" +// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "13" +// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON" +// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON" +// Retrieval info: CONSTANT: USE_EAB STRING "ON" +// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock" +// Retrieval info: USED_PORT: data 0 0 10 0 INPUT NODEFVAL "data[9..0]" +// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL "empty" +// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL "full" +// Retrieval info: USED_PORT: q 0 0 10 0 OUTPUT NODEFVAL "q[9..0]" +// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq" +// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq" +// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 +// Retrieval info: CONNECT: @data 0 0 10 0 data 0 0 10 0 +// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0 +// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0 +// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0 +// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0 +// Retrieval info: CONNECT: q 0 0 10 0 @q 0 0 10 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL FIFO.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL FIFO.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL FIFO.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL FIFO.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL FIFO_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL FIFO_bb.v TRUE +// Retrieval info: LIB_FILE: altera_mf diff --git a/part_4/ex17/FIFO_bb.v b/part_4/ex17/FIFO_bb.v new file mode 100644 index 0000000..ae93f52 --- /dev/null +++ b/part_4/ex17/FIFO_bb.v @@ -0,0 +1,120 @@ +// megafunction wizard: %FIFO%VBB% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: scfifo + +// ============================================================ +// File Name: FIFO.v +// Megafunction Name(s): +// scfifo +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 16.1.0 Build 196 10/24/2016 SJ Lite Edition +// ************************************************************ + +//Copyright (C) 2016 Intel Corporation. All rights reserved. +//Your use of Intel Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Intel Program License +//Subscription Agreement, the Intel Quartus Prime License Agreement, +//the Intel MegaCore Function License Agreement, or other +//applicable license agreement, including, without limitation, +//that your use is for the sole purpose of programming logic +//devices manufactured by Intel and sold by Intel or its +//authorized distributors. Please refer to the applicable +//agreement for further details. + +module FIFO ( + clock, + data, + rdreq, + wrreq, + empty, + full, + q); + + input clock; + input [9:0] data; + input rdreq; + input wrreq; + output empty; + output full; + output [9:0] q; + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0" +// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1" +// Retrieval info: PRIVATE: AlmostFull NUMERIC "0" +// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1" +// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0" +// Retrieval info: PRIVATE: Clock NUMERIC "0" +// Retrieval info: PRIVATE: Depth NUMERIC "8192" +// Retrieval info: PRIVATE: Empty NUMERIC "1" +// Retrieval info: PRIVATE: Full NUMERIC "1" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V" +// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0" +// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1" +// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0" +// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0" +// Retrieval info: PRIVATE: Optimize NUMERIC "0" +// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0" +// Retrieval info: PRIVATE: UsedW NUMERIC "0" +// Retrieval info: PRIVATE: Width NUMERIC "10" +// Retrieval info: PRIVATE: dc_aclr NUMERIC "0" +// Retrieval info: PRIVATE: diff_widths NUMERIC "0" +// Retrieval info: PRIVATE: msb_usedw NUMERIC "0" +// Retrieval info: PRIVATE: output_width NUMERIC "10" +// Retrieval info: PRIVATE: rsEmpty NUMERIC "1" +// Retrieval info: PRIVATE: rsFull NUMERIC "0" +// Retrieval info: PRIVATE: rsUsedW NUMERIC "0" +// Retrieval info: PRIVATE: sc_aclr NUMERIC "0" +// Retrieval info: PRIVATE: sc_sclr NUMERIC "0" +// Retrieval info: PRIVATE: wsEmpty NUMERIC "0" +// Retrieval info: PRIVATE: wsFull NUMERIC "1" +// Retrieval info: PRIVATE: wsUsedW NUMERIC "0" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V" +// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "8192" +// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF" +// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo" +// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "10" +// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "13" +// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON" +// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON" +// Retrieval info: CONSTANT: USE_EAB STRING "ON" +// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock" +// Retrieval info: USED_PORT: data 0 0 10 0 INPUT NODEFVAL "data[9..0]" +// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL "empty" +// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL "full" +// Retrieval info: USED_PORT: q 0 0 10 0 OUTPUT NODEFVAL "q[9..0]" +// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq" +// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq" +// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 +// Retrieval info: CONNECT: @data 0 0 10 0 data 0 0 10 0 +// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0 +// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0 +// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0 +// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0 +// Retrieval info: CONNECT: q 0 0 10 0 @q 0 0 10 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL FIFO.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL FIFO.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL FIFO.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL FIFO.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL FIFO_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL FIFO_bb.v TRUE +// Retrieval info: LIB_FILE: altera_mf diff --git a/part_4/ex17/ex17_top.v b/part_4/ex17/ex17_top.v new file mode 100644 index 0000000..8d804f7 --- /dev/null +++ b/part_4/ex17/ex17_top.v @@ -0,0 +1,48 @@ +module ex17_top (CLOCK_50, SW, HEX0, HEX1, HEX2, + DAC_SDI, DAC_SCK, DAC_CS, DAC_LD, + ADC_SDI, ADC_SCK, ADC_CS, ADC_SDO, PWM_OUT); + + input CLOCK_50; // DE0 50MHz system clock + input [9:0] SW; // 10 slide switches to specify address to ROM + output [6:0] HEX0, HEX1, HEX2; + output DAC_SDI; //Serial data out to SDI of the DAC + output DAC_SCK; //Serial clock signal to both DAC and ADC + output DAC_CS; //Chip select to the DAC, low active + output DAC_LD; //Load new data to DAC, low active + output ADC_SDI; //Serial data out to SDI of the ADC + output ADC_SCK; // ADC Clock signal + output ADC_CS; //Chip select to the ADC, low active + input ADC_SDO; //Converted serial data from ADC + output PWM_OUT; // PWM output to R channel + + wire tick_10k; // internal clock at 10kHz + wire [9:0] data_in; // converted data from ADC + wire [9:0] data_out; // processed data to DAC + wire data_valid; + wire DAC_SCK, ADC_SCK; + + clktick_16 GEN_10K (CLOCK_50, 1'b1, 16'd4999, tick_10k); // generate 10KHz sampling clock ticks + spi2dac SPI_DAC (CLOCK_50, data_out, tick_10k, // send processed sample to DAC + DAC_SDI, DAC_CS, DAC_SCK, DAC_LD); // order of signals matter + pwm PWM_DC(CLOCK_50, data_out, tick_10k, PWM_OUT); // output via PWM - R-channel + + spi2adc SPI_ADC ( // perform a A-to-D conversion + .sysclk (CLOCK_50), // order of parameters do not matter + .channel (1'b1), // use only CH1 + .start (tick_10k), + .data_from_adc (data_in), + .data_valid (data_valid), + .sdata_to_adc (ADC_SDI), + .adc_cs (ADC_CS), + .adc_sck (ADC_SCK), + .sdata_from_adc (ADC_SDO)); + + processor ALLPASS (CLOCK_50, data_in, data_out, data_valid); // do some processing on the data + + hex_to_7seg SEG0 (HEX0, data_in[3:0]); + hex_to_7seg SEG1 (HEX1, data_in[7:4]); + hex_to_7seg SEG2 (HEX2, {2'b0,data_in[9:8]}); + +endmodule + + diff --git a/part_4/ex17/output_files/ex17_top.asm.rpt b/part_4/ex17/output_files/ex17_top.asm.rpt new file mode 100644 index 0000000..962ca66 --- /dev/null +++ b/part_4/ex17/output_files/ex17_top.asm.rpt @@ -0,0 +1,92 @@ +Assembler report for ex17_top +Sat Dec 10 18:50:31 2016 +Quartus Prime Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Assembler Summary + 3. Assembler Settings + 4. Assembler Generated Files + 5. Assembler Device Options: H:/Year 2/VERI/part_4/ex17/output_files/ex17_top.sof + 6. Assembler Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2016 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel MegaCore Function License Agreement, or other +applicable license agreement, including, without limitation, +that your use is for the sole purpose of programming logic +devices manufactured by Intel and sold by Intel or its +authorized distributors. Please refer to the applicable +agreement for further details. + + + ++---------------------------------------------------------------+ +; Assembler Summary ; ++-----------------------+---------------------------------------+ +; Assembler Status ; Successful - Sat Dec 10 18:50:31 2016 ; +; Revision Name ; ex17_top ; +; Top-level Entity Name ; ex17_top ; +; Family ; Cyclone V ; +; Device ; 5CSEMA5F31C6 ; ++-----------------------+---------------------------------------+ + + ++----------------------------------+ +; Assembler Settings ; ++--------+---------+---------------+ +; Option ; Setting ; Default Value ; ++--------+---------+---------------+ + + ++------------------------------------------------------+ +; Assembler Generated Files ; ++------------------------------------------------------+ +; File Name ; ++------------------------------------------------------+ +; H:/Year 2/VERI/part_4/ex17/output_files/ex17_top.sof ; ++------------------------------------------------------+ + + ++--------------------------------------------------------------------------------+ +; Assembler Device Options: H:/Year 2/VERI/part_4/ex17/output_files/ex17_top.sof ; ++----------------+---------------------------------------------------------------+ +; Option ; Setting ; ++----------------+---------------------------------------------------------------+ +; Device ; 5CSEMA5F31C6 ; +; JTAG usercode ; 0x00DFFBE7 ; +; Checksum ; 0x00DFFBE7 ; ++----------------+---------------------------------------------------------------+ + + ++--------------------+ +; Assembler Messages ; ++--------------------+ +Info: ******************************************************************* +Info: Running Quartus Prime Assembler + Info: Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition + Info: Processing started: Sat Dec 10 18:49:26 2016 +Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off ex17 -c ex17_top +Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. +Info (115030): Assembler is generating device programming files +Info: Quartus Prime Assembler was successful. 0 errors, 1 warning + Info: Peak virtual memory: 716 megabytes + Info: Processing ended: Sat Dec 10 18:50:34 2016 + Info: Elapsed time: 00:01:08 + Info: Total CPU time (on all processors): 00:00:14 + + diff --git a/part_4/ex17/output_files/ex17_top.fit.rpt b/part_4/ex17/output_files/ex17_top.fit.rpt new file mode 100644 index 0000000..47cf314 --- /dev/null +++ b/part_4/ex17/output_files/ex17_top.fit.rpt @@ -0,0 +1,2124 @@ +Fitter report for ex17_top +Sat Dec 10 18:48:11 2016 +Quartus Prime Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Fitter Summary + 3. Fitter Settings + 4. Parallel Compilation + 5. Fitter Netlist Optimizations + 6. Ignored Assignments + 7. Incremental Compilation Preservation Summary + 8. Incremental Compilation Partition Settings + 9. Incremental Compilation Placement Preservation + 10. Pin-Out File + 11. Fitter Resource Usage Summary + 12. Fitter Partition Statistics + 13. Input Pins + 14. Output Pins + 15. I/O Bank Usage + 16. All Package Pins + 17. I/O Assignment Warnings + 18. Fitter Resource Utilization by Entity + 19. Delay Chain Summary + 20. Pad To Core Delay Chain Fanout + 21. Control Signals + 22. Global & Other Fast Signals + 23. Fitter RAM Summary + 24. Routing Usage Summary + 25. I/O Rules Summary + 26. I/O Rules Details + 27. I/O Rules Matrix + 28. Fitter Device Options + 29. Operating Settings and Conditions + 30. Estimated Delay Added for Hold Timing Summary + 31. Estimated Delay Added for Hold Timing Details + 32. Fitter Messages + 33. Fitter Suppressed Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2016 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel MegaCore Function License Agreement, or other +applicable license agreement, including, without limitation, +that your use is for the sole purpose of programming logic +devices manufactured by Intel and sold by Intel or its +authorized distributors. Please refer to the applicable +agreement for further details. + + + ++-------------------------------------------------------------------------------+ +; Fitter Summary ; ++---------------------------------+---------------------------------------------+ +; Fitter Status ; Successful - Sat Dec 10 18:48:09 2016 ; +; Quartus Prime Version ; 16.1.0 Build 196 10/24/2016 SJ Lite Edition ; +; Revision Name ; ex17_top ; +; Top-level Entity Name ; ex17_top ; +; Family ; Cyclone V ; +; Device ; 5CSEMA5F31C6 ; +; Timing Models ; Final ; +; Logic utilization (in ALMs) ; 94 / 32,070 ( < 1 % ) ; +; Total registers ; 179 ; +; Total pins ; 41 / 457 ( 9 % ) ; +; Total virtual pins ; 0 ; +; Total block memory bits ; 73,728 / 4,065,280 ( 2 % ) ; +; Total RAM Blocks ; 9 / 397 ( 2 % ) ; +; Total DSP Blocks ; 0 / 87 ( 0 % ) ; +; Total HSSI RX PCSs ; 0 ; +; Total HSSI PMA RX Deserializers ; 0 ; +; Total HSSI TX PCSs ; 0 ; +; Total HSSI PMA TX Serializers ; 0 ; +; Total PLLs ; 0 / 6 ( 0 % ) ; +; Total DLLs ; 0 / 4 ( 0 % ) ; ++---------------------------------+---------------------------------------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fitter Settings ; ++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+ +; Option ; Setting ; Default Value ; ++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+ +; Device ; 5CSEMA5F31C6 ; ; +; Minimum Core Junction Temperature ; 0 ; ; +; Maximum Core Junction Temperature ; 85 ; ; +; Use smart compilation ; Off ; Off ; +; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ; +; Enable compact report table ; Off ; Off ; +; Router Timing Optimization Level ; Normal ; Normal ; +; Perform Clocking Topology Analysis During Routing ; Off ; Off ; +; Placement Effort Multiplier ; 1.0 ; 1.0 ; +; Device initialization clock source ; INIT_INTOSC ; INIT_INTOSC ; +; Optimize Hold Timing ; All Paths ; All Paths ; +; Optimize Multi-Corner Timing ; On ; On ; +; Auto RAM to MLAB Conversion ; On ; On ; +; Equivalent RAM and MLAB Power Up ; Auto ; Auto ; +; Equivalent RAM and MLAB Paused Read Capabilities ; Care ; Care ; +; PowerPlay Power Optimization During Fitting ; Normal compilation ; Normal compilation ; +; SSN Optimization ; Off ; Off ; +; Optimize Timing ; Normal compilation ; Normal compilation ; +; Optimize Timing for ECOs ; Off ; Off ; +; Regenerate Full Fit Report During ECO Compiles ; Off ; Off ; +; Optimize IOC Register Placement for Timing ; Normal ; Normal ; +; Final Placement Optimizations ; Automatically ; Automatically ; +; Fitter Aggressive Routability Optimizations ; Automatically ; Automatically ; +; Fitter Initial Placement Seed ; 1 ; 1 ; +; Periphery to Core Placement and Routing Optimization ; Off ; Off ; +; Weak Pull-Up Resistor ; Off ; Off ; +; Enable Bus-Hold Circuitry ; Off ; Off ; +; Auto Packed Registers ; Auto ; Auto ; +; Auto Delay Chains ; On ; On ; +; Auto Delay Chains for High Fanout Input Pins ; Off ; Off ; +; Treat Bidirectional Pin as Output Pin ; Off ; Off ; +; Perform Physical Synthesis for Combinational Logic for Fitting ; Off ; Off ; +; Perform Physical Synthesis for Combinational Logic for Performance ; Off ; Off ; +; Perform Register Duplication for Performance ; Off ; Off ; +; Perform Register Retiming for Performance ; Off ; Off ; +; Perform Asynchronous Signal Pipelining ; Off ; Off ; +; Fitter Effort ; Auto Fit ; Auto Fit ; +; Physical Synthesis Effort Level ; Normal ; Normal ; +; Logic Cell Insertion - Logic Duplication ; Auto ; Auto ; +; Auto Register Duplication ; Auto ; Auto ; +; Auto Global Clock ; On ; On ; +; Auto Global Register Control Signals ; On ; On ; +; Reserve all unused pins ; As input tri-stated with weak pull-up ; As input tri-stated with weak pull-up ; +; Synchronizer Identification ; Auto ; Auto ; +; Enable Beneficial Skew Optimization ; On ; On ; +; Optimize Design for Metastability ; On ; On ; +; Active Serial clock source ; FREQ_100MHz ; FREQ_100MHz ; +; Force Fitter to Avoid Periphery Placement Warnings ; Off ; Off ; +; Clamping Diode ; Off ; Off ; +; Enable input tri-state on active configuration pins in user mode ; Off ; Off ; +; Advanced Physical Optimization ; On ; On ; ++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+ + + ++------------------------------------------+ +; Parallel Compilation ; ++----------------------------+-------------+ +; Processors ; Number ; ++----------------------------+-------------+ +; Number detected on machine ; 2 ; +; Maximum allowed ; 2 ; +; ; ; +; Average used ; 1.02 ; +; Maximum used ; 2 ; +; ; ; +; Usage by Processor ; % Time Used ; +; Processor 1 ; 100.0% ; +; Processor 2 ; 1.5% ; ++----------------------------+-------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fitter Netlist Optimizations ; ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------+---------------------------------------------------+----------------------------+-----------+----------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------+-----------------------+ +; Node ; Action ; Operation ; Reason ; Node Port ; Node Port Name ; Destination Node ; Destination Port ; Destination Port Name ; ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------+---------------------------------------------------+----------------------------+-----------+----------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------+-----------------------+ +; CLOCK_50~inputCLKENA0 ; Created ; Placement ; Fitter Periphery Placement ; ; ; ; ; ; +; clktick_16:GEN_10K|count[4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; clktick_16:GEN_10K|count[4]~DUPLICATE ; ; ; +; clktick_16:GEN_10K|count[15] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; clktick_16:GEN_10K|count[15]~DUPLICATE ; ; ; +; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|a_fefifo_4be:fifo_state|cntr_di7:count_usedw|counter_reg_bit[1] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|a_fefifo_4be:fifo_state|cntr_di7:count_usedw|counter_reg_bit[1]~DUPLICATE ; ; ; +; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|a_fefifo_4be:fifo_state|cntr_di7:count_usedw|counter_reg_bit[3] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|a_fefifo_4be:fifo_state|cntr_di7:count_usedw|counter_reg_bit[3]~DUPLICATE ; ; ; +; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|a_fefifo_4be:fifo_state|cntr_di7:count_usedw|counter_reg_bit[8] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|a_fefifo_4be:fifo_state|cntr_di7:count_usedw|counter_reg_bit[8]~DUPLICATE ; ; ; +; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|cntr_1ib:rd_ptr_count|counter_reg_bit[5] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|cntr_1ib:rd_ptr_count|counter_reg_bit[5]~DUPLICATE ; ; ; +; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|cntr_1ib:wr_ptr|counter_reg_bit[4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|cntr_1ib:wr_ptr|counter_reg_bit[4]~DUPLICATE ; ; ; +; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|cntr_1ib:wr_ptr|counter_reg_bit[9] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|cntr_1ib:wr_ptr|counter_reg_bit[9]~DUPLICATE ; ; ; +; processor:ALLPASS|data_out[0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; processor:ALLPASS|data_out[0]~DUPLICATE ; ; ; +; processor:ALLPASS|data_out[2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; processor:ALLPASS|data_out[2]~DUPLICATE ; ; ; +; processor:ALLPASS|data_out[3] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; processor:ALLPASS|data_out[3]~DUPLICATE ; ; ; +; processor:ALLPASS|data_out[6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; processor:ALLPASS|data_out[6]~DUPLICATE ; ; ; +; spi2adc:SPI_ADC|adc_cs ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; spi2adc:SPI_ADC|adc_cs~DUPLICATE ; ; ; +; spi2adc:SPI_ADC|ctr[0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; spi2adc:SPI_ADC|ctr[0]~DUPLICATE ; ; ; +; spi2adc:SPI_ADC|ctr[1] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; spi2adc:SPI_ADC|ctr[1]~DUPLICATE ; ; ; +; spi2adc:SPI_ADC|data_from_adc[0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; spi2adc:SPI_ADC|data_from_adc[0]~DUPLICATE ; ; ; +; spi2adc:SPI_ADC|data_from_adc[2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; spi2adc:SPI_ADC|data_from_adc[2]~DUPLICATE ; ; ; +; spi2adc:SPI_ADC|shift_reg[2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; spi2adc:SPI_ADC|shift_reg[2]~DUPLICATE ; ; ; +; spi2adc:SPI_ADC|shift_reg[4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; spi2adc:SPI_ADC|shift_reg[4]~DUPLICATE ; ; ; +; spi2adc:SPI_ADC|shift_reg[8] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; spi2adc:SPI_ADC|shift_reg[8]~DUPLICATE ; ; ; +; spi2adc:SPI_ADC|state[0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; spi2adc:SPI_ADC|state[0]~DUPLICATE ; ; ; +; spi2adc:SPI_ADC|state[1] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; spi2adc:SPI_ADC|state[1]~DUPLICATE ; ; ; +; spi2adc:SPI_ADC|state[2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; spi2adc:SPI_ADC|state[2]~DUPLICATE ; ; ; +; spi2dac:SPI_DAC|sr_state.WAIT_CSB_FALL ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; spi2dac:SPI_DAC|sr_state.WAIT_CSB_FALL~DUPLICATE ; ; ; +; spi2dac:SPI_DAC|state[0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; spi2dac:SPI_DAC|state[0]~DUPLICATE ; ; ; +; spi2dac:SPI_DAC|state[1] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; spi2dac:SPI_DAC|state[1]~DUPLICATE ; ; ; ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------+---------------------------------------------------+----------------------------+-----------+----------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------+-----------------------+ + + ++--------------------------------------------------------------------------------------------+ +; Ignored Assignments ; ++--------------+----------------+--------------+------------+---------------+----------------+ +; Name ; Ignored Entity ; Ignored From ; Ignored To ; Ignored Value ; Ignored Source ; ++--------------+----------------+--------------+------------+---------------+----------------+ +; Location ; ; ; HEX3[0] ; PIN_AD26 ; QSF Assignment ; +; Location ; ; ; HEX3[1] ; PIN_AC27 ; QSF Assignment ; +; Location ; ; ; HEX3[2] ; PIN_AD25 ; QSF Assignment ; +; Location ; ; ; HEX3[3] ; PIN_AC25 ; QSF Assignment ; +; Location ; ; ; HEX3[4] ; PIN_AB28 ; QSF Assignment ; +; Location ; ; ; HEX3[5] ; PIN_AB25 ; QSF Assignment ; +; Location ; ; ; HEX3[6] ; PIN_AB22 ; QSF Assignment ; +; Location ; ; ; HEX4[0] ; PIN_AA24 ; QSF Assignment ; +; Location ; ; ; HEX4[1] ; PIN_Y23 ; QSF Assignment ; +; Location ; ; ; HEX4[2] ; PIN_Y24 ; QSF Assignment ; +; Location ; ; ; HEX4[3] ; PIN_W22 ; QSF Assignment ; +; Location ; ; ; HEX4[4] ; PIN_W24 ; QSF Assignment ; +; Location ; ; ; HEX4[5] ; PIN_V23 ; QSF Assignment ; +; Location ; ; ; HEX4[6] ; PIN_W25 ; QSF Assignment ; +; Location ; ; ; HEX5[0] ; PIN_V25 ; QSF Assignment ; +; Location ; ; ; HEX5[1] ; PIN_AA28 ; QSF Assignment ; +; Location ; ; ; HEX5[2] ; PIN_Y27 ; QSF Assignment ; +; Location ; ; ; HEX5[3] ; PIN_AB27 ; QSF Assignment ; +; Location ; ; ; HEX5[4] ; PIN_AB26 ; QSF Assignment ; +; Location ; ; ; HEX5[5] ; PIN_AA26 ; QSF Assignment ; +; Location ; ; ; HEX5[6] ; PIN_AA25 ; QSF Assignment ; +; Location ; ; ; KEY[0] ; PIN_AA14 ; QSF Assignment ; +; Location ; ; ; KEY[1] ; PIN_AA15 ; QSF Assignment ; +; Location ; ; ; KEY[2] ; PIN_W15 ; QSF Assignment ; +; Location ; ; ; KEY[3] ; PIN_Y16 ; QSF Assignment ; +; Location ; ; ; LEDR[0] ; PIN_V16 ; QSF Assignment ; +; Location ; ; ; LEDR[1] ; PIN_W16 ; QSF Assignment ; +; Location ; ; ; LEDR[2] ; PIN_V17 ; QSF Assignment ; +; Location ; ; ; LEDR[3] ; PIN_V18 ; QSF Assignment ; +; Location ; ; ; LEDR[4] ; PIN_W17 ; QSF Assignment ; +; Location ; ; ; LEDR[5] ; PIN_W19 ; QSF Assignment ; +; Location ; ; ; LEDR[6] ; PIN_Y19 ; QSF Assignment ; +; Location ; ; ; LEDR[7] ; PIN_W20 ; QSF Assignment ; +; Location ; ; ; LEDR[8] ; PIN_W21 ; QSF Assignment ; +; Location ; ; ; LEDR[9] ; PIN_Y21 ; QSF Assignment ; +; Location ; ; ; OLED_CLK ; PIN_AJ19 ; QSF Assignment ; +; Location ; ; ; OLED_CS ; PIN_Y17 ; QSF Assignment ; +; Location ; ; ; OLED_DATA ; PIN_AJ16 ; QSF Assignment ; +; Location ; ; ; OLED_DC ; PIN_AK18 ; QSF Assignment ; +; Location ; ; ; OLED_RST ; PIN_Y18 ; QSF Assignment ; +; I/O Standard ; ex17_top ; ; HEX3[0] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ex17_top ; ; HEX3[1] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ex17_top ; ; HEX3[2] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ex17_top ; ; HEX3[3] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ex17_top ; ; HEX3[4] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ex17_top ; ; HEX3[5] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ex17_top ; ; HEX3[6] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ex17_top ; ; HEX4[0] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ex17_top ; ; HEX4[1] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ex17_top ; ; HEX4[2] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ex17_top ; ; HEX4[3] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ex17_top ; ; HEX4[4] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ex17_top ; ; HEX4[5] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ex17_top ; ; HEX4[6] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ex17_top ; ; HEX5[0] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ex17_top ; ; HEX5[1] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ex17_top ; ; HEX5[2] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ex17_top ; ; HEX5[3] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ex17_top ; ; HEX5[4] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ex17_top ; ; HEX5[5] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ex17_top ; ; HEX5[6] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ex17_top ; ; KEY[0] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ex17_top ; ; KEY[1] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ex17_top ; ; KEY[2] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ex17_top ; ; KEY[3] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ex17_top ; ; LEDR[0] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ex17_top ; ; LEDR[1] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ex17_top ; ; LEDR[2] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ex17_top ; ; LEDR[3] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ex17_top ; ; LEDR[4] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ex17_top ; ; LEDR[5] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ex17_top ; ; LEDR[6] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ex17_top ; ; LEDR[7] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ex17_top ; ; LEDR[8] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ex17_top ; ; LEDR[9] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ex17_top ; ; OLED_CLK ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ex17_top ; ; OLED_CS ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ex17_top ; ; OLED_DATA ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ex17_top ; ; OLED_DC ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ex17_top ; ; OLED_RST ; 3.3-V LVTTL ; QSF Assignment ; ++--------------+----------------+--------------+------------+---------------+----------------+ + + ++--------------------------------------------------------------------------------------------------+ +; Incremental Compilation Preservation Summary ; ++---------------------+--------------------+----------------------------+--------------------------+ +; Type ; Total [A + B] ; From Design Partitions [A] ; From Rapid Recompile [B] ; ++---------------------+--------------------+----------------------------+--------------------------+ +; Placement (by node) ; ; ; ; +; -- Requested ; 0.00 % ( 0 / 411 ) ; 0.00 % ( 0 / 411 ) ; 0.00 % ( 0 / 411 ) ; +; -- Achieved ; 0.00 % ( 0 / 411 ) ; 0.00 % ( 0 / 411 ) ; 0.00 % ( 0 / 411 ) ; +; ; ; ; ; +; Routing (by net) ; ; ; ; +; -- Requested ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; +; -- Achieved ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; ++---------------------+--------------------+----------------------------+--------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Incremental Compilation Partition Settings ; ++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+ +; Partition Name ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents ; ++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+ +; Top ; User-created ; Source File ; N/A ; Source File ; N/A ; ; +; hard_block:auto_generated_inst ; Auto-generated ; Source File ; N/A ; Source File ; N/A ; hard_block:auto_generated_inst ; ++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------+ +; Incremental Compilation Placement Preservation ; ++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+ +; Partition Name ; Preservation Achieved ; Preservation Level Used ; Netlist Type Used ; Preservation Method ; Notes ; ++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+ +; Top ; 0.00 % ( 0 / 411 ) ; N/A ; Source File ; N/A ; ; +; hard_block:auto_generated_inst ; 0.00 % ( 0 / 0 ) ; N/A ; Source File ; N/A ; ; ++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+ + + ++--------------+ +; Pin-Out File ; ++--------------+ +The pin-out file can be found in H:/Year 2/VERI/part_4/ex17/output_files/ex17_top.pin. + + ++------------------------------------------------------------------------------------------+ +; Fitter Resource Usage Summary ; ++-------------------------------------------------------------+--------------------+-------+ +; Resource ; Usage ; % ; ++-------------------------------------------------------------+--------------------+-------+ +; Logic utilization (ALMs needed / total ALMs on device) ; 94 / 32,070 ; < 1 % ; +; ALMs needed [=A-B+C] ; 94 ; ; +; [A] ALMs used in final placement [=a+b+c+d] ; 104 / 32,070 ; < 1 % ; +; [a] ALMs used for LUT logic and registers ; 64 ; ; +; [b] ALMs used for LUT logic ; 27 ; ; +; [c] ALMs used for registers ; 13 ; ; +; [d] ALMs used for memory (up to half of total ALMs) ; 0 ; ; +; [B] Estimate of ALMs recoverable by dense packing ; 10 / 32,070 ; < 1 % ; +; [C] Estimate of ALMs unavailable [=a+b+c+d] ; 0 / 32,070 ; 0 % ; +; [a] Due to location constrained logic ; 0 ; ; +; [b] Due to LAB-wide signal conflicts ; 0 ; ; +; [c] Due to LAB input limits ; 0 ; ; +; [d] Due to virtual I/Os ; 0 ; ; +; ; ; ; +; Difficulty packing design ; Low ; ; +; ; ; ; +; Total LABs: partially or completely used ; 18 / 3,207 ; < 1 % ; +; -- Logic LABs ; 18 ; ; +; -- Memory LABs (up to half of total LABs) ; 0 ; ; +; ; ; ; +; Combinational ALUT usage for logic ; 166 ; ; +; -- 7 input functions ; 0 ; ; +; -- 6 input functions ; 10 ; ; +; -- 5 input functions ; 23 ; ; +; -- 4 input functions ; 31 ; ; +; -- <=3 input functions ; 102 ; ; +; Combinational ALUT usage for route-throughs ; 20 ; ; +; ; ; ; +; Dedicated logic registers ; 179 ; ; +; -- By type: ; ; ; +; -- Primary logic registers ; 153 / 64,140 ; < 1 % ; +; -- Secondary logic registers ; 26 / 64,140 ; < 1 % ; +; -- By function: ; ; ; +; -- Design implementation registers ; 153 ; ; +; -- Routing optimization registers ; 26 ; ; +; ; ; ; +; Virtual pins ; 0 ; ; +; I/O pins ; 41 / 457 ; 9 % ; +; -- Clock pins ; 1 / 8 ; 13 % ; +; -- Dedicated input pins ; 0 / 21 ; 0 % ; +; ; ; ; +; Hard processor system peripheral utilization ; ; ; +; -- Boot from FPGA ; 0 / 1 ( 0 % ) ; ; +; -- Clock resets ; 0 / 1 ( 0 % ) ; ; +; -- Cross trigger ; 0 / 1 ( 0 % ) ; ; +; -- S2F AXI ; 0 / 1 ( 0 % ) ; ; +; -- F2S AXI ; 0 / 1 ( 0 % ) ; ; +; -- AXI Lightweight ; 0 / 1 ( 0 % ) ; ; +; -- SDRAM ; 0 / 1 ( 0 % ) ; ; +; -- Interrupts ; 0 / 1 ( 0 % ) ; ; +; -- JTAG ; 0 / 1 ( 0 % ) ; ; +; -- Loan I/O ; 0 / 1 ( 0 % ) ; ; +; -- MPU event standby ; 0 / 1 ( 0 % ) ; ; +; -- MPU general purpose ; 0 / 1 ( 0 % ) ; ; +; -- STM event ; 0 / 1 ( 0 % ) ; ; +; -- TPIU trace ; 0 / 1 ( 0 % ) ; ; +; -- DMA ; 0 / 1 ( 0 % ) ; ; +; -- CAN ; 0 / 2 ( 0 % ) ; ; +; -- EMAC ; 0 / 2 ( 0 % ) ; ; +; -- I2C ; 0 / 4 ( 0 % ) ; ; +; -- NAND Flash ; 0 / 1 ( 0 % ) ; ; +; -- QSPI ; 0 / 1 ( 0 % ) ; ; +; -- SDMMC ; 0 / 1 ( 0 % ) ; ; +; -- SPI Master ; 0 / 2 ( 0 % ) ; ; +; -- SPI Slave ; 0 / 2 ( 0 % ) ; ; +; -- UART ; 0 / 2 ( 0 % ) ; ; +; -- USB ; 0 / 2 ( 0 % ) ; ; +; ; ; ; +; M10K blocks ; 9 / 397 ; 2 % ; +; Total MLAB memory bits ; 0 ; ; +; Total block memory bits ; 73,728 / 4,065,280 ; 2 % ; +; Total block memory implementation bits ; 92,160 / 4,065,280 ; 2 % ; +; ; ; ; +; Total DSP Blocks ; 0 / 87 ; 0 % ; +; ; ; ; +; Fractional PLLs ; 0 / 6 ; 0 % ; +; Global signals ; 1 ; ; +; -- Global clocks ; 1 / 16 ; 6 % ; +; -- Quadrant clocks ; 0 / 66 ; 0 % ; +; -- Horizontal periphery clocks ; 0 / 18 ; 0 % ; +; SERDES Transmitters ; 0 / 100 ; 0 % ; +; SERDES Receivers ; 0 / 100 ; 0 % ; +; JTAGs ; 0 / 1 ; 0 % ; +; ASMI blocks ; 0 / 1 ; 0 % ; +; CRC blocks ; 0 / 1 ; 0 % ; +; Remote update blocks ; 0 / 1 ; 0 % ; +; Oscillator blocks ; 0 / 1 ; 0 % ; +; Impedance control blocks ; 0 / 4 ; 0 % ; +; Hard Memory Controllers ; 0 / 2 ; 0 % ; +; Average interconnect usage (total/H/V) ; 0.1% / 0.1% / 0.1% ; ; +; Peak interconnect usage (total/H/V) ; 4.2% / 4.5% / 3.2% ; ; +; Maximum fan-out ; 197 ; ; +; Highest non-global fan-out ; 45 ; ; +; Total fan-out ; 1375 ; ; +; Average fan-out ; 3.01 ; ; ++-------------------------------------------------------------+--------------------+-------+ + + ++----------------------------------------------------------------------------------------------------------------------+ +; Fitter Partition Statistics ; ++-------------------------------------------------------------+-----------------------+--------------------------------+ +; Statistic ; Top ; hard_block:auto_generated_inst ; ++-------------------------------------------------------------+-----------------------+--------------------------------+ +; Logic utilization (ALMs needed / total ALMs on device) ; 94 / 32070 ( < 1 % ) ; 0 / 32070 ( 0 % ) ; +; ALMs needed [=A-B+C] ; 94 ; 0 ; +; [A] ALMs used in final placement [=a+b+c+d] ; 104 / 32070 ( < 1 % ) ; 0 / 32070 ( 0 % ) ; +; [a] ALMs used for LUT logic and registers ; 64 ; 0 ; +; [b] ALMs used for LUT logic ; 27 ; 0 ; +; [c] ALMs used for registers ; 13 ; 0 ; +; [d] ALMs used for memory (up to half of total ALMs) ; 0 ; 0 ; +; [B] Estimate of ALMs recoverable by dense packing ; 10 / 32070 ( < 1 % ) ; 0 / 32070 ( 0 % ) ; +; [C] Estimate of ALMs unavailable [=a+b+c+d] ; 0 / 32070 ( 0 % ) ; 0 / 32070 ( 0 % ) ; +; [a] Due to location constrained logic ; 0 ; 0 ; +; [b] Due to LAB-wide signal conflicts ; 0 ; 0 ; +; [c] Due to LAB input limits ; 0 ; 0 ; +; [d] Due to virtual I/Os ; 0 ; 0 ; +; ; ; ; +; Difficulty packing design ; Low ; Low ; +; ; ; ; +; Total LABs: partially or completely used ; 18 / 3207 ( < 1 % ) ; 0 / 3207 ( 0 % ) ; +; -- Logic LABs ; 18 ; 0 ; +; -- Memory LABs (up to half of total LABs) ; 0 ; 0 ; +; ; ; ; +; Combinational ALUT usage for logic ; 166 ; 0 ; +; -- 7 input functions ; 0 ; 0 ; +; -- 6 input functions ; 10 ; 0 ; +; -- 5 input functions ; 23 ; 0 ; +; -- 4 input functions ; 31 ; 0 ; +; -- <=3 input functions ; 102 ; 0 ; +; Combinational ALUT usage for route-throughs ; 20 ; 0 ; +; Memory ALUT usage ; 0 ; 0 ; +; -- 64-address deep ; 0 ; 0 ; +; -- 32-address deep ; 0 ; 0 ; +; ; ; ; +; Dedicated logic registers ; 0 ; 0 ; +; -- By type: ; ; ; +; -- Primary logic registers ; 153 / 64140 ( < 1 % ) ; 0 / 64140 ( 0 % ) ; +; -- Secondary logic registers ; 26 / 64140 ( < 1 % ) ; 0 / 64140 ( 0 % ) ; +; -- By function: ; ; ; +; -- Design implementation registers ; 153 ; 0 ; +; -- Routing optimization registers ; 26 ; 0 ; +; ; ; ; +; ; ; ; +; Virtual pins ; 0 ; 0 ; +; I/O pins ; 41 ; 0 ; +; I/O registers ; 0 ; 0 ; +; Total block memory bits ; 73728 ; 0 ; +; Total block memory implementation bits ; 92160 ; 0 ; +; M10K block ; 9 / 397 ( 2 % ) ; 0 / 397 ( 0 % ) ; +; Clock enable block ; 1 / 116 ( < 1 % ) ; 0 / 116 ( 0 % ) ; +; ; ; ; +; Connections ; ; ; +; -- Input Connections ; 0 ; 0 ; +; -- Registered Input Connections ; 0 ; 0 ; +; -- Output Connections ; 0 ; 0 ; +; -- Registered Output Connections ; 0 ; 0 ; +; ; ; ; +; Internal Connections ; ; ; +; -- Total Connections ; 1528 ; 0 ; +; -- Registered Connections ; 725 ; 0 ; +; ; ; ; +; External Connections ; ; ; +; -- Top ; 0 ; 0 ; +; -- hard_block:auto_generated_inst ; 0 ; 0 ; +; ; ; ; +; Partition Interface ; ; ; +; -- Input Ports ; 12 ; 0 ; +; -- Output Ports ; 29 ; 0 ; +; -- Bidir Ports ; 0 ; 0 ; +; ; ; ; +; Registered Ports ; ; ; +; -- Registered Input Ports ; 0 ; 0 ; +; -- Registered Output Ports ; 0 ; 0 ; +; ; ; ; +; Port Connectivity ; ; ; +; -- Input Ports driven by GND ; 0 ; 0 ; +; -- Output Ports driven by GND ; 0 ; 0 ; +; -- Input Ports driven by VCC ; 0 ; 0 ; +; -- Output Ports driven by VCC ; 0 ; 0 ; +; -- Input Ports with no Source ; 0 ; 0 ; +; -- Output Ports with no Source ; 0 ; 0 ; +; -- Input Ports with no Fanout ; 0 ; 0 ; +; -- Output Ports with no Fanout ; 0 ; 0 ; ++-------------------------------------------------------------+-----------------------+--------------------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Input Pins ; ++----------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+ +; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Termination Control Block ; Location assigned by ; Slew Rate ; ++----------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+ +; ADC_SDO ; AJ21 ; 4A ; 62 ; 0 ; 51 ; 1 ; 0 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ; no ; +; CLOCK_50 ; AF14 ; 3B ; 32 ; 0 ; 0 ; 197 ; 0 ; yes ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ; no ; +; SW[0] ; AB12 ; 3A ; 12 ; 0 ; 17 ; 0 ; 0 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ; no ; +; SW[1] ; AC12 ; 3A ; 16 ; 0 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ; no ; +; SW[2] ; AF9 ; 3A ; 8 ; 0 ; 34 ; 0 ; 0 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ; no ; +; SW[3] ; AF10 ; 3A ; 4 ; 0 ; 51 ; 0 ; 0 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ; no ; +; SW[4] ; AD11 ; 3A ; 2 ; 0 ; 40 ; 0 ; 0 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ; no ; +; SW[5] ; AD12 ; 3A ; 16 ; 0 ; 17 ; 0 ; 0 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ; no ; +; SW[6] ; AE11 ; 3A ; 4 ; 0 ; 34 ; 0 ; 0 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ; no ; +; SW[7] ; AC9 ; 3A ; 4 ; 0 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ; no ; +; SW[8] ; AD10 ; 3A ; 4 ; 0 ; 17 ; 0 ; 0 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ; no ; +; SW[9] ; AE12 ; 3A ; 2 ; 0 ; 57 ; 0 ; 0 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ; no ; ++----------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Output Pins ; ++---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+ +; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Output Buffer Delay ; Output Buffer Delay Control ; Location assigned by ; Output Enable Source ; Output Enable Group ; ++---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+ +; ADC_CS ; AG20 ; 4A ; 62 ; 0 ; 17 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; +; ADC_SCK ; AF21 ; 4A ; 70 ; 0 ; 17 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; +; ADC_SDI ; AG21 ; 4A ; 54 ; 0 ; 0 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; +; DAC_CS ; AD20 ; 4A ; 82 ; 0 ; 40 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; +; DAC_LD ; AK21 ; 4A ; 68 ; 0 ; 34 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; +; DAC_SCK ; AF20 ; 4A ; 70 ; 0 ; 0 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; +; DAC_SDI ; AG18 ; 4A ; 58 ; 0 ; 74 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; +; HEX0[0] ; AE26 ; 5A ; 89 ; 8 ; 37 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; +; HEX0[1] ; AE27 ; 5A ; 89 ; 11 ; 77 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; +; HEX0[2] ; AE28 ; 5A ; 89 ; 11 ; 94 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; +; HEX0[3] ; AG27 ; 5A ; 89 ; 4 ; 77 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; +; HEX0[4] ; AF28 ; 5A ; 89 ; 13 ; 54 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; +; HEX0[5] ; AG28 ; 5A ; 89 ; 13 ; 37 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; +; HEX0[6] ; AH28 ; 5A ; 89 ; 4 ; 94 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; +; HEX1[0] ; AJ29 ; 5A ; 89 ; 6 ; 37 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; +; HEX1[1] ; AH29 ; 5A ; 89 ; 6 ; 54 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; +; HEX1[2] ; AH30 ; 5A ; 89 ; 16 ; 37 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; +; HEX1[3] ; AG30 ; 5A ; 89 ; 16 ; 54 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; +; HEX1[4] ; AF29 ; 5A ; 89 ; 15 ; 37 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; +; HEX1[5] ; AF30 ; 5A ; 89 ; 15 ; 54 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; +; HEX1[6] ; AD27 ; 5A ; 89 ; 8 ; 54 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; +; HEX2[0] ; AB23 ; 5A ; 89 ; 9 ; 20 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; +; HEX2[1] ; AE29 ; 5B ; 89 ; 23 ; 37 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; +; HEX2[2] ; AD29 ; 5B ; 89 ; 23 ; 54 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; +; HEX2[3] ; AC28 ; 5B ; 89 ; 20 ; 77 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; +; HEX2[4] ; AD30 ; 5B ; 89 ; 25 ; 37 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; +; HEX2[5] ; AC29 ; 5B ; 89 ; 20 ; 94 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; +; HEX2[6] ; AC30 ; 5B ; 89 ; 25 ; 54 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; +; PWM_OUT ; AJ20 ; 4A ; 62 ; 0 ; 34 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; ++---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+ + + ++----------------------------------------------------------------------------+ +; I/O Bank Usage ; ++----------+------------------+---------------+--------------+---------------+ +; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ; VCCPD Voltage ; ++----------+------------------+---------------+--------------+---------------+ +; B2L ; 0 / 0 ( -- ) ; -- ; -- ; -- ; +; B1L ; 0 / 0 ( -- ) ; -- ; -- ; -- ; +; 3A ; 10 / 32 ( 31 % ) ; 3.3V ; -- ; 3.3V ; +; 3B ; 1 / 48 ( 2 % ) ; 3.3V ; -- ; 3.3V ; +; 4A ; 9 / 80 ( 11 % ) ; 3.3V ; -- ; 3.3V ; +; 5A ; 15 / 32 ( 47 % ) ; 3.3V ; -- ; 3.3V ; +; 5B ; 6 / 16 ( 38 % ) ; 3.3V ; -- ; 3.3V ; +; 6B ; 0 / 44 ( 0 % ) ; 2.5V ; -- ; 2.5V ; +; 6A ; 0 / 56 ( 0 % ) ; 2.5V ; -- ; 2.5V ; +; 7A ; 0 / 19 ( 0 % ) ; 2.5V ; -- ; 2.5V ; +; 7B ; 0 / 22 ( 0 % ) ; 2.5V ; -- ; 2.5V ; +; 7C ; 0 / 12 ( 0 % ) ; 2.5V ; -- ; 2.5V ; +; 7D ; 0 / 14 ( 0 % ) ; 2.5V ; -- ; 2.5V ; +; 8A ; 0 / 80 ( 0 % ) ; 2.5V ; -- ; 2.5V ; ++----------+------------------+---------------+--------------+---------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; All Package Pins ; ++----------+------------+----------------+---------------------------------+--------+--------------+---------------------+--------------+-----------------+----------+--------------+ +; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; I/O Type ; User Assignment ; Bus Hold ; Weak Pull Up ; ++----------+------------+----------------+---------------------------------+--------+--------------+---------------------+--------------+-----------------+----------+--------------+ +; A2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; A3 ; 493 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A4 ; 491 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A5 ; 489 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A6 ; 487 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A7 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; A8 ; 473 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A9 ; 471 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A10 ; 465 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A11 ; 463 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; A13 ; 461 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A14 ; 455 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A15 ; 447 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A16 ; 439 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; A18 ; 425 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A19 ; 423 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A20 ; 415 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A21 ; 411 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; A23 ; 395 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A24 ; 391 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A25 ; 389 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A26 ; 382 ; 7A ; ^GND ; ; ; ; -- ; ; -- ; -- ; +; A27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; A28 ; 380 ; 7A ; ^HPS_TRST ; ; ; ; -- ; ; -- ; -- ; +; A29 ; 378 ; 7A ; ^HPS_TMS ; ; ; ; -- ; ; -- ; -- ; +; AA1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AA2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AA3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AA4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AA5 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; AA6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AA7 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; +; AA8 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AA9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AA10 ; ; 3A ; VCCPD3A ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AA11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AA12 ; 74 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA13 ; 90 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA14 ; 122 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA15 ; 120 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA16 ; 146 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA17 ; ; 4A ; VCCIO4A ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AA18 ; 168 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA19 ; 176 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA20 ; 200 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA21 ; 210 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AA23 ; ; -- ; VCCPGM ; power ; ; 1.8V/2.5V/3.0V/3.3V ; -- ; ; -- ; -- ; +; AA24 ; 228 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AA25 ; 224 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AA26 ; 252 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AA27 ; ; 5B ; VCCIO5B ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AA28 ; 251 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AA29 ; ; 5B ; VREFB5BN0 ; power ; ; ; -- ; ; -- ; -- ; +; AA30 ; 250 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AB1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AB2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AB3 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; +; AB4 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; +; AB5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AB6 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AB7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AB8 ; 43 ; 3A ; ^nCSO, DATA4 ; ; ; ; Weak Pull Up ; ; -- ; On ; +; AB9 ; 42 ; 3A ; #TDO ; output ; ; ; -- ; ; -- ; -- ; +; AB10 ; ; -- ; VCCPGM ; power ; ; 1.8V/2.5V/3.0V/3.3V ; -- ; ; -- ; -- ; +; AB11 ; ; -- ; VCC_AUX ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AB12 ; 72 ; 3A ; SW[0] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; AB13 ; 88 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB14 ; ; 3B ; VCCIO3B ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AB15 ; 106 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB16 ; ; -- ; VCC_AUX ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AB17 ; 144 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB18 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AB19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AB20 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AB21 ; 208 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB22 ; 225 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AB23 ; 227 ; 5A ; HEX2[0] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; AB24 ; ; 5A ; VCCIO5A ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AB25 ; 230 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AB26 ; 226 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AB27 ; 254 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AB28 ; 249 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AB29 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AB30 ; 248 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AC1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AC2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AC3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AC4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AC5 ; 46 ; 3A ; #TCK ; input ; ; ; -- ; ; -- ; -- ; +; AC6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AC7 ; 45 ; 3A ; ^AS_DATA3, DATA3 ; ; ; ; Weak Pull Up ; ; -- ; On ; +; AC8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AC9 ; 58 ; 3A ; SW[7] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; AC10 ; ; 3A ; VCCPD3A ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AC11 ; ; 3A ; VCCIO3A ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AC12 ; 82 ; 3A ; SW[1] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; AC13 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AC14 ; 104 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AC15 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AC16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AC17 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AC18 ; 162 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AC19 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AC20 ; 186 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AC21 ; ; 4A ; VCCIO4A ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AC22 ; 207 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AC23 ; 205 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AC24 ; ; 5A ; VREFB5AN0 ; power ; ; ; -- ; ; -- ; -- ; +; AC25 ; 215 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AC26 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AC27 ; 242 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AC28 ; 245 ; 5B ; HEX2[3] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; AC29 ; 247 ; 5B ; HEX2[5] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; AC30 ; 259 ; 5B ; HEX2[6] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; AD1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AD2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AD3 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; +; AD4 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; +; AD5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AD6 ; ; 3A ; VREFB3AN0 ; power ; ; ; -- ; ; -- ; -- ; +; AD7 ; 62 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AD8 ; ; 3A ; VCCIO3A ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AD9 ; 55 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AD10 ; 56 ; 3A ; SW[8] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; AD11 ; 54 ; 3A ; SW[4] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; AD12 ; 80 ; 3A ; SW[5] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; AD13 ; ; 3B ; VCCIO3B ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AD14 ; 98 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AD15 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; +; AD16 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AD17 ; 160 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AD18 ; ; 4A ; VCCIO4A ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AD19 ; 184 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AD20 ; 199 ; 4A ; DAC_CS ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; AD21 ; 197 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AD22 ; ; -- ; VCC_AUX ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AD23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AD24 ; 211 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AD25 ; 213 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AD26 ; 240 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AD27 ; 222 ; 5A ; HEX1[6] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; AD28 ; ; 5A ; VCCIO5A ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AD29 ; 255 ; 5B ; HEX2[2] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; AD30 ; 257 ; 5B ; HEX2[4] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; AE1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AE2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AE3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AE4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AE5 ; 49 ; 3A ; ^AS_DATA1, DATA1 ; ; ; ; Weak Pull Up ; ; -- ; On ; +; AE6 ; 51 ; 3A ; ^AS_DATA0, ASDO, DATA0 ; ; ; ; Weak Pull Up ; ; -- ; On ; +; AE7 ; 60 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AE8 ; 47 ; 3A ; ^AS_DATA2, DATA2 ; ; ; ; Weak Pull Up ; ; -- ; On ; +; AE9 ; 53 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AE10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AE11 ; 59 ; 3A ; SW[6] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; AE12 ; 52 ; 3A ; SW[9] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; AE13 ; 95 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AE14 ; 96 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AE15 ; ; 3B ; VCCIO3B ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AE16 ; 139 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AE17 ; 135 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AE18 ; 167 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AE19 ; 165 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AE20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AE21 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AE22 ; 191 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AE23 ; 189 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AE24 ; 209 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AE25 ; ; 4A ; VCCIO4A ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AE26 ; 220 ; 5A ; HEX0[0] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; AE27 ; 229 ; 5A ; HEX0[1] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; AE28 ; 231 ; 5A ; HEX0[2] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; AE29 ; 253 ; 5B ; HEX2[1] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; AE30 ; ; 5B ; VCCIO5B ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AF1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AF2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AF3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AF4 ; 66 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF5 ; 64 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF6 ; 75 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF7 ; ; 3A ; VCCIO3A ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AF8 ; 70 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF9 ; 67 ; 3A ; SW[2] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; AF10 ; 57 ; 3A ; SW[3] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; AF11 ; 87 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AF13 ; 93 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF14 ; 114 ; 3B ; CLOCK_50 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; AF15 ; 112 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF16 ; 137 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AF18 ; 133 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF19 ; 159 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF20 ; 175 ; 4A ; DAC_SCK ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; AF21 ; 173 ; 4A ; ADC_SCK ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; AF22 ; ; 4A ; VCCIO4A ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AF23 ; 183 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF24 ; 181 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF25 ; 206 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF26 ; 204 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AF28 ; 235 ; 5A ; HEX0[4] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; AF29 ; 237 ; 5A ; HEX1[4] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; AF30 ; 239 ; 5A ; HEX1[5] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; AG1 ; 71 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AG2 ; 83 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AG3 ; 63 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AG4 ; ; 3A ; VCCIO3A ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AG5 ; 78 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AG6 ; 73 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AG7 ; 68 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AG8 ; 65 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AG9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AG10 ; 86 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AG11 ; 85 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AG12 ; 103 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AG13 ; 101 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AG14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AG15 ; 127 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AG16 ; 134 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AG17 ; 132 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AG18 ; 150 ; 4A ; DAC_SDI ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; AG19 ; ; 4A ; VCCIO4A ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AG20 ; 157 ; 4A ; ADC_CS ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; AG21 ; 143 ; 4A ; ADC_SDI ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; AG22 ; 166 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AG23 ; 163 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AG24 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AG25 ; 190 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AG26 ; 203 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AG27 ; 212 ; 5A ; HEX0[3] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; AG28 ; 233 ; 5A ; HEX0[5] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; AG29 ; ; 5A ; VCCIO5A ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AG30 ; 243 ; 5A ; HEX1[3] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; AH1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AH2 ; 69 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AH3 ; 81 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AH4 ; 61 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AH5 ; 76 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AH6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AH7 ; 115 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AH8 ; 113 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AH9 ; 84 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AH10 ; 118 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AH11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AH12 ; 126 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AH13 ; 111 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AH14 ; 109 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AH15 ; 125 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AH16 ; ; 4A ; VCCIO4A ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AH17 ; 147 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AH18 ; 145 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AH19 ; 148 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AH20 ; 141 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AH21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AH22 ; 164 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AH23 ; 174 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AH24 ; 161 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AH25 ; 188 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AH26 ; ; 4A ; VCCIO4A ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AH27 ; 201 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AH28 ; 214 ; 5A ; HEX0[6] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; AH29 ; 218 ; 5A ; HEX1[1] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; AH30 ; 241 ; 5A ; HEX1[2] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; AJ1 ; 79 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AJ2 ; 77 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AJ3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AJ4 ; 94 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AJ5 ; 99 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AJ6 ; 102 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AJ7 ; 100 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AJ8 ; ; 3B ; VCCIO3B ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AJ9 ; 110 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AJ10 ; 116 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AJ11 ; 119 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AJ12 ; 124 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AJ13 ; ; 3B ; VCCIO3B ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AJ14 ; 131 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AJ15 ; ; 3B ; VREFB3BN0 ; power ; ; ; -- ; ; -- ; -- ; +; AJ16 ; 142 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AJ17 ; 151 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AJ18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AJ19 ; 155 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AJ20 ; 158 ; 4A ; PWM_OUT ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; AJ21 ; 156 ; 4A ; ADC_SDO ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; AJ22 ; 172 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AJ23 ; ; 4A ; VCCIO4A ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AJ24 ; 182 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AJ25 ; 180 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AJ26 ; 187 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AJ27 ; 195 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AJ28 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AJ29 ; 216 ; 5A ; HEX1[0] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; AJ30 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AK2 ; 91 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AK3 ; 89 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AK4 ; 92 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AK5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AK6 ; 97 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AK7 ; 107 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AK8 ; 105 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AK9 ; 108 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AK10 ; ; 3B ; VCCIO3B ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AK11 ; 117 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AK12 ; 123 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AK13 ; 121 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AK14 ; 129 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AK15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AK16 ; 140 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AK17 ; ; 4A ; VREFB4AN0 ; power ; ; ; -- ; ; -- ; -- ; +; AK18 ; 149 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AK19 ; 153 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AK20 ; ; 4A ; VCCIO4A ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AK21 ; 171 ; 4A ; DAC_LD ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; AK22 ; 169 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AK23 ; 179 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AK24 ; 177 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AK25 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AK26 ; 185 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AK27 ; 193 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AK28 ; 198 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AK29 ; 196 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B1 ; 509 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B2 ; 507 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B3 ; 513 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B4 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; B5 ; 512 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B6 ; 510 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B7 ; 477 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B8 ; 481 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B10 ; ; 8A ; VREFB8AN0 ; power ; ; ; -- ; ; -- ; -- ; +; B11 ; 469 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B12 ; 464 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B13 ; 459 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B15 ; 451 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B16 ; 441 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B17 ; 431 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B18 ; 418 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B20 ; 417 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B21 ; 413 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B22 ; 399 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B23 ; 397 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B24 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B25 ; 387 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B26 ; 386 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B27 ; 381 ; 7A ; ^HPS_TDI ; ; ; ; -- ; ; -- ; -- ; +; B28 ; 376 ; 7A ; ^HPS_TDO ; ; ; ; -- ; ; -- ; -- ; +; B29 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B30 ; 365 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; C1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; C2 ; 517 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C3 ; 511 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C4 ; 501 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C5 ; 497 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; C7 ; 475 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C8 ; 479 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C9 ; 485 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C10 ; 483 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C11 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; C12 ; 467 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C13 ; 462 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C14 ; 448 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C15 ; 453 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; C17 ; 433 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C18 ; 435 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C19 ; 427 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C20 ; 421 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; C22 ; 396 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C23 ; 401 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C24 ; 393 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C25 ; 388 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C26 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; C27 ; 374 ; 7A ; ^HPS_nRST ; ; ; ; -- ; ; -- ; -- ; +; C28 ; 369 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; C29 ; 367 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; C30 ; 363 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; D1 ; 529 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D2 ; 515 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; D4 ; 521 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D5 ; 499 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D6 ; 495 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D7 ; 505 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D8 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; D9 ; 480 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D10 ; 472 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D11 ; 470 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D12 ; 496 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; D14 ; 446 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D15 ; 449 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D16 ; 445 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D17 ; 440 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D18 ; ; 7C ; VCCIO7C_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; D19 ; 426 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D20 ; 420 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D21 ; 419 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D22 ; 402 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; D24 ; 404 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D25 ; 384 ; 7A ; ^HPS_CLK1 ; ; ; ; -- ; ; -- ; -- ; +; D26 ; 373 ; 7A ; ^GND ; ; ; ; -- ; ; -- ; -- ; +; D27 ; 371 ; 6A ; HPS_RZQ_0 ; ; ; ; -- ; ; no ; On ; +; D28 ; ; 6A ; VCCIO6A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; D29 ; 361 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; D30 ; 359 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E1 ; 527 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E2 ; 525 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E3 ; 523 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E4 ; 519 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E5 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; E6 ; 533 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E7 ; 531 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E8 ; 503 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E9 ; 478 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; E11 ; 504 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E12 ; 494 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E13 ; 488 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E14 ; 454 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E15 ; ; 7D ; VCCIO7D_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; E16 ; 443 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E17 ; 438 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E18 ; 437 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E19 ; 424 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E20 ; ; 7B ; VCCIO7B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; E21 ; 412 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E22 ; ; 7A, 7B, 7C, 7D ; VREFB7A7B7C7DN0_HPS ; power ; ; ; -- ; ; -- ; -- ; +; E23 ; 394 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E24 ; 403 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E25 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; E26 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; +; E27 ; 357 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E28 ; 351 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E29 ; 353 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E30 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; F1 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; +; F2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; F3 ; 539 ; 9A ; ^CONF_DONE ; ; ; ; -- ; ; -- ; -- ; +; F4 ; 541 ; 9A ; ^nSTATUS ; ; ; ; -- ; ; -- ; -- ; +; F5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; F6 ; 537 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; F8 ; 536 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F9 ; 534 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F10 ; 528 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F11 ; 502 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F12 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; F13 ; 486 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F14 ; 468 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F15 ; 466 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F16 ; 442 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; F18 ; 430 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F19 ; 410 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F20 ; 407 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F21 ; 409 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F22 ; ; 7A ; VCCIO7A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; F23 ; 375 ; 7A ; ^HPS_nPOR ; ; ; ; -- ; ; -- ; -- ; +; F24 ; 383 ; 7A ; ^HPS_PORSEL ; ; ; ; -- ; ; -- ; -- ; +; F25 ; 385 ; 7A ; ^HPS_CLK2 ; ; ; ; -- ; ; -- ; -- ; +; F26 ; 341 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; F28 ; 345 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F29 ; 349 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F30 ; 347 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G1 ; ; ; GND ; ; ; ; -- ; ; -- ; -- ; +; G2 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; +; G3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; G4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; G5 ; 542 ; 9A ; ^nCE ; ; ; ; -- ; ; -- ; -- ; +; G6 ; 543 ; 9A ; ^MSEL2 ; ; ; ; -- ; ; -- ; -- ; +; G7 ; 535 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; G8 ; 492 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; G9 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; G10 ; 526 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; G11 ; 520 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; G12 ; 518 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; G13 ; 484 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; G14 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; G15 ; 460 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; G16 ; 444 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; G17 ; 436 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; G18 ; 432 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; G19 ; ; 7B ; VCCIO7B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; G20 ; 416 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; G21 ; 392 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; G22 ; 400 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; G23 ; 377 ; 7A ; ^VCCRSTCLK_HPS ; ; ; ; -- ; ; -- ; -- ; +; G24 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; G25 ; 370 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G26 ; 362 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G27 ; 339 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ; +; G28 ; 335 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G29 ; ; 6A ; VCCIO6A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; G30 ; 343 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; H2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; H3 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; +; H4 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; +; H5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; H6 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; H7 ; 508 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H8 ; 490 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H9 ; ; -- ; VCCBAT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; H10 ; ; -- ; VCC_AUX ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; H11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; H12 ; 500 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H13 ; 498 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H14 ; 482 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H15 ; 458 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H16 ; ; 7D ; VCCIO7D_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; H17 ; 434 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H18 ; 422 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H19 ; 406 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H20 ; 398 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H21 ; ; 7A ; VCCIO7A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; H22 ; 379 ; 7A ; ^HPS_TCK ; ; ; ; -- ; ; -- ; -- ; +; H23 ; 390 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H24 ; 364 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H25 ; 368 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H26 ; ; 6A ; VCCIO6A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; H27 ; 360 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H28 ; 333 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H29 ; 331 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H30 ; 337 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J5 ; 545 ; 9A ; ^nCONFIG ; ; ; ; -- ; ; -- ; -- ; +; J6 ; 547 ; 9A ; ^GND ; ; ; ; -- ; ; -- ; -- ; +; J7 ; 506 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; J8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J9 ; 532 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; J10 ; 530 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; J11 ; ; -- ; VCCPGM ; power ; ; 1.8V/2.5V/3.0V/3.3V ; -- ; ; -- ; -- ; +; J12 ; 516 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; J13 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; J14 ; 476 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; J15 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; +; J16 ; ; -- ; VCC_AUX ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; J17 ; ; 7C ; VCCPD7C_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; J18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J19 ; 408 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; J20 ; ; -- ; VCCRSTCLK_HPS ; power ; ; 1.8V/2.5V/3.0V/3.3V ; -- ; ; -- ; -- ; +; J21 ; ; -- ; VCC_AUX_SHARED ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; J22 ; 372 ; 7A ; ^GND ; ; ; ; -- ; ; -- ; -- ; +; J23 ; 354 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J24 ; 352 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J25 ; 344 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J26 ; 323 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J27 ; 346 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J28 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J29 ; 327 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J30 ; 329 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K3 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; +; K4 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; +; K5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K6 ; 540 ; 9A ; ^MSEL1 ; ; ; ; -- ; ; -- ; -- ; +; K7 ; 522 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; K8 ; 524 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; K9 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; K10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K11 ; ; 8A ; VCCPD8A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; K12 ; 514 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; K13 ; ; 8A ; VCCPD8A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; K14 ; 474 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; K15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K16 ; ; 7D ; VCCPD7D_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; K17 ; 414 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; K18 ; ; 7B ; VCCPD7B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; K19 ; ; 7A ; VCCPD7A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; K20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K21 ; 366 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K22 ; 336 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K23 ; 338 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K24 ; ; 6A ; VCCIO6A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; K25 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K26 ; 322 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K27 ; 319 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K28 ; 325 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K29 ; 321 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K30 ; ; 6A ; VCCIO6A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; L1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L5 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; L6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L7 ; 544 ; 9A ; ^MSEL3 ; ; ; ; -- ; ; -- ; -- ; +; L8 ; 538 ; 9A ; ^MSEL0 ; ; ; ; -- ; ; -- ; -- ; +; L9 ; 546 ; 9A ; ^MSEL4 ; ; ; ; -- ; ; -- ; -- ; +; L10 ; ; 8A ; VCCPD8A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; L11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L12 ; ; 8A ; VCCPD8A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; L13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L14 ; ; 8A ; VCCPD8A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; L15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L16 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; L17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L18 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; L19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L20 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; L21 ; ; -- ; VCCPLL_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; L22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L23 ; 350 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L24 ; 328 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L25 ; 330 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L26 ; 320 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L27 ; ; 6A ; VCCIO6A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; L28 ; 313 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L29 ; 315 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L30 ; 317 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M3 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; +; M4 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; +; M5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M6 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; M7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M9 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; M10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M11 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; M12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M13 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; M14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M15 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; M16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M17 ; 450 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; M18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M19 ; 334 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M21 ; ; 6A, 6B ; VCCPD6A6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; M22 ; 308 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M23 ; 348 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M24 ; ; 6A ; VCCIO6A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; M25 ; 324 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M26 ; 314 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M27 ; 312 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M28 ; 309 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M29 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M30 ; 311 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N5 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; N6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N7 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; N8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N10 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; N11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N12 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; N13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N14 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; N15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N16 ; 452 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; N17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N18 ; 332 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N20 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; N21 ; ; 6A ; VCCIO6A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; N22 ; ; 6A, 6B ; VCCPD6A6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; N23 ; 310 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N24 ; 318 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N25 ; 316 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N26 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N27 ; 297 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N28 ; 303 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N29 ; 305 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N30 ; 307 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P3 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; +; P4 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; +; P5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P6 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; P7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P11 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; P12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P13 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; P14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P15 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; P16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P17 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; P18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P19 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; P20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P21 ; ; 6A, 6B ; VCCPD6A6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; P22 ; 294 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P23 ; ; 6B ; VCCIO6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; P24 ; 290 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P25 ; 288 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P26 ; 298 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P27 ; 296 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P28 ; ; 6B ; VCCIO6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; P29 ; 299 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P30 ; 301 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; R2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; R3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; R4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; R5 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; R6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; R7 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; R8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; R9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; R10 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; R11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; R12 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; R13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; R14 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; R15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; R16 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; R17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; R18 ; 302 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R19 ; 300 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R20 ; ; 6A, 6B ; VCCPD6A6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; R21 ; 286 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R22 ; 284 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R23 ; ; 6A, 6B ; VCCPD6A6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; R24 ; 272 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R25 ; ; 6B ; VCCIO6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; R26 ; 280 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R27 ; 282 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R28 ; 293 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R29 ; 295 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R30 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T3 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; +; T4 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; +; T5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T6 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; T7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T11 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; T12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T13 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; T14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T17 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; T18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T19 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; T20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T21 ; 278 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T22 ; ; 6B ; VCCIO6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; T23 ; 270 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T24 ; 268 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T25 ; 266 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T26 ; 304 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T28 ; 287 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T29 ; 289 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T30 ; 291 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; U2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; U3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; U4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; U5 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; U6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; U7 ; 50 ; 3A ; ^DCLK ; ; ; ; Weak Pull Up ; ; -- ; On ; +; U8 ; 48 ; 3A ; #TDI ; input ; ; ; -- ; ; -- ; -- ; +; U9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; U10 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; U11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; U12 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; U13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; U14 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; U15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; U16 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; U17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; U18 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; U19 ; ; 6B ; VCCIO6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; U20 ; 276 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U21 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; U22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; U23 ; ; 5B ; VCCPD5B ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; U24 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; U25 ; 264 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U26 ; 306 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U27 ; 273 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U28 ; 285 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U29 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; U30 ; 283 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ; +; V1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; V2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; V3 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; +; V4 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; +; V5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; V6 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; V7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; V8 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; V9 ; 44 ; 3A ; #TMS ; input ; ; ; -- ; ; -- ; -- ; +; V10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; V11 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; V12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; V13 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; V14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; V15 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; V16 ; 138 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V17 ; 154 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V18 ; 194 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; V20 ; 292 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; V22 ; ; 5A ; VCCPD5A ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; V23 ; 236 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V24 ; ; 5A ; VCCPD5A ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; V25 ; 246 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V26 ; ; 6B ; VCCIO6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; V27 ; 265 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V28 ; 271 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V29 ; 275 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V30 ; 281 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; W1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; W2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; W3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; W4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; W5 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; W6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; W7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; W8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; W9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; W10 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; W11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; W12 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; W13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; W14 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; W15 ; 130 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W16 ; 136 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W17 ; 152 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; W19 ; 192 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W20 ; 217 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; W21 ; 221 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; W22 ; 223 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; W23 ; ; 5A ; VCCIO5A ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; W24 ; 238 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; W25 ; 244 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; W26 ; 274 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; W27 ; 261 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; W28 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; W29 ; 279 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; W30 ; 277 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; Y1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y3 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; +; Y4 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; +; Y5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y6 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; Y7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y9 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; Y10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y11 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; Y12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y13 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; Y14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y16 ; 128 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y17 ; 170 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y18 ; 178 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y19 ; 202 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y21 ; 219 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; Y22 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; Y23 ; 232 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; Y24 ; 234 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; Y25 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y26 ; 256 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; Y27 ; 258 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; Y28 ; 269 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; Y29 ; 263 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; Y30 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ++----------+------------+----------------+---------------------------------+--------+--------------+---------------------+--------------+-----------------+----------+--------------+ +Note: Pin directions (input, output or bidir) are based on device operating in user mode. + + ++-------------------------------------------------+ +; I/O Assignment Warnings ; ++----------+--------------------------------------+ +; Pin Name ; Reason ; ++----------+--------------------------------------+ +; HEX0[0] ; Missing drive strength and slew rate ; +; HEX0[1] ; Missing drive strength and slew rate ; +; HEX0[2] ; Missing drive strength and slew rate ; +; HEX0[3] ; Missing drive strength and slew rate ; +; HEX0[4] ; Missing drive strength and slew rate ; +; HEX0[5] ; Missing drive strength and slew rate ; +; HEX0[6] ; Missing drive strength and slew rate ; +; HEX1[0] ; Missing drive strength and slew rate ; +; HEX1[1] ; Missing drive strength and slew rate ; +; HEX1[2] ; Missing drive strength and slew rate ; +; HEX1[3] ; Missing drive strength and slew rate ; +; HEX1[4] ; Missing drive strength and slew rate ; +; HEX1[5] ; Missing drive strength and slew rate ; +; HEX1[6] ; Missing drive strength and slew rate ; +; HEX2[0] ; Missing drive strength and slew rate ; +; HEX2[1] ; Missing drive strength and slew rate ; +; HEX2[2] ; Missing drive strength and slew rate ; +; HEX2[3] ; Missing drive strength and slew rate ; +; HEX2[4] ; Missing drive strength and slew rate ; +; HEX2[5] ; Missing drive strength and slew rate ; +; HEX2[6] ; Missing drive strength and slew rate ; +; DAC_SDI ; Missing drive strength and slew rate ; +; DAC_SCK ; Missing drive strength and slew rate ; +; DAC_CS ; Missing drive strength and slew rate ; +; DAC_LD ; Missing drive strength and slew rate ; +; ADC_SDI ; Missing drive strength and slew rate ; +; ADC_SCK ; Missing drive strength and slew rate ; +; ADC_CS ; Missing drive strength and slew rate ; +; PWM_OUT ; Missing drive strength and slew rate ; ++----------+--------------------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fitter Resource Utilization by Entity ; ++---------------------------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------+--------------+ +; Compilation Hierarchy Node ; ALMs needed [=A-B+C] ; [A] ALMs used in final placement ; [B] Estimate of ALMs recoverable by dense packing ; [C] Estimate of ALMs unavailable ; ALMs used for memory ; Combinational ALUTs ; Dedicated Logic Registers ; I/O Registers ; Block Memory Bits ; M10Ks ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name ; Entity Name ; Library Name ; ++---------------------------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------+--------------+ +; |ex17_top ; 94.0 (0.5) ; 103.0 (0.5) ; 9.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 166 (1) ; 179 (0) ; 0 (0) ; 73728 ; 9 ; 0 ; 41 ; 0 ; |ex17_top ; ex17_top ; work ; +; |clktick_16:GEN_10K| ; 11.5 (11.5) ; 12.0 (12.0) ; 0.5 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 20 (20) ; 19 (19) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex17_top|clktick_16:GEN_10K ; clktick_16 ; work ; +; |hex_to_7seg:SEG0| ; 3.5 (3.5) ; 3.5 (3.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 7 (7) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex17_top|hex_to_7seg:SEG0 ; hex_to_7seg ; work ; +; |hex_to_7seg:SEG1| ; 3.2 (3.2) ; 3.2 (3.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 7 (7) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex17_top|hex_to_7seg:SEG1 ; hex_to_7seg ; work ; +; |hex_to_7seg:SEG2| ; 1.5 (1.5) ; 1.5 (1.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 3 (3) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex17_top|hex_to_7seg:SEG2 ; hex_to_7seg ; work ; +; |processor:ALLPASS| ; 32.4 (8.5) ; 33.3 (9.2) ; 0.9 (0.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 69 (22) ; 63 (15) ; 0 (0) ; 73728 ; 9 ; 0 ; 0 ; 0 ; |ex17_top|processor:ALLPASS ; processor ; work ; +; |FIFO:DELAY1024| ; 23.2 (0.0) ; 23.2 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 45 (0) ; 46 (0) ; 0 (0) ; 73728 ; 9 ; 0 ; 0 ; 0 ; |ex17_top|processor:ALLPASS|FIFO:DELAY1024 ; FIFO ; work ; +; |scfifo:scfifo_component| ; 23.2 (0.0) ; 23.2 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 45 (0) ; 46 (0) ; 0 (0) ; 73728 ; 9 ; 0 ; 0 ; 0 ; |ex17_top|processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component ; scfifo ; work ; +; |scfifo_j791:auto_generated| ; 23.2 (0.0) ; 23.2 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 45 (0) ; 46 (0) ; 0 (0) ; 73728 ; 9 ; 0 ; 0 ; 0 ; |ex17_top|processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated ; scfifo_j791 ; work ; +; |a_dpfifo_qd91:dpfifo| ; 23.2 (0.5) ; 23.2 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 45 (1) ; 46 (0) ; 0 (0) ; 73728 ; 9 ; 0 ; 0 ; 0 ; |ex17_top|processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo ; a_dpfifo_qd91 ; work ; +; |a_fefifo_4be:fifo_state| ; 9.7 (3.2) ; 9.7 (3.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 18 (5) ; 17 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex17_top|processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|a_fefifo_4be:fifo_state ; a_fefifo_4be ; work ; +; |cntr_di7:count_usedw| ; 6.5 (6.5) ; 6.5 (6.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 13 (13) ; 16 (16) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex17_top|processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|a_fefifo_4be:fifo_state|cntr_di7:count_usedw ; cntr_di7 ; work ; +; |altsyncram_44t1:FIFOram| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 73728 ; 9 ; 0 ; 0 ; 0 ; |ex17_top|processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|altsyncram_44t1:FIFOram ; altsyncram_44t1 ; work ; +; |cntr_1ib:rd_ptr_count| ; 6.5 (6.5) ; 6.5 (6.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 13 (13) ; 14 (14) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex17_top|processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|cntr_1ib:rd_ptr_count ; cntr_1ib ; work ; +; |cntr_1ib:wr_ptr| ; 6.5 (6.5) ; 6.5 (6.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 13 (13) ; 15 (15) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex17_top|processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|cntr_1ib:wr_ptr ; cntr_1ib ; work ; +; |pulse_gen:PULSE0| ; 0.8 (0.8) ; 1.0 (1.0) ; 0.3 (0.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 2 (2) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex17_top|processor:ALLPASS|pulse_gen:PULSE0 ; pulse_gen ; work ; +; |pwm:PWM_DC| ; 11.2 (11.2) ; 11.8 (11.8) ; 0.6 (0.6) ; 0.0 (0.0) ; 0.0 (0.0) ; 19 (19) ; 21 (21) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex17_top|pwm:PWM_DC ; pwm ; work ; +; |spi2adc:SPI_ADC| ; 14.9 (14.9) ; 22.4 (22.4) ; 7.5 (7.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 23 (23) ; 51 (51) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex17_top|spi2adc:SPI_ADC ; spi2adc ; work ; +; |spi2dac:SPI_DAC| ; 14.8 (14.8) ; 14.8 (14.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 25 (25) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex17_top|spi2dac:SPI_DAC ; spi2dac ; work ; ++---------------------------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------+--------------+ +Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. + + ++-------------------------------------------------------------------------------------------------------------------------+ +; Delay Chain Summary ; ++----------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+ +; Name ; Pin Type ; D1 ; D3_0 ; D3_1 ; D4 ; D5 ; D5 OE ; D5 OCT ; T11 (Postamble Gating) ; T11 (Postamble Ungating) ; ++----------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+ +; SW[0] ; Input ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; +; SW[1] ; Input ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; +; SW[2] ; Input ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; +; SW[3] ; Input ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; +; SW[4] ; Input ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; +; SW[5] ; Input ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; +; SW[6] ; Input ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; +; SW[7] ; Input ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; +; SW[8] ; Input ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; +; SW[9] ; Input ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; +; HEX0[0] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; HEX0[1] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; HEX0[2] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; HEX0[3] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; HEX0[4] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; HEX0[5] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; HEX0[6] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; HEX1[0] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; HEX1[1] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; HEX1[2] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; HEX1[3] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; HEX1[4] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; HEX1[5] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; HEX1[6] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; HEX2[0] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; HEX2[1] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; HEX2[2] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; HEX2[3] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; HEX2[4] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; HEX2[5] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; HEX2[6] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; DAC_SDI ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; DAC_SCK ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; DAC_CS ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; DAC_LD ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; ADC_SDI ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; ADC_SCK ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; ADC_CS ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; PWM_OUT ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; CLOCK_50 ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; +; ADC_SDO ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; ++----------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+ + + ++--------------------------------------------------------------------------+ +; Pad To Core Delay Chain Fanout ; ++--------------------------------------------+-------------------+---------+ +; Source Pin / Fanout ; Pad To Core Index ; Setting ; ++--------------------------------------------+-------------------+---------+ +; SW[0] ; ; ; +; SW[1] ; ; ; +; SW[2] ; ; ; +; SW[3] ; ; ; +; SW[4] ; ; ; +; SW[5] ; ; ; +; SW[6] ; ; ; +; SW[7] ; ; ; +; SW[8] ; ; ; +; SW[9] ; ; ; +; CLOCK_50 ; ; ; +; ADC_SDO ; ; ; +; - spi2adc:SPI_ADC|shift_reg[0]~feeder ; 0 ; 0 ; ++--------------------------------------------+-------------------+---------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Control Signals ; ++--------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------+----------------------------+--------+----------------------+------------------+---------------------------+ +; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ; ++--------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------+----------------------------+--------+----------------------+------------------+---------------------------+ +; CLOCK_50 ; PIN_AF14 ; 188 ; Clock ; yes ; Global Clock ; GCLK6 ; -- ; +; clktick_16:GEN_10K|Equal0~3 ; LABCELL_X74_Y3_N15 ; 12 ; Sync. clear ; no ; -- ; -- ; -- ; +; clktick_16:GEN_10K|tick ; FF_X74_Y3_N2 ; 15 ; Clock enable ; no ; -- ; -- ; -- ; +; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|a_fefifo_4be:fifo_state|_~0 ; LABCELL_X73_Y4_N57 ; 16 ; Clock enable ; no ; -- ; -- ; -- ; +; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|valid_wreq ; LABCELL_X73_Y4_N54 ; 36 ; Clock enable, Write enable ; no ; -- ; -- ; -- ; +; processor:ALLPASS|comb~0 ; LABCELL_X73_Y4_N48 ; 24 ; Clock enable ; no ; -- ; -- ; -- ; +; spi2adc:SPI_ADC|adc_done ; FF_X72_Y4_N55 ; 12 ; Clock enable ; no ; -- ; -- ; -- ; +; spi2adc:SPI_ADC|always3~0 ; MLABCELL_X72_Y4_N27 ; 13 ; Clock enable ; no ; -- ; -- ; -- ; +; spi2adc:SPI_ADC|tick ; FF_X72_Y4_N5 ; 39 ; Clock enable ; no ; -- ; -- ; -- ; +; spi2dac:SPI_DAC|always5~0 ; LABCELL_X71_Y4_N3 ; 9 ; Sync. load ; no ; -- ; -- ; -- ; ++--------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------+----------------------------+--------+----------------------+------------------+---------------------------+ + + ++-----------------------------------------------------------------------------------------------------+ +; Global & Other Fast Signals ; ++----------+----------+---------+----------------------+------------------+---------------------------+ +; Name ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ; ++----------+----------+---------+----------------------+------------------+---------------------------+ +; CLOCK_50 ; PIN_AF14 ; 188 ; Global Clock ; GCLK6 ; -- ; ++----------+----------+---------+----------------------+------------------+---------------------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fitter RAM Summary ; ++---------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+-------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+-------------+------------+------+------------------------------------------------------------------------------------------------------------------------------------------------+----------------------+-----------------+-----------------+----------+------------------------+-----------------------+ +; Name ; Type ; Mode ; Clock Mode ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Port A Input Registers ; Port A Output Registers ; Port B Input Registers ; Port B Output Registers ; Size ; Implementation Port A Depth ; Implementation Port A Width ; Implementation Port B Depth ; Implementation Port B Width ; Implementation Bits ; M10K blocks ; MLAB cells ; MIF ; Location ; Mixed Width RDW Mode ; Port A RDW Mode ; Port B RDW Mode ; ECC Mode ; ECC Pipeline Registers ; Fits in MLABs ; ++---------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+-------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+-------------+------------+------+------------------------------------------------------------------------------------------------------------------------------------------------+----------------------+-----------------+-----------------+----------+------------------------+-----------------------+ +; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|altsyncram_44t1:FIFOram|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Single Clock ; 8192 ; 10 ; 8192 ; 10 ; yes ; no ; yes ; no ; 81920 ; 8192 ; 9 ; 8192 ; 9 ; 73728 ; 9 ; 0 ; None ; M10K_X69_Y5_N0, M10K_X76_Y7_N0, M10K_X76_Y6_N0, M10K_X76_Y5_N0, M10K_X69_Y7_N0, M10K_X69_Y6_N0, M10K_X76_Y3_N0, M10K_X76_Y4_N0, M10K_X69_Y4_N0 ; Don't care ; New data ; New data ; Off ; No ; No - Address Too Wide ; ++---------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+-------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+-------------+------------+------+------------------------------------------------------------------------------------------------------------------------------------------------+----------------------+-----------------+-----------------+----------+------------------------+-----------------------+ +Note: Fitter may spread logical memories into multiple blocks to improve timing. The actual required RAM blocks can be found in the Fitter Resource Usage section. + + ++-----------------------------------------------------------------------+ +; Routing Usage Summary ; ++---------------------------------------------+-------------------------+ +; Routing Resource Type ; Usage ; ++---------------------------------------------+-------------------------+ +; Block interconnects ; 463 / 289,320 ( < 1 % ) ; +; C12 interconnects ; 6 / 13,420 ( < 1 % ) ; +; C2 interconnects ; 119 / 119,108 ( < 1 % ) ; +; C4 interconnects ; 68 / 56,300 ( < 1 % ) ; +; DQS bus muxes ; 0 / 25 ( 0 % ) ; +; DQS-18 I/O buses ; 0 / 25 ( 0 % ) ; +; DQS-9 I/O buses ; 0 / 25 ( 0 % ) ; +; Direct links ; 77 / 289,320 ( < 1 % ) ; +; Global clocks ; 1 / 16 ( 6 % ) ; +; HPS SDRAM PLL inputs ; 0 / 1 ( 0 % ) ; +; HPS SDRAM PLL outputs ; 0 / 1 ( 0 % ) ; +; HPS_INTERFACE_BOOT_FROM_FPGA_INPUTs ; 0 / 9 ( 0 % ) ; +; HPS_INTERFACE_CLOCKS_RESETS_INPUTs ; 0 / 7 ( 0 % ) ; +; HPS_INTERFACE_CLOCKS_RESETS_OUTPUTs ; 0 / 6 ( 0 % ) ; +; HPS_INTERFACE_CROSS_TRIGGER_INPUTs ; 0 / 18 ( 0 % ) ; +; HPS_INTERFACE_CROSS_TRIGGER_OUTPUTs ; 0 / 24 ( 0 % ) ; +; HPS_INTERFACE_DBG_APB_INPUTs ; 0 / 37 ( 0 % ) ; +; HPS_INTERFACE_DBG_APB_OUTPUTs ; 0 / 55 ( 0 % ) ; +; HPS_INTERFACE_DMA_INPUTs ; 0 / 16 ( 0 % ) ; +; HPS_INTERFACE_DMA_OUTPUTs ; 0 / 8 ( 0 % ) ; +; HPS_INTERFACE_FPGA2HPS_INPUTs ; 0 / 287 ( 0 % ) ; +; HPS_INTERFACE_FPGA2HPS_OUTPUTs ; 0 / 154 ( 0 % ) ; +; HPS_INTERFACE_FPGA2SDRAM_INPUTs ; 0 / 852 ( 0 % ) ; +; HPS_INTERFACE_FPGA2SDRAM_OUTPUTs ; 0 / 408 ( 0 % ) ; +; HPS_INTERFACE_HPS2FPGA_INPUTs ; 0 / 165 ( 0 % ) ; +; HPS_INTERFACE_HPS2FPGA_LIGHT_WEIGHT_INPUTs ; 0 / 67 ( 0 % ) ; +; HPS_INTERFACE_HPS2FPGA_LIGHT_WEIGHT_OUTPUTs ; 0 / 156 ( 0 % ) ; +; HPS_INTERFACE_HPS2FPGA_OUTPUTs ; 0 / 282 ( 0 % ) ; +; HPS_INTERFACE_INTERRUPTS_INPUTs ; 0 / 64 ( 0 % ) ; +; HPS_INTERFACE_INTERRUPTS_OUTPUTs ; 0 / 42 ( 0 % ) ; +; HPS_INTERFACE_JTAG_OUTPUTs ; 0 / 5 ( 0 % ) ; +; HPS_INTERFACE_LOAN_IO_INPUTs ; 0 / 142 ( 0 % ) ; +; HPS_INTERFACE_LOAN_IO_OUTPUTs ; 0 / 85 ( 0 % ) ; +; HPS_INTERFACE_MPU_EVENT_STANDBY_INPUTs ; 0 / 1 ( 0 % ) ; +; HPS_INTERFACE_MPU_EVENT_STANDBY_OUTPUTs ; 0 / 5 ( 0 % ) ; +; HPS_INTERFACE_MPU_GENERAL_PURPOSE_INPUTs ; 0 / 32 ( 0 % ) ; +; HPS_INTERFACE_MPU_GENERAL_PURPOSE_OUTPUTs ; 0 / 32 ( 0 % ) ; +; HPS_INTERFACE_PERIPHERAL_CAN_INPUTs ; 0 / 2 ( 0 % ) ; +; HPS_INTERFACE_PERIPHERAL_CAN_OUTPUTs ; 0 / 2 ( 0 % ) ; +; HPS_INTERFACE_PERIPHERAL_EMAC_INPUTs ; 0 / 32 ( 0 % ) ; +; HPS_INTERFACE_PERIPHERAL_EMAC_OUTPUTs ; 0 / 34 ( 0 % ) ; +; HPS_INTERFACE_PERIPHERAL_I2C_INPUTs ; 0 / 8 ( 0 % ) ; +; HPS_INTERFACE_PERIPHERAL_I2C_OUTPUTs ; 0 / 8 ( 0 % ) ; +; HPS_INTERFACE_PERIPHERAL_NAND_INPUTs ; 0 / 12 ( 0 % ) ; +; HPS_INTERFACE_PERIPHERAL_NAND_OUTPUTs ; 0 / 18 ( 0 % ) ; +; HPS_INTERFACE_PERIPHERAL_QSPI_INPUTs ; 0 / 4 ( 0 % ) ; +; HPS_INTERFACE_PERIPHERAL_QSPI_OUTPUTs ; 0 / 13 ( 0 % ) ; +; HPS_INTERFACE_PERIPHERAL_SDMMC_INPUTs ; 0 / 13 ( 0 % ) ; +; HPS_INTERFACE_PERIPHERAL_SDMMC_OUTPUTs ; 0 / 22 ( 0 % ) ; +; HPS_INTERFACE_PERIPHERAL_SPI_MASTER_INPUTs ; 0 / 4 ( 0 % ) ; +; HPS_INTERFACE_PERIPHERAL_SPI_MASTER_OUTPUTs ; 0 / 14 ( 0 % ) ; +; HPS_INTERFACE_PERIPHERAL_SPI_SLAVE_INPUTs ; 0 / 6 ( 0 % ) ; +; HPS_INTERFACE_PERIPHERAL_SPI_SLAVE_OUTPUTs ; 0 / 4 ( 0 % ) ; +; HPS_INTERFACE_PERIPHERAL_UART_INPUTs ; 0 / 10 ( 0 % ) ; +; HPS_INTERFACE_PERIPHERAL_UART_OUTPUTs ; 0 / 10 ( 0 % ) ; +; HPS_INTERFACE_PERIPHERAL_USB_INPUTs ; 0 / 22 ( 0 % ) ; +; HPS_INTERFACE_PERIPHERAL_USB_OUTPUTs ; 0 / 34 ( 0 % ) ; +; HPS_INTERFACE_STM_EVENT_INPUTs ; 0 / 28 ( 0 % ) ; +; HPS_INTERFACE_TEST_INPUTs ; 0 / 610 ( 0 % ) ; +; HPS_INTERFACE_TEST_OUTPUTs ; 0 / 513 ( 0 % ) ; +; HPS_INTERFACE_TPIU_TRACE_INPUTs ; 0 / 2 ( 0 % ) ; +; HPS_INTERFACE_TPIU_TRACE_OUTPUTs ; 0 / 33 ( 0 % ) ; +; Horizontal periphery clocks ; 0 / 72 ( 0 % ) ; +; Local interconnects ; 95 / 84,580 ( < 1 % ) ; +; Quadrant clocks ; 0 / 66 ( 0 % ) ; +; R14 interconnects ; 10 / 12,676 ( < 1 % ) ; +; R14/C12 interconnect drivers ; 14 / 20,720 ( < 1 % ) ; +; R3 interconnects ; 200 / 130,992 ( < 1 % ) ; +; R6 interconnects ; 242 / 266,960 ( < 1 % ) ; +; Spine clocks ; 2 / 360 ( < 1 % ) ; +; Wire stub REs ; 0 / 15,858 ( 0 % ) ; ++---------------------------------------------+-------------------------+ + + ++------------------------------------------+ +; I/O Rules Summary ; ++----------------------------------+-------+ +; I/O Rules Statistic ; Total ; ++----------------------------------+-------+ +; Total I/O Rules ; 28 ; +; Number of I/O Rules Passed ; 6 ; +; Number of I/O Rules Failed ; 0 ; +; Number of I/O Rules Unchecked ; 0 ; +; Number of I/O Rules Inapplicable ; 22 ; ++----------------------------------+-------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; I/O Rules Details ; ++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+------+-------------------+ +; Status ; ID ; Category ; Rule Description ; Severity ; Information ; Area ; Extra Information ; ++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+------+-------------------+ +; Pass ; IO_000001 ; Capacity Checks ; Number of pins in an I/O bank should not exceed the number of locations available. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000002 ; Capacity Checks ; Number of clocks in an I/O bank should not exceed the number of clocks available. ; Critical ; No Global Signal assignments found. ; I/O ; ; +; Pass ; IO_000003 ; Capacity Checks ; Number of pins in a Vrefgroup should not exceed the number of locations available. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000004 ; Voltage Compatibility Checks ; The I/O bank should support the requested VCCIO. ; Critical ; No IOBANK_VCCIO assignments found. ; I/O ; ; +; Inapplicable ; IO_000005 ; Voltage Compatibility Checks ; The I/O bank should not have competing VREF values. ; Critical ; No VREF I/O Standard assignments found. ; I/O ; ; +; Pass ; IO_000006 ; Voltage Compatibility Checks ; The I/O bank should not have competing VCCIO values. ; Critical ; 0 such failures found. ; I/O ; ; +; Pass ; IO_000007 ; Valid Location Checks ; Checks for unavailable locations. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000008 ; Valid Location Checks ; Checks for reserved locations. ; Critical ; No reserved LogicLock region found. ; I/O ; ; +; Pass ; IO_000009 ; I/O Properties Checks for One I/O ; The location should support the requested I/O standard. ; Critical ; 0 such failures found. ; I/O ; ; +; Pass ; IO_000010 ; I/O Properties Checks for One I/O ; The location should support the requested I/O direction. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000011 ; I/O Properties Checks for One I/O ; The location should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ; +; Inapplicable ; IO_000012 ; I/O Properties Checks for One I/O ; The location should support the requested On Chip Termination value. ; Critical ; No Termination assignments found. ; I/O ; ; +; Inapplicable ; IO_000013 ; I/O Properties Checks for One I/O ; The location should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ; +; Inapplicable ; IO_000014 ; I/O Properties Checks for One I/O ; The location should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ; +; Inapplicable ; IO_000015 ; I/O Properties Checks for One I/O ; The location should support the requested PCI Clamp Diode. ; Critical ; No Clamping Diode assignments found. ; I/O ; ; +; Inapplicable ; IO_000018 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ; +; Inapplicable ; IO_000019 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested On Chip Termination value. ; Critical ; No Termination assignments found. ; I/O ; ; +; Inapplicable ; IO_000020 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested PCI Clamp Diode. ; Critical ; No Clamping Diode assignments found. ; I/O ; ; +; Inapplicable ; IO_000021 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ; +; Inapplicable ; IO_000022 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ; +; Inapplicable ; IO_000023 ; I/O Properties Checks for One I/O ; The I/O standard should support the Open Drain value. ; Critical ; No open drain assignments found. ; I/O ; ; +; Inapplicable ; IO_000024 ; I/O Properties Checks for One I/O ; The I/O direction should support the On Chip Termination value. ; Critical ; No Termination assignments found. ; I/O ; ; +; Inapplicable ; IO_000026 ; I/O Properties Checks for One I/O ; On Chip Termination and Current Strength should not be used at the same time. ; Critical ; No Current Strength or Termination assignments found. ; I/O ; ; +; Inapplicable ; IO_000027 ; I/O Properties Checks for One I/O ; Weak Pull Up and Bus Hold should not be used at the same time. ; Critical ; No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found. ; I/O ; ; +; Inapplicable ; IO_000045 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ; +; Inapplicable ; IO_000046 ; I/O Properties Checks for One I/O ; The location should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ; +; Inapplicable ; IO_000047 ; I/O Properties Checks for One I/O ; On Chip Termination and Slew Rate should not be used at the same time. ; Critical ; No Slew Rate assignments found. ; I/O ; ; +; Inapplicable ; IO_000034 ; SI Related Distance Checks ; Single-ended outputs should be 0 LAB row(s) away from a differential I/O. ; High ; No Differential I/O Standard assignments found. ; I/O ; ; ++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+------+-------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; I/O Rules Matrix ; ++--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+ +; Pin/Rules ; IO_000001 ; IO_000002 ; IO_000003 ; IO_000004 ; IO_000005 ; IO_000006 ; IO_000007 ; IO_000008 ; IO_000009 ; IO_000010 ; IO_000011 ; IO_000012 ; IO_000013 ; IO_000014 ; IO_000015 ; IO_000018 ; IO_000019 ; IO_000020 ; IO_000021 ; IO_000022 ; IO_000023 ; IO_000024 ; IO_000026 ; IO_000027 ; IO_000045 ; IO_000046 ; IO_000047 ; IO_000034 ; ++--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+ +; Total Pass ; 41 ; 0 ; 41 ; 0 ; 0 ; 41 ; 41 ; 0 ; 41 ; 41 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; Total Unchecked ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; Total Inapplicable ; 0 ; 41 ; 0 ; 41 ; 41 ; 0 ; 0 ; 41 ; 0 ; 0 ; 41 ; 41 ; 41 ; 41 ; 41 ; 41 ; 41 ; 41 ; 41 ; 41 ; 41 ; 41 ; 41 ; 41 ; 41 ; 41 ; 41 ; 41 ; +; Total Fail ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; SW[0] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; SW[1] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; SW[2] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; SW[3] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; SW[4] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; SW[5] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; SW[6] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; SW[7] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; SW[8] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; SW[9] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; HEX0[0] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; HEX0[1] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; HEX0[2] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; HEX0[3] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; HEX0[4] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; HEX0[5] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; HEX0[6] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; HEX1[0] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; HEX1[1] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; HEX1[2] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; HEX1[3] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; HEX1[4] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; HEX1[5] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; HEX1[6] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; HEX2[0] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; HEX2[1] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; HEX2[2] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; HEX2[3] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; HEX2[4] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; HEX2[5] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; HEX2[6] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; DAC_SDI ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; DAC_SCK ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; DAC_CS ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; DAC_LD ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; ADC_SDI ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; ADC_SCK ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; ADC_CS ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; PWM_OUT ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; CLOCK_50 ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; ADC_SDO ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; ++--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+ + + ++------------------------------------------------------------------------------------------------+ +; Fitter Device Options ; ++------------------------------------------------------------------+-----------------------------+ +; Option ; Setting ; ++------------------------------------------------------------------+-----------------------------+ +; Enable user-supplied start-up clock (CLKUSR) ; Off ; +; Enable device-wide reset (DEV_CLRn) ; Off ; +; Enable device-wide output enable (DEV_OE) ; Off ; +; Enable INIT_DONE output ; Off ; +; Configuration scheme ; Passive Serial ; +; Enable Error Detection CRC_ERROR pin ; Off ; +; Enable CvP_CONFDONE pin ; Off ; +; Enable open drain on CRC_ERROR pin ; On ; +; Enable open drain on CvP_CONFDONE pin ; On ; +; Enable open drain on INIT_DONE pin ; On ; +; Enable open drain on Partial Reconfiguration pins ; Off ; +; Enable open drain on nCEO pin ; On ; +; Enable Partial Reconfiguration pins ; Off ; +; Enable input tri-state on active configuration pins in user mode ; Off ; +; Enable internal scrubbing ; Off ; +; Active Serial clock source ; 100 MHz Internal Oscillator ; +; Device initialization clock source ; Internal Oscillator ; +; Configuration via Protocol ; Off ; +; Configuration Voltage Level ; Auto ; +; Force Configuration Voltage Level ; Off ; +; Enable nCEO output ; Off ; +; Data[15..8] ; Unreserved ; +; Data[7..5] ; Unreserved ; +; Base pin-out file on sameframe device ; Off ; ++------------------------------------------------------------------+-----------------------------+ + + ++------------------------------------+ +; Operating Settings and Conditions ; ++---------------------------+--------+ +; Setting ; Value ; ++---------------------------+--------+ +; Nominal Core Voltage ; 1.10 V ; +; Low Junction Temperature ; 0 °C ; +; High Junction Temperature ; 85 °C ; ++---------------------------+--------+ + + ++------------------------------------------------------------+ +; Estimated Delay Added for Hold Timing Summary ; ++-----------------+----------------------+-------------------+ +; Source Clock(s) ; Destination Clock(s) ; Delay Added in ns ; ++-----------------+----------------------+-------------------+ +; CLOCK_50 ; CLOCK_50 ; 52.7 ; ++-----------------+----------------------+-------------------+ +Note: For more information on problematic transfers, consider running the Fitter again with the Optimize hold timing option (Settings Menu) turned off. +This will disable optimization of problematic paths and expose them for further analysis using the TimeQuest Timing Analyzer. + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Estimated Delay Added for Hold Timing Details ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+ +; Source Register ; Destination Register ; Delay Added in ns ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+ +; pwm:PWM_DC|d[5] ; pwm:PWM_DC|pwm_out ; 0.490 ; +; pwm:PWM_DC|d[4] ; pwm:PWM_DC|pwm_out ; 0.490 ; +; pwm:PWM_DC|d[7] ; pwm:PWM_DC|pwm_out ; 0.490 ; +; pwm:PWM_DC|d[6] ; pwm:PWM_DC|pwm_out ; 0.490 ; +; pwm:PWM_DC|count[7] ; pwm:PWM_DC|pwm_out ; 0.490 ; +; pwm:PWM_DC|count[6] ; pwm:PWM_DC|pwm_out ; 0.490 ; +; pwm:PWM_DC|count[5] ; pwm:PWM_DC|pwm_out ; 0.490 ; +; pwm:PWM_DC|count[4] ; pwm:PWM_DC|pwm_out ; 0.490 ; +; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|cntr_1ib:rd_ptr_count|counter_reg_bit[0] ; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|altsyncram_44t1:FIFOram|ram_block1a8~portb_address_reg0 ; 0.402 ; +; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|cntr_1ib:rd_ptr_count|counter_reg_bit[1] ; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|altsyncram_44t1:FIFOram|ram_block1a8~portb_address_reg0 ; 0.391 ; +; spi2dac:SPI_DAC|state[0] ; spi2dac:SPI_DAC|shift_reg[14] ; 0.378 ; +; spi2adc:SPI_ADC|state[0] ; spi2adc:SPI_ADC|adc_din ; 0.358 ; +; spi2adc:SPI_ADC|ctr[2] ; spi2adc:SPI_ADC|clk_1MHz ; 0.354 ; +; spi2adc:SPI_ADC|state[1] ; spi2adc:SPI_ADC|adc_din ; 0.353 ; +; spi2adc:SPI_ADC|ctr[3] ; spi2adc:SPI_ADC|clk_1MHz ; 0.353 ; +; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|a_fefifo_4be:fifo_state|cntr_di7:count_usedw|counter_reg_bit[3] ; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|a_fefifo_4be:fifo_state|b_full ; 0.352 ; +; spi2dac:SPI_DAC|state[1] ; spi2dac:SPI_DAC|state[0] ; 0.351 ; +; spi2adc:SPI_ADC|shift_reg[4] ; spi2adc:SPI_ADC|shift_reg[5] ; 0.349 ; +; spi2adc:SPI_ADC|shift_reg[2] ; spi2adc:SPI_ADC|shift_reg[3] ; 0.346 ; +; spi2adc:SPI_ADC|ctr[0] ; spi2adc:SPI_ADC|ctr[4] ; 0.345 ; +; spi2adc:SPI_ADC|shift_reg[8] ; spi2adc:SPI_ADC|shift_reg[9] ; 0.343 ; +; spi2adc:SPI_ADC|shift_reg[0] ; spi2adc:SPI_ADC|shift_reg[1] ; 0.343 ; +; spi2dac:SPI_DAC|state[4] ; spi2dac:SPI_DAC|shift_reg[14] ; 0.338 ; +; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|cntr_1ib:wr_ptr|counter_reg_bit[1] ; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|altsyncram_44t1:FIFOram|ram_block1a9~porta_address_reg0 ; 0.337 ; +; spi2adc:SPI_ADC|shift_reg[5] ; spi2adc:SPI_ADC|shift_reg[6] ; 0.336 ; +; spi2adc:SPI_ADC|shift_reg[7] ; spi2adc:SPI_ADC|shift_reg[8] ; 0.331 ; +; spi2adc:SPI_ADC|shift_reg[3] ; spi2adc:SPI_ADC|shift_reg[4] ; 0.331 ; +; spi2adc:SPI_ADC|shift_reg[1] ; spi2adc:SPI_ADC|shift_reg[2] ; 0.331 ; +; spi2adc:SPI_ADC|ctr[4] ; spi2adc:SPI_ADC|ctr[2] ; 0.311 ; +; spi2adc:SPI_ADC|tick ; spi2adc:SPI_ADC|state[1] ; 0.310 ; +; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|cntr_1ib:wr_ptr|counter_reg_bit[0] ; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|altsyncram_44t1:FIFOram|ram_block1a9~porta_address_reg0 ; 0.307 ; +; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|cntr_1ib:wr_ptr|counter_reg_bit[10] ; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|altsyncram_44t1:FIFOram|ram_block1a5~porta_address_reg0 ; 0.304 ; +; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|cntr_1ib:wr_ptr|counter_reg_bit[12] ; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|altsyncram_44t1:FIFOram|ram_block1a5~porta_address_reg0 ; 0.297 ; +; spi2adc:SPI_ADC|adc_start ; spi2adc:SPI_ADC|adc_din ; 0.296 ; +; spi2dac:SPI_DAC|sr_state.WAIT_CSB_FALL ; spi2dac:SPI_DAC|shift_reg[12] ; 0.292 ; +; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|cntr_1ib:wr_ptr|counter_reg_bit[6] ; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|altsyncram_44t1:FIFOram|ram_block1a5~porta_address_reg0 ; 0.290 ; +; spi2adc:SPI_ADC|sr_state.IDLE ; spi2adc:SPI_ADC|sr_state.WAIT_CSB_FALL ; 0.289 ; +; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|cntr_1ib:wr_ptr|counter_reg_bit[9] ; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|altsyncram_44t1:FIFOram|ram_block1a5~porta_address_reg0 ; 0.288 ; +; spi2adc:SPI_ADC|state[2] ; spi2adc:SPI_ADC|shift_ena ; 0.288 ; +; spi2dac:SPI_DAC|sr_state.IDLE ; spi2dac:SPI_DAC|sr_state.WAIT_CSB_FALL ; 0.286 ; +; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|cntr_1ib:wr_ptr|counter_reg_bit[4] ; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|altsyncram_44t1:FIFOram|ram_block1a5~porta_address_reg0 ; 0.286 ; +; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|cntr_1ib:wr_ptr|counter_reg_bit[3] ; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|altsyncram_44t1:FIFOram|ram_block1a5~porta_address_reg0 ; 0.285 ; +; spi2adc:SPI_ADC|adc_cs ; spi2adc:SPI_ADC|sr_state.IDLE ; 0.281 ; +; spi2dac:SPI_DAC|state[3] ; spi2dac:SPI_DAC|shift_reg[14] ; 0.280 ; +; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|cntr_1ib:wr_ptr|counter_reg_bit[2] ; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|altsyncram_44t1:FIFOram|ram_block1a5~porta_address_reg0 ; 0.278 ; +; spi2dac:SPI_DAC|shift_reg[13] ; spi2dac:SPI_DAC|shift_reg[14] ; 0.275 ; +; spi2adc:SPI_ADC|shift_reg[6] ; spi2adc:SPI_ADC|shift_reg[7] ; 0.275 ; +; spi2adc:SPI_ADC|ctr[1] ; spi2adc:SPI_ADC|ctr[3] ; 0.273 ; +; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|cntr_1ib:wr_ptr|counter_reg_bit[11] ; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|altsyncram_44t1:FIFOram|ram_block1a5~porta_address_reg0 ; 0.271 ; +; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|cntr_1ib:wr_ptr|counter_reg_bit[5] ; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|altsyncram_44t1:FIFOram|ram_block1a5~porta_address_reg0 ; 0.271 ; +; processor:ALLPASS|pulse_gen:PULSE0|pulse ; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|altsyncram_44t1:FIFOram|ram_block1a9~porta_we_reg ; 0.270 ; +; spi2dac:SPI_DAC|shift_reg[11] ; spi2dac:SPI_DAC|shift_reg[12] ; 0.267 ; +; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|cntr_1ib:wr_ptr|counter_reg_bit[8] ; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|altsyncram_44t1:FIFOram|ram_block1a5~porta_address_reg0 ; 0.266 ; +; spi2dac:SPI_DAC|sr_state.WAIT_CSB_HIGH ; spi2dac:SPI_DAC|sr_state.WAIT_CSB_FALL ; 0.264 ; +; spi2adc:SPI_ADC|state[3] ; spi2adc:SPI_ADC|shift_ena ; 0.264 ; +; spi2dac:SPI_DAC|shift_reg[12] ; spi2dac:SPI_DAC|shift_reg[13] ; 0.260 ; +; spi2adc:SPI_ADC|state[4] ; spi2adc:SPI_ADC|adc_din ; 0.259 ; +; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|cntr_1ib:wr_ptr|counter_reg_bit[7] ; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|altsyncram_44t1:FIFOram|ram_block1a5~porta_address_reg0 ; 0.258 ; +; spi2adc:SPI_ADC|sr_state.WAIT_CSB_FALL ; spi2adc:SPI_ADC|adc_start ; 0.245 ; +; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|a_fefifo_4be:fifo_state|cntr_di7:count_usedw|counter_reg_bit[12] ; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|a_fefifo_4be:fifo_state|b_full ; 0.218 ; +; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|a_fefifo_4be:fifo_state|cntr_di7:count_usedw|counter_reg_bit[11] ; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|a_fefifo_4be:fifo_state|b_full ; 0.218 ; +; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|a_fefifo_4be:fifo_state|cntr_di7:count_usedw|counter_reg_bit[10] ; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|a_fefifo_4be:fifo_state|b_full ; 0.218 ; +; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|a_fefifo_4be:fifo_state|cntr_di7:count_usedw|counter_reg_bit[9] ; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|a_fefifo_4be:fifo_state|b_full ; 0.218 ; +; processor:ALLPASS|full_reg ; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|a_fefifo_4be:fifo_state|b_full ; 0.218 ; +; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|a_fefifo_4be:fifo_state|cntr_di7:count_usedw|counter_reg_bit[2] ; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|a_fefifo_4be:fifo_state|b_full ; 0.182 ; +; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|a_fefifo_4be:fifo_state|cntr_di7:count_usedw|counter_reg_bit[1] ; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|a_fefifo_4be:fifo_state|b_full ; 0.182 ; +; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|a_fefifo_4be:fifo_state|cntr_di7:count_usedw|counter_reg_bit[0] ; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|a_fefifo_4be:fifo_state|b_full ; 0.182 ; +; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|cntr_1ib:rd_ptr_count|counter_reg_bit[11] ; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|altsyncram_44t1:FIFOram|ram_block1a8~portb_address_reg0 ; 0.174 ; +; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|cntr_1ib:rd_ptr_count|counter_reg_bit[10] ; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|altsyncram_44t1:FIFOram|ram_block1a8~portb_address_reg0 ; 0.174 ; +; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|cntr_1ib:rd_ptr_count|counter_reg_bit[9] ; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|altsyncram_44t1:FIFOram|ram_block1a8~portb_address_reg0 ; 0.166 ; +; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|cntr_1ib:rd_ptr_count|counter_reg_bit[8] ; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|altsyncram_44t1:FIFOram|ram_block1a8~portb_address_reg0 ; 0.166 ; +; spi2adc:SPI_ADC|sr_state.WAIT_CSB_HIGH ; spi2adc:SPI_ADC|sr_state.IDLE ; 0.164 ; +; processor:ALLPASS|data_out[6] ; spi2dac:SPI_DAC|shift_reg[8] ; 0.164 ; +; processor:ALLPASS|data_out[4] ; spi2dac:SPI_DAC|shift_reg[6] ; 0.164 ; +; processor:ALLPASS|data_out[3] ; spi2dac:SPI_DAC|shift_reg[5] ; 0.164 ; +; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|cntr_1ib:rd_ptr_count|counter_reg_bit[5] ; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|altsyncram_44t1:FIFOram|ram_block1a8~portb_address_reg0 ; 0.163 ; +; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|cntr_1ib:rd_ptr_count|counter_reg_bit[4] ; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|altsyncram_44t1:FIFOram|ram_block1a8~portb_address_reg0 ; 0.163 ; +; processor:ALLPASS|data_out[8] ; spi2dac:SPI_DAC|shift_reg[10] ; 0.158 ; +; processor:ALLPASS|data_out[5] ; spi2dac:SPI_DAC|shift_reg[7] ; 0.158 ; +; processor:ALLPASS|data_out[2] ; spi2dac:SPI_DAC|shift_reg[4] ; 0.158 ; +; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|cntr_1ib:rd_ptr_count|counter_reg_bit[3] ; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|altsyncram_44t1:FIFOram|ram_block1a8~portb_address_reg0 ; 0.153 ; +; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|cntr_1ib:rd_ptr_count|counter_reg_bit[2] ; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|altsyncram_44t1:FIFOram|ram_block1a8~portb_address_reg0 ; 0.153 ; +; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|cntr_1ib:rd_ptr_count|counter_reg_bit[7] ; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|altsyncram_44t1:FIFOram|ram_block1a8~portb_address_reg0 ; 0.148 ; +; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|cntr_1ib:rd_ptr_count|counter_reg_bit[6] ; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|altsyncram_44t1:FIFOram|ram_block1a8~portb_address_reg0 ; 0.148 ; +; spi2dac:SPI_DAC|state[2] ; spi2dac:SPI_DAC|state[0] ; 0.143 ; +; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|cntr_1ib:rd_ptr_count|counter_reg_bit[12] ; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|altsyncram_44t1:FIFOram|ram_block1a8~portb_address_reg0 ; 0.143 ; +; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|a_fefifo_4be:fifo_state|b_full ; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|altsyncram_44t1:FIFOram|ram_block1a9~porta_we_reg ; 0.120 ; +; pwm:PWM_DC|d[9] ; pwm:PWM_DC|pwm_out ; 0.094 ; +; pwm:PWM_DC|d[8] ; pwm:PWM_DC|pwm_out ; 0.094 ; +; pwm:PWM_DC|count[9] ; pwm:PWM_DC|pwm_out ; 0.094 ; +; pwm:PWM_DC|count[8] ; pwm:PWM_DC|pwm_out ; 0.094 ; +; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|a_fefifo_4be:fifo_state|cntr_di7:count_usedw|counter_reg_bit[8] ; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|a_fefifo_4be:fifo_state|b_full ; 0.078 ; +; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|a_fefifo_4be:fifo_state|cntr_di7:count_usedw|counter_reg_bit[7] ; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|a_fefifo_4be:fifo_state|b_full ; 0.078 ; +; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|a_fefifo_4be:fifo_state|cntr_di7:count_usedw|counter_reg_bit[6] ; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|a_fefifo_4be:fifo_state|b_full ; 0.078 ; +; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|a_fefifo_4be:fifo_state|cntr_di7:count_usedw|counter_reg_bit[5] ; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|a_fefifo_4be:fifo_state|b_full ; 0.078 ; +; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|a_fefifo_4be:fifo_state|cntr_di7:count_usedw|counter_reg_bit[4] ; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|a_fefifo_4be:fifo_state|b_full ; 0.078 ; +; processor:ALLPASS|data_out[9] ; spi2dac:SPI_DAC|shift_reg[11] ; 0.059 ; +; pwm:PWM_DC|d[3] ; pwm:PWM_DC|pwm_out ; 0.039 ; +; pwm:PWM_DC|d[2] ; pwm:PWM_DC|pwm_out ; 0.039 ; +; pwm:PWM_DC|d[1] ; pwm:PWM_DC|pwm_out ; 0.039 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+ +Note: This table only shows the top 100 path(s) that have the largest delay added for hold. + + ++-----------------+ +; Fitter Messages ; ++-----------------+ +Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. +Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected +Info (119006): Selected device 5CSEMA5F31C6 for design "ex17_top" +Info (21077): Low junction temperature is 0 degrees C +Info (21077): High junction temperature is 85 degrees C +Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time +Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature. +Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details +Info (176045): Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements. +Info (184020): Starting Fitter periphery placement operations +Info (11191): Automatically promoted 1 clock (1 global) + Info (11162): CLOCK_50~inputCLKENA0 with 171 fanout uses global clock CLKCTRL_G6 +Info (184021): Fitter periphery placement operations ending: elapsed time is 00:00:00 +Info (176233): Starting register packing +Info (332104): Reading SDC File: 'ex17_top.sdc' +Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty" +Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. +Info (332129): Detected timing requirements -- optimizing circuit to achieve only the specified requirements +Info (332111): Found 1 clocks + Info (332111): Period Clock Name + Info (332111): ======== ============ + Info (332111): 20.000 CLOCK_50 +Info (176235): Finished register packing + Extra Info (176219): No registers were packed into other blocks +Warning (15705): Ignored locations or region assignments to the following nodes + Warning (15706): Node "HEX3[0]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HEX3[1]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HEX3[2]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HEX3[3]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HEX3[4]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HEX3[5]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HEX3[6]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HEX4[0]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HEX4[1]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HEX4[2]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HEX4[3]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HEX4[4]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HEX4[5]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HEX4[6]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HEX5[0]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HEX5[1]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HEX5[2]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HEX5[3]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HEX5[4]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HEX5[5]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HEX5[6]" is assigned to location or region, but does not exist in design + Warning (15706): Node "KEY[0]" is assigned to location or region, but does not exist in design + Warning (15706): Node "KEY[1]" is assigned to location or region, but does not exist in design + Warning (15706): Node "KEY[2]" is assigned to location or region, but does not exist in design + Warning (15706): Node "KEY[3]" is assigned to location or region, but does not exist in design + Warning (15706): Node "LEDR[0]" is assigned to location or region, but does not exist in design + Warning (15706): Node "LEDR[1]" is assigned to location or region, but does not exist in design + Warning (15706): Node "LEDR[2]" is assigned to location or region, but does not exist in design + Warning (15706): Node "LEDR[3]" is assigned to location or region, but does not exist in design + Warning (15706): Node "LEDR[4]" is assigned to location or region, but does not exist in design + Warning (15706): Node "LEDR[5]" is assigned to location or region, but does not exist in design + Warning (15706): Node "LEDR[6]" is assigned to location or region, but does not exist in design + Warning (15706): Node "LEDR[7]" is assigned to location or region, but does not exist in design + Warning (15706): Node "LEDR[8]" is assigned to location or region, but does not exist in design + Warning (15706): Node "LEDR[9]" is assigned to location or region, but does not exist in design + Warning (15706): Node "OLED_CLK" is assigned to location or region, but does not exist in design + Warning (15706): Node "OLED_CS" is assigned to location or region, but does not exist in design + Warning (15706): Node "OLED_DATA" is assigned to location or region, but does not exist in design + Warning (15706): Node "OLED_DC" is assigned to location or region, but does not exist in design + Warning (15706): Node "OLED_RST" is assigned to location or region, but does not exist in design +Info (11798): Fitter preparation operations ending: elapsed time is 00:00:51 +Info (170189): Fitter placement preparation operations beginning +Info (14951): The Fitter is using Advanced Physical Optimization. +Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:09 +Info (170191): Fitter placement operations beginning +Info (170137): Fitter placement was successful +Info (170192): Fitter placement operations ending: elapsed time is 00:00:02 +Info (170193): Fitter routing operations beginning +Info (170195): Router estimated average interconnect usage is 0% of the available device resources + Info (170196): Router estimated peak interconnect usage is 4% of the available device resources in the region that extends from location X67_Y0 to location X77_Y10 +Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time. + Info (170201): Optimizations that may affect the design's routability were skipped + Info (170200): Optimizations that may affect the design's timing were skipped +Info (170194): Fitter routing operations ending: elapsed time is 00:00:08 +Info (11888): Total time spent on timing analysis during the Fitter is 6.35 seconds. +Info (334003): Started post-fitting delay annotation +Info (334004): Delay annotation completed successfully +Info (334003): Started post-fitting delay annotation +Info (334004): Delay annotation completed successfully +Info (11801): Fitter post-fit operations ending: elapsed time is 00:00:19 +Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information. +Info (144001): Generated suppressed messages file H:/Year 2/VERI/part_4/ex17/output_files/ex17_top.fit.smsg +Info: Quartus Prime Fitter was successful. 0 errors, 45 warnings + Info: Peak virtual memory: 2177 megabytes + Info: Processing ended: Sat Dec 10 18:48:37 2016 + Info: Elapsed time: 00:03:34 + Info: Total CPU time (on all processors): 00:02:08 + + ++----------------------------+ +; Fitter Suppressed Messages ; ++----------------------------+ +The suppressed messages can be found in H:/Year 2/VERI/part_4/ex17/output_files/ex17_top.fit.smsg. + + diff --git a/part_4/ex17/output_files/ex17_top.flow.rpt b/part_4/ex17/output_files/ex17_top.flow.rpt new file mode 100644 index 0000000..869e609 --- /dev/null +++ b/part_4/ex17/output_files/ex17_top.flow.rpt @@ -0,0 +1,129 @@ +Flow report for ex17_top +Sat Dec 10 18:51:59 2016 +Quartus Prime Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Flow Summary + 3. Flow Settings + 4. Flow Non-Default Global Settings + 5. Flow Elapsed Time + 6. Flow OS Summary + 7. Flow Log + 8. Flow Messages + 9. Flow Suppressed Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2016 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel MegaCore Function License Agreement, or other +applicable license agreement, including, without limitation, +that your use is for the sole purpose of programming logic +devices manufactured by Intel and sold by Intel or its +authorized distributors. Please refer to the applicable +agreement for further details. + + + ++-------------------------------------------------------------------------------+ +; Flow Summary ; ++---------------------------------+---------------------------------------------+ +; Flow Status ; Successful - Sat Dec 10 18:50:31 2016 ; +; Quartus Prime Version ; 16.1.0 Build 196 10/24/2016 SJ Lite Edition ; +; Revision Name ; ex17_top ; +; Top-level Entity Name ; ex17_top ; +; Family ; Cyclone V ; +; Device ; 5CSEMA5F31C6 ; +; Timing Models ; Final ; +; Logic utilization (in ALMs) ; 94 / 32,070 ( < 1 % ) ; +; Total registers ; 179 ; +; Total pins ; 41 / 457 ( 9 % ) ; +; Total virtual pins ; 0 ; +; Total block memory bits ; 73,728 / 4,065,280 ( 2 % ) ; +; Total DSP Blocks ; 0 / 87 ( 0 % ) ; +; Total HSSI RX PCSs ; 0 ; +; Total HSSI PMA RX Deserializers ; 0 ; +; Total HSSI TX PCSs ; 0 ; +; Total HSSI PMA TX Serializers ; 0 ; +; Total PLLs ; 0 / 6 ( 0 % ) ; +; Total DLLs ; 0 / 4 ( 0 % ) ; ++---------------------------------+---------------------------------------------+ + + ++-----------------------------------------+ +; Flow Settings ; ++-------------------+---------------------+ +; Option ; Setting ; ++-------------------+---------------------+ +; Start date & time ; 12/10/2016 18:43:47 ; +; Main task ; Compilation ; +; Revision Name ; ex17_top ; ++-------------------+---------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------+ +; Flow Non-Default Global Settings ; ++-------------------------------------+----------------------------------------+---------------+-------------+------------+ +; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ; ++-------------------------------------+----------------------------------------+---------------+-------------+------------+ +; COMPILER_SIGNATURE_ID ; 147774608559.148139542301876 ; -- ; -- ; -- ; +; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ; +; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ; +; MISC_FILE ; FIFO_bb.v ; -- ; -- ; -- ; +; PARTITION_COLOR ; -- (Not supported for targeted family) ; -- ; -- ; Top ; +; PARTITION_FITTER_PRESERVATION_LEVEL ; -- (Not supported for targeted family) ; -- ; -- ; Top ; +; PARTITION_NETLIST_TYPE ; -- (Not supported for targeted family) ; -- ; -- ; Top ; +; POWER_BOARD_THERMAL_MODEL ; None (CONSERVATIVE) ; -- ; -- ; -- ; +; POWER_PRESET_COOLING_SOLUTION ; 23 MM HEAT SINK WITH 200 LFPM AIRFLOW ; -- ; -- ; -- ; +; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ; ++-------------------------------------+----------------------------------------+---------------+-------------+------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------+ +; Flow Elapsed Time ; ++---------------------------+--------------+-------------------------+---------------------+------------------------------------+ +; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; ++---------------------------+--------------+-------------------------+---------------------+------------------------------------+ +; Analysis & Synthesis ; 00:00:54 ; 1.0 ; 704 MB ; 00:00:40 ; +; Fitter ; 00:03:06 ; 1.0 ; 2177 MB ; 00:02:06 ; +; Assembler ; 00:01:05 ; 1.0 ; 715 MB ; 00:00:14 ; +; TimeQuest Timing Analyzer ; 00:01:16 ; 1.0 ; 1033 MB ; 00:00:13 ; +; Total ; 00:06:21 ; -- ; -- ; 00:03:13 ; ++---------------------------+--------------+-------------------------+---------------------+------------------------------------+ + + ++-----------------------------------------------------------------------------------------+ +; Flow OS Summary ; ++---------------------------+------------------+------------+------------+----------------+ +; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ; ++---------------------------+------------------+------------+------------+----------------+ +; Analysis & Synthesis ; Xav-Laptop ; Windows 10 ; 10.0 ; x86_64 ; +; Fitter ; Xav-Laptop ; Windows 10 ; 10.0 ; x86_64 ; +; Assembler ; Xav-Laptop ; Windows 10 ; 10.0 ; x86_64 ; +; TimeQuest Timing Analyzer ; Xav-Laptop ; Windows 10 ; 10.0 ; x86_64 ; ++---------------------------+------------------+------------+------------+----------------+ + + +------------ +; Flow Log ; +------------ +quartus_map --read_settings_files=on --write_settings_files=off ex17 -c ex17_top +quartus_fit --read_settings_files=off --write_settings_files=off ex17 -c ex17_top +quartus_asm --read_settings_files=off --write_settings_files=off ex17 -c ex17_top +quartus_sta ex17 -c ex17_top + + + diff --git a/part_4/ex17/output_files/ex17_top.map.rpt b/part_4/ex17/output_files/ex17_top.map.rpt new file mode 100644 index 0000000..d309653 --- /dev/null +++ b/part_4/ex17/output_files/ex17_top.map.rpt @@ -0,0 +1,714 @@ +Analysis & Synthesis report for ex17_top +Sat Dec 10 18:44:45 2016 +Quartus Prime Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Analysis & Synthesis Summary + 3. Analysis & Synthesis Settings + 4. Parallel Compilation + 5. Analysis & Synthesis Source Files Read + 6. Analysis & Synthesis Resource Usage Summary + 7. Analysis & Synthesis Resource Utilization by Entity + 8. Analysis & Synthesis RAM Summary + 9. Analysis & Synthesis IP Cores Summary + 10. State Machine - |ex17_top|processor:ALLPASS|pulse_gen:PULSE0|state + 11. State Machine - |ex17_top|spi2adc:SPI_ADC|sr_state + 12. State Machine - |ex17_top|spi2dac:SPI_DAC|sr_state + 13. Registers Removed During Synthesis + 14. Removed Registers Triggering Further Register Optimizations + 15. General Register Statistics + 16. Inverted Register Statistics + 17. Multiplexer Restructuring Statistics (Restructuring Performed) + 18. Source assignments for processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|altsyncram_44t1:FIFOram + 19. Parameter Settings for User Entity Instance: clktick_16:GEN_10K + 20. Parameter Settings for User Entity Instance: spi2dac:SPI_DAC + 21. Parameter Settings for User Entity Instance: spi2adc:SPI_ADC + 22. Parameter Settings for User Entity Instance: processor:ALLPASS + 23. Parameter Settings for User Entity Instance: processor:ALLPASS|pulse_gen:PULSE0 + 24. Parameter Settings for User Entity Instance: processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component + 25. scfifo Parameter Settings by Entity Instance + 26. Port Connectivity Checks: "hex_to_7seg:SEG2" + 27. Port Connectivity Checks: "processor:ALLPASS|FIFO:DELAY1024" + 28. Port Connectivity Checks: "spi2adc:SPI_ADC" + 29. Port Connectivity Checks: "clktick_16:GEN_10K" + 30. Post-Synthesis Netlist Statistics for Top Partition + 31. Elapsed Time Per Partition + 32. Analysis & Synthesis Messages + 33. Analysis & Synthesis Suppressed Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2016 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel MegaCore Function License Agreement, or other +applicable license agreement, including, without limitation, +that your use is for the sole purpose of programming logic +devices manufactured by Intel and sold by Intel or its +authorized distributors. Please refer to the applicable +agreement for further details. + + + ++-------------------------------------------------------------------------------+ +; Analysis & Synthesis Summary ; ++---------------------------------+---------------------------------------------+ +; Analysis & Synthesis Status ; Successful - Sat Dec 10 18:44:44 2016 ; +; Quartus Prime Version ; 16.1.0 Build 196 10/24/2016 SJ Lite Edition ; +; Revision Name ; ex17_top ; +; Top-level Entity Name ; ex17_top ; +; Family ; Cyclone V ; +; Logic utilization (in ALMs) ; N/A ; +; Total registers ; 153 ; +; Total pins ; 41 ; +; Total virtual pins ; 0 ; +; Total block memory bits ; 73,728 ; +; Total DSP Blocks ; 0 ; +; Total HSSI RX PCSs ; 0 ; +; Total HSSI PMA RX Deserializers ; 0 ; +; Total HSSI TX PCSs ; 0 ; +; Total HSSI PMA TX Serializers ; 0 ; +; Total PLLs ; 0 ; +; Total DLLs ; 0 ; ++---------------------------------+---------------------------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Settings ; ++---------------------------------------------------------------------------------+--------------------+--------------------+ +; Option ; Setting ; Default Value ; ++---------------------------------------------------------------------------------+--------------------+--------------------+ +; Device ; 5CSEMA5F31C6 ; ; +; Top-level entity name ; ex17_top ; ex17_top ; +; Family name ; Cyclone V ; Cyclone V ; +; Use smart compilation ; Off ; Off ; +; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ; +; Enable compact report table ; Off ; Off ; +; Restructure Multiplexers ; Auto ; Auto ; +; MLAB Add Timing Constraints For Mixed-Port Feed-Through Mode Setting Don't Care ; Off ; Off ; +; Create Debugging Nodes for IP Cores ; Off ; Off ; +; Preserve fewer node names ; On ; On ; +; OpenCore Plus hardware evaluation ; Enable ; Enable ; +; Verilog Version ; Verilog_2001 ; Verilog_2001 ; +; VHDL Version ; VHDL_1993 ; VHDL_1993 ; +; State Machine Processing ; Auto ; Auto ; +; Safe State Machine ; Off ; Off ; +; Extract Verilog State Machines ; On ; On ; +; Extract VHDL State Machines ; On ; On ; +; Ignore Verilog initial constructs ; Off ; Off ; +; Iteration limit for constant Verilog loops ; 5000 ; 5000 ; +; Iteration limit for non-constant Verilog loops ; 250 ; 250 ; +; Add Pass-Through Logic to Inferred RAMs ; On ; On ; +; Infer RAMs from Raw Logic ; On ; On ; +; Parallel Synthesis ; On ; On ; +; DSP Block Balancing ; Auto ; Auto ; +; NOT Gate Push-Back ; On ; On ; +; Power-Up Don't Care ; On ; On ; +; Remove Redundant Logic Cells ; Off ; Off ; +; Remove Duplicate Registers ; On ; On ; +; Ignore CARRY Buffers ; Off ; Off ; +; Ignore CASCADE Buffers ; Off ; Off ; +; Ignore GLOBAL Buffers ; Off ; Off ; +; Ignore ROW GLOBAL Buffers ; Off ; Off ; +; Ignore LCELL Buffers ; Off ; Off ; +; Ignore SOFT Buffers ; On ; On ; +; Limit AHDL Integers to 32 Bits ; Off ; Off ; +; Optimization Technique ; Balanced ; Balanced ; +; Carry Chain Length ; 70 ; 70 ; +; Auto Carry Chains ; On ; On ; +; Auto Open-Drain Pins ; On ; On ; +; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ; +; Auto ROM Replacement ; On ; On ; +; Auto RAM Replacement ; On ; On ; +; Auto DSP Block Replacement ; On ; On ; +; Auto Shift Register Replacement ; Auto ; Auto ; +; Allow Shift Register Merging across Hierarchies ; Auto ; Auto ; +; Auto Clock Enable Replacement ; On ; On ; +; Strict RAM Replacement ; Off ; Off ; +; Allow Synchronous Control Signals ; On ; On ; +; Force Use of Synchronous Clear Signals ; Off ; Off ; +; Auto Resource Sharing ; Off ; Off ; +; Allow Any RAM Size For Recognition ; Off ; Off ; +; Allow Any ROM Size For Recognition ; Off ; Off ; +; Allow Any Shift Register Size For Recognition ; Off ; Off ; +; Use LogicLock Constraints during Resource Balancing ; On ; On ; +; Ignore translate_off and synthesis_off directives ; Off ; Off ; +; Timing-Driven Synthesis ; On ; On ; +; Report Parameter Settings ; On ; On ; +; Report Source Assignments ; On ; On ; +; Report Connectivity Checks ; On ; On ; +; Ignore Maximum Fan-Out Assignments ; Off ; Off ; +; Synchronization Register Chain Length ; 3 ; 3 ; +; PowerPlay Power Optimization During Synthesis ; Normal compilation ; Normal compilation ; +; HDL message level ; Level2 ; Level2 ; +; Suppress Register Optimization Related Messages ; Off ; Off ; +; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ; +; Number of Swept Nodes Reported in Synthesis Report ; 5000 ; 5000 ; +; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ; +; Clock MUX Protection ; On ; On ; +; Auto Gated Clock Conversion ; Off ; Off ; +; Block Design Naming ; Auto ; Auto ; +; SDC constraint protection ; Off ; Off ; +; Synthesis Effort ; Auto ; Auto ; +; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ; +; Pre-Mapping Resynthesis Optimization ; Off ; Off ; +; Analysis & Synthesis Message Level ; Medium ; Medium ; +; Disable Register Merging Across Hierarchies ; Auto ; Auto ; +; Resource Aware Inference For Block RAM ; On ; On ; +; Automatic Parallel Synthesis ; On ; On ; +; Partial Reconfiguration Bitstream ID ; Off ; Off ; ++---------------------------------------------------------------------------------+--------------------+--------------------+ + + ++------------------------------------------+ +; Parallel Compilation ; ++----------------------------+-------------+ +; Processors ; Number ; ++----------------------------+-------------+ +; Number detected on machine ; 2 ; +; Maximum allowed ; 2 ; +; ; ; +; Average used ; 1.00 ; +; Maximum used ; 2 ; +; ; ; +; Usage by Processor ; % Time Used ; +; Processor 1 ; 100.0% ; +; Processor 2 ; 0.0% ; ++----------------------------+-------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Source Files Read ; ++----------------------------------+-----------------+------------------------------+-----------------------------------------------------------------------+---------+ +; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ; ++----------------------------------+-----------------+------------------------------+-----------------------------------------------------------------------+---------+ +; single_echo.v ; yes ; User Verilog HDL File ; H:/Year 2/VERI/part_4/ex17/single_echo.v ; ; +; ex17_top.v ; yes ; User Verilog HDL File ; H:/Year 2/VERI/part_4/ex17/ex17_top.v ; ; +; ../mylib/spi2dac.v ; yes ; User Verilog HDL File ; H:/Year 2/VERI/part_4/mylib/spi2dac.v ; ; +; ../mylib/spi2adc.v ; yes ; User Verilog HDL File ; H:/Year 2/VERI/part_4/mylib/spi2adc.v ; ; +; ../mylib/pwm.v ; yes ; User Verilog HDL File ; H:/Year 2/VERI/part_4/mylib/pwm.v ; ; +; ../mylib/pulse_gen.v ; yes ; User Verilog HDL File ; H:/Year 2/VERI/part_4/mylib/pulse_gen.v ; ; +; ../mylib/hex_to_7seg.v ; yes ; User Verilog HDL File ; H:/Year 2/VERI/part_4/mylib/hex_to_7seg.v ; ; +; ../mylib/clktick_16.v ; yes ; User Verilog HDL File ; H:/Year 2/VERI/part_4/mylib/clktick_16.v ; ; +; FIFO.v ; yes ; User Wizard-Generated File ; H:/Year 2/VERI/part_4/ex17/FIFO.v ; ; +; scfifo.tdf ; yes ; Megafunction ; c:/intelfpga_lite/16.1/quartus/libraries/megafunctions/scfifo.tdf ; ; +; a_regfifo.inc ; yes ; Megafunction ; c:/intelfpga_lite/16.1/quartus/libraries/megafunctions/a_regfifo.inc ; ; +; a_dpfifo.inc ; yes ; Megafunction ; c:/intelfpga_lite/16.1/quartus/libraries/megafunctions/a_dpfifo.inc ; ; +; a_i2fifo.inc ; yes ; Megafunction ; c:/intelfpga_lite/16.1/quartus/libraries/megafunctions/a_i2fifo.inc ; ; +; a_fffifo.inc ; yes ; Megafunction ; c:/intelfpga_lite/16.1/quartus/libraries/megafunctions/a_fffifo.inc ; ; +; a_f2fifo.inc ; yes ; Megafunction ; c:/intelfpga_lite/16.1/quartus/libraries/megafunctions/a_f2fifo.inc ; ; +; aglobal161.inc ; yes ; Megafunction ; c:/intelfpga_lite/16.1/quartus/libraries/megafunctions/aglobal161.inc ; ; +; db/scfifo_j791.tdf ; yes ; Auto-Generated Megafunction ; H:/Year 2/VERI/part_4/ex17/db/scfifo_j791.tdf ; ; +; db/a_dpfifo_qd91.tdf ; yes ; Auto-Generated Megafunction ; H:/Year 2/VERI/part_4/ex17/db/a_dpfifo_qd91.tdf ; ; +; db/a_fefifo_4be.tdf ; yes ; Auto-Generated Megafunction ; H:/Year 2/VERI/part_4/ex17/db/a_fefifo_4be.tdf ; ; +; db/cntr_di7.tdf ; yes ; Auto-Generated Megafunction ; H:/Year 2/VERI/part_4/ex17/db/cntr_di7.tdf ; ; +; db/altsyncram_44t1.tdf ; yes ; Auto-Generated Megafunction ; H:/Year 2/VERI/part_4/ex17/db/altsyncram_44t1.tdf ; ; +; db/cntr_1ib.tdf ; yes ; Auto-Generated Megafunction ; H:/Year 2/VERI/part_4/ex17/db/cntr_1ib.tdf ; ; ++----------------------------------+-----------------+------------------------------+-----------------------------------------------------------------------+---------+ + + ++--------------------------------------------------------------+ +; Analysis & Synthesis Resource Usage Summary ; ++---------------------------------------------+----------------+ +; Resource ; Usage ; ++---------------------------------------------+----------------+ +; Estimate of Logic utilization (ALMs needed) ; 96 ; +; ; ; +; Combinational ALUT usage for logic ; 165 ; +; -- 7 input functions ; 0 ; +; -- 6 input functions ; 10 ; +; -- 5 input functions ; 23 ; +; -- 4 input functions ; 31 ; +; -- <=3 input functions ; 101 ; +; ; ; +; Dedicated logic registers ; 153 ; +; ; ; +; I/O pins ; 41 ; +; Total MLAB memory bits ; 0 ; +; Total block memory bits ; 73728 ; +; ; ; +; Total DSP Blocks ; 0 ; +; ; ; +; Maximum fan-out node ; CLOCK_50~input ; +; Maximum fan-out ; 162 ; +; Total fan-out ; 1285 ; +; Average fan-out ; 3.14 ; ++---------------------------------------------+----------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Resource Utilization by Entity ; ++---------------------------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------+--------------+ +; Compilation Hierarchy Node ; Combinational ALUTs ; Dedicated Logic Registers ; Block Memory Bits ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name ; Entity Name ; Library Name ; ++---------------------------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------+--------------+ +; |ex17_top ; 165 (0) ; 153 (0) ; 73728 ; 0 ; 41 ; 0 ; |ex17_top ; ex17_top ; work ; +; |clktick_16:GEN_10K| ; 20 (20) ; 17 (17) ; 0 ; 0 ; 0 ; 0 ; |ex17_top|clktick_16:GEN_10K ; clktick_16 ; work ; +; |hex_to_7seg:SEG0| ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex17_top|hex_to_7seg:SEG0 ; hex_to_7seg ; work ; +; |hex_to_7seg:SEG1| ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex17_top|hex_to_7seg:SEG1 ; hex_to_7seg ; work ; +; |hex_to_7seg:SEG2| ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex17_top|hex_to_7seg:SEG2 ; hex_to_7seg ; work ; +; |processor:ALLPASS| ; 69 (22) ; 53 (11) ; 73728 ; 0 ; 0 ; 0 ; |ex17_top|processor:ALLPASS ; processor ; work ; +; |FIFO:DELAY1024| ; 45 (0) ; 40 (0) ; 73728 ; 0 ; 0 ; 0 ; |ex17_top|processor:ALLPASS|FIFO:DELAY1024 ; FIFO ; work ; +; |scfifo:scfifo_component| ; 45 (0) ; 40 (0) ; 73728 ; 0 ; 0 ; 0 ; |ex17_top|processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component ; scfifo ; work ; +; |scfifo_j791:auto_generated| ; 45 (0) ; 40 (0) ; 73728 ; 0 ; 0 ; 0 ; |ex17_top|processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated ; scfifo_j791 ; work ; +; |a_dpfifo_qd91:dpfifo| ; 45 (1) ; 40 (0) ; 73728 ; 0 ; 0 ; 0 ; |ex17_top|processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo ; a_dpfifo_qd91 ; work ; +; |a_fefifo_4be:fifo_state| ; 18 (5) ; 14 (1) ; 0 ; 0 ; 0 ; 0 ; |ex17_top|processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|a_fefifo_4be:fifo_state ; a_fefifo_4be ; work ; +; |cntr_di7:count_usedw| ; 13 (13) ; 13 (13) ; 0 ; 0 ; 0 ; 0 ; |ex17_top|processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|a_fefifo_4be:fifo_state|cntr_di7:count_usedw ; cntr_di7 ; work ; +; |altsyncram_44t1:FIFOram| ; 0 (0) ; 0 (0) ; 73728 ; 0 ; 0 ; 0 ; |ex17_top|processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|altsyncram_44t1:FIFOram ; altsyncram_44t1 ; work ; +; |cntr_1ib:rd_ptr_count| ; 13 (13) ; 13 (13) ; 0 ; 0 ; 0 ; 0 ; |ex17_top|processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|cntr_1ib:rd_ptr_count ; cntr_1ib ; work ; +; |cntr_1ib:wr_ptr| ; 13 (13) ; 13 (13) ; 0 ; 0 ; 0 ; 0 ; |ex17_top|processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|cntr_1ib:wr_ptr ; cntr_1ib ; work ; +; |pulse_gen:PULSE0| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; |ex17_top|processor:ALLPASS|pulse_gen:PULSE0 ; pulse_gen ; work ; +; |pwm:PWM_DC| ; 19 (19) ; 21 (21) ; 0 ; 0 ; 0 ; 0 ; |ex17_top|pwm:PWM_DC ; pwm ; work ; +; |spi2adc:SPI_ADC| ; 23 (23) ; 40 (40) ; 0 ; 0 ; 0 ; 0 ; |ex17_top|spi2adc:SPI_ADC ; spi2adc ; work ; +; |spi2dac:SPI_DAC| ; 17 (17) ; 22 (22) ; 0 ; 0 ; 0 ; 0 ; |ex17_top|spi2dac:SPI_DAC ; spi2dac ; work ; ++---------------------------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------+--------------+ +Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis RAM Summary ; ++---------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+-------+------+ +; Name ; Type ; Mode ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size ; MIF ; ++---------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+-------+------+ +; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|altsyncram_44t1:FIFOram|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 8192 ; 10 ; 8192 ; 10 ; 81920 ; None ; ++---------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+-------+------+ + + ++------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis IP Cores Summary ; ++--------+--------------+---------+--------------+--------------+--------------------------------------------+-----------------+ +; Vendor ; IP Core Name ; Version ; Release Date ; License Type ; Entity Instance ; IP Include File ; ++--------+--------------+---------+--------------+--------------+--------------------------------------------+-----------------+ +; Altera ; FIFO ; 16.1 ; N/A ; N/A ; |ex17_top|processor:ALLPASS|FIFO:DELAY1024 ; FIFO.v ; ++--------+--------------+---------+--------------+--------------+--------------------------------------------+-----------------+ + + +Encoding Type: One-Hot ++--------------------------------------------------------------------+ +; State Machine - |ex17_top|processor:ALLPASS|pulse_gen:PULSE0|state ; ++----------------+------------+----------------+---------------------+ +; Name ; state.IDLE ; state.WAIT_LOW ; state.IN_HIGH ; ++----------------+------------+----------------+---------------------+ +; state.IDLE ; 0 ; 0 ; 0 ; +; state.IN_HIGH ; 1 ; 0 ; 1 ; +; state.WAIT_LOW ; 1 ; 1 ; 0 ; ++----------------+------------+----------------+---------------------+ + + +Encoding Type: One-Hot ++------------------------------------------------------------------------------------------+ +; State Machine - |ex17_top|spi2adc:SPI_ADC|sr_state ; ++------------------------+---------------+------------------------+------------------------+ +; Name ; sr_state.IDLE ; sr_state.WAIT_CSB_HIGH ; sr_state.WAIT_CSB_FALL ; ++------------------------+---------------+------------------------+------------------------+ +; sr_state.IDLE ; 0 ; 0 ; 0 ; +; sr_state.WAIT_CSB_FALL ; 1 ; 0 ; 1 ; +; sr_state.WAIT_CSB_HIGH ; 1 ; 1 ; 0 ; ++------------------------+---------------+------------------------+------------------------+ + + +Encoding Type: One-Hot ++------------------------------------------------------------------------------------------+ +; State Machine - |ex17_top|spi2dac:SPI_DAC|sr_state ; ++------------------------+---------------+------------------------+------------------------+ +; Name ; sr_state.IDLE ; sr_state.WAIT_CSB_HIGH ; sr_state.WAIT_CSB_FALL ; ++------------------------+---------------+------------------------+------------------------+ +; sr_state.IDLE ; 0 ; 0 ; 0 ; +; sr_state.WAIT_CSB_FALL ; 1 ; 0 ; 1 ; +; sr_state.WAIT_CSB_HIGH ; 1 ; 1 ; 0 ; ++------------------------+---------------+------------------------+------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Registers Removed During Synthesis ; ++----------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------+ +; Register name ; Reason for Removal ; ++----------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------+ +; spi2dac:SPI_DAC|clk_1MHz ; Merged with spi2adc:SPI_ADC|clk_1MHz ; +; spi2dac:SPI_DAC|tick ; Merged with spi2adc:SPI_ADC|tick ; +; spi2dac:SPI_DAC|ctr[4] ; Merged with spi2adc:SPI_ADC|ctr[4] ; +; spi2dac:SPI_DAC|ctr[3] ; Merged with spi2adc:SPI_ADC|ctr[3] ; +; spi2dac:SPI_DAC|ctr[2] ; Merged with spi2adc:SPI_ADC|ctr[2] ; +; spi2dac:SPI_DAC|ctr[1] ; Merged with spi2adc:SPI_ADC|ctr[1] ; +; spi2dac:SPI_DAC|ctr[0] ; Merged with spi2adc:SPI_ADC|ctr[0] ; +; spi2dac:SPI_DAC|shift_reg[0,1] ; Stuck at GND due to stuck port data_in ; +; processor:ALLPASS|pulse_gen:PULSE0|state.IN_HIGH ; Lost fanout ; +; processor:ALLPASS|pulse_gen:PULSE0|state.WAIT_LOW ; Lost fanout ; +; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|a_fefifo_4be:fifo_state|b_non_empty ; Stuck at VCC due to stuck port data_in ; +; Total Number of Removed Registers = 12 ; ; ++----------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------+ + + ++---------------------------------------------------------------------------------------------------+ +; Removed Registers Triggering Further Register Optimizations ; ++------------------------------+---------------------------+----------------------------------------+ +; Register name ; Reason for Removal ; Registers Removed due to This Register ; ++------------------------------+---------------------------+----------------------------------------+ +; spi2dac:SPI_DAC|shift_reg[0] ; Stuck at GND ; spi2dac:SPI_DAC|shift_reg[1] ; +; ; due to stuck port data_in ; ; ++------------------------------+---------------------------+----------------------------------------+ + + ++------------------------------------------------------+ +; General Register Statistics ; ++----------------------------------------------+-------+ +; Statistic ; Value ; ++----------------------------------------------+-------+ +; Total registers ; 153 ; +; Number of registers using Synchronous Clear ; 9 ; +; Number of registers using Synchronous Load ; 9 ; +; Number of registers using Asynchronous Clear ; 0 ; +; Number of registers using Asynchronous Load ; 0 ; +; Number of registers using Clock Enable ; 93 ; +; Number of registers using Preset ; 0 ; ++----------------------------------------------+-------+ + + ++--------------------------------------------------+ +; Inverted Register Statistics ; ++----------------------------------------+---------+ +; Inverted Register ; Fan out ; ++----------------------------------------+---------+ +; spi2adc:SPI_ADC|adc_cs ; 9 ; +; Total number of inverted registers = 1 ; ; ++----------------------------------------+---------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Multiplexer Restructuring Statistics (Restructuring Performed) ; ++--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------------------+ +; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ; ++--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------------------+ +; 3:1 ; 3 bits ; 6 LEs ; 3 LEs ; 3 LEs ; Yes ; |ex17_top|spi2dac:SPI_DAC|shift_reg[13] ; +; 3:1 ; 9 bits ; 18 LEs ; 0 LEs ; 18 LEs ; Yes ; |ex17_top|spi2dac:SPI_DAC|shift_reg[11] ; +; 6:1 ; 3 bits ; 12 LEs ; 6 LEs ; 6 LEs ; No ; |ex17_top|spi2dac:SPI_DAC|Selector2 ; ++--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|altsyncram_44t1:FIFOram ; ++---------------------------------+--------------------+------+-------------------------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++---------------------------------+--------------------+------+-------------------------------------------------------------------------------------------+ +; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ; ++---------------------------------+--------------------+------+-------------------------------------------------------------------------------------------+ + + ++-----------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: clktick_16:GEN_10K ; ++----------------+-------+----------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+-------+----------------------------------------+ +; N_BIT ; 16 ; Signed Integer ; ++----------------+-------+----------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++--------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: spi2dac:SPI_DAC ; ++----------------+-------+-------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+-------+-------------------------------------+ +; BUF ; 1 ; Unsigned Binary ; +; GA_N ; 1 ; Unsigned Binary ; +; SHDN_N ; 1 ; Unsigned Binary ; +; TC ; 11000 ; Unsigned Binary ; +; IDLE ; 00 ; Unsigned Binary ; +; WAIT_CSB_FALL ; 01 ; Unsigned Binary ; +; WAIT_CSB_HIGH ; 10 ; Unsigned Binary ; ++----------------+-------+-------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++--------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: spi2adc:SPI_ADC ; ++----------------+-------+-------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+-------+-------------------------------------+ +; SGL ; 1 ; Unsigned Binary ; +; MSBF ; 1 ; Unsigned Binary ; +; TIME_CONSTANT ; 11000 ; Unsigned Binary ; +; IDLE ; 00 ; Unsigned Binary ; +; WAIT_CSB_FALL ; 01 ; Unsigned Binary ; +; WAIT_CSB_HIGH ; 10 ; Unsigned Binary ; ++----------------+-------+-------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++----------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: processor:ALLPASS ; ++----------------+------------+----------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+------------+----------------------------------+ +; ADC_OFFSET ; 0110000001 ; Unsigned Binary ; +; DAC_OFFSET ; 1000000000 ; Unsigned Binary ; ++----------------+------------+----------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++---------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: processor:ALLPASS|pulse_gen:PULSE0 ; ++----------------+-------+--------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+-------+--------------------------------------------------------+ +; IDLE ; 00 ; Unsigned Binary ; +; IN_HIGH ; 01 ; Unsigned Binary ; +; WAIT_LOW ; 10 ; Unsigned Binary ; ++----------------+-------+--------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++-------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component ; ++-------------------------+-------------+---------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++-------------------------+-------------+---------------------------------------------------------------+ +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; +; lpm_width ; 10 ; Signed Integer ; +; LPM_NUMWORDS ; 8192 ; Signed Integer ; +; LPM_WIDTHU ; 13 ; Signed Integer ; +; LPM_SHOWAHEAD ; OFF ; Untyped ; +; UNDERFLOW_CHECKING ; ON ; Untyped ; +; OVERFLOW_CHECKING ; ON ; Untyped ; +; ALLOW_RWCYCLE_WHEN_FULL ; OFF ; Untyped ; +; ADD_RAM_OUTPUT_REGISTER ; OFF ; Untyped ; +; ALMOST_FULL_VALUE ; 0 ; Untyped ; +; ALMOST_EMPTY_VALUE ; 0 ; Untyped ; +; ENABLE_ECC ; FALSE ; Untyped ; +; USE_EAB ; ON ; Untyped ; +; MAXIMIZE_SPEED ; 5 ; Untyped ; +; DEVICE_FAMILY ; Cyclone V ; Untyped ; +; OPTIMIZE_FOR_SPEED ; 5 ; Untyped ; +; CBXI_PARAMETER ; scfifo_j791 ; Untyped ; ++-------------------------+-------------+---------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++---------------------------------------------------------------------------------------+ +; scfifo Parameter Settings by Entity Instance ; ++----------------------------+----------------------------------------------------------+ +; Name ; Value ; ++----------------------------+----------------------------------------------------------+ +; Number of entity instances ; 1 ; +; Entity Instance ; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component ; +; -- FIFO Type ; Single Clock ; +; -- lpm_width ; 10 ; +; -- LPM_NUMWORDS ; 8192 ; +; -- LPM_SHOWAHEAD ; OFF ; +; -- USE_EAB ; ON ; ++----------------------------+----------------------------------------------------------+ + + ++----------------------------------------------+ +; Port Connectivity Checks: "hex_to_7seg:SEG2" ; ++----------+-------+----------+----------------+ +; Port ; Type ; Severity ; Details ; ++----------+-------+----------+----------------+ +; in[3..2] ; Input ; Info ; Stuck at GND ; ++----------+-------+----------+----------------+ + + ++-----------------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "processor:ALLPASS|FIFO:DELAY1024" ; ++-------+--------+----------+-------------------------------------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++-------+--------+----------+-------------------------------------------------------------------------------------+ +; empty ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; +; q[0] ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; ++-------+--------+----------+-------------------------------------------------------------------------------------+ + + ++---------------------------------------------+ +; Port Connectivity Checks: "spi2adc:SPI_ADC" ; ++---------+-------+----------+----------------+ +; Port ; Type ; Severity ; Details ; ++---------+-------+----------+----------------+ +; channel ; Input ; Info ; Stuck at VCC ; ++---------+-------+----------+----------------+ + + ++------------------------------------------------+ +; Port Connectivity Checks: "clktick_16:GEN_10K" ; ++-----------+-------+----------+-----------------+ +; Port ; Type ; Severity ; Details ; ++-----------+-------+----------+-----------------+ +; enable ; Input ; Info ; Stuck at VCC ; +; N[9..7] ; Input ; Info ; Stuck at VCC ; +; N[2..0] ; Input ; Info ; Stuck at VCC ; +; N[15..13] ; Input ; Info ; Stuck at GND ; +; N[11..10] ; Input ; Info ; Stuck at GND ; +; N[6..3] ; Input ; Info ; Stuck at GND ; +; N[12] ; Input ; Info ; Stuck at VCC ; ++-----------+-------+----------+-----------------+ + + ++-----------------------------------------------------+ +; Post-Synthesis Netlist Statistics for Top Partition ; ++-----------------------+-----------------------------+ +; Type ; Count ; ++-----------------------+-----------------------------+ +; arriav_ff ; 153 ; +; ENA ; 84 ; +; ENA SLD ; 9 ; +; SCLR ; 9 ; +; plain ; 51 ; +; arriav_lcell_comb ; 173 ; +; arith ; 84 ; +; 1 data inputs ; 61 ; +; 2 data inputs ; 23 ; +; normal ; 89 ; +; 0 data inputs ; 1 ; +; 1 data inputs ; 10 ; +; 2 data inputs ; 8 ; +; 3 data inputs ; 6 ; +; 4 data inputs ; 31 ; +; 5 data inputs ; 23 ; +; 6 data inputs ; 10 ; +; boundary_port ; 41 ; +; stratixv_ram_block ; 9 ; +; ; ; +; Max LUT depth ; 3.90 ; +; Average LUT depth ; 1.90 ; ++-----------------------+-----------------------------+ + + ++-------------------------------+ +; Elapsed Time Per Partition ; ++----------------+--------------+ +; Partition Name ; Elapsed Time ; ++----------------+--------------+ +; Top ; 00:00:03 ; ++----------------+--------------+ + + ++-------------------------------+ +; Analysis & Synthesis Messages ; ++-------------------------------+ +Info: ******************************************************************* +Info: Running Quartus Prime Analysis & Synthesis + Info: Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition + Info: Processing started: Sat Dec 10 18:43:39 2016 +Info: Command: quartus_map --read_settings_files=on --write_settings_files=off ex17 -c ex17_top +Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. +Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected +Info (12021): Found 1 design units, including 1 entities, in source file single_echo.v + Info (12023): Found entity 1: processor File: H:/Year 2/VERI/part_4/ex17/single_echo.v Line: 1 +Info (12021): Found 1 design units, including 1 entities, in source file ex17_top.v + Info (12023): Found entity 1: ex17_top File: H:/Year 2/VERI/part_4/ex17/ex17_top.v Line: 1 +Info (12021): Found 1 design units, including 1 entities, in source file /year 2/veri/part_4/mylib/spi2dac.v + Info (12023): Found entity 1: spi2dac File: H:/Year 2/VERI/part_4/mylib/spi2dac.v Line: 9 +Info (12021): Found 1 design units, including 1 entities, in source file /year 2/veri/part_4/mylib/spi2adc.v + Info (12023): Found entity 1: spi2adc File: H:/Year 2/VERI/part_4/mylib/spi2adc.v Line: 9 +Info (12021): Found 1 design units, including 1 entities, in source file /year 2/veri/part_4/mylib/pwm.v + Info (12023): Found entity 1: pwm File: H:/Year 2/VERI/part_4/mylib/pwm.v Line: 1 +Info (12021): Found 1 design units, including 1 entities, in source file /year 2/veri/part_4/mylib/pulse_gen.v + Info (12023): Found entity 1: pulse_gen File: H:/Year 2/VERI/part_4/mylib/pulse_gen.v Line: 9 +Info (12021): Found 1 design units, including 1 entities, in source file /year 2/veri/part_4/mylib/multiply_k.v + Info (12023): Found entity 1: multiply_k File: H:/Year 2/VERI/part_4/mylib/multiply_k.v Line: 39 +Info (12021): Found 1 design units, including 1 entities, in source file /year 2/veri/part_4/mylib/multiply_4.v + Info (12023): Found entity 1: multiply_4 File: H:/Year 2/VERI/part_4/mylib/multiply_4.v Line: 39 +Info (12021): Found 1 design units, including 1 entities, in source file /year 2/veri/part_4/mylib/hex_to_7seg.v + Info (12023): Found entity 1: hex_to_7seg File: H:/Year 2/VERI/part_4/mylib/hex_to_7seg.v Line: 10 +Info (12021): Found 1 design units, including 1 entities, in source file /year 2/veri/part_4/mylib/counter_13.v + Info (12023): Found entity 1: counter_13 File: H:/Year 2/VERI/part_4/mylib/counter_13.v Line: 3 +Info (12021): Found 1 design units, including 1 entities, in source file /year 2/veri/part_4/mylib/clktick_16.v + Info (12023): Found entity 1: clktick_16 File: H:/Year 2/VERI/part_4/mylib/clktick_16.v Line: 6 +Info (12021): Found 1 design units, including 1 entities, in source file /year 2/veri/part_4/mylib/bin2bcd_16.v + Info (12023): Found entity 1: bin2bcd_16 File: H:/Year 2/VERI/part_4/mylib/bin2bcd_16.v Line: 12 +Info (12021): Found 1 design units, including 1 entities, in source file /year 2/veri/part_4/mylib/add3_ge5.v + Info (12023): Found entity 1: add3_ge5 File: H:/Year 2/VERI/part_4/mylib/add3_ge5.v Line: 9 +Info (12021): Found 1 design units, including 1 entities, in source file fifo.v + Info (12023): Found entity 1: FIFO File: H:/Year 2/VERI/part_4/ex17/FIFO.v Line: 40 +Info (12127): Elaborating entity "ex17_top" for the top level hierarchy +Info (12128): Elaborating entity "clktick_16" for hierarchy "clktick_16:GEN_10K" File: H:/Year 2/VERI/part_4/ex17/ex17_top.v Line: 24 +Info (12128): Elaborating entity "spi2dac" for hierarchy "spi2dac:SPI_DAC" File: H:/Year 2/VERI/part_4/ex17/ex17_top.v Line: 26 +Info (12128): Elaborating entity "pwm" for hierarchy "pwm:PWM_DC" File: H:/Year 2/VERI/part_4/ex17/ex17_top.v Line: 27 +Info (12128): Elaborating entity "spi2adc" for hierarchy "spi2adc:SPI_ADC" File: H:/Year 2/VERI/part_4/ex17/ex17_top.v Line: 38 +Info (12128): Elaborating entity "processor" for hierarchy "processor:ALLPASS" File: H:/Year 2/VERI/part_4/ex17/ex17_top.v Line: 40 +Info (12128): Elaborating entity "pulse_gen" for hierarchy "processor:ALLPASS|pulse_gen:PULSE0" File: H:/Year 2/VERI/part_4/ex17/single_echo.v Line: 23 +Info (12128): Elaborating entity "FIFO" for hierarchy "processor:ALLPASS|FIFO:DELAY1024" File: H:/Year 2/VERI/part_4/ex17/single_echo.v Line: 33 +Info (12128): Elaborating entity "scfifo" for hierarchy "processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component" File: H:/Year 2/VERI/part_4/ex17/FIFO.v Line: 77 +Info (12130): Elaborated megafunction instantiation "processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component" File: H:/Year 2/VERI/part_4/ex17/FIFO.v Line: 77 +Info (12133): Instantiated megafunction "processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component" with the following parameter: File: H:/Year 2/VERI/part_4/ex17/FIFO.v Line: 77 + Info (12134): Parameter "add_ram_output_register" = "OFF" + Info (12134): Parameter "intended_device_family" = "Cyclone V" + Info (12134): Parameter "lpm_numwords" = "8192" + Info (12134): Parameter "lpm_showahead" = "OFF" + Info (12134): Parameter "lpm_type" = "scfifo" + Info (12134): Parameter "lpm_width" = "10" + Info (12134): Parameter "lpm_widthu" = "13" + Info (12134): Parameter "overflow_checking" = "ON" + Info (12134): Parameter "underflow_checking" = "ON" + Info (12134): Parameter "use_eab" = "ON" +Info (12021): Found 1 design units, including 1 entities, in source file db/scfifo_j791.tdf + Info (12023): Found entity 1: scfifo_j791 File: H:/Year 2/VERI/part_4/ex17/db/scfifo_j791.tdf Line: 25 +Info (12128): Elaborating entity "scfifo_j791" for hierarchy "processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated" File: c:/intelfpga_lite/16.1/quartus/libraries/megafunctions/scfifo.tdf Line: 300 +Info (12021): Found 1 design units, including 1 entities, in source file db/a_dpfifo_qd91.tdf + Info (12023): Found entity 1: a_dpfifo_qd91 File: H:/Year 2/VERI/part_4/ex17/db/a_dpfifo_qd91.tdf Line: 29 +Info (12128): Elaborating entity "a_dpfifo_qd91" for hierarchy "processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo" File: H:/Year 2/VERI/part_4/ex17/db/scfifo_j791.tdf Line: 36 +Info (12021): Found 1 design units, including 1 entities, in source file db/a_fefifo_4be.tdf + Info (12023): Found entity 1: a_fefifo_4be File: H:/Year 2/VERI/part_4/ex17/db/a_fefifo_4be.tdf Line: 25 +Info (12128): Elaborating entity "a_fefifo_4be" for hierarchy "processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|a_fefifo_4be:fifo_state" File: H:/Year 2/VERI/part_4/ex17/db/a_dpfifo_qd91.tdf Line: 41 +Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_di7.tdf + Info (12023): Found entity 1: cntr_di7 File: H:/Year 2/VERI/part_4/ex17/db/cntr_di7.tdf Line: 26 +Info (12128): Elaborating entity "cntr_di7" for hierarchy "processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|a_fefifo_4be:fifo_state|cntr_di7:count_usedw" File: H:/Year 2/VERI/part_4/ex17/db/a_fefifo_4be.tdf Line: 38 +Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_44t1.tdf + Info (12023): Found entity 1: altsyncram_44t1 File: H:/Year 2/VERI/part_4/ex17/db/altsyncram_44t1.tdf Line: 28 +Info (12128): Elaborating entity "altsyncram_44t1" for hierarchy "processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|altsyncram_44t1:FIFOram" File: H:/Year 2/VERI/part_4/ex17/db/a_dpfifo_qd91.tdf Line: 42 +Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_1ib.tdf + Info (12023): Found entity 1: cntr_1ib File: H:/Year 2/VERI/part_4/ex17/db/cntr_1ib.tdf Line: 26 +Info (12128): Elaborating entity "cntr_1ib" for hierarchy "processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|cntr_1ib:rd_ptr_count" File: H:/Year 2/VERI/part_4/ex17/db/a_dpfifo_qd91.tdf Line: 43 +Info (12128): Elaborating entity "hex_to_7seg" for hierarchy "hex_to_7seg:SEG0" File: H:/Year 2/VERI/part_4/ex17/ex17_top.v Line: 42 +Warning (14284): Synthesized away the following node(s): + Warning (14285): Synthesized away the following RAM node(s): + Warning (14320): Synthesized away node "processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|altsyncram_44t1:FIFOram|q_b[0]" File: H:/Year 2/VERI/part_4/ex17/db/altsyncram_44t1.tdf Line: 40 +Warning (13024): Output pins are stuck at VCC or GND + Warning (13410): Pin "HEX2[1]" is stuck at GND File: H:/Year 2/VERI/part_4/ex17/ex17_top.v Line: 7 +Info (286030): Timing-Driven Synthesis is running +Info (17049): 2 registers lost all their fanouts during netlist optimizations. +Info (144001): Generated suppressed messages file H:/Year 2/VERI/part_4/ex17/output_files/ex17_top.map.smsg +Info (16010): Generating hard_block partition "hard_block:auto_generated_inst" + Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL +Warning (21074): Design contains 10 input pin(s) that do not drive logic + Warning (15610): No output dependent on input pin "SW[0]" File: H:/Year 2/VERI/part_4/ex17/ex17_top.v Line: 6 + Warning (15610): No output dependent on input pin "SW[1]" File: H:/Year 2/VERI/part_4/ex17/ex17_top.v Line: 6 + Warning (15610): No output dependent on input pin "SW[2]" File: H:/Year 2/VERI/part_4/ex17/ex17_top.v Line: 6 + Warning (15610): No output dependent on input pin "SW[3]" File: H:/Year 2/VERI/part_4/ex17/ex17_top.v Line: 6 + Warning (15610): No output dependent on input pin "SW[4]" File: H:/Year 2/VERI/part_4/ex17/ex17_top.v Line: 6 + Warning (15610): No output dependent on input pin "SW[5]" File: H:/Year 2/VERI/part_4/ex17/ex17_top.v Line: 6 + Warning (15610): No output dependent on input pin "SW[6]" File: H:/Year 2/VERI/part_4/ex17/ex17_top.v Line: 6 + Warning (15610): No output dependent on input pin "SW[7]" File: H:/Year 2/VERI/part_4/ex17/ex17_top.v Line: 6 + Warning (15610): No output dependent on input pin "SW[8]" File: H:/Year 2/VERI/part_4/ex17/ex17_top.v Line: 6 + Warning (15610): No output dependent on input pin "SW[9]" File: H:/Year 2/VERI/part_4/ex17/ex17_top.v Line: 6 +Info (21057): Implemented 256 device resources after synthesis - the final resource count might be different + Info (21058): Implemented 12 input pins + Info (21059): Implemented 29 output pins + Info (21061): Implemented 206 logic cells + Info (21064): Implemented 9 RAM segments +Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 17 warnings + Info: Peak virtual memory: 710 megabytes + Info: Processing ended: Sat Dec 10 18:44:47 2016 + Info: Elapsed time: 00:01:08 + Info: Total CPU time (on all processors): 00:00:40 + + ++------------------------------------------+ +; Analysis & Synthesis Suppressed Messages ; ++------------------------------------------+ +The suppressed messages can be found in H:/Year 2/VERI/part_4/ex17/output_files/ex17_top.map.smsg. + + diff --git a/part_4/ex17/output_files/ex17_top.sta.rpt b/part_4/ex17/output_files/ex17_top.sta.rpt new file mode 100644 index 0000000..2877bd6 --- /dev/null +++ b/part_4/ex17/output_files/ex17_top.sta.rpt @@ -0,0 +1,791 @@ +TimeQuest Timing Analyzer report for ex17_top +Sat Dec 10 18:52:02 2016 +Quartus Prime Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. TimeQuest Timing Analyzer Summary + 3. Parallel Compilation + 4. SDC File List + 5. Clocks + 6. Slow 1100mV 85C Model Fmax Summary + 7. Timing Closure Recommendations + 8. Slow 1100mV 85C Model Setup Summary + 9. Slow 1100mV 85C Model Hold Summary + 10. Slow 1100mV 85C Model Recovery Summary + 11. Slow 1100mV 85C Model Removal Summary + 12. Slow 1100mV 85C Model Minimum Pulse Width Summary + 13. Slow 1100mV 85C Model Metastability Summary + 14. Slow 1100mV 0C Model Fmax Summary + 15. Slow 1100mV 0C Model Setup Summary + 16. Slow 1100mV 0C Model Hold Summary + 17. Slow 1100mV 0C Model Recovery Summary + 18. Slow 1100mV 0C Model Removal Summary + 19. Slow 1100mV 0C Model Minimum Pulse Width Summary + 20. Slow 1100mV 0C Model Metastability Summary + 21. Fast 1100mV 85C Model Setup Summary + 22. Fast 1100mV 85C Model Hold Summary + 23. Fast 1100mV 85C Model Recovery Summary + 24. Fast 1100mV 85C Model Removal Summary + 25. Fast 1100mV 85C Model Minimum Pulse Width Summary + 26. Fast 1100mV 85C Model Metastability Summary + 27. Fast 1100mV 0C Model Setup Summary + 28. Fast 1100mV 0C Model Hold Summary + 29. Fast 1100mV 0C Model Recovery Summary + 30. Fast 1100mV 0C Model Removal Summary + 31. Fast 1100mV 0C Model Minimum Pulse Width Summary + 32. Fast 1100mV 0C Model Metastability Summary + 33. Multicorner Timing Analysis Summary + 34. Board Trace Model Assignments + 35. Input Transition Times + 36. Signal Integrity Metrics (Slow 1100mv 0c Model) + 37. Signal Integrity Metrics (Slow 1100mv 85c Model) + 38. Signal Integrity Metrics (Fast 1100mv 0c Model) + 39. Signal Integrity Metrics (Fast 1100mv 85c Model) + 40. Setup Transfers + 41. Hold Transfers + 42. Report TCCS + 43. Report RSKM + 44. Unconstrained Paths Summary + 45. Clock Status Summary + 46. Unconstrained Input Ports + 47. Unconstrained Output Ports + 48. Unconstrained Input Ports + 49. Unconstrained Output Ports + 50. TimeQuest Timing Analyzer Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2016 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel MegaCore Function License Agreement, or other +applicable license agreement, including, without limitation, +that your use is for the sole purpose of programming logic +devices manufactured by Intel and sold by Intel or its +authorized distributors. Please refer to the applicable +agreement for further details. + + + ++-----------------------------------------------------------------------------+ +; TimeQuest Timing Analyzer Summary ; ++-----------------------+-----------------------------------------------------+ +; Quartus Prime Version ; Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition ; +; Timing Analyzer ; TimeQuest ; +; Revision Name ; ex17_top ; +; Device Family ; Cyclone V ; +; Device Name ; 5CSEMA5F31C6 ; +; Timing Models ; Final ; +; Delay Model ; Combined ; +; Rise/Fall Delays ; Enabled ; ++-----------------------+-----------------------------------------------------+ + + ++------------------------------------------+ +; Parallel Compilation ; ++----------------------------+-------------+ +; Processors ; Number ; ++----------------------------+-------------+ +; Number detected on machine ; 2 ; +; Maximum allowed ; 2 ; +; ; ; +; Average used ; 1.02 ; +; Maximum used ; 2 ; +; ; ; +; Usage by Processor ; % Time Used ; +; Processor 1 ; 100.0% ; +; Processor 2 ; 2.1% ; ++----------------------------+-------------+ + + ++---------------------------------------------------+ +; SDC File List ; ++---------------+--------+--------------------------+ +; SDC File Path ; Status ; Read at ; ++---------------+--------+--------------------------+ +; ex17_top.sdc ; OK ; Sat Dec 10 18:50:59 2016 ; ++---------------+--------+--------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Clocks ; ++------------+------+--------+-----------+-------+--------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+--------------+ +; Clock Name ; Type ; Period ; Frequency ; Rise ; Fall ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets ; ++------------+------+--------+-----------+-------+--------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+--------------+ +; CLOCK_50 ; Base ; 20.000 ; 50.0 MHz ; 0.000 ; 10.000 ; ; ; ; ; ; ; ; ; ; ; { CLOCK_50 } ; ++------------+------+--------+-----------+-------+--------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+--------------+ + + ++--------------------------------------------------+ +; Slow 1100mV 85C Model Fmax Summary ; ++------------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++------------+-----------------+------------+------+ +; 178.67 MHz ; 178.67 MHz ; CLOCK_50 ; ; ++------------+-----------------+------------+------+ +This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis. + + +---------------------------------- +; Timing Closure Recommendations ; +---------------------------------- +HTML report is unavailable in plain text report export. + + ++-------------------------------------+ +; Slow 1100mV 85C Model Setup Summary ; ++----------+-------+------------------+ +; Clock ; Slack ; End Point TNS ; ++----------+-------+------------------+ +; CLOCK_50 ; 7.864 ; 0.000 ; ++----------+-------+------------------+ + + ++------------------------------------+ +; Slow 1100mV 85C Model Hold Summary ; ++----------+-------+-----------------+ +; Clock ; Slack ; End Point TNS ; ++----------+-------+-----------------+ +; CLOCK_50 ; 0.354 ; 0.000 ; ++----------+-------+-----------------+ + + +------------------------------------------ +; Slow 1100mV 85C Model Recovery Summary ; +------------------------------------------ +No paths to report. + + +----------------------------------------- +; Slow 1100mV 85C Model Removal Summary ; +----------------------------------------- +No paths to report. + + ++---------------------------------------------------+ +; Slow 1100mV 85C Model Minimum Pulse Width Summary ; ++----------+-------+--------------------------------+ +; Clock ; Slack ; End Point TNS ; ++----------+-------+--------------------------------+ +; CLOCK_50 ; 8.877 ; 0.000 ; ++----------+-------+--------------------------------+ + + +----------------------------------------------- +; Slow 1100mV 85C Model Metastability Summary ; +----------------------------------------------- +No synchronizer chains to report. + + ++--------------------------------------------------+ +; Slow 1100mV 0C Model Fmax Summary ; ++------------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++------------+-----------------+------------+------+ +; 175.75 MHz ; 175.75 MHz ; CLOCK_50 ; ; ++------------+-----------------+------------+------+ +This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis. + + ++------------------------------------+ +; Slow 1100mV 0C Model Setup Summary ; ++----------+-------+-----------------+ +; Clock ; Slack ; End Point TNS ; ++----------+-------+-----------------+ +; CLOCK_50 ; 7.952 ; 0.000 ; ++----------+-------+-----------------+ + + ++-----------------------------------+ +; Slow 1100mV 0C Model Hold Summary ; ++----------+-------+----------------+ +; Clock ; Slack ; End Point TNS ; ++----------+-------+----------------+ +; CLOCK_50 ; 0.348 ; 0.000 ; ++----------+-------+----------------+ + + +----------------------------------------- +; Slow 1100mV 0C Model Recovery Summary ; +----------------------------------------- +No paths to report. + + +---------------------------------------- +; Slow 1100mV 0C Model Removal Summary ; +---------------------------------------- +No paths to report. + + ++--------------------------------------------------+ +; Slow 1100mV 0C Model Minimum Pulse Width Summary ; ++----------+-------+-------------------------------+ +; Clock ; Slack ; End Point TNS ; ++----------+-------+-------------------------------+ +; CLOCK_50 ; 8.912 ; 0.000 ; ++----------+-------+-------------------------------+ + + +---------------------------------------------- +; Slow 1100mV 0C Model Metastability Summary ; +---------------------------------------------- +No synchronizer chains to report. + + ++-------------------------------------+ +; Fast 1100mV 85C Model Setup Summary ; ++----------+-------+------------------+ +; Clock ; Slack ; End Point TNS ; ++----------+-------+------------------+ +; CLOCK_50 ; 8.618 ; 0.000 ; ++----------+-------+------------------+ + + ++------------------------------------+ +; Fast 1100mV 85C Model Hold Summary ; ++----------+-------+-----------------+ +; Clock ; Slack ; End Point TNS ; ++----------+-------+-----------------+ +; CLOCK_50 ; 0.182 ; 0.000 ; ++----------+-------+-----------------+ + + +------------------------------------------ +; Fast 1100mV 85C Model Recovery Summary ; +------------------------------------------ +No paths to report. + + +----------------------------------------- +; Fast 1100mV 85C Model Removal Summary ; +----------------------------------------- +No paths to report. + + ++---------------------------------------------------+ +; Fast 1100mV 85C Model Minimum Pulse Width Summary ; ++----------+-------+--------------------------------+ +; Clock ; Slack ; End Point TNS ; ++----------+-------+--------------------------------+ +; CLOCK_50 ; 8.480 ; 0.000 ; ++----------+-------+--------------------------------+ + + +----------------------------------------------- +; Fast 1100mV 85C Model Metastability Summary ; +----------------------------------------------- +No synchronizer chains to report. + + ++------------------------------------+ +; Fast 1100mV 0C Model Setup Summary ; ++----------+-------+-----------------+ +; Clock ; Slack ; End Point TNS ; ++----------+-------+-----------------+ +; CLOCK_50 ; 8.627 ; 0.000 ; ++----------+-------+-----------------+ + + ++-----------------------------------+ +; Fast 1100mV 0C Model Hold Summary ; ++----------+-------+----------------+ +; Clock ; Slack ; End Point TNS ; ++----------+-------+----------------+ +; CLOCK_50 ; 0.173 ; 0.000 ; ++----------+-------+----------------+ + + +----------------------------------------- +; Fast 1100mV 0C Model Recovery Summary ; +----------------------------------------- +No paths to report. + + +---------------------------------------- +; Fast 1100mV 0C Model Removal Summary ; +---------------------------------------- +No paths to report. + + ++--------------------------------------------------+ +; Fast 1100mV 0C Model Minimum Pulse Width Summary ; ++----------+-------+-------------------------------+ +; Clock ; Slack ; End Point TNS ; ++----------+-------+-------------------------------+ +; CLOCK_50 ; 8.437 ; 0.000 ; ++----------+-------+-------------------------------+ + + +---------------------------------------------- +; Fast 1100mV 0C Model Metastability Summary ; +---------------------------------------------- +No synchronizer chains to report. + + ++-----------------------------------------------------------------------------+ +; Multicorner Timing Analysis Summary ; ++------------------+-------+-------+----------+---------+---------------------+ +; Clock ; Setup ; Hold ; Recovery ; Removal ; Minimum Pulse Width ; ++------------------+-------+-------+----------+---------+---------------------+ +; Worst-case Slack ; 7.864 ; 0.173 ; N/A ; N/A ; 8.437 ; +; CLOCK_50 ; 7.864 ; 0.173 ; N/A ; N/A ; 8.437 ; +; Design-wide TNS ; 0.0 ; 0.0 ; 0.0 ; 0.0 ; 0.0 ; +; CLOCK_50 ; 0.000 ; 0.000 ; N/A ; N/A ; 0.000 ; ++------------------+-------+-------+----------+---------+---------------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Board Trace Model Assignments ; ++---------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ +; Pin ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ; ++---------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ +; HEX0[0] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX0[1] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX0[2] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX0[3] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX0[4] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX0[5] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX0[6] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX1[0] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX1[1] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX1[2] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX1[3] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX1[4] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX1[5] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX1[6] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX2[0] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX2[1] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX2[2] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX2[3] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX2[4] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX2[5] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX2[6] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DAC_SDI ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DAC_SCK ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DAC_CS ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DAC_LD ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; ADC_SDI ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; ADC_SCK ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; ADC_CS ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; PWM_OUT ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; ++---------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ + + ++-------------------------------------------------------------+ +; Input Transition Times ; ++----------+--------------+-----------------+-----------------+ +; Pin ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ; ++----------+--------------+-----------------+-----------------+ +; SW[0] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; SW[1] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; SW[2] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; SW[3] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; SW[4] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; SW[5] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; SW[6] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; SW[7] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; SW[8] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; SW[9] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; CLOCK_50 ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; ADC_SDO ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; ++----------+--------------+-----------------+-----------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Signal Integrity Metrics (Slow 1100mv 0c Model) ; ++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; ++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; HEX0[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; +; HEX0[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; +; HEX0[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; +; HEX0[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; +; HEX0[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; +; HEX0[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; +; HEX0[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; +; HEX1[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; +; HEX1[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; +; HEX1[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; +; HEX1[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; +; HEX1[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; +; HEX1[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; +; HEX1[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; +; HEX2[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ; +; HEX2[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; +; HEX2[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; +; HEX2[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; +; HEX2[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; +; HEX2[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; +; HEX2[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; +; DAC_SDI ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; +; DAC_SCK ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ; +; DAC_CS ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ; +; DAC_LD ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; +; ADC_SDI ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ; +; ADC_SCK ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ; +; ADC_CS ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ; +; PWM_OUT ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; ++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Signal Integrity Metrics (Slow 1100mv 85c Model) ; ++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; ++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; HEX0[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; +; HEX0[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; +; HEX0[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; +; HEX0[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; +; HEX0[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; +; HEX0[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; +; HEX0[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; +; HEX1[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; +; HEX1[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; +; HEX1[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; +; HEX1[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; +; HEX1[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; +; HEX1[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; +; HEX1[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; +; HEX2[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ; +; HEX2[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; +; HEX2[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; +; HEX2[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; +; HEX2[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; +; HEX2[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; +; HEX2[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; +; DAC_SDI ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; +; DAC_SCK ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ; +; DAC_CS ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ; +; DAC_LD ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; +; ADC_SDI ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ; +; ADC_SCK ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ; +; ADC_CS ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ; +; PWM_OUT ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; ++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Signal Integrity Metrics (Fast 1100mv 0c Model) ; ++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; ++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; HEX0[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; +; HEX0[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; +; HEX0[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; +; HEX0[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; +; HEX0[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; +; HEX0[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; +; HEX0[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; +; HEX1[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; +; HEX1[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; +; HEX1[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; +; HEX1[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; +; HEX1[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; +; HEX1[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; +; HEX1[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; +; HEX2[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ; +; HEX2[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; +; HEX2[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; +; HEX2[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; +; HEX2[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; +; HEX2[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; +; HEX2[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; +; DAC_SDI ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; +; DAC_SCK ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ; +; DAC_CS ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ; +; DAC_LD ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; +; ADC_SDI ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ; +; ADC_SCK ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ; +; ADC_CS ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ; +; PWM_OUT ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; ++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Signal Integrity Metrics (Fast 1100mv 85c Model) ; ++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; ++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; HEX0[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; +; HEX0[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; +; HEX0[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; +; HEX0[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; +; HEX0[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; +; HEX0[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; +; HEX0[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; +; HEX1[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; +; HEX1[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; +; HEX1[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; +; HEX1[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; +; HEX1[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; +; HEX1[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; +; HEX1[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; +; HEX2[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ; +; HEX2[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; +; HEX2[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; +; HEX2[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; +; HEX2[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; +; HEX2[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; +; HEX2[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; +; DAC_SDI ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; +; DAC_SCK ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ; +; DAC_CS ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ; +; DAC_LD ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; +; ADC_SDI ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ; +; ADC_SCK ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ; +; ADC_CS ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ; +; PWM_OUT ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; ++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ + + ++-------------------------------------------------------------------+ +; Setup Transfers ; ++------------+----------+----------+----------+----------+----------+ +; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; ++------------+----------+----------+----------+----------+----------+ +; CLOCK_50 ; CLOCK_50 ; 2919 ; 12 ; 39 ; 12 ; ++------------+----------+----------+----------+----------+----------+ +Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. + + ++-------------------------------------------------------------------+ +; Hold Transfers ; ++------------+----------+----------+----------+----------+----------+ +; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; ++------------+----------+----------+----------+----------+----------+ +; CLOCK_50 ; CLOCK_50 ; 2919 ; 12 ; 39 ; 12 ; ++------------+----------+----------+----------+----------+----------+ +Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. + + +--------------- +; Report TCCS ; +--------------- +No dedicated SERDES Transmitter circuitry present in device or used in design + + +--------------- +; Report RSKM ; +--------------- +No non-DPA dedicated SERDES Receiver circuitry present in device or used in design + + ++------------------------------------------------+ +; Unconstrained Paths Summary ; ++---------------------------------+-------+------+ +; Property ; Setup ; Hold ; ++---------------------------------+-------+------+ +; Illegal Clocks ; 0 ; 0 ; +; Unconstrained Clocks ; 0 ; 0 ; +; Unconstrained Input Ports ; 1 ; 1 ; +; Unconstrained Input Port Paths ; 1 ; 1 ; +; Unconstrained Output Ports ; 28 ; 28 ; +; Unconstrained Output Port Paths ; 88 ; 88 ; ++---------------------------------+-------+------+ + + ++------------------------------------------+ +; Clock Status Summary ; ++----------+----------+------+-------------+ +; Target ; Clock ; Type ; Status ; ++----------+----------+------+-------------+ +; CLOCK_50 ; CLOCK_50 ; Base ; Constrained ; ++----------+----------+------+-------------+ + + ++---------------------------------------------------------------------------------------------------+ +; Unconstrained Input Ports ; ++------------+--------------------------------------------------------------------------------------+ +; Input Port ; Comment ; ++------------+--------------------------------------------------------------------------------------+ +; ADC_SDO ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ++------------+--------------------------------------------------------------------------------------+ + + ++-----------------------------------------------------------------------------------------------------+ +; Unconstrained Output Ports ; ++-------------+---------------------------------------------------------------------------------------+ +; Output Port ; Comment ; ++-------------+---------------------------------------------------------------------------------------+ +; ADC_CS ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; ADC_SCK ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; ADC_SDI ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; DAC_CS ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; DAC_LD ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; DAC_SCK ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; DAC_SDI ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX0[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX0[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX0[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX0[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX0[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX0[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX0[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX1[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX1[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX1[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX1[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX1[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX1[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX1[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX2[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX2[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX2[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX2[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX2[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX2[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; PWM_OUT ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ++-------------+---------------------------------------------------------------------------------------+ + + ++---------------------------------------------------------------------------------------------------+ +; Unconstrained Input Ports ; ++------------+--------------------------------------------------------------------------------------+ +; Input Port ; Comment ; ++------------+--------------------------------------------------------------------------------------+ +; ADC_SDO ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ++------------+--------------------------------------------------------------------------------------+ + + ++-----------------------------------------------------------------------------------------------------+ +; Unconstrained Output Ports ; ++-------------+---------------------------------------------------------------------------------------+ +; Output Port ; Comment ; ++-------------+---------------------------------------------------------------------------------------+ +; ADC_CS ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; ADC_SCK ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; ADC_SDI ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; DAC_CS ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; DAC_LD ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; DAC_SCK ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; DAC_SDI ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX0[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX0[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX0[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX0[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX0[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX0[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX0[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX1[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX1[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX1[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX1[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX1[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX1[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX1[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX2[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX2[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX2[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX2[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX2[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX2[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; PWM_OUT ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ++-------------+---------------------------------------------------------------------------------------+ + + ++------------------------------------+ +; TimeQuest Timing Analyzer Messages ; ++------------------------------------+ +Info: ******************************************************************* +Info: Running Quartus Prime TimeQuest Timing Analyzer + Info: Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition + Info: Processing started: Sat Dec 10 18:50:42 2016 +Info: Command: quartus_sta ex17 -c ex17_top +Info: qsta_default_script.tcl version: #1 +Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. +Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected +Info (21077): Low junction temperature is 0 degrees C +Info (21077): High junction temperature is 85 degrees C +Info (332104): Reading SDC File: 'ex17_top.sdc' +Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty" +Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. +Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON +Info: Analyzing Slow 1100mV 85C Model +Info (332146): Worst-case setup slack is 7.864 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): 7.864 0.000 CLOCK_50 +Info (332146): Worst-case hold slack is 0.354 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): 0.354 0.000 CLOCK_50 +Info (332140): No Recovery paths to report +Info (332140): No Removal paths to report +Info (332146): Worst-case minimum pulse width slack is 8.877 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): 8.877 0.000 CLOCK_50 +Info: Analyzing Slow 1100mV 0C Model +Info (334003): Started post-fitting delay annotation +Info (334004): Delay annotation completed successfully +Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. +Info (332146): Worst-case setup slack is 7.952 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): 7.952 0.000 CLOCK_50 +Info (332146): Worst-case hold slack is 0.348 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): 0.348 0.000 CLOCK_50 +Info (332140): No Recovery paths to report +Info (332140): No Removal paths to report +Info (332146): Worst-case minimum pulse width slack is 8.912 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): 8.912 0.000 CLOCK_50 +Info: Analyzing Fast 1100mV 85C Model +Info (334003): Started post-fitting delay annotation +Info (334004): Delay annotation completed successfully +Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. +Info (332146): Worst-case setup slack is 8.618 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): 8.618 0.000 CLOCK_50 +Info (332146): Worst-case hold slack is 0.182 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): 0.182 0.000 CLOCK_50 +Info (332140): No Recovery paths to report +Info (332140): No Removal paths to report +Info (332146): Worst-case minimum pulse width slack is 8.480 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): 8.480 0.000 CLOCK_50 +Info: Analyzing Fast 1100mV 0C Model +Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. +Info (332146): Worst-case setup slack is 8.627 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): 8.627 0.000 CLOCK_50 +Info (332146): Worst-case hold slack is 0.173 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): 0.173 0.000 CLOCK_50 +Info (332140): No Recovery paths to report +Info (332140): No Removal paths to report +Info (332146): Worst-case minimum pulse width slack is 8.437 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): 8.437 0.000 CLOCK_50 +Info (332102): Design is not fully constrained for setup requirements +Info (332102): Design is not fully constrained for hold requirements +Info: Quartus Prime TimeQuest Timing Analyzer was successful. 0 errors, 1 warning + Info: Peak virtual memory: 1033 megabytes + Info: Processing ended: Sat Dec 10 18:52:02 2016 + Info: Elapsed time: 00:01:20 + Info: Total CPU time (on all processors): 00:00:13 + + diff --git a/part_4/ex17/single_echo.v b/part_4/ex17/single_echo.v new file mode 100644 index 0000000..c413689 --- /dev/null +++ b/part_4/ex17/single_echo.v @@ -0,0 +1,43 @@ +module processor (sysclk, data_in, data_out, data_valid); + + input sysclk; // system clock + input data_valid; + input [9:0] data_in; // 10-bit input data + output [9:0] data_out; // 10-bit output data + + wire sysclk; + wire [9:0] data_in; + reg [9:0] data_out; + wire [9:0] x,y,FIFO_out; + wire pulse; + wire FIFO_full, FIFO_empty; + reg full_reg; + + parameter ADC_OFFSET = 10'h181; + parameter DAC_OFFSET = 10'h200; + + assign x = data_in[9:0] - ADC_OFFSET; // x is input in 2's complement + + assign y = x + {FIFO_out[9],FIFO_out[9:1]}; + + pulse_gen PULSE0 (pulse, data_valid, sysclk); + + FIFO DELAY1024 ( + .clock(sysclk), + .data(x), + .full(FIFO_full), + .empty(FIFO_empty), + .wrreq(pulse), + .rdreq(pulse && full_reg), + .q(FIFO_out) + ); + + + // Now clock y output with system clock + always @ (posedge sysclk) + begin + full_reg <= FIFO_full; + data_out <= y + DAC_OFFSET; + end +endmodule + \ No newline at end of file diff --git a/part_4/ex18/FIFO.v b/part_4/ex18/FIFO.v new file mode 100644 index 0000000..34128f9 --- /dev/null +++ b/part_4/ex18/FIFO.v @@ -0,0 +1,159 @@ +// megafunction wizard: %FIFO% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: scfifo + +// ============================================================ +// File Name: FIFO.v +// Megafunction Name(s): +// scfifo +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 16.1.0 Build 196 10/24/2016 SJ Lite Edition +// ************************************************************ + + +//Copyright (C) 2016 Intel Corporation. All rights reserved. +//Your use of Intel Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Intel Program License +//Subscription Agreement, the Intel Quartus Prime License Agreement, +//the Intel MegaCore Function License Agreement, or other +//applicable license agreement, including, without limitation, +//that your use is for the sole purpose of programming logic +//devices manufactured by Intel and sold by Intel or its +//authorized distributors. Please refer to the applicable +//agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module FIFO ( + clock, + data, + rdreq, + wrreq, + empty, + full, + q); + + input clock; + input [9:0] data; + input rdreq; + input wrreq; + output empty; + output full; + output [9:0] q; + + wire sub_wire0; + wire sub_wire1; + wire [9:0] sub_wire2; + wire empty = sub_wire0; + wire full = sub_wire1; + wire [9:0] q = sub_wire2[9:0]; + + scfifo scfifo_component ( + .clock (clock), + .data (data), + .rdreq (rdreq), + .wrreq (wrreq), + .empty (sub_wire0), + .full (sub_wire1), + .q (sub_wire2), + .aclr (), + .almost_empty (), + .almost_full (), + .eccstatus (), + .sclr (), + .usedw ()); + defparam + scfifo_component.add_ram_output_register = "OFF", + scfifo_component.intended_device_family = "Cyclone V", + scfifo_component.lpm_numwords = 8192, + scfifo_component.lpm_showahead = "OFF", + scfifo_component.lpm_type = "scfifo", + scfifo_component.lpm_width = 10, + scfifo_component.lpm_widthu = 13, + scfifo_component.overflow_checking = "ON", + scfifo_component.underflow_checking = "ON", + scfifo_component.use_eab = "ON"; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0" +// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1" +// Retrieval info: PRIVATE: AlmostFull NUMERIC "0" +// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1" +// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0" +// Retrieval info: PRIVATE: Clock NUMERIC "0" +// Retrieval info: PRIVATE: Depth NUMERIC "8192" +// Retrieval info: PRIVATE: Empty NUMERIC "1" +// Retrieval info: PRIVATE: Full NUMERIC "1" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V" +// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0" +// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1" +// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0" +// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0" +// Retrieval info: PRIVATE: Optimize NUMERIC "0" +// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0" +// Retrieval info: PRIVATE: UsedW NUMERIC "0" +// Retrieval info: PRIVATE: Width NUMERIC "10" +// Retrieval info: PRIVATE: dc_aclr NUMERIC "0" +// Retrieval info: PRIVATE: diff_widths NUMERIC "0" +// Retrieval info: PRIVATE: msb_usedw NUMERIC "0" +// Retrieval info: PRIVATE: output_width NUMERIC "10" +// Retrieval info: PRIVATE: rsEmpty NUMERIC "1" +// Retrieval info: PRIVATE: rsFull NUMERIC "0" +// Retrieval info: PRIVATE: rsUsedW NUMERIC "0" +// Retrieval info: PRIVATE: sc_aclr NUMERIC "0" +// Retrieval info: PRIVATE: sc_sclr NUMERIC "0" +// Retrieval info: PRIVATE: wsEmpty NUMERIC "0" +// Retrieval info: PRIVATE: wsFull NUMERIC "1" +// Retrieval info: PRIVATE: wsUsedW NUMERIC "0" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V" +// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "8192" +// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF" +// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo" +// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "10" +// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "13" +// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON" +// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON" +// Retrieval info: CONSTANT: USE_EAB STRING "ON" +// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock" +// Retrieval info: USED_PORT: data 0 0 10 0 INPUT NODEFVAL "data[9..0]" +// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL "empty" +// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL "full" +// Retrieval info: USED_PORT: q 0 0 10 0 OUTPUT NODEFVAL "q[9..0]" +// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq" +// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq" +// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 +// Retrieval info: CONNECT: @data 0 0 10 0 data 0 0 10 0 +// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0 +// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0 +// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0 +// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0 +// Retrieval info: CONNECT: q 0 0 10 0 @q 0 0 10 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL FIFO.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL FIFO.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL FIFO.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL FIFO.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL FIFO_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL FIFO_bb.v TRUE +// Retrieval info: LIB_FILE: altera_mf diff --git a/part_4/ex18/FIFO_bb.v b/part_4/ex18/FIFO_bb.v new file mode 100644 index 0000000..ae93f52 --- /dev/null +++ b/part_4/ex18/FIFO_bb.v @@ -0,0 +1,120 @@ +// megafunction wizard: %FIFO%VBB% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: scfifo + +// ============================================================ +// File Name: FIFO.v +// Megafunction Name(s): +// scfifo +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 16.1.0 Build 196 10/24/2016 SJ Lite Edition +// ************************************************************ + +//Copyright (C) 2016 Intel Corporation. All rights reserved. +//Your use of Intel Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Intel Program License +//Subscription Agreement, the Intel Quartus Prime License Agreement, +//the Intel MegaCore Function License Agreement, or other +//applicable license agreement, including, without limitation, +//that your use is for the sole purpose of programming logic +//devices manufactured by Intel and sold by Intel or its +//authorized distributors. Please refer to the applicable +//agreement for further details. + +module FIFO ( + clock, + data, + rdreq, + wrreq, + empty, + full, + q); + + input clock; + input [9:0] data; + input rdreq; + input wrreq; + output empty; + output full; + output [9:0] q; + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0" +// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1" +// Retrieval info: PRIVATE: AlmostFull NUMERIC "0" +// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1" +// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0" +// Retrieval info: PRIVATE: Clock NUMERIC "0" +// Retrieval info: PRIVATE: Depth NUMERIC "8192" +// Retrieval info: PRIVATE: Empty NUMERIC "1" +// Retrieval info: PRIVATE: Full NUMERIC "1" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V" +// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0" +// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1" +// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0" +// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0" +// Retrieval info: PRIVATE: Optimize NUMERIC "0" +// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0" +// Retrieval info: PRIVATE: UsedW NUMERIC "0" +// Retrieval info: PRIVATE: Width NUMERIC "10" +// Retrieval info: PRIVATE: dc_aclr NUMERIC "0" +// Retrieval info: PRIVATE: diff_widths NUMERIC "0" +// Retrieval info: PRIVATE: msb_usedw NUMERIC "0" +// Retrieval info: PRIVATE: output_width NUMERIC "10" +// Retrieval info: PRIVATE: rsEmpty NUMERIC "1" +// Retrieval info: PRIVATE: rsFull NUMERIC "0" +// Retrieval info: PRIVATE: rsUsedW NUMERIC "0" +// Retrieval info: PRIVATE: sc_aclr NUMERIC "0" +// Retrieval info: PRIVATE: sc_sclr NUMERIC "0" +// Retrieval info: PRIVATE: wsEmpty NUMERIC "0" +// Retrieval info: PRIVATE: wsFull NUMERIC "1" +// Retrieval info: PRIVATE: wsUsedW NUMERIC "0" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V" +// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "8192" +// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF" +// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo" +// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "10" +// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "13" +// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON" +// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON" +// Retrieval info: CONSTANT: USE_EAB STRING "ON" +// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock" +// Retrieval info: USED_PORT: data 0 0 10 0 INPUT NODEFVAL "data[9..0]" +// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL "empty" +// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL "full" +// Retrieval info: USED_PORT: q 0 0 10 0 OUTPUT NODEFVAL "q[9..0]" +// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq" +// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq" +// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 +// Retrieval info: CONNECT: @data 0 0 10 0 data 0 0 10 0 +// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0 +// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0 +// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0 +// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0 +// Retrieval info: CONNECT: q 0 0 10 0 @q 0 0 10 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL FIFO.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL FIFO.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL FIFO.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL FIFO.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL FIFO_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL FIFO_bb.v TRUE +// Retrieval info: LIB_FILE: altera_mf diff --git a/part_4/ex18/ex18_top.v b/part_4/ex18/ex18_top.v new file mode 100644 index 0000000..93816d2 --- /dev/null +++ b/part_4/ex18/ex18_top.v @@ -0,0 +1,48 @@ +module ex18_top (CLOCK_50, SW, HEX0, HEX1, HEX2, + DAC_SDI, DAC_SCK, DAC_CS, DAC_LD, + ADC_SDI, ADC_SCK, ADC_CS, ADC_SDO, PWM_OUT); + + input CLOCK_50; // DE0 50MHz system clock + input [9:0] SW; // 10 slide switches to specify address to ROM + output [6:0] HEX0, HEX1, HEX2; + output DAC_SDI; //Serial data out to SDI of the DAC + output DAC_SCK; //Serial clock signal to both DAC and ADC + output DAC_CS; //Chip select to the DAC, low active + output DAC_LD; //Load new data to DAC, low active + output ADC_SDI; //Serial data out to SDI of the ADC + output ADC_SCK; // ADC Clock signal + output ADC_CS; //Chip select to the ADC, low active + input ADC_SDO; //Converted serial data from ADC + output PWM_OUT; // PWM output to R channel + + wire tick_10k; // internal clock at 10kHz + wire [9:0] data_in; // converted data from ADC + wire [9:0] data_out; // processed data to DAC + wire data_valid; + wire DAC_SCK, ADC_SCK; + + clktick_16 GEN_10K (CLOCK_50, 1'b1, 16'd4999, tick_10k); // generate 10KHz sampling clock ticks + spi2dac SPI_DAC (CLOCK_50, data_out, tick_10k, // send processed sample to DAC + DAC_SDI, DAC_CS, DAC_SCK, DAC_LD); // order of signals matter + pwm PWM_DC(CLOCK_50, data_out, tick_10k, PWM_OUT); // output via PWM - R-channel + + spi2adc SPI_ADC ( // perform a A-to-D conversion + .sysclk (CLOCK_50), // order of parameters do not matter + .channel (1'b1), // use only CH1 + .start (tick_10k), + .data_from_adc (data_in), + .data_valid (data_valid), + .sdata_to_adc (ADC_SDI), + .adc_cs (ADC_CS), + .adc_sck (ADC_SCK), + .sdata_from_adc (ADC_SDO)); + + processor ALLPASS (CLOCK_50, data_in, data_out, data_valid); // do some processing on the data + + hex_to_7seg SEG0 (HEX0, data_in[3:0]); + hex_to_7seg SEG1 (HEX1, data_in[7:4]); + hex_to_7seg SEG2 (HEX2, {2'b0,data_in[9:8]}); + +endmodule + + diff --git a/part_4/ex18/multi_echo.v b/part_4/ex18/multi_echo.v new file mode 100644 index 0000000..74df5a6 --- /dev/null +++ b/part_4/ex18/multi_echo.v @@ -0,0 +1,52 @@ +//------------------------------ +// Module name: allpass processor +// Function: Simply to pass input to output +// Creator: Peter Cheung +// Version: 1.1 +// Date: 24 Jan 2014 +//------------------------------ + +module processor (sysclk, data_in, data_out, data_valid); + + input sysclk; // system clock + input data_valid; + input [9:0] data_in; // 10-bit input data + output [9:0] data_out; // 10-bit output data + + wire sysclk; + wire [9:0] data_in; + reg [9:0] data_out; + wire [9:0] x,y,FIFO_out; + wire pulse; + wire FIFO_full, FIFO_empty; + reg full_reg; + + parameter ADC_OFFSET = 10'h181; + parameter DAC_OFFSET = 10'h200; + + assign x = data_in[9:0] - ADC_OFFSET; // x is input in 2's complement + + assign y = x - {FIFO_out[9],FIFO_out[9:1]}; + + pulse_gen PULSE0 (pulse, data_valid, sysclk); + + FIFO DELAY1024 ( + .clock(sysclk), + .data(y), + .full(FIFO_full), + .empty(FIFO_empty), + .wrreq(pulse), + .rdreq(pulse && full_reg), + .q(FIFO_out) + ); + + + // Now clock y output with system clock + always @(posedge sysclk) + begin + full_reg <= FIFO_full; + data_out <= y + DAC_OFFSET; + end + +endmodule + \ No newline at end of file diff --git a/part_4/ex18/output_files/ex18_top.asm.rpt b/part_4/ex18/output_files/ex18_top.asm.rpt new file mode 100644 index 0000000..7a64d80 --- /dev/null +++ b/part_4/ex18/output_files/ex18_top.asm.rpt @@ -0,0 +1,92 @@ +Assembler report for ex18_top +Sat Dec 10 19:03:26 2016 +Quartus Prime Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Assembler Summary + 3. Assembler Settings + 4. Assembler Generated Files + 5. Assembler Device Options: H:/Year 2/VERI/part_4/ex18/output_files/ex18_top.sof + 6. Assembler Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2016 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel MegaCore Function License Agreement, or other +applicable license agreement, including, without limitation, +that your use is for the sole purpose of programming logic +devices manufactured by Intel and sold by Intel or its +authorized distributors. Please refer to the applicable +agreement for further details. + + + ++---------------------------------------------------------------+ +; Assembler Summary ; ++-----------------------+---------------------------------------+ +; Assembler Status ; Successful - Sat Dec 10 19:03:26 2016 ; +; Revision Name ; ex18_top ; +; Top-level Entity Name ; ex18_top ; +; Family ; Cyclone V ; +; Device ; 5CSEMA5F31C6 ; ++-----------------------+---------------------------------------+ + + ++----------------------------------+ +; Assembler Settings ; ++--------+---------+---------------+ +; Option ; Setting ; Default Value ; ++--------+---------+---------------+ + + ++------------------------------------------------------+ +; Assembler Generated Files ; ++------------------------------------------------------+ +; File Name ; ++------------------------------------------------------+ +; H:/Year 2/VERI/part_4/ex18/output_files/ex18_top.sof ; ++------------------------------------------------------+ + + ++--------------------------------------------------------------------------------+ +; Assembler Device Options: H:/Year 2/VERI/part_4/ex18/output_files/ex18_top.sof ; ++----------------+---------------------------------------------------------------+ +; Option ; Setting ; ++----------------+---------------------------------------------------------------+ +; Device ; 5CSEMA5F31C6 ; +; JTAG usercode ; 0x00DFEA2A ; +; Checksum ; 0x00DFEA2A ; ++----------------+---------------------------------------------------------------+ + + ++--------------------+ +; Assembler Messages ; ++--------------------+ +Info: ******************************************************************* +Info: Running Quartus Prime Assembler + Info: Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition + Info: Processing started: Sat Dec 10 19:02:37 2016 +Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off ex18 -c ex18_top +Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. +Info (115030): Assembler is generating device programming files +Info: Quartus Prime Assembler was successful. 0 errors, 1 warning + Info: Peak virtual memory: 727 megabytes + Info: Processing ended: Sat Dec 10 19:03:28 2016 + Info: Elapsed time: 00:00:51 + Info: Total CPU time (on all processors): 00:00:13 + + diff --git a/part_4/ex18/output_files/ex18_top.fit.rpt b/part_4/ex18/output_files/ex18_top.fit.rpt new file mode 100644 index 0000000..d58d4bb --- /dev/null +++ b/part_4/ex18/output_files/ex18_top.fit.rpt @@ -0,0 +1,2039 @@ +Fitter report for ex18_top +Sat Dec 10 19:01:37 2016 +Quartus Prime Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Fitter Summary + 3. Fitter Settings + 4. Parallel Compilation + 5. Fitter Netlist Optimizations + 6. Incremental Compilation Preservation Summary + 7. Incremental Compilation Partition Settings + 8. Incremental Compilation Placement Preservation + 9. Pin-Out File + 10. Fitter Resource Usage Summary + 11. Fitter Partition Statistics + 12. Input Pins + 13. Output Pins + 14. I/O Bank Usage + 15. All Package Pins + 16. I/O Assignment Warnings + 17. Fitter Resource Utilization by Entity + 18. Delay Chain Summary + 19. Pad To Core Delay Chain Fanout + 20. Control Signals + 21. Global & Other Fast Signals + 22. Fitter RAM Summary + 23. Routing Usage Summary + 24. I/O Rules Summary + 25. I/O Rules Details + 26. I/O Rules Matrix + 27. Fitter Device Options + 28. Operating Settings and Conditions + 29. Estimated Delay Added for Hold Timing Summary + 30. Estimated Delay Added for Hold Timing Details + 31. Fitter Messages + 32. Fitter Suppressed Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2016 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel MegaCore Function License Agreement, or other +applicable license agreement, including, without limitation, +that your use is for the sole purpose of programming logic +devices manufactured by Intel and sold by Intel or its +authorized distributors. Please refer to the applicable +agreement for further details. + + + ++-------------------------------------------------------------------------------+ +; Fitter Summary ; ++---------------------------------+---------------------------------------------+ +; Fitter Status ; Successful - Sat Dec 10 19:01:37 2016 ; +; Quartus Prime Version ; 16.1.0 Build 196 10/24/2016 SJ Lite Edition ; +; Revision Name ; ex18_top ; +; Top-level Entity Name ; ex18_top ; +; Family ; Cyclone V ; +; Device ; 5CSEMA5F31C6 ; +; Timing Models ; Final ; +; Logic utilization (in ALMs) ; 91 / 32,070 ( < 1 % ) ; +; Total registers ; 170 ; +; Total pins ; 41 / 457 ( 9 % ) ; +; Total virtual pins ; 0 ; +; Total block memory bits ; 73,728 / 4,065,280 ( 2 % ) ; +; Total RAM Blocks ; 9 / 397 ( 2 % ) ; +; Total DSP Blocks ; 0 / 87 ( 0 % ) ; +; Total HSSI RX PCSs ; 0 ; +; Total HSSI PMA RX Deserializers ; 0 ; +; Total HSSI TX PCSs ; 0 ; +; Total HSSI PMA TX Serializers ; 0 ; +; Total PLLs ; 0 / 6 ( 0 % ) ; +; Total DLLs ; 0 / 4 ( 0 % ) ; ++---------------------------------+---------------------------------------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fitter Settings ; ++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+ +; Option ; Setting ; Default Value ; ++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+ +; Device ; 5CSEMA5F31C6 ; ; +; Minimum Core Junction Temperature ; 0 ; ; +; Maximum Core Junction Temperature ; 85 ; ; +; Use smart compilation ; Off ; Off ; +; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ; +; Enable compact report table ; Off ; Off ; +; Router Timing Optimization Level ; Normal ; Normal ; +; Perform Clocking Topology Analysis During Routing ; Off ; Off ; +; Placement Effort Multiplier ; 1.0 ; 1.0 ; +; Device initialization clock source ; INIT_INTOSC ; INIT_INTOSC ; +; Optimize Hold Timing ; All Paths ; All Paths ; +; Optimize Multi-Corner Timing ; On ; On ; +; Auto RAM to MLAB Conversion ; On ; On ; +; Equivalent RAM and MLAB Power Up ; Auto ; Auto ; +; Equivalent RAM and MLAB Paused Read Capabilities ; Care ; Care ; +; PowerPlay Power Optimization During Fitting ; Normal compilation ; Normal compilation ; +; SSN Optimization ; Off ; Off ; +; Optimize Timing ; Normal compilation ; Normal compilation ; +; Optimize Timing for ECOs ; Off ; Off ; +; Regenerate Full Fit Report During ECO Compiles ; Off ; Off ; +; Optimize IOC Register Placement for Timing ; Normal ; Normal ; +; Final Placement Optimizations ; Automatically ; Automatically ; +; Fitter Aggressive Routability Optimizations ; Automatically ; Automatically ; +; Fitter Initial Placement Seed ; 1 ; 1 ; +; Periphery to Core Placement and Routing Optimization ; Off ; Off ; +; Weak Pull-Up Resistor ; Off ; Off ; +; Enable Bus-Hold Circuitry ; Off ; Off ; +; Auto Packed Registers ; Auto ; Auto ; +; Auto Delay Chains ; On ; On ; +; Auto Delay Chains for High Fanout Input Pins ; Off ; Off ; +; Treat Bidirectional Pin as Output Pin ; Off ; Off ; +; Perform Physical Synthesis for Combinational Logic for Fitting ; Off ; Off ; +; Perform Physical Synthesis for Combinational Logic for Performance ; Off ; Off ; +; Perform Register Duplication for Performance ; Off ; Off ; +; Perform Register Retiming for Performance ; Off ; Off ; +; Perform Asynchronous Signal Pipelining ; Off ; Off ; +; Fitter Effort ; Auto Fit ; Auto Fit ; +; Physical Synthesis Effort Level ; Normal ; Normal ; +; Logic Cell Insertion - Logic Duplication ; Auto ; Auto ; +; Auto Register Duplication ; Auto ; Auto ; +; Auto Global Clock ; On ; On ; +; Auto Global Register Control Signals ; On ; On ; +; Reserve all unused pins ; As input tri-stated with weak pull-up ; As input tri-stated with weak pull-up ; +; Synchronizer Identification ; Auto ; Auto ; +; Enable Beneficial Skew Optimization ; On ; On ; +; Optimize Design for Metastability ; On ; On ; +; Active Serial clock source ; FREQ_100MHz ; FREQ_100MHz ; +; Force Fitter to Avoid Periphery Placement Warnings ; Off ; Off ; +; Clamping Diode ; Off ; Off ; +; Enable input tri-state on active configuration pins in user mode ; Off ; Off ; +; Advanced Physical Optimization ; On ; On ; ++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+ + + ++------------------------------------------+ +; Parallel Compilation ; ++----------------------------+-------------+ +; Processors ; Number ; ++----------------------------+-------------+ +; Number detected on machine ; 2 ; +; Maximum allowed ; 2 ; +; ; ; +; Average used ; 1.01 ; +; Maximum used ; 2 ; +; ; ; +; Usage by Processor ; % Time Used ; +; Processor 1 ; 100.0% ; +; Processor 2 ; 0.7% ; ++----------------------------+-------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fitter Netlist Optimizations ; ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------+---------------------------------------------------+----------------------------+-----------+----------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------+-----------------------+ +; Node ; Action ; Operation ; Reason ; Node Port ; Node Port Name ; Destination Node ; Destination Port ; Destination Port Name ; ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------+---------------------------------------------------+----------------------------+-----------+----------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------+-----------------------+ +; CLOCK_50~inputCLKENA0 ; Created ; Placement ; Fitter Periphery Placement ; ; ; ; ; ; +; clktick_16:GEN_10K|count[4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; clktick_16:GEN_10K|count[4]~DUPLICATE ; ; ; +; clktick_16:GEN_10K|count[15] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; clktick_16:GEN_10K|count[15]~DUPLICATE ; ; ; +; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|a_fefifo_4be:fifo_state|cntr_di7:count_usedw|counter_reg_bit[0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|a_fefifo_4be:fifo_state|cntr_di7:count_usedw|counter_reg_bit[0]~DUPLICATE ; ; ; +; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|cntr_1ib:rd_ptr_count|counter_reg_bit[1] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|cntr_1ib:rd_ptr_count|counter_reg_bit[1]~DUPLICATE ; ; ; +; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|cntr_1ib:rd_ptr_count|counter_reg_bit[3] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|cntr_1ib:rd_ptr_count|counter_reg_bit[3]~DUPLICATE ; ; ; +; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|cntr_1ib:wr_ptr|counter_reg_bit[3] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|cntr_1ib:wr_ptr|counter_reg_bit[3]~DUPLICATE ; ; ; +; processor:ALLPASS|data_out[3] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; processor:ALLPASS|data_out[3]~DUPLICATE ; ; ; +; processor:ALLPASS|pulse_gen:PULSE0|pulse ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; processor:ALLPASS|pulse_gen:PULSE0|pulse~DUPLICATE ; ; ; +; spi2adc:SPI_ADC|adc_start ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; spi2adc:SPI_ADC|adc_start~DUPLICATE ; ; ; +; spi2adc:SPI_ADC|clk_1MHz ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; spi2adc:SPI_ADC|clk_1MHz~DUPLICATE ; ; ; +; spi2adc:SPI_ADC|ctr[0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; spi2adc:SPI_ADC|ctr[0]~DUPLICATE ; ; ; +; spi2adc:SPI_ADC|sr_state.IDLE ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; spi2adc:SPI_ADC|sr_state.IDLE~DUPLICATE ; ; ; +; spi2adc:SPI_ADC|state[0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; spi2adc:SPI_ADC|state[0]~DUPLICATE ; ; ; +; spi2adc:SPI_ADC|state[1] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; spi2adc:SPI_ADC|state[1]~DUPLICATE ; ; ; +; spi2adc:SPI_ADC|state[3] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; spi2adc:SPI_ADC|state[3]~DUPLICATE ; ; ; +; spi2dac:SPI_DAC|state[1] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; spi2dac:SPI_DAC|state[1]~DUPLICATE ; ; ; +; spi2dac:SPI_DAC|state[3] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; spi2dac:SPI_DAC|state[3]~DUPLICATE ; ; ; ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------+---------------------------------------------------+----------------------------+-----------+----------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------+-----------------------+ + + ++--------------------------------------------------------------------------------------------------+ +; Incremental Compilation Preservation Summary ; ++---------------------+--------------------+----------------------------+--------------------------+ +; Type ; Total [A + B] ; From Design Partitions [A] ; From Rapid Recompile [B] ; ++---------------------+--------------------+----------------------------+--------------------------+ +; Placement (by node) ; ; ; ; +; -- Requested ; 0.00 % ( 0 / 404 ) ; 0.00 % ( 0 / 404 ) ; 0.00 % ( 0 / 404 ) ; +; -- Achieved ; 0.00 % ( 0 / 404 ) ; 0.00 % ( 0 / 404 ) ; 0.00 % ( 0 / 404 ) ; +; ; ; ; ; +; Routing (by net) ; ; ; ; +; -- Requested ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; +; -- Achieved ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; ++---------------------+--------------------+----------------------------+--------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Incremental Compilation Partition Settings ; ++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+ +; Partition Name ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents ; ++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+ +; Top ; User-created ; Source File ; N/A ; Source File ; N/A ; ; +; hard_block:auto_generated_inst ; Auto-generated ; Source File ; N/A ; Source File ; N/A ; hard_block:auto_generated_inst ; ++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------+ +; Incremental Compilation Placement Preservation ; ++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+ +; Partition Name ; Preservation Achieved ; Preservation Level Used ; Netlist Type Used ; Preservation Method ; Notes ; ++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+ +; Top ; 0.00 % ( 0 / 404 ) ; N/A ; Source File ; N/A ; ; +; hard_block:auto_generated_inst ; 0.00 % ( 0 / 0 ) ; N/A ; Source File ; N/A ; ; ++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+ + + ++--------------+ +; Pin-Out File ; ++--------------+ +The pin-out file can be found in H:/Year 2/VERI/part_4/ex18/output_files/ex18_top.pin. + + ++------------------------------------------------------------------------------------------+ +; Fitter Resource Usage Summary ; ++-------------------------------------------------------------+--------------------+-------+ +; Resource ; Usage ; % ; ++-------------------------------------------------------------+--------------------+-------+ +; Logic utilization (ALMs needed / total ALMs on device) ; 91 / 32,070 ; < 1 % ; +; ALMs needed [=A-B+C] ; 91 ; ; +; [A] ALMs used in final placement [=a+b+c+d] ; 104 / 32,070 ; < 1 % ; +; [a] ALMs used for LUT logic and registers ; 63 ; ; +; [b] ALMs used for LUT logic ; 27 ; ; +; [c] ALMs used for registers ; 14 ; ; +; [d] ALMs used for memory (up to half of total ALMs) ; 0 ; ; +; [B] Estimate of ALMs recoverable by dense packing ; 13 / 32,070 ; < 1 % ; +; [C] Estimate of ALMs unavailable [=a+b+c+d] ; 0 / 32,070 ; 0 % ; +; [a] Due to location constrained logic ; 0 ; ; +; [b] Due to LAB-wide signal conflicts ; 0 ; ; +; [c] Due to LAB input limits ; 0 ; ; +; [d] Due to virtual I/Os ; 0 ; ; +; ; ; ; +; Difficulty packing design ; Low ; ; +; ; ; ; +; Total LABs: partially or completely used ; 17 / 3,207 ; < 1 % ; +; -- Logic LABs ; 17 ; ; +; -- Memory LABs (up to half of total LABs) ; 0 ; ; +; ; ; ; +; Combinational ALUT usage for logic ; 159 ; ; +; -- 7 input functions ; 0 ; ; +; -- 6 input functions ; 10 ; ; +; -- 5 input functions ; 23 ; ; +; -- 4 input functions ; 31 ; ; +; -- <=3 input functions ; 95 ; ; +; Combinational ALUT usage for route-throughs ; 20 ; ; +; ; ; ; +; Dedicated logic registers ; 170 ; ; +; -- By type: ; ; ; +; -- Primary logic registers ; 153 / 64,140 ; < 1 % ; +; -- Secondary logic registers ; 17 / 64,140 ; < 1 % ; +; -- By function: ; ; ; +; -- Design implementation registers ; 153 ; ; +; -- Routing optimization registers ; 17 ; ; +; ; ; ; +; Virtual pins ; 0 ; ; +; I/O pins ; 41 / 457 ; 9 % ; +; -- Clock pins ; 3 / 8 ; 38 % ; +; -- Dedicated input pins ; 0 / 21 ; 0 % ; +; ; ; ; +; Hard processor system peripheral utilization ; ; ; +; -- Boot from FPGA ; 0 / 1 ( 0 % ) ; ; +; -- Clock resets ; 0 / 1 ( 0 % ) ; ; +; -- Cross trigger ; 0 / 1 ( 0 % ) ; ; +; -- S2F AXI ; 0 / 1 ( 0 % ) ; ; +; -- F2S AXI ; 0 / 1 ( 0 % ) ; ; +; -- AXI Lightweight ; 0 / 1 ( 0 % ) ; ; +; -- SDRAM ; 0 / 1 ( 0 % ) ; ; +; -- Interrupts ; 0 / 1 ( 0 % ) ; ; +; -- JTAG ; 0 / 1 ( 0 % ) ; ; +; -- Loan I/O ; 0 / 1 ( 0 % ) ; ; +; -- MPU event standby ; 0 / 1 ( 0 % ) ; ; +; -- MPU general purpose ; 0 / 1 ( 0 % ) ; ; +; -- STM event ; 0 / 1 ( 0 % ) ; ; +; -- TPIU trace ; 0 / 1 ( 0 % ) ; ; +; -- DMA ; 0 / 1 ( 0 % ) ; ; +; -- CAN ; 0 / 2 ( 0 % ) ; ; +; -- EMAC ; 0 / 2 ( 0 % ) ; ; +; -- I2C ; 0 / 4 ( 0 % ) ; ; +; -- NAND Flash ; 0 / 1 ( 0 % ) ; ; +; -- QSPI ; 0 / 1 ( 0 % ) ; ; +; -- SDMMC ; 0 / 1 ( 0 % ) ; ; +; -- SPI Master ; 0 / 2 ( 0 % ) ; ; +; -- SPI Slave ; 0 / 2 ( 0 % ) ; ; +; -- UART ; 0 / 2 ( 0 % ) ; ; +; -- USB ; 0 / 2 ( 0 % ) ; ; +; ; ; ; +; M10K blocks ; 9 / 397 ; 2 % ; +; Total MLAB memory bits ; 0 ; ; +; Total block memory bits ; 73,728 / 4,065,280 ; 2 % ; +; Total block memory implementation bits ; 92,160 / 4,065,280 ; 2 % ; +; ; ; ; +; Total DSP Blocks ; 0 / 87 ; 0 % ; +; ; ; ; +; Fractional PLLs ; 0 / 6 ; 0 % ; +; Global signals ; 1 ; ; +; -- Global clocks ; 1 / 16 ; 6 % ; +; -- Quadrant clocks ; 0 / 66 ; 0 % ; +; -- Horizontal periphery clocks ; 0 / 18 ; 0 % ; +; SERDES Transmitters ; 0 / 100 ; 0 % ; +; SERDES Receivers ; 0 / 100 ; 0 % ; +; JTAGs ; 0 / 1 ; 0 % ; +; ASMI blocks ; 0 / 1 ; 0 % ; +; CRC blocks ; 0 / 1 ; 0 % ; +; Remote update blocks ; 0 / 1 ; 0 % ; +; Oscillator blocks ; 0 / 1 ; 0 % ; +; Impedance control blocks ; 0 / 4 ; 0 % ; +; Hard Memory Controllers ; 0 / 2 ; 0 % ; +; Average interconnect usage (total/H/V) ; 0.1% / 0.1% / 0.1% ; ; +; Peak interconnect usage (total/H/V) ; 2.8% / 3.3% / 1.4% ; ; +; Maximum fan-out ; 188 ; ; +; Highest non-global fan-out ; 44 ; ; +; Total fan-out ; 1335 ; ; +; Average fan-out ; 3.03 ; ; ++-------------------------------------------------------------+--------------------+-------+ + + ++----------------------------------------------------------------------------------------------------------------------+ +; Fitter Partition Statistics ; ++-------------------------------------------------------------+-----------------------+--------------------------------+ +; Statistic ; Top ; hard_block:auto_generated_inst ; ++-------------------------------------------------------------+-----------------------+--------------------------------+ +; Logic utilization (ALMs needed / total ALMs on device) ; 91 / 32070 ( < 1 % ) ; 0 / 32070 ( 0 % ) ; +; ALMs needed [=A-B+C] ; 91 ; 0 ; +; [A] ALMs used in final placement [=a+b+c+d] ; 104 / 32070 ( < 1 % ) ; 0 / 32070 ( 0 % ) ; +; [a] ALMs used for LUT logic and registers ; 63 ; 0 ; +; [b] ALMs used for LUT logic ; 27 ; 0 ; +; [c] ALMs used for registers ; 14 ; 0 ; +; [d] ALMs used for memory (up to half of total ALMs) ; 0 ; 0 ; +; [B] Estimate of ALMs recoverable by dense packing ; 13 / 32070 ( < 1 % ) ; 0 / 32070 ( 0 % ) ; +; [C] Estimate of ALMs unavailable [=a+b+c+d] ; 0 / 32070 ( 0 % ) ; 0 / 32070 ( 0 % ) ; +; [a] Due to location constrained logic ; 0 ; 0 ; +; [b] Due to LAB-wide signal conflicts ; 0 ; 0 ; +; [c] Due to LAB input limits ; 0 ; 0 ; +; [d] Due to virtual I/Os ; 0 ; 0 ; +; ; ; ; +; Difficulty packing design ; Low ; Low ; +; ; ; ; +; Total LABs: partially or completely used ; 17 / 3207 ( < 1 % ) ; 0 / 3207 ( 0 % ) ; +; -- Logic LABs ; 17 ; 0 ; +; -- Memory LABs (up to half of total LABs) ; 0 ; 0 ; +; ; ; ; +; Combinational ALUT usage for logic ; 159 ; 0 ; +; -- 7 input functions ; 0 ; 0 ; +; -- 6 input functions ; 10 ; 0 ; +; -- 5 input functions ; 23 ; 0 ; +; -- 4 input functions ; 31 ; 0 ; +; -- <=3 input functions ; 95 ; 0 ; +; Combinational ALUT usage for route-throughs ; 20 ; 0 ; +; Memory ALUT usage ; 0 ; 0 ; +; -- 64-address deep ; 0 ; 0 ; +; -- 32-address deep ; 0 ; 0 ; +; ; ; ; +; Dedicated logic registers ; 0 ; 0 ; +; -- By type: ; ; ; +; -- Primary logic registers ; 153 / 64140 ( < 1 % ) ; 0 / 64140 ( 0 % ) ; +; -- Secondary logic registers ; 17 / 64140 ( < 1 % ) ; 0 / 64140 ( 0 % ) ; +; -- By function: ; ; ; +; -- Design implementation registers ; 153 ; 0 ; +; -- Routing optimization registers ; 17 ; 0 ; +; ; ; ; +; ; ; ; +; Virtual pins ; 0 ; 0 ; +; I/O pins ; 41 ; 0 ; +; I/O registers ; 0 ; 0 ; +; Total block memory bits ; 73728 ; 0 ; +; Total block memory implementation bits ; 92160 ; 0 ; +; M10K block ; 9 / 397 ( 2 % ) ; 0 / 397 ( 0 % ) ; +; Clock enable block ; 1 / 116 ( < 1 % ) ; 0 / 116 ( 0 % ) ; +; ; ; ; +; Connections ; ; ; +; -- Input Connections ; 0 ; 0 ; +; -- Registered Input Connections ; 0 ; 0 ; +; -- Output Connections ; 0 ; 0 ; +; -- Registered Output Connections ; 0 ; 0 ; +; ; ; ; +; Internal Connections ; ; ; +; -- Total Connections ; 1488 ; 0 ; +; -- Registered Connections ; 720 ; 0 ; +; ; ; ; +; External Connections ; ; ; +; -- Top ; 0 ; 0 ; +; -- hard_block:auto_generated_inst ; 0 ; 0 ; +; ; ; ; +; Partition Interface ; ; ; +; -- Input Ports ; 12 ; 0 ; +; -- Output Ports ; 29 ; 0 ; +; -- Bidir Ports ; 0 ; 0 ; +; ; ; ; +; Registered Ports ; ; ; +; -- Registered Input Ports ; 0 ; 0 ; +; -- Registered Output Ports ; 0 ; 0 ; +; ; ; ; +; Port Connectivity ; ; ; +; -- Input Ports driven by GND ; 0 ; 0 ; +; -- Output Ports driven by GND ; 0 ; 0 ; +; -- Input Ports driven by VCC ; 0 ; 0 ; +; -- Output Ports driven by VCC ; 0 ; 0 ; +; -- Input Ports with no Source ; 0 ; 0 ; +; -- Output Ports with no Source ; 0 ; 0 ; +; -- Input Ports with no Fanout ; 0 ; 0 ; +; -- Output Ports with no Fanout ; 0 ; 0 ; ++-------------------------------------------------------------+-----------------------+--------------------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Input Pins ; ++----------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+ +; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Termination Control Block ; Location assigned by ; Slew Rate ; ++----------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+ +; ADC_SDO ; AH19 ; 4A ; 58 ; 0 ; 91 ; 1 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; no ; +; CLOCK_50 ; Y27 ; 5B ; 89 ; 25 ; 20 ; 188 ; 0 ; yes ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; no ; +; SW[0] ; AK9 ; 3B ; 30 ; 0 ; 51 ; 0 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; no ; +; SW[1] ; AF21 ; 4A ; 70 ; 0 ; 17 ; 0 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; no ; +; SW[2] ; AH15 ; 3B ; 38 ; 0 ; 17 ; 0 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; no ; +; SW[3] ; AJ22 ; 4A ; 70 ; 0 ; 51 ; 0 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; no ; +; SW[4] ; Y21 ; 5A ; 89 ; 6 ; 20 ; 0 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; no ; +; SW[5] ; J10 ; 8A ; 4 ; 81 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; no ; +; SW[6] ; B3 ; 8A ; 14 ; 81 ; 51 ; 0 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; no ; +; SW[7] ; C7 ; 8A ; 32 ; 81 ; 34 ; 0 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; no ; +; SW[8] ; AE7 ; 3A ; 6 ; 0 ; 17 ; 0 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; no ; +; SW[9] ; AD7 ; 3A ; 6 ; 0 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; no ; ++----------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Output Pins ; ++---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+ +; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Output Buffer Delay ; Output Buffer Delay Control ; Location assigned by ; Output Enable Source ; Output Enable Group ; ++---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+ +; ADC_CS ; AH18 ; 4A ; 56 ; 0 ; 51 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ; +; ADC_SCK ; AJ21 ; 4A ; 62 ; 0 ; 51 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ; +; ADC_SDI ; AH17 ; 4A ; 56 ; 0 ; 34 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ; +; DAC_CS ; AH20 ; 4A ; 54 ; 0 ; 17 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ; +; DAC_LD ; AJ20 ; 4A ; 62 ; 0 ; 34 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ; +; DAC_SCK ; AA16 ; 4A ; 56 ; 0 ; 0 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ; +; DAC_SDI ; AK18 ; 4A ; 58 ; 0 ; 57 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ; +; HEX0[0] ; AE16 ; 4A ; 52 ; 0 ; 34 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ; +; HEX0[1] ; AE17 ; 4A ; 50 ; 0 ; 40 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ; +; HEX0[2] ; AF16 ; 4A ; 52 ; 0 ; 51 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ; +; HEX0[3] ; AJ16 ; 4A ; 54 ; 0 ; 34 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ; +; HEX0[4] ; W16 ; 4A ; 52 ; 0 ; 17 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ; +; HEX0[5] ; V16 ; 4A ; 52 ; 0 ; 0 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ; +; HEX0[6] ; AB17 ; 4A ; 56 ; 0 ; 17 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ; +; HEX1[0] ; AG16 ; 4A ; 50 ; 0 ; 74 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ; +; HEX1[1] ; AK19 ; 4A ; 60 ; 0 ; 51 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ; +; HEX1[2] ; AJ17 ; 4A ; 58 ; 0 ; 40 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ; +; HEX1[3] ; AJ19 ; 4A ; 60 ; 0 ; 34 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ; +; HEX1[4] ; AG20 ; 4A ; 62 ; 0 ; 17 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ; +; HEX1[5] ; AC18 ; 4A ; 64 ; 0 ; 0 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ; +; HEX1[6] ; AH24 ; 4A ; 64 ; 0 ; 51 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ; +; HEX2[0] ; AG23 ; 4A ; 64 ; 0 ; 34 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ; +; HEX2[1] ; AK22 ; 4A ; 68 ; 0 ; 51 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ; +; HEX2[2] ; W17 ; 4A ; 60 ; 0 ; 17 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ; +; HEX2[3] ; AD17 ; 4A ; 64 ; 0 ; 17 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ; +; HEX2[4] ; AK16 ; 4A ; 54 ; 0 ; 51 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ; +; HEX2[5] ; V17 ; 4A ; 60 ; 0 ; 0 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ; +; HEX2[6] ; AG18 ; 4A ; 58 ; 0 ; 74 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ; +; PWM_OUT ; AG21 ; 4A ; 54 ; 0 ; 0 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ; ++---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+ + + ++----------------------------------------------------------------------------+ +; I/O Bank Usage ; ++----------+------------------+---------------+--------------+---------------+ +; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ; VCCPD Voltage ; ++----------+------------------+---------------+--------------+---------------+ +; B2L ; 0 / 0 ( -- ) ; -- ; -- ; -- ; +; B1L ; 0 / 0 ( -- ) ; -- ; -- ; -- ; +; 3A ; 2 / 32 ( 6 % ) ; 2.5V ; -- ; 2.5V ; +; 3B ; 2 / 48 ( 4 % ) ; 2.5V ; -- ; 2.5V ; +; 4A ; 32 / 80 ( 40 % ) ; 2.5V ; -- ; 2.5V ; +; 5A ; 1 / 32 ( 3 % ) ; 2.5V ; -- ; 2.5V ; +; 5B ; 1 / 16 ( 6 % ) ; 2.5V ; -- ; 2.5V ; +; 6B ; 0 / 44 ( 0 % ) ; 2.5V ; -- ; 2.5V ; +; 6A ; 0 / 56 ( 0 % ) ; 2.5V ; -- ; 2.5V ; +; 7A ; 0 / 19 ( 0 % ) ; 2.5V ; -- ; 2.5V ; +; 7B ; 0 / 22 ( 0 % ) ; 2.5V ; -- ; 2.5V ; +; 7C ; 0 / 12 ( 0 % ) ; 2.5V ; -- ; 2.5V ; +; 7D ; 0 / 14 ( 0 % ) ; 2.5V ; -- ; 2.5V ; +; 8A ; 3 / 80 ( 4 % ) ; 2.5V ; -- ; 2.5V ; ++----------+------------------+---------------+--------------+---------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; All Package Pins ; ++----------+------------+----------------+---------------------------------+--------+--------------+---------------------+--------------+-----------------+----------+--------------+ +; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; I/O Type ; User Assignment ; Bus Hold ; Weak Pull Up ; ++----------+------------+----------------+---------------------------------+--------+--------------+---------------------+--------------+-----------------+----------+--------------+ +; A2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; A3 ; 493 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A4 ; 491 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A5 ; 489 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A6 ; 487 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A7 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; A8 ; 473 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A9 ; 471 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A10 ; 465 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A11 ; 463 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; A13 ; 461 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A14 ; 455 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A15 ; 447 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A16 ; 439 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; A18 ; 425 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A19 ; 423 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A20 ; 415 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A21 ; 411 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; A23 ; 395 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A24 ; 391 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A25 ; 389 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A26 ; 382 ; 7A ; ^GND ; ; ; ; -- ; ; -- ; -- ; +; A27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; A28 ; 380 ; 7A ; ^HPS_TRST ; ; ; ; -- ; ; -- ; -- ; +; A29 ; 378 ; 7A ; ^HPS_TMS ; ; ; ; -- ; ; -- ; -- ; +; AA1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AA2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AA3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AA4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AA5 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; AA6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AA7 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; +; AA8 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AA9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AA10 ; ; 3A ; VCCPD3A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AA11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AA12 ; 74 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA13 ; 90 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA14 ; 122 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA15 ; 120 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA16 ; 146 ; 4A ; DAC_SCK ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; AA17 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AA18 ; 168 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA19 ; 176 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA20 ; 200 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA21 ; 210 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AA23 ; ; -- ; VCCPGM ; power ; ; 1.8V/2.5V/3.0V/3.3V ; -- ; ; -- ; -- ; +; AA24 ; 228 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AA25 ; 224 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AA26 ; 252 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AA27 ; ; 5B ; VCCIO5B ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AA28 ; 251 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AA29 ; ; 5B ; VREFB5BN0 ; power ; ; ; -- ; ; -- ; -- ; +; AA30 ; 250 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AB1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AB2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AB3 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; +; AB4 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; +; AB5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AB6 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AB7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AB8 ; 43 ; 3A ; ^nCSO, DATA4 ; ; ; ; Weak Pull Up ; ; -- ; On ; +; AB9 ; 42 ; 3A ; #TDO ; output ; ; ; -- ; ; -- ; -- ; +; AB10 ; ; -- ; VCCPGM ; power ; ; 1.8V/2.5V/3.0V/3.3V ; -- ; ; -- ; -- ; +; AB11 ; ; -- ; VCC_AUX ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AB12 ; 72 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB13 ; 88 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB14 ; ; 3B ; VCCIO3B ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AB15 ; 106 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB16 ; ; -- ; VCC_AUX ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AB17 ; 144 ; 4A ; HEX0[6] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; AB18 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AB19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AB20 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AB21 ; 208 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB22 ; 225 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AB23 ; 227 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AB24 ; ; 5A ; VCCIO5A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AB25 ; 230 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AB26 ; 226 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AB27 ; 254 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AB28 ; 249 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AB29 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AB30 ; 248 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AC1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AC2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AC3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AC4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AC5 ; 46 ; 3A ; #TCK ; input ; ; ; -- ; ; -- ; -- ; +; AC6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AC7 ; 45 ; 3A ; ^AS_DATA3, DATA3 ; ; ; ; Weak Pull Up ; ; -- ; On ; +; AC8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AC9 ; 58 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AC10 ; ; 3A ; VCCPD3A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AC11 ; ; 3A ; VCCIO3A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AC12 ; 82 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AC13 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AC14 ; 104 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AC15 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AC16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AC17 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AC18 ; 162 ; 4A ; HEX1[5] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; AC19 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AC20 ; 186 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AC21 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AC22 ; 207 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AC23 ; 205 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AC24 ; ; 5A ; VREFB5AN0 ; power ; ; ; -- ; ; -- ; -- ; +; AC25 ; 215 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AC26 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AC27 ; 242 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AC28 ; 245 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AC29 ; 247 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AC30 ; 259 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AD1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AD2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AD3 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; +; AD4 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; +; AD5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AD6 ; ; 3A ; VREFB3AN0 ; power ; ; ; -- ; ; -- ; -- ; +; AD7 ; 62 ; 3A ; SW[9] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; AD8 ; ; 3A ; VCCIO3A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AD9 ; 55 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AD10 ; 56 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AD11 ; 54 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AD12 ; 80 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AD13 ; ; 3B ; VCCIO3B ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AD14 ; 98 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AD15 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; +; AD16 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AD17 ; 160 ; 4A ; HEX2[3] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; AD18 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AD19 ; 184 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AD20 ; 199 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AD21 ; 197 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AD22 ; ; -- ; VCC_AUX ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AD23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AD24 ; 211 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AD25 ; 213 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AD26 ; 240 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AD27 ; 222 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AD28 ; ; 5A ; VCCIO5A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AD29 ; 255 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AD30 ; 257 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AE1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AE2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AE3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AE4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AE5 ; 49 ; 3A ; ^AS_DATA1, DATA1 ; ; ; ; Weak Pull Up ; ; -- ; On ; +; AE6 ; 51 ; 3A ; ^AS_DATA0, ASDO, DATA0 ; ; ; ; Weak Pull Up ; ; -- ; On ; +; AE7 ; 60 ; 3A ; SW[8] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; AE8 ; 47 ; 3A ; ^AS_DATA2, DATA2 ; ; ; ; Weak Pull Up ; ; -- ; On ; +; AE9 ; 53 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AE10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AE11 ; 59 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AE12 ; 52 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AE13 ; 95 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AE14 ; 96 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AE15 ; ; 3B ; VCCIO3B ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AE16 ; 139 ; 4A ; HEX0[0] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; AE17 ; 135 ; 4A ; HEX0[1] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; AE18 ; 167 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AE19 ; 165 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AE20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AE21 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AE22 ; 191 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AE23 ; 189 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AE24 ; 209 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AE25 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AE26 ; 220 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AE27 ; 229 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AE28 ; 231 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AE29 ; 253 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AE30 ; ; 5B ; VCCIO5B ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AF1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AF2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AF3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AF4 ; 66 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF5 ; 64 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF6 ; 75 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF7 ; ; 3A ; VCCIO3A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AF8 ; 70 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF9 ; 67 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF10 ; 57 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF11 ; 87 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AF13 ; 93 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF14 ; 114 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF15 ; 112 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF16 ; 137 ; 4A ; HEX0[2] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; AF17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AF18 ; 133 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF19 ; 159 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF20 ; 175 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF21 ; 173 ; 4A ; SW[1] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; AF22 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AF23 ; 183 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF24 ; 181 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF25 ; 206 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF26 ; 204 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AF28 ; 235 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AF29 ; 237 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AF30 ; 239 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AG1 ; 71 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AG2 ; 83 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AG3 ; 63 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AG4 ; ; 3A ; VCCIO3A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AG5 ; 78 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AG6 ; 73 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AG7 ; 68 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AG8 ; 65 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AG9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AG10 ; 86 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AG11 ; 85 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AG12 ; 103 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AG13 ; 101 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AG14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AG15 ; 127 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AG16 ; 134 ; 4A ; HEX1[0] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; AG17 ; 132 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AG18 ; 150 ; 4A ; HEX2[6] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; AG19 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AG20 ; 157 ; 4A ; HEX1[4] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; AG21 ; 143 ; 4A ; PWM_OUT ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; AG22 ; 166 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AG23 ; 163 ; 4A ; HEX2[0] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; AG24 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AG25 ; 190 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AG26 ; 203 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AG27 ; 212 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AG28 ; 233 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AG29 ; ; 5A ; VCCIO5A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AG30 ; 243 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AH1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AH2 ; 69 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AH3 ; 81 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AH4 ; 61 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AH5 ; 76 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AH6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AH7 ; 115 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AH8 ; 113 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AH9 ; 84 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AH10 ; 118 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AH11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AH12 ; 126 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AH13 ; 111 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AH14 ; 109 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AH15 ; 125 ; 3B ; SW[2] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; AH16 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AH17 ; 147 ; 4A ; ADC_SDI ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; AH18 ; 145 ; 4A ; ADC_CS ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; AH19 ; 148 ; 4A ; ADC_SDO ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; AH20 ; 141 ; 4A ; DAC_CS ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; AH21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AH22 ; 164 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AH23 ; 174 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AH24 ; 161 ; 4A ; HEX1[6] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; AH25 ; 188 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AH26 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AH27 ; 201 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AH28 ; 214 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AH29 ; 218 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AH30 ; 241 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AJ1 ; 79 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AJ2 ; 77 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AJ3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AJ4 ; 94 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AJ5 ; 99 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AJ6 ; 102 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AJ7 ; 100 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AJ8 ; ; 3B ; VCCIO3B ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AJ9 ; 110 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AJ10 ; 116 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AJ11 ; 119 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AJ12 ; 124 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AJ13 ; ; 3B ; VCCIO3B ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AJ14 ; 131 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AJ15 ; ; 3B ; VREFB3BN0 ; power ; ; ; -- ; ; -- ; -- ; +; AJ16 ; 142 ; 4A ; HEX0[3] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; AJ17 ; 151 ; 4A ; HEX1[2] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; AJ18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AJ19 ; 155 ; 4A ; HEX1[3] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; AJ20 ; 158 ; 4A ; DAC_LD ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; AJ21 ; 156 ; 4A ; ADC_SCK ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; AJ22 ; 172 ; 4A ; SW[3] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; AJ23 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AJ24 ; 182 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AJ25 ; 180 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AJ26 ; 187 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AJ27 ; 195 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AJ28 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AJ29 ; 216 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AJ30 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AK2 ; 91 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AK3 ; 89 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AK4 ; 92 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AK5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AK6 ; 97 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AK7 ; 107 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AK8 ; 105 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AK9 ; 108 ; 3B ; SW[0] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; AK10 ; ; 3B ; VCCIO3B ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AK11 ; 117 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AK12 ; 123 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AK13 ; 121 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AK14 ; 129 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AK15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AK16 ; 140 ; 4A ; HEX2[4] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; AK17 ; ; 4A ; VREFB4AN0 ; power ; ; ; -- ; ; -- ; -- ; +; AK18 ; 149 ; 4A ; DAC_SDI ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; AK19 ; 153 ; 4A ; HEX1[1] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; AK20 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AK21 ; 171 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AK22 ; 169 ; 4A ; HEX2[1] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; AK23 ; 179 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AK24 ; 177 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AK25 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AK26 ; 185 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AK27 ; 193 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AK28 ; 198 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AK29 ; 196 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B1 ; 509 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B2 ; 507 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B3 ; 513 ; 8A ; SW[6] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; B4 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; B5 ; 512 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B6 ; 510 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B7 ; 477 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B8 ; 481 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B10 ; ; 8A ; VREFB8AN0 ; power ; ; ; -- ; ; -- ; -- ; +; B11 ; 469 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B12 ; 464 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B13 ; 459 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B15 ; 451 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B16 ; 441 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B17 ; 431 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B18 ; 418 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B20 ; 417 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B21 ; 413 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B22 ; 399 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B23 ; 397 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B24 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B25 ; 387 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B26 ; 386 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B27 ; 381 ; 7A ; ^HPS_TDI ; ; ; ; -- ; ; -- ; -- ; +; B28 ; 376 ; 7A ; ^HPS_TDO ; ; ; ; -- ; ; -- ; -- ; +; B29 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B30 ; 365 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; C1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; C2 ; 517 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C3 ; 511 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C4 ; 501 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C5 ; 497 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; C7 ; 475 ; 8A ; SW[7] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; C8 ; 479 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C9 ; 485 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C10 ; 483 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C11 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; C12 ; 467 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C13 ; 462 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C14 ; 448 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C15 ; 453 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; C17 ; 433 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C18 ; 435 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C19 ; 427 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C20 ; 421 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; C22 ; 396 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C23 ; 401 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C24 ; 393 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C25 ; 388 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C26 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; C27 ; 374 ; 7A ; ^HPS_nRST ; ; ; ; -- ; ; -- ; -- ; +; C28 ; 369 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; C29 ; 367 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; C30 ; 363 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; D1 ; 529 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D2 ; 515 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; D4 ; 521 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D5 ; 499 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D6 ; 495 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D7 ; 505 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D8 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; D9 ; 480 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D10 ; 472 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D11 ; 470 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D12 ; 496 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; D14 ; 446 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D15 ; 449 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D16 ; 445 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D17 ; 440 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D18 ; ; 7C ; VCCIO7C_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; D19 ; 426 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D20 ; 420 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D21 ; 419 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D22 ; 402 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; D24 ; 404 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D25 ; 384 ; 7A ; ^HPS_CLK1 ; ; ; ; -- ; ; -- ; -- ; +; D26 ; 373 ; 7A ; ^GND ; ; ; ; -- ; ; -- ; -- ; +; D27 ; 371 ; 6A ; HPS_RZQ_0 ; ; ; ; -- ; ; no ; On ; +; D28 ; ; 6A ; VCCIO6A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; D29 ; 361 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; D30 ; 359 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E1 ; 527 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E2 ; 525 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E3 ; 523 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E4 ; 519 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E5 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; E6 ; 533 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E7 ; 531 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E8 ; 503 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E9 ; 478 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; E11 ; 504 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E12 ; 494 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E13 ; 488 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E14 ; 454 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E15 ; ; 7D ; VCCIO7D_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; E16 ; 443 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E17 ; 438 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E18 ; 437 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E19 ; 424 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E20 ; ; 7B ; VCCIO7B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; E21 ; 412 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E22 ; ; 7A, 7B, 7C, 7D ; VREFB7A7B7C7DN0_HPS ; power ; ; ; -- ; ; -- ; -- ; +; E23 ; 394 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E24 ; 403 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E25 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; E26 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; +; E27 ; 357 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E28 ; 351 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E29 ; 353 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E30 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; F1 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; +; F2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; F3 ; 539 ; 9A ; ^CONF_DONE ; ; ; ; -- ; ; -- ; -- ; +; F4 ; 541 ; 9A ; ^nSTATUS ; ; ; ; -- ; ; -- ; -- ; +; F5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; F6 ; 537 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; F8 ; 536 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F9 ; 534 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F10 ; 528 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F11 ; 502 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F12 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; F13 ; 486 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F14 ; 468 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F15 ; 466 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F16 ; 442 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; F18 ; 430 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F19 ; 410 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F20 ; 407 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F21 ; 409 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F22 ; ; 7A ; VCCIO7A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; F23 ; 375 ; 7A ; ^HPS_nPOR ; ; ; ; -- ; ; -- ; -- ; +; F24 ; 383 ; 7A ; ^HPS_PORSEL ; ; ; ; -- ; ; -- ; -- ; +; F25 ; 385 ; 7A ; ^HPS_CLK2 ; ; ; ; -- ; ; -- ; -- ; +; F26 ; 341 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; F28 ; 345 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F29 ; 349 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F30 ; 347 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G1 ; ; ; GND ; ; ; ; -- ; ; -- ; -- ; +; G2 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; +; G3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; G4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; G5 ; 542 ; 9A ; ^nCE ; ; ; ; -- ; ; -- ; -- ; +; G6 ; 543 ; 9A ; ^MSEL2 ; ; ; ; -- ; ; -- ; -- ; +; G7 ; 535 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; G8 ; 492 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; G9 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; G10 ; 526 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; G11 ; 520 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; G12 ; 518 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; G13 ; 484 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; G14 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; G15 ; 460 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; G16 ; 444 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; G17 ; 436 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; G18 ; 432 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; G19 ; ; 7B ; VCCIO7B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; G20 ; 416 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; G21 ; 392 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; G22 ; 400 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; G23 ; 377 ; 7A ; ^VCCRSTCLK_HPS ; ; ; ; -- ; ; -- ; -- ; +; G24 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; G25 ; 370 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G26 ; 362 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G27 ; 339 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ; +; G28 ; 335 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G29 ; ; 6A ; VCCIO6A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; G30 ; 343 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; H2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; H3 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; +; H4 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; +; H5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; H6 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; H7 ; 508 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H8 ; 490 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H9 ; ; -- ; VCCBAT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; H10 ; ; -- ; VCC_AUX ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; H11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; H12 ; 500 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H13 ; 498 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H14 ; 482 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H15 ; 458 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H16 ; ; 7D ; VCCIO7D_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; H17 ; 434 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H18 ; 422 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H19 ; 406 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H20 ; 398 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H21 ; ; 7A ; VCCIO7A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; H22 ; 379 ; 7A ; ^HPS_TCK ; ; ; ; -- ; ; -- ; -- ; +; H23 ; 390 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H24 ; 364 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H25 ; 368 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H26 ; ; 6A ; VCCIO6A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; H27 ; 360 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H28 ; 333 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H29 ; 331 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H30 ; 337 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J5 ; 545 ; 9A ; ^nCONFIG ; ; ; ; -- ; ; -- ; -- ; +; J6 ; 547 ; 9A ; ^GND ; ; ; ; -- ; ; -- ; -- ; +; J7 ; 506 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; J8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J9 ; 532 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; J10 ; 530 ; 8A ; SW[5] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; J11 ; ; -- ; VCCPGM ; power ; ; 1.8V/2.5V/3.0V/3.3V ; -- ; ; -- ; -- ; +; J12 ; 516 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; J13 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; J14 ; 476 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; J15 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; +; J16 ; ; -- ; VCC_AUX ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; J17 ; ; 7C ; VCCPD7C_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; J18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J19 ; 408 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; J20 ; ; -- ; VCCRSTCLK_HPS ; power ; ; 1.8V/2.5V/3.0V/3.3V ; -- ; ; -- ; -- ; +; J21 ; ; -- ; VCC_AUX_SHARED ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; J22 ; 372 ; 7A ; ^GND ; ; ; ; -- ; ; -- ; -- ; +; J23 ; 354 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J24 ; 352 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J25 ; 344 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J26 ; 323 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J27 ; 346 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J28 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J29 ; 327 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J30 ; 329 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K3 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; +; K4 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; +; K5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K6 ; 540 ; 9A ; ^MSEL1 ; ; ; ; -- ; ; -- ; -- ; +; K7 ; 522 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; K8 ; 524 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; K9 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; K10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K11 ; ; 8A ; VCCPD8A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; K12 ; 514 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; K13 ; ; 8A ; VCCPD8A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; K14 ; 474 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; K15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K16 ; ; 7D ; VCCPD7D_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; K17 ; 414 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; K18 ; ; 7B ; VCCPD7B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; K19 ; ; 7A ; VCCPD7A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; K20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K21 ; 366 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K22 ; 336 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K23 ; 338 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K24 ; ; 6A ; VCCIO6A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; K25 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K26 ; 322 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K27 ; 319 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K28 ; 325 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K29 ; 321 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K30 ; ; 6A ; VCCIO6A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; L1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L5 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; L6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L7 ; 544 ; 9A ; ^MSEL3 ; ; ; ; -- ; ; -- ; -- ; +; L8 ; 538 ; 9A ; ^MSEL0 ; ; ; ; -- ; ; -- ; -- ; +; L9 ; 546 ; 9A ; ^MSEL4 ; ; ; ; -- ; ; -- ; -- ; +; L10 ; ; 8A ; VCCPD8A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; L11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L12 ; ; 8A ; VCCPD8A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; L13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L14 ; ; 8A ; VCCPD8A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; L15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L16 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; L17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L18 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; L19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L20 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; L21 ; ; -- ; VCCPLL_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; L22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L23 ; 350 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L24 ; 328 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L25 ; 330 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L26 ; 320 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L27 ; ; 6A ; VCCIO6A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; L28 ; 313 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L29 ; 315 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L30 ; 317 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M3 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; +; M4 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; +; M5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M6 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; M7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M9 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; M10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M11 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; M12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M13 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; M14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M15 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; M16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M17 ; 450 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; M18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M19 ; 334 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M21 ; ; 6A, 6B ; VCCPD6A6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; M22 ; 308 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M23 ; 348 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M24 ; ; 6A ; VCCIO6A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; M25 ; 324 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M26 ; 314 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M27 ; 312 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M28 ; 309 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M29 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M30 ; 311 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N5 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; N6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N7 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; N8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N10 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; N11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N12 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; N13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N14 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; N15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N16 ; 452 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; N17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N18 ; 332 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N20 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; N21 ; ; 6A ; VCCIO6A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; N22 ; ; 6A, 6B ; VCCPD6A6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; N23 ; 310 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N24 ; 318 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N25 ; 316 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N26 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N27 ; 297 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N28 ; 303 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N29 ; 305 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N30 ; 307 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P3 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; +; P4 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; +; P5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P6 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; P7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P11 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; P12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P13 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; P14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P15 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; P16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P17 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; P18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P19 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; P20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P21 ; ; 6A, 6B ; VCCPD6A6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; P22 ; 294 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P23 ; ; 6B ; VCCIO6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; P24 ; 290 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P25 ; 288 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P26 ; 298 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P27 ; 296 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P28 ; ; 6B ; VCCIO6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; P29 ; 299 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P30 ; 301 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; R2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; R3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; R4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; R5 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; R6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; R7 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; R8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; R9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; R10 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; R11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; R12 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; R13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; R14 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; R15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; R16 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; R17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; R18 ; 302 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R19 ; 300 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R20 ; ; 6A, 6B ; VCCPD6A6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; R21 ; 286 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R22 ; 284 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R23 ; ; 6A, 6B ; VCCPD6A6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; R24 ; 272 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R25 ; ; 6B ; VCCIO6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; R26 ; 280 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R27 ; 282 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R28 ; 293 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R29 ; 295 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R30 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T3 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; +; T4 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; +; T5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T6 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; T7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T11 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; T12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T13 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; T14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T17 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; T18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T19 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; T20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T21 ; 278 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T22 ; ; 6B ; VCCIO6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; T23 ; 270 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T24 ; 268 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T25 ; 266 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T26 ; 304 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T28 ; 287 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T29 ; 289 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T30 ; 291 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; U2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; U3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; U4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; U5 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; U6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; U7 ; 50 ; 3A ; ^DCLK ; ; ; ; Weak Pull Up ; ; -- ; On ; +; U8 ; 48 ; 3A ; #TDI ; input ; ; ; -- ; ; -- ; -- ; +; U9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; U10 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; U11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; U12 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; U13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; U14 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; U15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; U16 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; U17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; U18 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; U19 ; ; 6B ; VCCIO6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; U20 ; 276 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U21 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; U22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; U23 ; ; 5B ; VCCPD5B ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; U24 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; U25 ; 264 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U26 ; 306 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U27 ; 273 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U28 ; 285 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U29 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; U30 ; 283 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ; +; V1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; V2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; V3 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; +; V4 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; +; V5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; V6 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; V7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; V8 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; V9 ; 44 ; 3A ; #TMS ; input ; ; ; -- ; ; -- ; -- ; +; V10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; V11 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; V12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; V13 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; V14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; V15 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; V16 ; 138 ; 4A ; HEX0[5] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; V17 ; 154 ; 4A ; HEX2[5] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; V18 ; 194 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; V20 ; 292 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; V22 ; ; 5A ; VCCPD5A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; V23 ; 236 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V24 ; ; 5A ; VCCPD5A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; V25 ; 246 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V26 ; ; 6B ; VCCIO6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; V27 ; 265 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V28 ; 271 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V29 ; 275 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V30 ; 281 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; W1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; W2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; W3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; W4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; W5 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; W6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; W7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; W8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; W9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; W10 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; W11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; W12 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; W13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; W14 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; W15 ; 130 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W16 ; 136 ; 4A ; HEX0[4] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; W17 ; 152 ; 4A ; HEX2[2] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; W18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; W19 ; 192 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W20 ; 217 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; W21 ; 221 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; W22 ; 223 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; W23 ; ; 5A ; VCCIO5A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; W24 ; 238 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; W25 ; 244 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; W26 ; 274 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; W27 ; 261 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; W28 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; W29 ; 279 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; W30 ; 277 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; Y1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y3 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; +; Y4 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; +; Y5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y6 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; Y7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y9 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; Y10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y11 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; Y12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y13 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; Y14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y16 ; 128 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y17 ; 170 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y18 ; 178 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y19 ; 202 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y21 ; 219 ; 5A ; SW[4] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; Y22 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; Y23 ; 232 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; Y24 ; 234 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; Y25 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y26 ; 256 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; Y27 ; 258 ; 5B ; CLOCK_50 ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; Y28 ; 269 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; Y29 ; 263 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; Y30 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ++----------+------------+----------------+---------------------------------+--------+--------------+---------------------+--------------+-----------------+----------+--------------+ +Note: Pin directions (input, output or bidir) are based on device operating in user mode. + + ++------------------------------------------+ +; I/O Assignment Warnings ; ++----------+-------------------------------+ +; Pin Name ; Reason ; ++----------+-------------------------------+ +; SW[0] ; Incomplete set of assignments ; +; SW[1] ; Incomplete set of assignments ; +; SW[2] ; Incomplete set of assignments ; +; SW[3] ; Incomplete set of assignments ; +; SW[4] ; Incomplete set of assignments ; +; SW[5] ; Incomplete set of assignments ; +; SW[6] ; Incomplete set of assignments ; +; SW[7] ; Incomplete set of assignments ; +; SW[8] ; Incomplete set of assignments ; +; SW[9] ; Incomplete set of assignments ; +; HEX0[0] ; Incomplete set of assignments ; +; HEX0[1] ; Incomplete set of assignments ; +; HEX0[2] ; Incomplete set of assignments ; +; HEX0[3] ; Incomplete set of assignments ; +; HEX0[4] ; Incomplete set of assignments ; +; HEX0[5] ; Incomplete set of assignments ; +; HEX0[6] ; Incomplete set of assignments ; +; HEX1[0] ; Incomplete set of assignments ; +; HEX1[1] ; Incomplete set of assignments ; +; HEX1[2] ; Incomplete set of assignments ; +; HEX1[3] ; Incomplete set of assignments ; +; HEX1[4] ; Incomplete set of assignments ; +; HEX1[5] ; Incomplete set of assignments ; +; HEX1[6] ; Incomplete set of assignments ; +; HEX2[0] ; Incomplete set of assignments ; +; HEX2[1] ; Incomplete set of assignments ; +; HEX2[2] ; Incomplete set of assignments ; +; HEX2[3] ; Incomplete set of assignments ; +; HEX2[4] ; Incomplete set of assignments ; +; HEX2[5] ; Incomplete set of assignments ; +; HEX2[6] ; Incomplete set of assignments ; +; DAC_SDI ; Incomplete set of assignments ; +; DAC_SCK ; Incomplete set of assignments ; +; DAC_CS ; Incomplete set of assignments ; +; DAC_LD ; Incomplete set of assignments ; +; ADC_SDI ; Incomplete set of assignments ; +; ADC_SCK ; Incomplete set of assignments ; +; ADC_CS ; Incomplete set of assignments ; +; PWM_OUT ; Incomplete set of assignments ; +; CLOCK_50 ; Incomplete set of assignments ; +; ADC_SDO ; Incomplete set of assignments ; +; SW[0] ; Missing location assignment ; +; SW[1] ; Missing location assignment ; +; SW[2] ; Missing location assignment ; +; SW[3] ; Missing location assignment ; +; SW[4] ; Missing location assignment ; +; SW[5] ; Missing location assignment ; +; SW[6] ; Missing location assignment ; +; SW[7] ; Missing location assignment ; +; SW[8] ; Missing location assignment ; +; SW[9] ; Missing location assignment ; +; HEX0[0] ; Missing location assignment ; +; HEX0[1] ; Missing location assignment ; +; HEX0[2] ; Missing location assignment ; +; HEX0[3] ; Missing location assignment ; +; HEX0[4] ; Missing location assignment ; +; HEX0[5] ; Missing location assignment ; +; HEX0[6] ; Missing location assignment ; +; HEX1[0] ; Missing location assignment ; +; HEX1[1] ; Missing location assignment ; +; HEX1[2] ; Missing location assignment ; +; HEX1[3] ; Missing location assignment ; +; HEX1[4] ; Missing location assignment ; +; HEX1[5] ; Missing location assignment ; +; HEX1[6] ; Missing location assignment ; +; HEX2[0] ; Missing location assignment ; +; HEX2[1] ; Missing location assignment ; +; HEX2[2] ; Missing location assignment ; +; HEX2[3] ; Missing location assignment ; +; HEX2[4] ; Missing location assignment ; +; HEX2[5] ; Missing location assignment ; +; HEX2[6] ; Missing location assignment ; +; DAC_SDI ; Missing location assignment ; +; DAC_SCK ; Missing location assignment ; +; DAC_CS ; Missing location assignment ; +; DAC_LD ; Missing location assignment ; +; ADC_SDI ; Missing location assignment ; +; ADC_SCK ; Missing location assignment ; +; ADC_CS ; Missing location assignment ; +; PWM_OUT ; Missing location assignment ; +; CLOCK_50 ; Missing location assignment ; +; ADC_SDO ; Missing location assignment ; ++----------+-------------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fitter Resource Utilization by Entity ; ++---------------------------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------+--------------+ +; Compilation Hierarchy Node ; ALMs needed [=A-B+C] ; [A] ALMs used in final placement ; [B] Estimate of ALMs recoverable by dense packing ; [C] Estimate of ALMs unavailable ; ALMs used for memory ; Combinational ALUTs ; Dedicated Logic Registers ; I/O Registers ; Block Memory Bits ; M10Ks ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name ; Entity Name ; Library Name ; ++---------------------------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------+--------------+ +; |ex18_top ; 90.5 (0.5) ; 103.5 (0.5) ; 13.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 159 (1) ; 170 (0) ; 0 (0) ; 73728 ; 9 ; 0 ; 41 ; 0 ; |ex18_top ; ex18_top ; work ; +; |clktick_16:GEN_10K| ; 11.5 (11.5) ; 12.0 (12.0) ; 0.5 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 20 (20) ; 19 (19) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex18_top|clktick_16:GEN_10K ; clktick_16 ; work ; +; |hex_to_7seg:SEG0| ; 2.3 (2.3) ; 2.5 (2.5) ; 0.3 (0.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 7 (7) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex18_top|hex_to_7seg:SEG0 ; hex_to_7seg ; work ; +; |hex_to_7seg:SEG1| ; 2.8 (2.8) ; 2.8 (2.8) ; 0.1 (0.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 7 (7) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex18_top|hex_to_7seg:SEG1 ; hex_to_7seg ; work ; +; |hex_to_7seg:SEG2| ; 1.5 (1.5) ; 1.5 (1.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 3 (3) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex18_top|hex_to_7seg:SEG2 ; hex_to_7seg ; work ; +; |processor:ALLPASS| ; 31.4 (7.5) ; 33.0 (8.5) ; 1.6 (1.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 62 (15) ; 59 (12) ; 0 (0) ; 73728 ; 9 ; 0 ; 0 ; 0 ; |ex18_top|processor:ALLPASS ; processor ; work ; +; |FIFO:DELAY1024| ; 23.2 (0.0) ; 23.5 (0.0) ; 0.3 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 45 (0) ; 44 (0) ; 0 (0) ; 73728 ; 9 ; 0 ; 0 ; 0 ; |ex18_top|processor:ALLPASS|FIFO:DELAY1024 ; FIFO ; work ; +; |scfifo:scfifo_component| ; 23.2 (0.0) ; 23.5 (0.0) ; 0.3 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 45 (0) ; 44 (0) ; 0 (0) ; 73728 ; 9 ; 0 ; 0 ; 0 ; |ex18_top|processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component ; scfifo ; work ; +; |scfifo_j791:auto_generated| ; 23.2 (0.0) ; 23.5 (0.0) ; 0.3 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 45 (0) ; 44 (0) ; 0 (0) ; 73728 ; 9 ; 0 ; 0 ; 0 ; |ex18_top|processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated ; scfifo_j791 ; work ; +; |a_dpfifo_qd91:dpfifo| ; 23.2 (0.5) ; 23.5 (0.5) ; 0.3 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 45 (1) ; 44 (0) ; 0 (0) ; 73728 ; 9 ; 0 ; 0 ; 0 ; |ex18_top|processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo ; a_dpfifo_qd91 ; work ; +; |a_fefifo_4be:fifo_state| ; 9.7 (3.2) ; 10.0 (3.5) ; 0.3 (0.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 18 (5) ; 15 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex18_top|processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|a_fefifo_4be:fifo_state ; a_fefifo_4be ; work ; +; |cntr_di7:count_usedw| ; 6.5 (6.5) ; 6.5 (6.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 13 (13) ; 14 (14) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex18_top|processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|a_fefifo_4be:fifo_state|cntr_di7:count_usedw ; cntr_di7 ; work ; +; |altsyncram_44t1:FIFOram| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 73728 ; 9 ; 0 ; 0 ; 0 ; |ex18_top|processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|altsyncram_44t1:FIFOram ; altsyncram_44t1 ; work ; +; |cntr_1ib:rd_ptr_count| ; 6.5 (6.5) ; 6.5 (6.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 13 (13) ; 15 (15) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex18_top|processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|cntr_1ib:rd_ptr_count ; cntr_1ib ; work ; +; |cntr_1ib:wr_ptr| ; 6.5 (6.5) ; 6.5 (6.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 13 (13) ; 14 (14) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex18_top|processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|cntr_1ib:wr_ptr ; cntr_1ib ; work ; +; |pulse_gen:PULSE0| ; 0.8 (0.8) ; 1.0 (1.0) ; 0.3 (0.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 2 (2) ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex18_top|processor:ALLPASS|pulse_gen:PULSE0 ; pulse_gen ; work ; +; |pwm:PWM_DC| ; 11.2 (11.2) ; 12.0 (12.0) ; 0.8 (0.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 19 (19) ; 21 (21) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex18_top|pwm:PWM_DC ; pwm ; work ; +; |spi2adc:SPI_ADC| ; 15.1 (15.1) ; 24.2 (24.2) ; 9.1 (9.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 23 (23) ; 47 (47) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex18_top|spi2adc:SPI_ADC ; spi2adc ; work ; +; |spi2dac:SPI_DAC| ; 14.2 (14.2) ; 15.0 (15.0) ; 0.7 (0.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 24 (24) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex18_top|spi2dac:SPI_DAC ; spi2dac ; work ; ++---------------------------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------+--------------+ +Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. + + ++-------------------------------------------------------------------------------------------------------------------------+ +; Delay Chain Summary ; ++----------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+ +; Name ; Pin Type ; D1 ; D3_0 ; D3_1 ; D4 ; D5 ; D5 OE ; D5 OCT ; T11 (Postamble Gating) ; T11 (Postamble Ungating) ; ++----------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+ +; SW[0] ; Input ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; +; SW[1] ; Input ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; +; SW[2] ; Input ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; +; SW[3] ; Input ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; +; SW[4] ; Input ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; +; SW[5] ; Input ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; +; SW[6] ; Input ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; +; SW[7] ; Input ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; +; SW[8] ; Input ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; +; SW[9] ; Input ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; +; HEX0[0] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; HEX0[1] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; HEX0[2] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; HEX0[3] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; HEX0[4] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; HEX0[5] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; HEX0[6] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; HEX1[0] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; HEX1[1] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; HEX1[2] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; HEX1[3] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; HEX1[4] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; HEX1[5] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; HEX1[6] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; HEX2[0] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; HEX2[1] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; HEX2[2] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; HEX2[3] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; HEX2[4] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; HEX2[5] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; HEX2[6] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; DAC_SDI ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; DAC_SCK ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; DAC_CS ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; DAC_LD ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; ADC_SDI ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; ADC_SCK ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; ADC_CS ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; PWM_OUT ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; CLOCK_50 ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; +; ADC_SDO ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; ++----------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+ + + ++--------------------------------------------------------------------------+ +; Pad To Core Delay Chain Fanout ; ++--------------------------------------------+-------------------+---------+ +; Source Pin / Fanout ; Pad To Core Index ; Setting ; ++--------------------------------------------+-------------------+---------+ +; SW[0] ; ; ; +; SW[1] ; ; ; +; SW[2] ; ; ; +; SW[3] ; ; ; +; SW[4] ; ; ; +; SW[5] ; ; ; +; SW[6] ; ; ; +; SW[7] ; ; ; +; SW[8] ; ; ; +; SW[9] ; ; ; +; CLOCK_50 ; ; ; +; ADC_SDO ; ; ; +; - spi2adc:SPI_ADC|shift_reg[0]~feeder ; 1 ; 0 ; ++--------------------------------------------+-------------------+---------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Control Signals ; ++--------------------------------------------------------------------------------------------------------------------------------------+--------------------+---------+----------------------------+--------+----------------------+------------------+---------------------------+ +; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ; ++--------------------------------------------------------------------------------------------------------------------------------------+--------------------+---------+----------------------------+--------+----------------------+------------------+---------------------------+ +; CLOCK_50 ; PIN_Y27 ; 179 ; Clock ; yes ; Global Clock ; GCLK10 ; -- ; +; clktick_16:GEN_10K|Equal0~3 ; LABCELL_X56_Y2_N15 ; 12 ; Sync. clear ; no ; -- ; -- ; -- ; +; clktick_16:GEN_10K|tick ; FF_X56_Y2_N32 ; 15 ; Clock enable ; no ; -- ; -- ; -- ; +; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|a_fefifo_4be:fifo_state|_~0 ; LABCELL_X51_Y5_N57 ; 14 ; Clock enable ; no ; -- ; -- ; -- ; +; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|valid_wreq ; LABCELL_X51_Y5_N6 ; 35 ; Clock enable, Write enable ; no ; -- ; -- ; -- ; +; processor:ALLPASS|comb~0 ; LABCELL_X51_Y5_N51 ; 25 ; Clock enable ; no ; -- ; -- ; -- ; +; spi2adc:SPI_ADC|adc_done ; FF_X57_Y2_N32 ; 10 ; Clock enable ; no ; -- ; -- ; -- ; +; spi2adc:SPI_ADC|always3~0 ; LABCELL_X57_Y3_N39 ; 10 ; Clock enable ; no ; -- ; -- ; -- ; +; spi2adc:SPI_ADC|tick ; FF_X53_Y2_N14 ; 38 ; Clock enable ; no ; -- ; -- ; -- ; +; spi2dac:SPI_DAC|always5~0 ; LABCELL_X51_Y2_N36 ; 9 ; Sync. load ; no ; -- ; -- ; -- ; ++--------------------------------------------------------------------------------------------------------------------------------------+--------------------+---------+----------------------------+--------+----------------------+------------------+---------------------------+ + + ++-----------------------------------------------------------------------------------------------------+ +; Global & Other Fast Signals ; ++----------+----------+---------+----------------------+------------------+---------------------------+ +; Name ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ; ++----------+----------+---------+----------------------+------------------+---------------------------+ +; CLOCK_50 ; PIN_Y27 ; 179 ; Global Clock ; GCLK10 ; -- ; ++----------+----------+---------+----------------------+------------------+---------------------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fitter RAM Summary ; ++---------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+-------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+-------------+------------+------+------------------------------------------------------------------------------------------------------------------------------------------------+----------------------+-----------------+-----------------+----------+------------------------+-----------------------+ +; Name ; Type ; Mode ; Clock Mode ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Port A Input Registers ; Port A Output Registers ; Port B Input Registers ; Port B Output Registers ; Size ; Implementation Port A Depth ; Implementation Port A Width ; Implementation Port B Depth ; Implementation Port B Width ; Implementation Bits ; M10K blocks ; MLAB cells ; MIF ; Location ; Mixed Width RDW Mode ; Port A RDW Mode ; Port B RDW Mode ; ECC Mode ; ECC Pipeline Registers ; Fits in MLABs ; ++---------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+-------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+-------------+------------+------+------------------------------------------------------------------------------------------------------------------------------------------------+----------------------+-----------------+-----------------+----------+------------------------+-----------------------+ +; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|altsyncram_44t1:FIFOram|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Single Clock ; 8192 ; 10 ; 8192 ; 10 ; yes ; no ; yes ; no ; 81920 ; 8192 ; 9 ; 8192 ; 9 ; 73728 ; 9 ; 0 ; None ; M10K_X41_Y5_N0, M10K_X49_Y4_N0, M10K_X41_Y4_N0, M10K_X49_Y3_N0, M10K_X58_Y4_N0, M10K_X41_Y3_N0, M10K_X58_Y5_N0, M10K_X49_Y5_N0, M10K_X58_Y3_N0 ; Don't care ; New data ; New data ; Off ; No ; No - Address Too Wide ; ++---------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+-------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+-------------+------------+------+------------------------------------------------------------------------------------------------------------------------------------------------+----------------------+-----------------+-----------------+----------+------------------------+-----------------------+ +Note: Fitter may spread logical memories into multiple blocks to improve timing. The actual required RAM blocks can be found in the Fitter Resource Usage section. + + ++-----------------------------------------------------------------------+ +; Routing Usage Summary ; ++---------------------------------------------+-------------------------+ +; Routing Resource Type ; Usage ; ++---------------------------------------------+-------------------------+ +; Block interconnects ; 453 / 289,320 ( < 1 % ) ; +; C12 interconnects ; 0 / 13,420 ( 0 % ) ; +; C2 interconnects ; 132 / 119,108 ( < 1 % ) ; +; C4 interconnects ; 56 / 56,300 ( < 1 % ) ; +; DQS bus muxes ; 0 / 25 ( 0 % ) ; +; DQS-18 I/O buses ; 0 / 25 ( 0 % ) ; +; DQS-9 I/O buses ; 0 / 25 ( 0 % ) ; +; Direct links ; 57 / 289,320 ( < 1 % ) ; +; Global clocks ; 1 / 16 ( 6 % ) ; +; HPS SDRAM PLL inputs ; 0 / 1 ( 0 % ) ; +; HPS SDRAM PLL outputs ; 0 / 1 ( 0 % ) ; +; HPS_INTERFACE_BOOT_FROM_FPGA_INPUTs ; 0 / 9 ( 0 % ) ; +; HPS_INTERFACE_CLOCKS_RESETS_INPUTs ; 0 / 7 ( 0 % ) ; +; HPS_INTERFACE_CLOCKS_RESETS_OUTPUTs ; 0 / 6 ( 0 % ) ; +; HPS_INTERFACE_CROSS_TRIGGER_INPUTs ; 0 / 18 ( 0 % ) ; +; HPS_INTERFACE_CROSS_TRIGGER_OUTPUTs ; 0 / 24 ( 0 % ) ; +; HPS_INTERFACE_DBG_APB_INPUTs ; 0 / 37 ( 0 % ) ; +; HPS_INTERFACE_DBG_APB_OUTPUTs ; 0 / 55 ( 0 % ) ; +; HPS_INTERFACE_DMA_INPUTs ; 0 / 16 ( 0 % ) ; +; HPS_INTERFACE_DMA_OUTPUTs ; 0 / 8 ( 0 % ) ; +; HPS_INTERFACE_FPGA2HPS_INPUTs ; 0 / 287 ( 0 % ) ; +; HPS_INTERFACE_FPGA2HPS_OUTPUTs ; 0 / 154 ( 0 % ) ; +; HPS_INTERFACE_FPGA2SDRAM_INPUTs ; 0 / 852 ( 0 % ) ; +; HPS_INTERFACE_FPGA2SDRAM_OUTPUTs ; 0 / 408 ( 0 % ) ; +; HPS_INTERFACE_HPS2FPGA_INPUTs ; 0 / 165 ( 0 % ) ; +; HPS_INTERFACE_HPS2FPGA_LIGHT_WEIGHT_INPUTs ; 0 / 67 ( 0 % ) ; +; HPS_INTERFACE_HPS2FPGA_LIGHT_WEIGHT_OUTPUTs ; 0 / 156 ( 0 % ) ; +; HPS_INTERFACE_HPS2FPGA_OUTPUTs ; 0 / 282 ( 0 % ) ; +; HPS_INTERFACE_INTERRUPTS_INPUTs ; 0 / 64 ( 0 % ) ; +; HPS_INTERFACE_INTERRUPTS_OUTPUTs ; 0 / 42 ( 0 % ) ; +; HPS_INTERFACE_JTAG_OUTPUTs ; 0 / 5 ( 0 % ) ; +; HPS_INTERFACE_LOAN_IO_INPUTs ; 0 / 142 ( 0 % ) ; +; HPS_INTERFACE_LOAN_IO_OUTPUTs ; 0 / 85 ( 0 % ) ; +; HPS_INTERFACE_MPU_EVENT_STANDBY_INPUTs ; 0 / 1 ( 0 % ) ; +; HPS_INTERFACE_MPU_EVENT_STANDBY_OUTPUTs ; 0 / 5 ( 0 % ) ; +; HPS_INTERFACE_MPU_GENERAL_PURPOSE_INPUTs ; 0 / 32 ( 0 % ) ; +; HPS_INTERFACE_MPU_GENERAL_PURPOSE_OUTPUTs ; 0 / 32 ( 0 % ) ; +; HPS_INTERFACE_PERIPHERAL_CAN_INPUTs ; 0 / 2 ( 0 % ) ; +; HPS_INTERFACE_PERIPHERAL_CAN_OUTPUTs ; 0 / 2 ( 0 % ) ; +; HPS_INTERFACE_PERIPHERAL_EMAC_INPUTs ; 0 / 32 ( 0 % ) ; +; HPS_INTERFACE_PERIPHERAL_EMAC_OUTPUTs ; 0 / 34 ( 0 % ) ; +; HPS_INTERFACE_PERIPHERAL_I2C_INPUTs ; 0 / 8 ( 0 % ) ; +; HPS_INTERFACE_PERIPHERAL_I2C_OUTPUTs ; 0 / 8 ( 0 % ) ; +; HPS_INTERFACE_PERIPHERAL_NAND_INPUTs ; 0 / 12 ( 0 % ) ; +; HPS_INTERFACE_PERIPHERAL_NAND_OUTPUTs ; 0 / 18 ( 0 % ) ; +; HPS_INTERFACE_PERIPHERAL_QSPI_INPUTs ; 0 / 4 ( 0 % ) ; +; HPS_INTERFACE_PERIPHERAL_QSPI_OUTPUTs ; 0 / 13 ( 0 % ) ; +; HPS_INTERFACE_PERIPHERAL_SDMMC_INPUTs ; 0 / 13 ( 0 % ) ; +; HPS_INTERFACE_PERIPHERAL_SDMMC_OUTPUTs ; 0 / 22 ( 0 % ) ; +; HPS_INTERFACE_PERIPHERAL_SPI_MASTER_INPUTs ; 0 / 4 ( 0 % ) ; +; HPS_INTERFACE_PERIPHERAL_SPI_MASTER_OUTPUTs ; 0 / 14 ( 0 % ) ; +; HPS_INTERFACE_PERIPHERAL_SPI_SLAVE_INPUTs ; 0 / 6 ( 0 % ) ; +; HPS_INTERFACE_PERIPHERAL_SPI_SLAVE_OUTPUTs ; 0 / 4 ( 0 % ) ; +; HPS_INTERFACE_PERIPHERAL_UART_INPUTs ; 0 / 10 ( 0 % ) ; +; HPS_INTERFACE_PERIPHERAL_UART_OUTPUTs ; 0 / 10 ( 0 % ) ; +; HPS_INTERFACE_PERIPHERAL_USB_INPUTs ; 0 / 22 ( 0 % ) ; +; HPS_INTERFACE_PERIPHERAL_USB_OUTPUTs ; 0 / 34 ( 0 % ) ; +; HPS_INTERFACE_STM_EVENT_INPUTs ; 0 / 28 ( 0 % ) ; +; HPS_INTERFACE_TEST_INPUTs ; 0 / 610 ( 0 % ) ; +; HPS_INTERFACE_TEST_OUTPUTs ; 0 / 513 ( 0 % ) ; +; HPS_INTERFACE_TPIU_TRACE_INPUTs ; 0 / 2 ( 0 % ) ; +; HPS_INTERFACE_TPIU_TRACE_OUTPUTs ; 0 / 33 ( 0 % ) ; +; Horizontal periphery clocks ; 0 / 72 ( 0 % ) ; +; Local interconnects ; 92 / 84,580 ( < 1 % ) ; +; Quadrant clocks ; 0 / 66 ( 0 % ) ; +; R14 interconnects ; 20 / 12,676 ( < 1 % ) ; +; R14/C12 interconnect drivers ; 17 / 20,720 ( < 1 % ) ; +; R3 interconnects ; 199 / 130,992 ( < 1 % ) ; +; R6 interconnects ; 274 / 266,960 ( < 1 % ) ; +; Spine clocks ; 2 / 360 ( < 1 % ) ; +; Wire stub REs ; 0 / 15,858 ( 0 % ) ; ++---------------------------------------------+-------------------------+ + + ++------------------------------------------+ +; I/O Rules Summary ; ++----------------------------------+-------+ +; I/O Rules Statistic ; Total ; ++----------------------------------+-------+ +; Total I/O Rules ; 28 ; +; Number of I/O Rules Passed ; 6 ; +; Number of I/O Rules Failed ; 0 ; +; Number of I/O Rules Unchecked ; 0 ; +; Number of I/O Rules Inapplicable ; 22 ; ++----------------------------------+-------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; I/O Rules Details ; ++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+ +; Status ; ID ; Category ; Rule Description ; Severity ; Information ; Area ; Extra Information ; ++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+ +; Inapplicable ; IO_000001 ; Capacity Checks ; Number of pins in an I/O bank should not exceed the number of locations available. ; Critical ; No Location assignments found. ; I/O ; ; +; Inapplicable ; IO_000002 ; Capacity Checks ; Number of clocks in an I/O bank should not exceed the number of clocks available. ; Critical ; No Global Signal assignments found. ; I/O ; ; +; Inapplicable ; IO_000003 ; Capacity Checks ; Number of pins in a Vrefgroup should not exceed the number of locations available. ; Critical ; No Location assignments found. ; I/O ; ; +; Inapplicable ; IO_000004 ; Voltage Compatibility Checks ; The I/O bank should support the requested VCCIO. ; Critical ; No IOBANK_VCCIO assignments found. ; I/O ; ; +; Inapplicable ; IO_000005 ; Voltage Compatibility Checks ; The I/O bank should not have competing VREF values. ; Critical ; No VREF I/O Standard assignments found. ; I/O ; ; +; Pass ; IO_000006 ; Voltage Compatibility Checks ; The I/O bank should not have competing VCCIO values. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000007 ; Valid Location Checks ; Checks for unavailable locations. ; Critical ; No Location assignments found. ; I/O ; ; +; Inapplicable ; IO_000008 ; Valid Location Checks ; Checks for reserved locations. ; Critical ; No reserved LogicLock region found. ; I/O ; ; +; Pass ; IO_000009 ; I/O Properties Checks for One I/O ; The location should support the requested I/O standard. ; Critical ; 0 such failures found. ; I/O ; ; +; Pass ; IO_000010 ; I/O Properties Checks for One I/O ; The location should support the requested I/O direction. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000011 ; I/O Properties Checks for One I/O ; The location should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ; +; Pass ; IO_000012 ; I/O Properties Checks for One I/O ; The location should support the requested On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000013 ; I/O Properties Checks for One I/O ; The location should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ; +; Inapplicable ; IO_000014 ; I/O Properties Checks for One I/O ; The location should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ; +; Inapplicable ; IO_000015 ; I/O Properties Checks for One I/O ; The location should support the requested PCI Clamp Diode. ; Critical ; No Clamping Diode assignments found. ; I/O ; ; +; Inapplicable ; IO_000018 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ; +; Pass ; IO_000019 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000020 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested PCI Clamp Diode. ; Critical ; No Clamping Diode assignments found. ; I/O ; ; +; Inapplicable ; IO_000021 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ; +; Inapplicable ; IO_000022 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ; +; Inapplicable ; IO_000023 ; I/O Properties Checks for One I/O ; The I/O standard should support the Open Drain value. ; Critical ; No open drain assignments found. ; I/O ; ; +; Pass ; IO_000024 ; I/O Properties Checks for One I/O ; The I/O direction should support the On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000026 ; I/O Properties Checks for One I/O ; On Chip Termination and Current Strength should not be used at the same time. ; Critical ; No Current Strength assignments found. ; I/O ; ; +; Inapplicable ; IO_000027 ; I/O Properties Checks for One I/O ; Weak Pull Up and Bus Hold should not be used at the same time. ; Critical ; No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found. ; I/O ; ; +; Inapplicable ; IO_000045 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ; +; Inapplicable ; IO_000046 ; I/O Properties Checks for One I/O ; The location should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ; +; Inapplicable ; IO_000047 ; I/O Properties Checks for One I/O ; On Chip Termination and Slew Rate should not be used at the same time. ; Critical ; No Slew Rate assignments found. ; I/O ; ; +; Inapplicable ; IO_000034 ; SI Related Distance Checks ; Single-ended outputs should be 0 LAB row(s) away from a differential I/O. ; High ; No Differential I/O Standard assignments found. ; I/O ; ; +; ---- ; ---- ; Disclaimer ; OCT rules are checked but not reported. ; None ; ---- ; On Chip Termination ; ; ++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; I/O Rules Matrix ; ++--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+ +; Pin/Rules ; IO_000001 ; IO_000002 ; IO_000003 ; IO_000004 ; IO_000005 ; IO_000006 ; IO_000007 ; IO_000008 ; IO_000009 ; IO_000010 ; IO_000011 ; IO_000012 ; IO_000013 ; IO_000014 ; IO_000015 ; IO_000018 ; IO_000019 ; IO_000020 ; IO_000021 ; IO_000022 ; IO_000023 ; IO_000024 ; IO_000026 ; IO_000027 ; IO_000045 ; IO_000046 ; IO_000047 ; IO_000034 ; ++--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+ +; Total Pass ; 0 ; 0 ; 0 ; 0 ; 0 ; 41 ; 0 ; 0 ; 41 ; 41 ; 0 ; 29 ; 0 ; 0 ; 0 ; 0 ; 29 ; 0 ; 0 ; 0 ; 0 ; 29 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; Total Unchecked ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; Total Inapplicable ; 41 ; 41 ; 41 ; 41 ; 41 ; 0 ; 41 ; 41 ; 0 ; 0 ; 41 ; 12 ; 41 ; 41 ; 41 ; 41 ; 12 ; 41 ; 41 ; 41 ; 41 ; 12 ; 41 ; 41 ; 41 ; 41 ; 41 ; 41 ; +; Total Fail ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; SW[0] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; SW[1] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; SW[2] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; SW[3] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; SW[4] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; SW[5] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; SW[6] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; SW[7] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; SW[8] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; SW[9] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; HEX0[0] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; HEX0[1] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; HEX0[2] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; HEX0[3] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; HEX0[4] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; HEX0[5] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; HEX0[6] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; HEX1[0] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; HEX1[1] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; HEX1[2] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; HEX1[3] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; HEX1[4] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; HEX1[5] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; HEX1[6] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; HEX2[0] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; HEX2[1] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; HEX2[2] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; HEX2[3] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; HEX2[4] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; HEX2[5] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; HEX2[6] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; DAC_SDI ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; DAC_SCK ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; DAC_CS ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; DAC_LD ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; ADC_SDI ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; ADC_SCK ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; ADC_CS ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; PWM_OUT ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; CLOCK_50 ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; ADC_SDO ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; ++--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+ + + ++------------------------------------------------------------------------------------------------+ +; Fitter Device Options ; ++------------------------------------------------------------------+-----------------------------+ +; Option ; Setting ; ++------------------------------------------------------------------+-----------------------------+ +; Enable user-supplied start-up clock (CLKUSR) ; Off ; +; Enable device-wide reset (DEV_CLRn) ; Off ; +; Enable device-wide output enable (DEV_OE) ; Off ; +; Enable INIT_DONE output ; Off ; +; Configuration scheme ; Passive Serial ; +; Enable Error Detection CRC_ERROR pin ; Off ; +; Enable CvP_CONFDONE pin ; Off ; +; Enable open drain on CRC_ERROR pin ; On ; +; Enable open drain on CvP_CONFDONE pin ; On ; +; Enable open drain on INIT_DONE pin ; On ; +; Enable open drain on Partial Reconfiguration pins ; Off ; +; Enable open drain on nCEO pin ; On ; +; Enable Partial Reconfiguration pins ; Off ; +; Enable input tri-state on active configuration pins in user mode ; Off ; +; Enable internal scrubbing ; Off ; +; Active Serial clock source ; 100 MHz Internal Oscillator ; +; Device initialization clock source ; Internal Oscillator ; +; Configuration via Protocol ; Off ; +; Configuration Voltage Level ; Auto ; +; Force Configuration Voltage Level ; Off ; +; Enable nCEO output ; Off ; +; Data[15..8] ; Unreserved ; +; Data[7..5] ; Unreserved ; +; Base pin-out file on sameframe device ; Off ; ++------------------------------------------------------------------+-----------------------------+ + + ++------------------------------------+ +; Operating Settings and Conditions ; ++---------------------------+--------+ +; Setting ; Value ; ++---------------------------+--------+ +; Nominal Core Voltage ; 1.10 V ; +; Low Junction Temperature ; 0 °C ; +; High Junction Temperature ; 85 °C ; ++---------------------------+--------+ + + ++------------------------------------------------------------+ +; Estimated Delay Added for Hold Timing Summary ; ++-----------------+----------------------+-------------------+ +; Source Clock(s) ; Destination Clock(s) ; Delay Added in ns ; ++-----------------+----------------------+-------------------+ +; CLOCK_50 ; CLOCK_50 ; 53.0 ; ++-----------------+----------------------+-------------------+ +Note: For more information on problematic transfers, consider running the Fitter again with the Optimize hold timing option (Settings Menu) turned off. +This will disable optimization of problematic paths and expose them for further analysis using the TimeQuest Timing Analyzer. + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Estimated Delay Added for Hold Timing Details ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+ +; Source Register ; Destination Register ; Delay Added in ns ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+ +; pwm:PWM_DC|count[6] ; pwm:PWM_DC|pwm_out ; 0.647 ; +; pwm:PWM_DC|count[7] ; pwm:PWM_DC|pwm_out ; 0.568 ; +; pwm:PWM_DC|d[5] ; pwm:PWM_DC|pwm_out ; 0.528 ; +; pwm:PWM_DC|d[4] ; pwm:PWM_DC|pwm_out ; 0.528 ; +; pwm:PWM_DC|d[7] ; pwm:PWM_DC|pwm_out ; 0.528 ; +; pwm:PWM_DC|d[6] ; pwm:PWM_DC|pwm_out ; 0.528 ; +; pwm:PWM_DC|count[5] ; pwm:PWM_DC|pwm_out ; 0.528 ; +; pwm:PWM_DC|count[4] ; pwm:PWM_DC|pwm_out ; 0.528 ; +; spi2adc:SPI_ADC|data_from_adc[2] ; processor:ALLPASS|data_out[9] ; 0.484 ; +; spi2adc:SPI_ADC|data_from_adc[0] ; processor:ALLPASS|data_out[9] ; 0.479 ; +; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|cntr_1ib:rd_ptr_count|counter_reg_bit[8] ; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|altsyncram_44t1:FIFOram|ram_block1a6~portb_address_reg0 ; 0.399 ; +; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|cntr_1ib:rd_ptr_count|counter_reg_bit[6] ; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|altsyncram_44t1:FIFOram|ram_block1a6~portb_address_reg0 ; 0.399 ; +; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|cntr_1ib:rd_ptr_count|counter_reg_bit[5] ; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|altsyncram_44t1:FIFOram|ram_block1a6~portb_address_reg0 ; 0.399 ; +; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|cntr_1ib:rd_ptr_count|counter_reg_bit[2] ; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|altsyncram_44t1:FIFOram|ram_block1a6~portb_address_reg0 ; 0.399 ; +; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|cntr_1ib:rd_ptr_count|counter_reg_bit[12] ; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|altsyncram_44t1:FIFOram|ram_block1a6~portb_address_reg0 ; 0.399 ; +; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|cntr_1ib:rd_ptr_count|counter_reg_bit[11] ; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|altsyncram_44t1:FIFOram|ram_block1a6~portb_address_reg0 ; 0.396 ; +; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|cntr_1ib:rd_ptr_count|counter_reg_bit[10] ; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|altsyncram_44t1:FIFOram|ram_block1a6~portb_address_reg0 ; 0.396 ; +; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|cntr_1ib:rd_ptr_count|counter_reg_bit[7] ; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|altsyncram_44t1:FIFOram|ram_block1a6~portb_address_reg0 ; 0.396 ; +; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|cntr_1ib:rd_ptr_count|counter_reg_bit[4] ; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|altsyncram_44t1:FIFOram|ram_block1a6~portb_address_reg0 ; 0.396 ; +; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|cntr_1ib:rd_ptr_count|counter_reg_bit[9] ; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|altsyncram_44t1:FIFOram|ram_block1a6~portb_address_reg0 ; 0.395 ; +; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|cntr_1ib:rd_ptr_count|counter_reg_bit[3] ; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|altsyncram_44t1:FIFOram|ram_block1a6~portb_address_reg0 ; 0.395 ; +; spi2adc:SPI_ADC|shift_reg[7] ; spi2adc:SPI_ADC|shift_reg[8] ; 0.356 ; +; spi2adc:SPI_ADC|shift_reg[5] ; spi2adc:SPI_ADC|shift_reg[6] ; 0.356 ; +; spi2adc:SPI_ADC|shift_reg[3] ; spi2adc:SPI_ADC|shift_reg[4] ; 0.356 ; +; spi2adc:SPI_ADC|state[1] ; spi2adc:SPI_ADC|adc_din ; 0.350 ; +; spi2adc:SPI_ADC|ctr[0] ; spi2adc:SPI_ADC|ctr[2] ; 0.349 ; +; spi2adc:SPI_ADC|state[0] ; spi2adc:SPI_ADC|adc_din ; 0.347 ; +; spi2adc:SPI_ADC|ctr[2] ; spi2adc:SPI_ADC|clk_1MHz ; 0.344 ; +; spi2adc:SPI_ADC|shift_reg[8] ; spi2adc:SPI_ADC|shift_reg[9] ; 0.343 ; +; spi2adc:SPI_ADC|shift_reg[4] ; spi2adc:SPI_ADC|shift_reg[5] ; 0.343 ; +; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|a_fefifo_4be:fifo_state|cntr_di7:count_usedw|counter_reg_bit[3] ; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|a_fefifo_4be:fifo_state|b_full ; 0.342 ; +; spi2dac:SPI_DAC|state[1] ; spi2dac:SPI_DAC|state[0] ; 0.340 ; +; spi2adc:SPI_ADC|shift_reg[6] ; spi2adc:SPI_ADC|shift_reg[7] ; 0.338 ; +; spi2adc:SPI_ADC|shift_reg[0] ; spi2adc:SPI_ADC|shift_reg[1] ; 0.338 ; +; spi2adc:SPI_ADC|ctr[1] ; spi2adc:SPI_ADC|ctr[3] ; 0.335 ; +; spi2dac:SPI_DAC|state[0] ; spi2dac:SPI_DAC|state[3] ; 0.334 ; +; spi2adc:SPI_ADC|state[4] ; spi2adc:SPI_ADC|adc_din ; 0.325 ; +; spi2dac:SPI_DAC|sr_state.WAIT_CSB_FALL ; spi2dac:SPI_DAC|shift_reg[15] ; 0.324 ; +; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|cntr_1ib:wr_ptr|counter_reg_bit[9] ; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|altsyncram_44t1:FIFOram|ram_block1a5~porta_address_reg0 ; 0.317 ; +; spi2adc:SPI_ADC|ctr[4] ; spi2adc:SPI_ADC|ctr[2] ; 0.317 ; +; spi2adc:SPI_ADC|clk_1MHz ; spi2adc:SPI_ADC|tick ; 0.316 ; +; processor:ALLPASS|pulse_gen:PULSE0|pulse ; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|altsyncram_44t1:FIFOram|ram_block1a9~porta_we_reg ; 0.313 ; +; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|cntr_1ib:wr_ptr|counter_reg_bit[8] ; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|altsyncram_44t1:FIFOram|ram_block1a5~porta_address_reg0 ; 0.307 ; +; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|cntr_1ib:wr_ptr|counter_reg_bit[4] ; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|altsyncram_44t1:FIFOram|ram_block1a5~porta_address_reg0 ; 0.305 ; +; spi2dac:SPI_DAC|state[4] ; spi2dac:SPI_DAC|sr_state.WAIT_CSB_HIGH ; 0.303 ; +; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|cntr_1ib:wr_ptr|counter_reg_bit[10] ; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|altsyncram_44t1:FIFOram|ram_block1a5~porta_address_reg0 ; 0.297 ; +; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|cntr_1ib:wr_ptr|counter_reg_bit[6] ; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|altsyncram_44t1:FIFOram|ram_block1a5~porta_address_reg0 ; 0.297 ; +; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|cntr_1ib:wr_ptr|counter_reg_bit[12] ; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|altsyncram_44t1:FIFOram|ram_block1a5~porta_address_reg0 ; 0.296 ; +; spi2adc:SPI_ADC|adc_cs ; spi2adc:SPI_ADC|sr_state.WAIT_CSB_FALL ; 0.292 ; +; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|cntr_1ib:wr_ptr|counter_reg_bit[5] ; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|altsyncram_44t1:FIFOram|ram_block1a5~porta_address_reg0 ; 0.285 ; +; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|a_fefifo_4be:fifo_state|cntr_di7:count_usedw|counter_reg_bit[2] ; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|a_fefifo_4be:fifo_state|b_full ; 0.283 ; +; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|a_fefifo_4be:fifo_state|cntr_di7:count_usedw|counter_reg_bit[1] ; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|a_fefifo_4be:fifo_state|b_full ; 0.283 ; +; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|a_fefifo_4be:fifo_state|cntr_di7:count_usedw|counter_reg_bit[0] ; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|a_fefifo_4be:fifo_state|b_full ; 0.283 ; +; spi2adc:SPI_ADC|adc_start ; spi2adc:SPI_ADC|adc_din ; 0.281 ; +; spi2adc:SPI_ADC|state[2] ; spi2adc:SPI_ADC|shift_ena ; 0.280 ; +; processor:ALLPASS|pulse_gen:PULSE0|state.IDLE ; processor:ALLPASS|pulse_gen:PULSE0|pulse ; 0.274 ; +; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|cntr_1ib:wr_ptr|counter_reg_bit[11] ; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|altsyncram_44t1:FIFOram|ram_block1a5~porta_address_reg0 ; 0.271 ; +; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|cntr_1ib:wr_ptr|counter_reg_bit[7] ; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|altsyncram_44t1:FIFOram|ram_block1a5~porta_address_reg0 ; 0.265 ; +; spi2dac:SPI_DAC|shift_reg[12] ; spi2dac:SPI_DAC|shift_reg[13] ; 0.264 ; +; spi2dac:SPI_DAC|sr_state.IDLE ; spi2dac:SPI_DAC|sr_state.WAIT_CSB_FALL ; 0.263 ; +; spi2dac:SPI_DAC|sr_state.WAIT_CSB_HIGH ; spi2dac:SPI_DAC|sr_state.IDLE ; 0.263 ; +; spi2adc:SPI_ADC|state[3] ; spi2adc:SPI_ADC|shift_ena ; 0.255 ; +; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|cntr_1ib:wr_ptr|counter_reg_bit[1] ; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|altsyncram_44t1:FIFOram|ram_block1a5~porta_address_reg0 ; 0.254 ; +; spi2adc:SPI_ADC|data_from_adc[1] ; processor:ALLPASS|data_out[9] ; 0.254 ; +; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|cntr_1ib:wr_ptr|counter_reg_bit[0] ; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|altsyncram_44t1:FIFOram|ram_block1a5~porta_address_reg0 ; 0.245 ; +; spi2dac:SPI_DAC|shift_reg[13] ; spi2dac:SPI_DAC|shift_reg[14] ; 0.241 ; +; spi2dac:SPI_DAC|state[3] ; spi2dac:SPI_DAC|state[4] ; 0.240 ; +; spi2dac:SPI_DAC|shift_reg[14] ; spi2dac:SPI_DAC|shift_reg[15] ; 0.240 ; +; spi2dac:SPI_DAC|state[2] ; spi2dac:SPI_DAC|state[0] ; 0.239 ; +; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|cntr_1ib:rd_ptr_count|counter_reg_bit[0] ; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|altsyncram_44t1:FIFOram|ram_block1a6~portb_address_reg0 ; 0.237 ; +; spi2adc:SPI_ADC|ctr[3] ; spi2adc:SPI_ADC|clk_1MHz ; 0.236 ; +; spi2adc:SPI_ADC|sr_state.WAIT_CSB_FALL ; spi2adc:SPI_ADC|adc_start ; 0.226 ; +; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|cntr_1ib:wr_ptr|counter_reg_bit[2] ; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|altsyncram_44t1:FIFOram|ram_block1a5~porta_address_reg0 ; 0.224 ; +; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|cntr_1ib:wr_ptr|counter_reg_bit[3] ; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|altsyncram_44t1:FIFOram|ram_block1a5~porta_address_reg0 ; 0.221 ; +; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|a_fefifo_4be:fifo_state|cntr_di7:count_usedw|counter_reg_bit[12] ; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|a_fefifo_4be:fifo_state|b_full ; 0.220 ; +; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|a_fefifo_4be:fifo_state|cntr_di7:count_usedw|counter_reg_bit[11] ; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|a_fefifo_4be:fifo_state|b_full ; 0.220 ; +; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|a_fefifo_4be:fifo_state|cntr_di7:count_usedw|counter_reg_bit[10] ; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|a_fefifo_4be:fifo_state|b_full ; 0.220 ; +; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|a_fefifo_4be:fifo_state|cntr_di7:count_usedw|counter_reg_bit[9] ; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|a_fefifo_4be:fifo_state|b_full ; 0.220 ; +; processor:ALLPASS|full_reg ; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|a_fefifo_4be:fifo_state|b_full ; 0.220 ; +; pwm:PWM_DC|d[9] ; pwm:PWM_DC|pwm_out ; 0.218 ; +; pwm:PWM_DC|d[8] ; pwm:PWM_DC|pwm_out ; 0.218 ; +; pwm:PWM_DC|count[9] ; pwm:PWM_DC|pwm_out ; 0.218 ; +; pwm:PWM_DC|count[8] ; pwm:PWM_DC|pwm_out ; 0.218 ; +; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|cntr_1ib:rd_ptr_count|counter_reg_bit[1] ; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|altsyncram_44t1:FIFOram|ram_block1a6~portb_address_reg0 ; 0.214 ; +; spi2adc:SPI_ADC|sr_state.IDLE ; spi2adc:SPI_ADC|sr_state.WAIT_CSB_FALL ; 0.189 ; +; spi2adc:SPI_ADC|shift_reg[2] ; spi2adc:SPI_ADC|shift_reg[3] ; 0.184 ; +; spi2adc:SPI_ADC|shift_reg[1] ; spi2adc:SPI_ADC|shift_reg[2] ; 0.183 ; +; spi2adc:SPI_ADC|sr_state.WAIT_CSB_HIGH ; spi2adc:SPI_ADC|sr_state.IDLE ; 0.180 ; +; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|a_fefifo_4be:fifo_state|b_full ; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|altsyncram_44t1:FIFOram|ram_block1a9~porta_we_reg ; 0.166 ; +; processor:ALLPASS|data_out[3] ; spi2dac:SPI_DAC|shift_reg[5] ; 0.165 ; +; pwm:PWM_DC|d[3] ; pwm:PWM_DC|pwm_out ; 0.165 ; +; pwm:PWM_DC|d[2] ; pwm:PWM_DC|pwm_out ; 0.165 ; +; pwm:PWM_DC|d[1] ; pwm:PWM_DC|pwm_out ; 0.165 ; +; pwm:PWM_DC|d[0] ; pwm:PWM_DC|pwm_out ; 0.165 ; +; pwm:PWM_DC|count[3] ; pwm:PWM_DC|pwm_out ; 0.165 ; +; pwm:PWM_DC|count[2] ; pwm:PWM_DC|pwm_out ; 0.165 ; +; pwm:PWM_DC|count[1] ; pwm:PWM_DC|pwm_out ; 0.165 ; +; pwm:PWM_DC|count[0] ; pwm:PWM_DC|pwm_out ; 0.165 ; +; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|a_fefifo_4be:fifo_state|cntr_di7:count_usedw|counter_reg_bit[8] ; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|a_fefifo_4be:fifo_state|b_full ; 0.073 ; +; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|a_fefifo_4be:fifo_state|cntr_di7:count_usedw|counter_reg_bit[7] ; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|a_fefifo_4be:fifo_state|b_full ; 0.073 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+ +Note: This table only shows the top 100 path(s) that have the largest delay added for hold. + + ++-----------------+ +; Fitter Messages ; ++-----------------+ +Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. +Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected +Info (119006): Selected device 5CSEMA5F31C6 for design "ex18_top" +Info (21077): Low junction temperature is 0 degrees C +Info (21077): High junction temperature is 85 degrees C +Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time +Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature. +Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details +Info (176045): Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements. +Critical Warning (169085): No exact pin location assignment(s) for 41 pins of 41 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report. +Info (184020): Starting Fitter periphery placement operations +Info (11191): Automatically promoted 1 clock (1 global) + Info (11162): CLOCK_50~inputCLKENA0 with 171 fanout uses global clock CLKCTRL_G10 +Info (184021): Fitter periphery placement operations ending: elapsed time is 00:00:01 +Info (176233): Starting register packing +Info (332104): Reading SDC File: 'ex18_top.sdc' +Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty" +Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. +Info (332129): Detected timing requirements -- optimizing circuit to achieve only the specified requirements +Info (332111): Found 1 clocks + Info (332111): Period Clock Name + Info (332111): ======== ============ + Info (332111): 20.000 CLOCK_50 +Info (176235): Finished register packing + Extra Info (176219): No registers were packed into other blocks +Info (11798): Fitter preparation operations ending: elapsed time is 00:00:58 +Info (170189): Fitter placement preparation operations beginning +Info (14951): The Fitter is using Advanced Physical Optimization. +Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:09 +Info (170191): Fitter placement operations beginning +Info (170137): Fitter placement was successful +Info (170192): Fitter placement operations ending: elapsed time is 00:00:01 +Info (170193): Fitter routing operations beginning +Info (170195): Router estimated average interconnect usage is 0% of the available device resources + Info (170196): Router estimated peak interconnect usage is 2% of the available device resources in the region that extends from location X45_Y0 to location X55_Y10 +Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time. + Info (170201): Optimizations that may affect the design's routability were skipped + Info (170200): Optimizations that may affect the design's timing were skipped +Info (170194): Fitter routing operations ending: elapsed time is 00:00:03 +Info (11888): Total time spent on timing analysis during the Fitter is 1.98 seconds. +Info (334003): Started post-fitting delay annotation +Info (334004): Delay annotation completed successfully +Info (334003): Started post-fitting delay annotation +Info (334004): Delay annotation completed successfully +Info (11801): Fitter post-fit operations ending: elapsed time is 00:00:11 +Info (144001): Generated suppressed messages file H:/Year 2/VERI/part_4/ex18/output_files/ex18_top.fit.smsg +Info: Quartus Prime Fitter was successful. 0 errors, 4 warnings + Info: Peak virtual memory: 2163 megabytes + Info: Processing ended: Sat Dec 10 19:01:58 2016 + Info: Elapsed time: 00:02:58 + Info: Total CPU time (on all processors): 00:02:03 + + ++----------------------------+ +; Fitter Suppressed Messages ; ++----------------------------+ +The suppressed messages can be found in H:/Year 2/VERI/part_4/ex18/output_files/ex18_top.fit.smsg. + + diff --git a/part_4/ex18/output_files/ex18_top.flow.rpt b/part_4/ex18/output_files/ex18_top.flow.rpt new file mode 100644 index 0000000..975dcc2 --- /dev/null +++ b/part_4/ex18/output_files/ex18_top.flow.rpt @@ -0,0 +1,127 @@ +Flow report for ex18_top +Sat Dec 10 19:04:46 2016 +Quartus Prime Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Flow Summary + 3. Flow Settings + 4. Flow Non-Default Global Settings + 5. Flow Elapsed Time + 6. Flow OS Summary + 7. Flow Log + 8. Flow Messages + 9. Flow Suppressed Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2016 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel MegaCore Function License Agreement, or other +applicable license agreement, including, without limitation, +that your use is for the sole purpose of programming logic +devices manufactured by Intel and sold by Intel or its +authorized distributors. Please refer to the applicable +agreement for further details. + + + ++-------------------------------------------------------------------------------+ +; Flow Summary ; ++---------------------------------+---------------------------------------------+ +; Flow Status ; Successful - Sat Dec 10 19:03:26 2016 ; +; Quartus Prime Version ; 16.1.0 Build 196 10/24/2016 SJ Lite Edition ; +; Revision Name ; ex18_top ; +; Top-level Entity Name ; ex18_top ; +; Family ; Cyclone V ; +; Device ; 5CSEMA5F31C6 ; +; Timing Models ; Final ; +; Logic utilization (in ALMs) ; 91 / 32,070 ( < 1 % ) ; +; Total registers ; 170 ; +; Total pins ; 41 / 457 ( 9 % ) ; +; Total virtual pins ; 0 ; +; Total block memory bits ; 73,728 / 4,065,280 ( 2 % ) ; +; Total DSP Blocks ; 0 / 87 ( 0 % ) ; +; Total HSSI RX PCSs ; 0 ; +; Total HSSI PMA RX Deserializers ; 0 ; +; Total HSSI TX PCSs ; 0 ; +; Total HSSI PMA TX Serializers ; 0 ; +; Total PLLs ; 0 / 6 ( 0 % ) ; +; Total DLLs ; 0 / 4 ( 0 % ) ; ++---------------------------------+---------------------------------------------+ + + ++-----------------------------------------+ +; Flow Settings ; ++-------------------+---------------------+ +; Option ; Setting ; ++-------------------+---------------------+ +; Start date & time ; 12/10/2016 18:57:39 ; +; Main task ; Compilation ; +; Revision Name ; ex18_top ; ++-------------------+---------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------+ +; Flow Non-Default Global Settings ; ++-------------------------------------+----------------------------------------+---------------+-------------+------------+ +; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ; ++-------------------------------------+----------------------------------------+---------------+-------------+------------+ +; COMPILER_SIGNATURE_ID ; 147774608559.148139625803232 ; -- ; -- ; -- ; +; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ; +; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ; +; MISC_FILE ; FIFO_bb.v ; -- ; -- ; -- ; +; PARTITION_COLOR ; -- (Not supported for targeted family) ; -- ; -- ; Top ; +; PARTITION_FITTER_PRESERVATION_LEVEL ; -- (Not supported for targeted family) ; -- ; -- ; Top ; +; PARTITION_NETLIST_TYPE ; -- (Not supported for targeted family) ; -- ; -- ; Top ; +; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ; ++-------------------------------------+----------------------------------------+---------------+-------------+------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------+ +; Flow Elapsed Time ; ++---------------------------+--------------+-------------------------+---------------------+------------------------------------+ +; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; ++---------------------------+--------------+-------------------------+---------------------+------------------------------------+ +; Analysis & Synthesis ; 00:00:58 ; 1.0 ; 703 MB ; 00:00:38 ; +; Fitter ; 00:02:37 ; 1.0 ; 2163 MB ; 00:02:01 ; +; Assembler ; 00:00:49 ; 1.0 ; 726 MB ; 00:00:13 ; +; TimeQuest Timing Analyzer ; 00:01:11 ; 1.0 ; 1027 MB ; 00:00:13 ; +; Total ; 00:05:35 ; -- ; -- ; 00:03:05 ; ++---------------------------+--------------+-------------------------+---------------------+------------------------------------+ + + ++-----------------------------------------------------------------------------------------+ +; Flow OS Summary ; ++---------------------------+------------------+------------+------------+----------------+ +; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ; ++---------------------------+------------------+------------+------------+----------------+ +; Analysis & Synthesis ; Xav-Laptop ; Windows 10 ; 10.0 ; x86_64 ; +; Fitter ; Xav-Laptop ; Windows 10 ; 10.0 ; x86_64 ; +; Assembler ; Xav-Laptop ; Windows 10 ; 10.0 ; x86_64 ; +; TimeQuest Timing Analyzer ; Xav-Laptop ; Windows 10 ; 10.0 ; x86_64 ; ++---------------------------+------------------+------------+------------+----------------+ + + +------------ +; Flow Log ; +------------ +quartus_map --read_settings_files=on --write_settings_files=off ex18 -c ex18_top +quartus_fit --read_settings_files=off --write_settings_files=off ex18 -c ex18_top +quartus_asm --read_settings_files=off --write_settings_files=off ex18 -c ex18_top +quartus_sta ex18 -c ex18_top + + + diff --git a/part_4/ex18/output_files/ex18_top.map.rpt b/part_4/ex18/output_files/ex18_top.map.rpt new file mode 100644 index 0000000..179348c --- /dev/null +++ b/part_4/ex18/output_files/ex18_top.map.rpt @@ -0,0 +1,714 @@ +Analysis & Synthesis report for ex18_top +Sat Dec 10 18:58:45 2016 +Quartus Prime Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Analysis & Synthesis Summary + 3. Analysis & Synthesis Settings + 4. Parallel Compilation + 5. Analysis & Synthesis Source Files Read + 6. Analysis & Synthesis Resource Usage Summary + 7. Analysis & Synthesis Resource Utilization by Entity + 8. Analysis & Synthesis RAM Summary + 9. Analysis & Synthesis IP Cores Summary + 10. State Machine - |ex18_top|processor:ALLPASS|pulse_gen:PULSE0|state + 11. State Machine - |ex18_top|spi2adc:SPI_ADC|sr_state + 12. State Machine - |ex18_top|spi2dac:SPI_DAC|sr_state + 13. Registers Removed During Synthesis + 14. Removed Registers Triggering Further Register Optimizations + 15. General Register Statistics + 16. Inverted Register Statistics + 17. Multiplexer Restructuring Statistics (Restructuring Performed) + 18. Source assignments for processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|altsyncram_44t1:FIFOram + 19. Parameter Settings for User Entity Instance: clktick_16:GEN_10K + 20. Parameter Settings for User Entity Instance: spi2dac:SPI_DAC + 21. Parameter Settings for User Entity Instance: spi2adc:SPI_ADC + 22. Parameter Settings for User Entity Instance: processor:ALLPASS + 23. Parameter Settings for User Entity Instance: processor:ALLPASS|pulse_gen:PULSE0 + 24. Parameter Settings for User Entity Instance: processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component + 25. scfifo Parameter Settings by Entity Instance + 26. Port Connectivity Checks: "hex_to_7seg:SEG2" + 27. Port Connectivity Checks: "processor:ALLPASS|FIFO:DELAY1024" + 28. Port Connectivity Checks: "spi2adc:SPI_ADC" + 29. Port Connectivity Checks: "clktick_16:GEN_10K" + 30. Post-Synthesis Netlist Statistics for Top Partition + 31. Elapsed Time Per Partition + 32. Analysis & Synthesis Messages + 33. Analysis & Synthesis Suppressed Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2016 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel MegaCore Function License Agreement, or other +applicable license agreement, including, without limitation, +that your use is for the sole purpose of programming logic +devices manufactured by Intel and sold by Intel or its +authorized distributors. Please refer to the applicable +agreement for further details. + + + ++-------------------------------------------------------------------------------+ +; Analysis & Synthesis Summary ; ++---------------------------------+---------------------------------------------+ +; Analysis & Synthesis Status ; Successful - Sat Dec 10 18:58:43 2016 ; +; Quartus Prime Version ; 16.1.0 Build 196 10/24/2016 SJ Lite Edition ; +; Revision Name ; ex18_top ; +; Top-level Entity Name ; ex18_top ; +; Family ; Cyclone V ; +; Logic utilization (in ALMs) ; N/A ; +; Total registers ; 153 ; +; Total pins ; 41 ; +; Total virtual pins ; 0 ; +; Total block memory bits ; 73,728 ; +; Total DSP Blocks ; 0 ; +; Total HSSI RX PCSs ; 0 ; +; Total HSSI PMA RX Deserializers ; 0 ; +; Total HSSI TX PCSs ; 0 ; +; Total HSSI PMA TX Serializers ; 0 ; +; Total PLLs ; 0 ; +; Total DLLs ; 0 ; ++---------------------------------+---------------------------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Settings ; ++---------------------------------------------------------------------------------+--------------------+--------------------+ +; Option ; Setting ; Default Value ; ++---------------------------------------------------------------------------------+--------------------+--------------------+ +; Device ; 5CSEMA5F31C6 ; ; +; Top-level entity name ; ex18_top ; ex18_top ; +; Family name ; Cyclone V ; Cyclone V ; +; Use smart compilation ; Off ; Off ; +; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ; +; Enable compact report table ; Off ; Off ; +; Restructure Multiplexers ; Auto ; Auto ; +; MLAB Add Timing Constraints For Mixed-Port Feed-Through Mode Setting Don't Care ; Off ; Off ; +; Create Debugging Nodes for IP Cores ; Off ; Off ; +; Preserve fewer node names ; On ; On ; +; OpenCore Plus hardware evaluation ; Enable ; Enable ; +; Verilog Version ; Verilog_2001 ; Verilog_2001 ; +; VHDL Version ; VHDL_1993 ; VHDL_1993 ; +; State Machine Processing ; Auto ; Auto ; +; Safe State Machine ; Off ; Off ; +; Extract Verilog State Machines ; On ; On ; +; Extract VHDL State Machines ; On ; On ; +; Ignore Verilog initial constructs ; Off ; Off ; +; Iteration limit for constant Verilog loops ; 5000 ; 5000 ; +; Iteration limit for non-constant Verilog loops ; 250 ; 250 ; +; Add Pass-Through Logic to Inferred RAMs ; On ; On ; +; Infer RAMs from Raw Logic ; On ; On ; +; Parallel Synthesis ; On ; On ; +; DSP Block Balancing ; Auto ; Auto ; +; NOT Gate Push-Back ; On ; On ; +; Power-Up Don't Care ; On ; On ; +; Remove Redundant Logic Cells ; Off ; Off ; +; Remove Duplicate Registers ; On ; On ; +; Ignore CARRY Buffers ; Off ; Off ; +; Ignore CASCADE Buffers ; Off ; Off ; +; Ignore GLOBAL Buffers ; Off ; Off ; +; Ignore ROW GLOBAL Buffers ; Off ; Off ; +; Ignore LCELL Buffers ; Off ; Off ; +; Ignore SOFT Buffers ; On ; On ; +; Limit AHDL Integers to 32 Bits ; Off ; Off ; +; Optimization Technique ; Balanced ; Balanced ; +; Carry Chain Length ; 70 ; 70 ; +; Auto Carry Chains ; On ; On ; +; Auto Open-Drain Pins ; On ; On ; +; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ; +; Auto ROM Replacement ; On ; On ; +; Auto RAM Replacement ; On ; On ; +; Auto DSP Block Replacement ; On ; On ; +; Auto Shift Register Replacement ; Auto ; Auto ; +; Allow Shift Register Merging across Hierarchies ; Auto ; Auto ; +; Auto Clock Enable Replacement ; On ; On ; +; Strict RAM Replacement ; Off ; Off ; +; Allow Synchronous Control Signals ; On ; On ; +; Force Use of Synchronous Clear Signals ; Off ; Off ; +; Auto Resource Sharing ; Off ; Off ; +; Allow Any RAM Size For Recognition ; Off ; Off ; +; Allow Any ROM Size For Recognition ; Off ; Off ; +; Allow Any Shift Register Size For Recognition ; Off ; Off ; +; Use LogicLock Constraints during Resource Balancing ; On ; On ; +; Ignore translate_off and synthesis_off directives ; Off ; Off ; +; Timing-Driven Synthesis ; On ; On ; +; Report Parameter Settings ; On ; On ; +; Report Source Assignments ; On ; On ; +; Report Connectivity Checks ; On ; On ; +; Ignore Maximum Fan-Out Assignments ; Off ; Off ; +; Synchronization Register Chain Length ; 3 ; 3 ; +; PowerPlay Power Optimization During Synthesis ; Normal compilation ; Normal compilation ; +; HDL message level ; Level2 ; Level2 ; +; Suppress Register Optimization Related Messages ; Off ; Off ; +; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ; +; Number of Swept Nodes Reported in Synthesis Report ; 5000 ; 5000 ; +; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ; +; Clock MUX Protection ; On ; On ; +; Auto Gated Clock Conversion ; Off ; Off ; +; Block Design Naming ; Auto ; Auto ; +; SDC constraint protection ; Off ; Off ; +; Synthesis Effort ; Auto ; Auto ; +; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ; +; Pre-Mapping Resynthesis Optimization ; Off ; Off ; +; Analysis & Synthesis Message Level ; Medium ; Medium ; +; Disable Register Merging Across Hierarchies ; Auto ; Auto ; +; Resource Aware Inference For Block RAM ; On ; On ; +; Automatic Parallel Synthesis ; On ; On ; +; Partial Reconfiguration Bitstream ID ; Off ; Off ; ++---------------------------------------------------------------------------------+--------------------+--------------------+ + + ++------------------------------------------+ +; Parallel Compilation ; ++----------------------------+-------------+ +; Processors ; Number ; ++----------------------------+-------------+ +; Number detected on machine ; 2 ; +; Maximum allowed ; 2 ; +; ; ; +; Average used ; 1.00 ; +; Maximum used ; 2 ; +; ; ; +; Usage by Processor ; % Time Used ; +; Processor 1 ; 100.0% ; +; Processor 2 ; 0.0% ; ++----------------------------+-------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Source Files Read ; ++----------------------------------+-----------------+------------------------------+-----------------------------------------------------------------------+---------+ +; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ; ++----------------------------------+-----------------+------------------------------+-----------------------------------------------------------------------+---------+ +; multi_echo.v ; yes ; User Verilog HDL File ; H:/Year 2/VERI/part_4/ex18/multi_echo.v ; ; +; ex18_top.v ; yes ; User Verilog HDL File ; H:/Year 2/VERI/part_4/ex18/ex18_top.v ; ; +; ../mylib/spi2dac.v ; yes ; User Verilog HDL File ; H:/Year 2/VERI/part_4/mylib/spi2dac.v ; ; +; ../mylib/spi2adc.v ; yes ; User Verilog HDL File ; H:/Year 2/VERI/part_4/mylib/spi2adc.v ; ; +; ../mylib/pwm.v ; yes ; User Verilog HDL File ; H:/Year 2/VERI/part_4/mylib/pwm.v ; ; +; ../mylib/pulse_gen.v ; yes ; User Verilog HDL File ; H:/Year 2/VERI/part_4/mylib/pulse_gen.v ; ; +; ../mylib/hex_to_7seg.v ; yes ; User Verilog HDL File ; H:/Year 2/VERI/part_4/mylib/hex_to_7seg.v ; ; +; ../mylib/clktick_16.v ; yes ; User Verilog HDL File ; H:/Year 2/VERI/part_4/mylib/clktick_16.v ; ; +; FIFO.v ; yes ; User Wizard-Generated File ; H:/Year 2/VERI/part_4/ex18/FIFO.v ; ; +; scfifo.tdf ; yes ; Megafunction ; c:/intelfpga_lite/16.1/quartus/libraries/megafunctions/scfifo.tdf ; ; +; a_regfifo.inc ; yes ; Megafunction ; c:/intelfpga_lite/16.1/quartus/libraries/megafunctions/a_regfifo.inc ; ; +; a_dpfifo.inc ; yes ; Megafunction ; c:/intelfpga_lite/16.1/quartus/libraries/megafunctions/a_dpfifo.inc ; ; +; a_i2fifo.inc ; yes ; Megafunction ; c:/intelfpga_lite/16.1/quartus/libraries/megafunctions/a_i2fifo.inc ; ; +; a_fffifo.inc ; yes ; Megafunction ; c:/intelfpga_lite/16.1/quartus/libraries/megafunctions/a_fffifo.inc ; ; +; a_f2fifo.inc ; yes ; Megafunction ; c:/intelfpga_lite/16.1/quartus/libraries/megafunctions/a_f2fifo.inc ; ; +; aglobal161.inc ; yes ; Megafunction ; c:/intelfpga_lite/16.1/quartus/libraries/megafunctions/aglobal161.inc ; ; +; db/scfifo_j791.tdf ; yes ; Auto-Generated Megafunction ; H:/Year 2/VERI/part_4/ex18/db/scfifo_j791.tdf ; ; +; db/a_dpfifo_qd91.tdf ; yes ; Auto-Generated Megafunction ; H:/Year 2/VERI/part_4/ex18/db/a_dpfifo_qd91.tdf ; ; +; db/a_fefifo_4be.tdf ; yes ; Auto-Generated Megafunction ; H:/Year 2/VERI/part_4/ex18/db/a_fefifo_4be.tdf ; ; +; db/cntr_di7.tdf ; yes ; Auto-Generated Megafunction ; H:/Year 2/VERI/part_4/ex18/db/cntr_di7.tdf ; ; +; db/altsyncram_44t1.tdf ; yes ; Auto-Generated Megafunction ; H:/Year 2/VERI/part_4/ex18/db/altsyncram_44t1.tdf ; ; +; db/cntr_1ib.tdf ; yes ; Auto-Generated Megafunction ; H:/Year 2/VERI/part_4/ex18/db/cntr_1ib.tdf ; ; ++----------------------------------+-----------------+------------------------------+-----------------------------------------------------------------------+---------+ + + ++--------------------------------------------------------------+ +; Analysis & Synthesis Resource Usage Summary ; ++---------------------------------------------+----------------+ +; Resource ; Usage ; ++---------------------------------------------+----------------+ +; Estimate of Logic utilization (ALMs needed) ; 92 ; +; ; ; +; Combinational ALUT usage for logic ; 158 ; +; -- 7 input functions ; 0 ; +; -- 6 input functions ; 10 ; +; -- 5 input functions ; 23 ; +; -- 4 input functions ; 31 ; +; -- <=3 input functions ; 94 ; +; ; ; +; Dedicated logic registers ; 153 ; +; ; ; +; I/O pins ; 41 ; +; Total MLAB memory bits ; 0 ; +; Total block memory bits ; 73728 ; +; ; ; +; Total DSP Blocks ; 0 ; +; ; ; +; Maximum fan-out node ; CLOCK_50~input ; +; Maximum fan-out ; 162 ; +; Total fan-out ; 1271 ; +; Average fan-out ; 3.16 ; ++---------------------------------------------+----------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Resource Utilization by Entity ; ++---------------------------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------+--------------+ +; Compilation Hierarchy Node ; Combinational ALUTs ; Dedicated Logic Registers ; Block Memory Bits ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name ; Entity Name ; Library Name ; ++---------------------------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------+--------------+ +; |ex18_top ; 158 (0) ; 153 (0) ; 73728 ; 0 ; 41 ; 0 ; |ex18_top ; ex18_top ; work ; +; |clktick_16:GEN_10K| ; 20 (20) ; 17 (17) ; 0 ; 0 ; 0 ; 0 ; |ex18_top|clktick_16:GEN_10K ; clktick_16 ; work ; +; |hex_to_7seg:SEG0| ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex18_top|hex_to_7seg:SEG0 ; hex_to_7seg ; work ; +; |hex_to_7seg:SEG1| ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex18_top|hex_to_7seg:SEG1 ; hex_to_7seg ; work ; +; |hex_to_7seg:SEG2| ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex18_top|hex_to_7seg:SEG2 ; hex_to_7seg ; work ; +; |processor:ALLPASS| ; 62 (15) ; 53 (11) ; 73728 ; 0 ; 0 ; 0 ; |ex18_top|processor:ALLPASS ; processor ; work ; +; |FIFO:DELAY1024| ; 45 (0) ; 40 (0) ; 73728 ; 0 ; 0 ; 0 ; |ex18_top|processor:ALLPASS|FIFO:DELAY1024 ; FIFO ; work ; +; |scfifo:scfifo_component| ; 45 (0) ; 40 (0) ; 73728 ; 0 ; 0 ; 0 ; |ex18_top|processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component ; scfifo ; work ; +; |scfifo_j791:auto_generated| ; 45 (0) ; 40 (0) ; 73728 ; 0 ; 0 ; 0 ; |ex18_top|processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated ; scfifo_j791 ; work ; +; |a_dpfifo_qd91:dpfifo| ; 45 (1) ; 40 (0) ; 73728 ; 0 ; 0 ; 0 ; |ex18_top|processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo ; a_dpfifo_qd91 ; work ; +; |a_fefifo_4be:fifo_state| ; 18 (5) ; 14 (1) ; 0 ; 0 ; 0 ; 0 ; |ex18_top|processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|a_fefifo_4be:fifo_state ; a_fefifo_4be ; work ; +; |cntr_di7:count_usedw| ; 13 (13) ; 13 (13) ; 0 ; 0 ; 0 ; 0 ; |ex18_top|processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|a_fefifo_4be:fifo_state|cntr_di7:count_usedw ; cntr_di7 ; work ; +; |altsyncram_44t1:FIFOram| ; 0 (0) ; 0 (0) ; 73728 ; 0 ; 0 ; 0 ; |ex18_top|processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|altsyncram_44t1:FIFOram ; altsyncram_44t1 ; work ; +; |cntr_1ib:rd_ptr_count| ; 13 (13) ; 13 (13) ; 0 ; 0 ; 0 ; 0 ; |ex18_top|processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|cntr_1ib:rd_ptr_count ; cntr_1ib ; work ; +; |cntr_1ib:wr_ptr| ; 13 (13) ; 13 (13) ; 0 ; 0 ; 0 ; 0 ; |ex18_top|processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|cntr_1ib:wr_ptr ; cntr_1ib ; work ; +; |pulse_gen:PULSE0| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; |ex18_top|processor:ALLPASS|pulse_gen:PULSE0 ; pulse_gen ; work ; +; |pwm:PWM_DC| ; 19 (19) ; 21 (21) ; 0 ; 0 ; 0 ; 0 ; |ex18_top|pwm:PWM_DC ; pwm ; work ; +; |spi2adc:SPI_ADC| ; 23 (23) ; 40 (40) ; 0 ; 0 ; 0 ; 0 ; |ex18_top|spi2adc:SPI_ADC ; spi2adc ; work ; +; |spi2dac:SPI_DAC| ; 17 (17) ; 22 (22) ; 0 ; 0 ; 0 ; 0 ; |ex18_top|spi2dac:SPI_DAC ; spi2dac ; work ; ++---------------------------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------+--------------+ +Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis RAM Summary ; ++---------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+-------+------+ +; Name ; Type ; Mode ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size ; MIF ; ++---------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+-------+------+ +; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|altsyncram_44t1:FIFOram|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 8192 ; 10 ; 8192 ; 10 ; 81920 ; None ; ++---------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+-------+------+ + + ++------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis IP Cores Summary ; ++--------+--------------+---------+--------------+--------------+--------------------------------------------+-----------------+ +; Vendor ; IP Core Name ; Version ; Release Date ; License Type ; Entity Instance ; IP Include File ; ++--------+--------------+---------+--------------+--------------+--------------------------------------------+-----------------+ +; Altera ; FIFO ; 16.1 ; N/A ; N/A ; |ex18_top|processor:ALLPASS|FIFO:DELAY1024 ; FIFO.v ; ++--------+--------------+---------+--------------+--------------+--------------------------------------------+-----------------+ + + +Encoding Type: One-Hot ++--------------------------------------------------------------------+ +; State Machine - |ex18_top|processor:ALLPASS|pulse_gen:PULSE0|state ; ++----------------+------------+----------------+---------------------+ +; Name ; state.IDLE ; state.WAIT_LOW ; state.IN_HIGH ; ++----------------+------------+----------------+---------------------+ +; state.IDLE ; 0 ; 0 ; 0 ; +; state.IN_HIGH ; 1 ; 0 ; 1 ; +; state.WAIT_LOW ; 1 ; 1 ; 0 ; ++----------------+------------+----------------+---------------------+ + + +Encoding Type: One-Hot ++------------------------------------------------------------------------------------------+ +; State Machine - |ex18_top|spi2adc:SPI_ADC|sr_state ; ++------------------------+---------------+------------------------+------------------------+ +; Name ; sr_state.IDLE ; sr_state.WAIT_CSB_HIGH ; sr_state.WAIT_CSB_FALL ; ++------------------------+---------------+------------------------+------------------------+ +; sr_state.IDLE ; 0 ; 0 ; 0 ; +; sr_state.WAIT_CSB_FALL ; 1 ; 0 ; 1 ; +; sr_state.WAIT_CSB_HIGH ; 1 ; 1 ; 0 ; ++------------------------+---------------+------------------------+------------------------+ + + +Encoding Type: One-Hot ++------------------------------------------------------------------------------------------+ +; State Machine - |ex18_top|spi2dac:SPI_DAC|sr_state ; ++------------------------+---------------+------------------------+------------------------+ +; Name ; sr_state.IDLE ; sr_state.WAIT_CSB_HIGH ; sr_state.WAIT_CSB_FALL ; ++------------------------+---------------+------------------------+------------------------+ +; sr_state.IDLE ; 0 ; 0 ; 0 ; +; sr_state.WAIT_CSB_FALL ; 1 ; 0 ; 1 ; +; sr_state.WAIT_CSB_HIGH ; 1 ; 1 ; 0 ; ++------------------------+---------------+------------------------+------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Registers Removed During Synthesis ; ++----------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------+ +; Register name ; Reason for Removal ; ++----------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------+ +; spi2dac:SPI_DAC|clk_1MHz ; Merged with spi2adc:SPI_ADC|clk_1MHz ; +; spi2dac:SPI_DAC|tick ; Merged with spi2adc:SPI_ADC|tick ; +; spi2dac:SPI_DAC|ctr[4] ; Merged with spi2adc:SPI_ADC|ctr[4] ; +; spi2dac:SPI_DAC|ctr[3] ; Merged with spi2adc:SPI_ADC|ctr[3] ; +; spi2dac:SPI_DAC|ctr[2] ; Merged with spi2adc:SPI_ADC|ctr[2] ; +; spi2dac:SPI_DAC|ctr[1] ; Merged with spi2adc:SPI_ADC|ctr[1] ; +; spi2dac:SPI_DAC|ctr[0] ; Merged with spi2adc:SPI_ADC|ctr[0] ; +; spi2dac:SPI_DAC|shift_reg[0,1] ; Stuck at GND due to stuck port data_in ; +; processor:ALLPASS|pulse_gen:PULSE0|state.IN_HIGH ; Lost fanout ; +; processor:ALLPASS|pulse_gen:PULSE0|state.WAIT_LOW ; Lost fanout ; +; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|a_fefifo_4be:fifo_state|b_non_empty ; Stuck at VCC due to stuck port data_in ; +; Total Number of Removed Registers = 12 ; ; ++----------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------+ + + ++---------------------------------------------------------------------------------------------------+ +; Removed Registers Triggering Further Register Optimizations ; ++------------------------------+---------------------------+----------------------------------------+ +; Register name ; Reason for Removal ; Registers Removed due to This Register ; ++------------------------------+---------------------------+----------------------------------------+ +; spi2dac:SPI_DAC|shift_reg[0] ; Stuck at GND ; spi2dac:SPI_DAC|shift_reg[1] ; +; ; due to stuck port data_in ; ; ++------------------------------+---------------------------+----------------------------------------+ + + ++------------------------------------------------------+ +; General Register Statistics ; ++----------------------------------------------+-------+ +; Statistic ; Value ; ++----------------------------------------------+-------+ +; Total registers ; 153 ; +; Number of registers using Synchronous Clear ; 9 ; +; Number of registers using Synchronous Load ; 9 ; +; Number of registers using Asynchronous Clear ; 0 ; +; Number of registers using Asynchronous Load ; 0 ; +; Number of registers using Clock Enable ; 93 ; +; Number of registers using Preset ; 0 ; ++----------------------------------------------+-------+ + + ++--------------------------------------------------+ +; Inverted Register Statistics ; ++----------------------------------------+---------+ +; Inverted Register ; Fan out ; ++----------------------------------------+---------+ +; spi2adc:SPI_ADC|adc_cs ; 9 ; +; Total number of inverted registers = 1 ; ; ++----------------------------------------+---------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Multiplexer Restructuring Statistics (Restructuring Performed) ; ++--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------------------+ +; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ; ++--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------------------+ +; 3:1 ; 3 bits ; 6 LEs ; 3 LEs ; 3 LEs ; Yes ; |ex18_top|spi2dac:SPI_DAC|shift_reg[13] ; +; 3:1 ; 9 bits ; 18 LEs ; 0 LEs ; 18 LEs ; Yes ; |ex18_top|spi2dac:SPI_DAC|shift_reg[11] ; +; 6:1 ; 3 bits ; 12 LEs ; 6 LEs ; 6 LEs ; No ; |ex18_top|spi2dac:SPI_DAC|Selector2 ; ++--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|altsyncram_44t1:FIFOram ; ++---------------------------------+--------------------+------+-------------------------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++---------------------------------+--------------------+------+-------------------------------------------------------------------------------------------+ +; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ; ++---------------------------------+--------------------+------+-------------------------------------------------------------------------------------------+ + + ++-----------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: clktick_16:GEN_10K ; ++----------------+-------+----------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+-------+----------------------------------------+ +; N_BIT ; 16 ; Signed Integer ; ++----------------+-------+----------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++--------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: spi2dac:SPI_DAC ; ++----------------+-------+-------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+-------+-------------------------------------+ +; BUF ; 1 ; Unsigned Binary ; +; GA_N ; 1 ; Unsigned Binary ; +; SHDN_N ; 1 ; Unsigned Binary ; +; TC ; 11000 ; Unsigned Binary ; +; IDLE ; 00 ; Unsigned Binary ; +; WAIT_CSB_FALL ; 01 ; Unsigned Binary ; +; WAIT_CSB_HIGH ; 10 ; Unsigned Binary ; ++----------------+-------+-------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++--------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: spi2adc:SPI_ADC ; ++----------------+-------+-------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+-------+-------------------------------------+ +; SGL ; 1 ; Unsigned Binary ; +; MSBF ; 1 ; Unsigned Binary ; +; TIME_CONSTANT ; 11000 ; Unsigned Binary ; +; IDLE ; 00 ; Unsigned Binary ; +; WAIT_CSB_FALL ; 01 ; Unsigned Binary ; +; WAIT_CSB_HIGH ; 10 ; Unsigned Binary ; ++----------------+-------+-------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++----------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: processor:ALLPASS ; ++----------------+------------+----------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+------------+----------------------------------+ +; ADC_OFFSET ; 0110000001 ; Unsigned Binary ; +; DAC_OFFSET ; 1000000000 ; Unsigned Binary ; ++----------------+------------+----------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++---------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: processor:ALLPASS|pulse_gen:PULSE0 ; ++----------------+-------+--------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+-------+--------------------------------------------------------+ +; IDLE ; 00 ; Unsigned Binary ; +; IN_HIGH ; 01 ; Unsigned Binary ; +; WAIT_LOW ; 10 ; Unsigned Binary ; ++----------------+-------+--------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++-------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component ; ++-------------------------+-------------+---------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++-------------------------+-------------+---------------------------------------------------------------+ +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; +; lpm_width ; 10 ; Signed Integer ; +; LPM_NUMWORDS ; 8192 ; Signed Integer ; +; LPM_WIDTHU ; 13 ; Signed Integer ; +; LPM_SHOWAHEAD ; OFF ; Untyped ; +; UNDERFLOW_CHECKING ; ON ; Untyped ; +; OVERFLOW_CHECKING ; ON ; Untyped ; +; ALLOW_RWCYCLE_WHEN_FULL ; OFF ; Untyped ; +; ADD_RAM_OUTPUT_REGISTER ; OFF ; Untyped ; +; ALMOST_FULL_VALUE ; 0 ; Untyped ; +; ALMOST_EMPTY_VALUE ; 0 ; Untyped ; +; ENABLE_ECC ; FALSE ; Untyped ; +; USE_EAB ; ON ; Untyped ; +; MAXIMIZE_SPEED ; 5 ; Untyped ; +; DEVICE_FAMILY ; Cyclone V ; Untyped ; +; OPTIMIZE_FOR_SPEED ; 5 ; Untyped ; +; CBXI_PARAMETER ; scfifo_j791 ; Untyped ; ++-------------------------+-------------+---------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++---------------------------------------------------------------------------------------+ +; scfifo Parameter Settings by Entity Instance ; ++----------------------------+----------------------------------------------------------+ +; Name ; Value ; ++----------------------------+----------------------------------------------------------+ +; Number of entity instances ; 1 ; +; Entity Instance ; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component ; +; -- FIFO Type ; Single Clock ; +; -- lpm_width ; 10 ; +; -- LPM_NUMWORDS ; 8192 ; +; -- LPM_SHOWAHEAD ; OFF ; +; -- USE_EAB ; ON ; ++----------------------------+----------------------------------------------------------+ + + ++----------------------------------------------+ +; Port Connectivity Checks: "hex_to_7seg:SEG2" ; ++----------+-------+----------+----------------+ +; Port ; Type ; Severity ; Details ; ++----------+-------+----------+----------------+ +; in[3..2] ; Input ; Info ; Stuck at GND ; ++----------+-------+----------+----------------+ + + ++-----------------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "processor:ALLPASS|FIFO:DELAY1024" ; ++-------+--------+----------+-------------------------------------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++-------+--------+----------+-------------------------------------------------------------------------------------+ +; empty ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; +; q[0] ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; ++-------+--------+----------+-------------------------------------------------------------------------------------+ + + ++---------------------------------------------+ +; Port Connectivity Checks: "spi2adc:SPI_ADC" ; ++---------+-------+----------+----------------+ +; Port ; Type ; Severity ; Details ; ++---------+-------+----------+----------------+ +; channel ; Input ; Info ; Stuck at VCC ; ++---------+-------+----------+----------------+ + + ++------------------------------------------------+ +; Port Connectivity Checks: "clktick_16:GEN_10K" ; ++-----------+-------+----------+-----------------+ +; Port ; Type ; Severity ; Details ; ++-----------+-------+----------+-----------------+ +; enable ; Input ; Info ; Stuck at VCC ; +; N[9..7] ; Input ; Info ; Stuck at VCC ; +; N[2..0] ; Input ; Info ; Stuck at VCC ; +; N[15..13] ; Input ; Info ; Stuck at GND ; +; N[11..10] ; Input ; Info ; Stuck at GND ; +; N[6..3] ; Input ; Info ; Stuck at GND ; +; N[12] ; Input ; Info ; Stuck at VCC ; ++-----------+-------+----------+-----------------+ + + ++-----------------------------------------------------+ +; Post-Synthesis Netlist Statistics for Top Partition ; ++-----------------------+-----------------------------+ +; Type ; Count ; ++-----------------------+-----------------------------+ +; arriav_ff ; 153 ; +; ENA ; 84 ; +; ENA SLD ; 9 ; +; SCLR ; 9 ; +; plain ; 51 ; +; arriav_lcell_comb ; 166 ; +; arith ; 77 ; +; 1 data inputs ; 54 ; +; 2 data inputs ; 23 ; +; normal ; 89 ; +; 0 data inputs ; 1 ; +; 1 data inputs ; 10 ; +; 2 data inputs ; 8 ; +; 3 data inputs ; 6 ; +; 4 data inputs ; 31 ; +; 5 data inputs ; 23 ; +; 6 data inputs ; 10 ; +; boundary_port ; 41 ; +; stratixv_ram_block ; 9 ; +; ; ; +; Max LUT depth ; 3.90 ; +; Average LUT depth ; 1.84 ; ++-----------------------+-----------------------------+ + + ++-------------------------------+ +; Elapsed Time Per Partition ; ++----------------+--------------+ +; Partition Name ; Elapsed Time ; ++----------------+--------------+ +; Top ; 00:00:02 ; ++----------------+--------------+ + + ++-------------------------------+ +; Analysis & Synthesis Messages ; ++-------------------------------+ +Info: ******************************************************************* +Info: Running Quartus Prime Analysis & Synthesis + Info: Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition + Info: Processing started: Sat Dec 10 18:57:37 2016 +Info: Command: quartus_map --read_settings_files=on --write_settings_files=off ex18 -c ex18_top +Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. +Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected +Info (12021): Found 1 design units, including 1 entities, in source file multi_echo.v + Info (12023): Found entity 1: processor File: H:/Year 2/VERI/part_4/ex18/multi_echo.v Line: 9 +Info (12021): Found 1 design units, including 1 entities, in source file ex18_top.v + Info (12023): Found entity 1: ex18_top File: H:/Year 2/VERI/part_4/ex18/ex18_top.v Line: 1 +Info (12021): Found 1 design units, including 1 entities, in source file /year 2/veri/part_4/mylib/spi2dac.v + Info (12023): Found entity 1: spi2dac File: H:/Year 2/VERI/part_4/mylib/spi2dac.v Line: 9 +Info (12021): Found 1 design units, including 1 entities, in source file /year 2/veri/part_4/mylib/spi2adc.v + Info (12023): Found entity 1: spi2adc File: H:/Year 2/VERI/part_4/mylib/spi2adc.v Line: 9 +Info (12021): Found 1 design units, including 1 entities, in source file /year 2/veri/part_4/mylib/pwm.v + Info (12023): Found entity 1: pwm File: H:/Year 2/VERI/part_4/mylib/pwm.v Line: 1 +Info (12021): Found 1 design units, including 1 entities, in source file /year 2/veri/part_4/mylib/pulse_gen.v + Info (12023): Found entity 1: pulse_gen File: H:/Year 2/VERI/part_4/mylib/pulse_gen.v Line: 9 +Info (12021): Found 1 design units, including 1 entities, in source file /year 2/veri/part_4/mylib/multiply_k.v + Info (12023): Found entity 1: multiply_k File: H:/Year 2/VERI/part_4/mylib/multiply_k.v Line: 39 +Info (12021): Found 1 design units, including 1 entities, in source file /year 2/veri/part_4/mylib/multiply_4.v + Info (12023): Found entity 1: multiply_4 File: H:/Year 2/VERI/part_4/mylib/multiply_4.v Line: 39 +Info (12021): Found 1 design units, including 1 entities, in source file /year 2/veri/part_4/mylib/hex_to_7seg.v + Info (12023): Found entity 1: hex_to_7seg File: H:/Year 2/VERI/part_4/mylib/hex_to_7seg.v Line: 10 +Info (12021): Found 1 design units, including 1 entities, in source file /year 2/veri/part_4/mylib/counter_13.v + Info (12023): Found entity 1: counter_13 File: H:/Year 2/VERI/part_4/mylib/counter_13.v Line: 3 +Info (12021): Found 1 design units, including 1 entities, in source file /year 2/veri/part_4/mylib/clktick_16.v + Info (12023): Found entity 1: clktick_16 File: H:/Year 2/VERI/part_4/mylib/clktick_16.v Line: 6 +Info (12021): Found 1 design units, including 1 entities, in source file /year 2/veri/part_4/mylib/bin2bcd_16.v + Info (12023): Found entity 1: bin2bcd_16 File: H:/Year 2/VERI/part_4/mylib/bin2bcd_16.v Line: 12 +Info (12021): Found 1 design units, including 1 entities, in source file /year 2/veri/part_4/mylib/add3_ge5.v + Info (12023): Found entity 1: add3_ge5 File: H:/Year 2/VERI/part_4/mylib/add3_ge5.v Line: 9 +Info (12021): Found 1 design units, including 1 entities, in source file fifo.v + Info (12023): Found entity 1: FIFO File: H:/Year 2/VERI/part_4/ex18/FIFO.v Line: 40 +Info (12127): Elaborating entity "ex18_top" for the top level hierarchy +Info (12128): Elaborating entity "clktick_16" for hierarchy "clktick_16:GEN_10K" File: H:/Year 2/VERI/part_4/ex18/ex18_top.v Line: 24 +Info (12128): Elaborating entity "spi2dac" for hierarchy "spi2dac:SPI_DAC" File: H:/Year 2/VERI/part_4/ex18/ex18_top.v Line: 26 +Info (12128): Elaborating entity "pwm" for hierarchy "pwm:PWM_DC" File: H:/Year 2/VERI/part_4/ex18/ex18_top.v Line: 27 +Info (12128): Elaborating entity "spi2adc" for hierarchy "spi2adc:SPI_ADC" File: H:/Year 2/VERI/part_4/ex18/ex18_top.v Line: 38 +Info (12128): Elaborating entity "processor" for hierarchy "processor:ALLPASS" File: H:/Year 2/VERI/part_4/ex18/ex18_top.v Line: 40 +Info (12128): Elaborating entity "pulse_gen" for hierarchy "processor:ALLPASS|pulse_gen:PULSE0" File: H:/Year 2/VERI/part_4/ex18/multi_echo.v Line: 31 +Info (12128): Elaborating entity "FIFO" for hierarchy "processor:ALLPASS|FIFO:DELAY1024" File: H:/Year 2/VERI/part_4/ex18/multi_echo.v Line: 41 +Info (12128): Elaborating entity "scfifo" for hierarchy "processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component" File: H:/Year 2/VERI/part_4/ex18/FIFO.v Line: 77 +Info (12130): Elaborated megafunction instantiation "processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component" File: H:/Year 2/VERI/part_4/ex18/FIFO.v Line: 77 +Info (12133): Instantiated megafunction "processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component" with the following parameter: File: H:/Year 2/VERI/part_4/ex18/FIFO.v Line: 77 + Info (12134): Parameter "add_ram_output_register" = "OFF" + Info (12134): Parameter "intended_device_family" = "Cyclone V" + Info (12134): Parameter "lpm_numwords" = "8192" + Info (12134): Parameter "lpm_showahead" = "OFF" + Info (12134): Parameter "lpm_type" = "scfifo" + Info (12134): Parameter "lpm_width" = "10" + Info (12134): Parameter "lpm_widthu" = "13" + Info (12134): Parameter "overflow_checking" = "ON" + Info (12134): Parameter "underflow_checking" = "ON" + Info (12134): Parameter "use_eab" = "ON" +Info (12021): Found 1 design units, including 1 entities, in source file db/scfifo_j791.tdf + Info (12023): Found entity 1: scfifo_j791 File: H:/Year 2/VERI/part_4/ex18/db/scfifo_j791.tdf Line: 25 +Info (12128): Elaborating entity "scfifo_j791" for hierarchy "processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated" File: c:/intelfpga_lite/16.1/quartus/libraries/megafunctions/scfifo.tdf Line: 300 +Info (12021): Found 1 design units, including 1 entities, in source file db/a_dpfifo_qd91.tdf + Info (12023): Found entity 1: a_dpfifo_qd91 File: H:/Year 2/VERI/part_4/ex18/db/a_dpfifo_qd91.tdf Line: 29 +Info (12128): Elaborating entity "a_dpfifo_qd91" for hierarchy "processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo" File: H:/Year 2/VERI/part_4/ex18/db/scfifo_j791.tdf Line: 36 +Info (12021): Found 1 design units, including 1 entities, in source file db/a_fefifo_4be.tdf + Info (12023): Found entity 1: a_fefifo_4be File: H:/Year 2/VERI/part_4/ex18/db/a_fefifo_4be.tdf Line: 25 +Info (12128): Elaborating entity "a_fefifo_4be" for hierarchy "processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|a_fefifo_4be:fifo_state" File: H:/Year 2/VERI/part_4/ex18/db/a_dpfifo_qd91.tdf Line: 41 +Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_di7.tdf + Info (12023): Found entity 1: cntr_di7 File: H:/Year 2/VERI/part_4/ex18/db/cntr_di7.tdf Line: 26 +Info (12128): Elaborating entity "cntr_di7" for hierarchy "processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|a_fefifo_4be:fifo_state|cntr_di7:count_usedw" File: H:/Year 2/VERI/part_4/ex18/db/a_fefifo_4be.tdf Line: 38 +Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_44t1.tdf + Info (12023): Found entity 1: altsyncram_44t1 File: H:/Year 2/VERI/part_4/ex18/db/altsyncram_44t1.tdf Line: 28 +Info (12128): Elaborating entity "altsyncram_44t1" for hierarchy "processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|altsyncram_44t1:FIFOram" File: H:/Year 2/VERI/part_4/ex18/db/a_dpfifo_qd91.tdf Line: 42 +Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_1ib.tdf + Info (12023): Found entity 1: cntr_1ib File: H:/Year 2/VERI/part_4/ex18/db/cntr_1ib.tdf Line: 26 +Info (12128): Elaborating entity "cntr_1ib" for hierarchy "processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|cntr_1ib:rd_ptr_count" File: H:/Year 2/VERI/part_4/ex18/db/a_dpfifo_qd91.tdf Line: 43 +Info (12128): Elaborating entity "hex_to_7seg" for hierarchy "hex_to_7seg:SEG0" File: H:/Year 2/VERI/part_4/ex18/ex18_top.v Line: 42 +Warning (14284): Synthesized away the following node(s): + Warning (14285): Synthesized away the following RAM node(s): + Warning (14320): Synthesized away node "processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|altsyncram_44t1:FIFOram|q_b[0]" File: H:/Year 2/VERI/part_4/ex18/db/altsyncram_44t1.tdf Line: 40 +Warning (13024): Output pins are stuck at VCC or GND + Warning (13410): Pin "HEX2[1]" is stuck at GND File: H:/Year 2/VERI/part_4/ex18/ex18_top.v Line: 7 +Info (286030): Timing-Driven Synthesis is running +Info (17049): 2 registers lost all their fanouts during netlist optimizations. +Info (144001): Generated suppressed messages file H:/Year 2/VERI/part_4/ex18/output_files/ex18_top.map.smsg +Info (16010): Generating hard_block partition "hard_block:auto_generated_inst" + Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL +Warning (21074): Design contains 10 input pin(s) that do not drive logic + Warning (15610): No output dependent on input pin "SW[0]" File: H:/Year 2/VERI/part_4/ex18/ex18_top.v Line: 6 + Warning (15610): No output dependent on input pin "SW[1]" File: H:/Year 2/VERI/part_4/ex18/ex18_top.v Line: 6 + Warning (15610): No output dependent on input pin "SW[2]" File: H:/Year 2/VERI/part_4/ex18/ex18_top.v Line: 6 + Warning (15610): No output dependent on input pin "SW[3]" File: H:/Year 2/VERI/part_4/ex18/ex18_top.v Line: 6 + Warning (15610): No output dependent on input pin "SW[4]" File: H:/Year 2/VERI/part_4/ex18/ex18_top.v Line: 6 + Warning (15610): No output dependent on input pin "SW[5]" File: H:/Year 2/VERI/part_4/ex18/ex18_top.v Line: 6 + Warning (15610): No output dependent on input pin "SW[6]" File: H:/Year 2/VERI/part_4/ex18/ex18_top.v Line: 6 + Warning (15610): No output dependent on input pin "SW[7]" File: H:/Year 2/VERI/part_4/ex18/ex18_top.v Line: 6 + Warning (15610): No output dependent on input pin "SW[8]" File: H:/Year 2/VERI/part_4/ex18/ex18_top.v Line: 6 + Warning (15610): No output dependent on input pin "SW[9]" File: H:/Year 2/VERI/part_4/ex18/ex18_top.v Line: 6 +Info (21057): Implemented 257 device resources after synthesis - the final resource count might be different + Info (21058): Implemented 12 input pins + Info (21059): Implemented 29 output pins + Info (21061): Implemented 207 logic cells + Info (21064): Implemented 9 RAM segments +Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 17 warnings + Info: Peak virtual memory: 716 megabytes + Info: Processing ended: Sat Dec 10 18:58:47 2016 + Info: Elapsed time: 00:01:10 + Info: Total CPU time (on all processors): 00:00:39 + + ++------------------------------------------+ +; Analysis & Synthesis Suppressed Messages ; ++------------------------------------------+ +The suppressed messages can be found in H:/Year 2/VERI/part_4/ex18/output_files/ex18_top.map.smsg. + + diff --git a/part_4/ex18/output_files/ex18_top.sta.rpt b/part_4/ex18/output_files/ex18_top.sta.rpt new file mode 100644 index 0000000..f2e38d6 --- /dev/null +++ b/part_4/ex18/output_files/ex18_top.sta.rpt @@ -0,0 +1,791 @@ +TimeQuest Timing Analyzer report for ex18_top +Sat Dec 10 19:04:49 2016 +Quartus Prime Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. TimeQuest Timing Analyzer Summary + 3. Parallel Compilation + 4. SDC File List + 5. Clocks + 6. Slow 1100mV 85C Model Fmax Summary + 7. Timing Closure Recommendations + 8. Slow 1100mV 85C Model Setup Summary + 9. Slow 1100mV 85C Model Hold Summary + 10. Slow 1100mV 85C Model Recovery Summary + 11. Slow 1100mV 85C Model Removal Summary + 12. Slow 1100mV 85C Model Minimum Pulse Width Summary + 13. Slow 1100mV 85C Model Metastability Summary + 14. Slow 1100mV 0C Model Fmax Summary + 15. Slow 1100mV 0C Model Setup Summary + 16. Slow 1100mV 0C Model Hold Summary + 17. Slow 1100mV 0C Model Recovery Summary + 18. Slow 1100mV 0C Model Removal Summary + 19. Slow 1100mV 0C Model Minimum Pulse Width Summary + 20. Slow 1100mV 0C Model Metastability Summary + 21. Fast 1100mV 85C Model Setup Summary + 22. Fast 1100mV 85C Model Hold Summary + 23. Fast 1100mV 85C Model Recovery Summary + 24. Fast 1100mV 85C Model Removal Summary + 25. Fast 1100mV 85C Model Minimum Pulse Width Summary + 26. Fast 1100mV 85C Model Metastability Summary + 27. Fast 1100mV 0C Model Setup Summary + 28. Fast 1100mV 0C Model Hold Summary + 29. Fast 1100mV 0C Model Recovery Summary + 30. Fast 1100mV 0C Model Removal Summary + 31. Fast 1100mV 0C Model Minimum Pulse Width Summary + 32. Fast 1100mV 0C Model Metastability Summary + 33. Multicorner Timing Analysis Summary + 34. Board Trace Model Assignments + 35. Input Transition Times + 36. Signal Integrity Metrics (Slow 1100mv 0c Model) + 37. Signal Integrity Metrics (Slow 1100mv 85c Model) + 38. Signal Integrity Metrics (Fast 1100mv 0c Model) + 39. Signal Integrity Metrics (Fast 1100mv 85c Model) + 40. Setup Transfers + 41. Hold Transfers + 42. Report TCCS + 43. Report RSKM + 44. Unconstrained Paths Summary + 45. Clock Status Summary + 46. Unconstrained Input Ports + 47. Unconstrained Output Ports + 48. Unconstrained Input Ports + 49. Unconstrained Output Ports + 50. TimeQuest Timing Analyzer Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2016 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel MegaCore Function License Agreement, or other +applicable license agreement, including, without limitation, +that your use is for the sole purpose of programming logic +devices manufactured by Intel and sold by Intel or its +authorized distributors. Please refer to the applicable +agreement for further details. + + + ++-----------------------------------------------------------------------------+ +; TimeQuest Timing Analyzer Summary ; ++-----------------------+-----------------------------------------------------+ +; Quartus Prime Version ; Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition ; +; Timing Analyzer ; TimeQuest ; +; Revision Name ; ex18_top ; +; Device Family ; Cyclone V ; +; Device Name ; 5CSEMA5F31C6 ; +; Timing Models ; Final ; +; Delay Model ; Combined ; +; Rise/Fall Delays ; Enabled ; ++-----------------------+-----------------------------------------------------+ + + ++------------------------------------------+ +; Parallel Compilation ; ++----------------------------+-------------+ +; Processors ; Number ; ++----------------------------+-------------+ +; Number detected on machine ; 2 ; +; Maximum allowed ; 2 ; +; ; ; +; Average used ; 1.02 ; +; Maximum used ; 2 ; +; ; ; +; Usage by Processor ; % Time Used ; +; Processor 1 ; 100.0% ; +; Processor 2 ; 1.8% ; ++----------------------------+-------------+ + + ++---------------------------------------------------+ +; SDC File List ; ++---------------+--------+--------------------------+ +; SDC File Path ; Status ; Read at ; ++---------------+--------+--------------------------+ +; ex18_top.sdc ; OK ; Sat Dec 10 19:03:43 2016 ; ++---------------+--------+--------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Clocks ; ++------------+------+--------+-----------+-------+--------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+--------------+ +; Clock Name ; Type ; Period ; Frequency ; Rise ; Fall ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets ; ++------------+------+--------+-----------+-------+--------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+--------------+ +; CLOCK_50 ; Base ; 20.000 ; 50.0 MHz ; 0.000 ; 10.000 ; ; ; ; ; ; ; ; ; ; ; { CLOCK_50 } ; ++------------+------+--------+-----------+-------+--------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+--------------+ + + ++--------------------------------------------------+ +; Slow 1100mV 85C Model Fmax Summary ; ++------------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++------------+-----------------+------------+------+ +; 126.87 MHz ; 126.87 MHz ; CLOCK_50 ; ; ++------------+-----------------+------------+------+ +This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis. + + +---------------------------------- +; Timing Closure Recommendations ; +---------------------------------- +HTML report is unavailable in plain text report export. + + ++-------------------------------------+ +; Slow 1100mV 85C Model Setup Summary ; ++----------+-------+------------------+ +; Clock ; Slack ; End Point TNS ; ++----------+-------+------------------+ +; CLOCK_50 ; 7.144 ; 0.000 ; ++----------+-------+------------------+ + + ++------------------------------------+ +; Slow 1100mV 85C Model Hold Summary ; ++----------+-------+-----------------+ +; Clock ; Slack ; End Point TNS ; ++----------+-------+-----------------+ +; CLOCK_50 ; 0.372 ; 0.000 ; ++----------+-------+-----------------+ + + +------------------------------------------ +; Slow 1100mV 85C Model Recovery Summary ; +------------------------------------------ +No paths to report. + + +----------------------------------------- +; Slow 1100mV 85C Model Removal Summary ; +----------------------------------------- +No paths to report. + + ++---------------------------------------------------+ +; Slow 1100mV 85C Model Minimum Pulse Width Summary ; ++----------+-------+--------------------------------+ +; Clock ; Slack ; End Point TNS ; ++----------+-------+--------------------------------+ +; CLOCK_50 ; 8.863 ; 0.000 ; ++----------+-------+--------------------------------+ + + +----------------------------------------------- +; Slow 1100mV 85C Model Metastability Summary ; +----------------------------------------------- +No synchronizer chains to report. + + ++--------------------------------------------------+ +; Slow 1100mV 0C Model Fmax Summary ; ++------------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++------------+-----------------+------------+------+ +; 125.41 MHz ; 125.41 MHz ; CLOCK_50 ; ; ++------------+-----------------+------------+------+ +This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis. + + ++------------------------------------+ +; Slow 1100mV 0C Model Setup Summary ; ++----------+-------+-----------------+ +; Clock ; Slack ; End Point TNS ; ++----------+-------+-----------------+ +; CLOCK_50 ; 7.224 ; 0.000 ; ++----------+-------+-----------------+ + + ++-----------------------------------+ +; Slow 1100mV 0C Model Hold Summary ; ++----------+-------+----------------+ +; Clock ; Slack ; End Point TNS ; ++----------+-------+----------------+ +; CLOCK_50 ; 0.372 ; 0.000 ; ++----------+-------+----------------+ + + +----------------------------------------- +; Slow 1100mV 0C Model Recovery Summary ; +----------------------------------------- +No paths to report. + + +---------------------------------------- +; Slow 1100mV 0C Model Removal Summary ; +---------------------------------------- +No paths to report. + + ++--------------------------------------------------+ +; Slow 1100mV 0C Model Minimum Pulse Width Summary ; ++----------+-------+-------------------------------+ +; Clock ; Slack ; End Point TNS ; ++----------+-------+-------------------------------+ +; CLOCK_50 ; 8.824 ; 0.000 ; ++----------+-------+-------------------------------+ + + +---------------------------------------------- +; Slow 1100mV 0C Model Metastability Summary ; +---------------------------------------------- +No synchronizer chains to report. + + ++-------------------------------------+ +; Fast 1100mV 85C Model Setup Summary ; ++----------+-------+------------------+ +; Clock ; Slack ; End Point TNS ; ++----------+-------+------------------+ +; CLOCK_50 ; 8.606 ; 0.000 ; ++----------+-------+------------------+ + + ++------------------------------------+ +; Fast 1100mV 85C Model Hold Summary ; ++----------+-------+-----------------+ +; Clock ; Slack ; End Point TNS ; ++----------+-------+-----------------+ +; CLOCK_50 ; 0.180 ; 0.000 ; ++----------+-------+-----------------+ + + +------------------------------------------ +; Fast 1100mV 85C Model Recovery Summary ; +------------------------------------------ +No paths to report. + + +----------------------------------------- +; Fast 1100mV 85C Model Removal Summary ; +----------------------------------------- +No paths to report. + + ++---------------------------------------------------+ +; Fast 1100mV 85C Model Minimum Pulse Width Summary ; ++----------+-------+--------------------------------+ +; Clock ; Slack ; End Point TNS ; ++----------+-------+--------------------------------+ +; CLOCK_50 ; 8.795 ; 0.000 ; ++----------+-------+--------------------------------+ + + +----------------------------------------------- +; Fast 1100mV 85C Model Metastability Summary ; +----------------------------------------------- +No synchronizer chains to report. + + ++------------------------------------+ +; Fast 1100mV 0C Model Setup Summary ; ++----------+-------+-----------------+ +; Clock ; Slack ; End Point TNS ; ++----------+-------+-----------------+ +; CLOCK_50 ; 8.770 ; 0.000 ; ++----------+-------+-----------------+ + + ++-----------------------------------+ +; Fast 1100mV 0C Model Hold Summary ; ++----------+-------+----------------+ +; Clock ; Slack ; End Point TNS ; ++----------+-------+----------------+ +; CLOCK_50 ; 0.171 ; 0.000 ; ++----------+-------+----------------+ + + +----------------------------------------- +; Fast 1100mV 0C Model Recovery Summary ; +----------------------------------------- +No paths to report. + + +---------------------------------------- +; Fast 1100mV 0C Model Removal Summary ; +---------------------------------------- +No paths to report. + + ++--------------------------------------------------+ +; Fast 1100mV 0C Model Minimum Pulse Width Summary ; ++----------+-------+-------------------------------+ +; Clock ; Slack ; End Point TNS ; ++----------+-------+-------------------------------+ +; CLOCK_50 ; 8.790 ; 0.000 ; ++----------+-------+-------------------------------+ + + +---------------------------------------------- +; Fast 1100mV 0C Model Metastability Summary ; +---------------------------------------------- +No synchronizer chains to report. + + ++-----------------------------------------------------------------------------+ +; Multicorner Timing Analysis Summary ; ++------------------+-------+-------+----------+---------+---------------------+ +; Clock ; Setup ; Hold ; Recovery ; Removal ; Minimum Pulse Width ; ++------------------+-------+-------+----------+---------+---------------------+ +; Worst-case Slack ; 7.144 ; 0.171 ; N/A ; N/A ; 8.790 ; +; CLOCK_50 ; 7.144 ; 0.171 ; N/A ; N/A ; 8.790 ; +; Design-wide TNS ; 0.0 ; 0.0 ; 0.0 ; 0.0 ; 0.0 ; +; CLOCK_50 ; 0.000 ; 0.000 ; N/A ; N/A ; 0.000 ; ++------------------+-------+-------+----------+---------+---------------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Board Trace Model Assignments ; ++---------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ +; Pin ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ; ++---------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ +; HEX0[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX0[1] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX0[2] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX0[3] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX0[4] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX0[5] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX0[6] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX1[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX1[1] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX1[2] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX1[3] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX1[4] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX1[5] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX1[6] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX2[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX2[1] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX2[2] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX2[3] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX2[4] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX2[5] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX2[6] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DAC_SDI ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DAC_SCK ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DAC_CS ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DAC_LD ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; ADC_SDI ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; ADC_SCK ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; ADC_CS ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; PWM_OUT ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; ++---------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ + + ++-------------------------------------------------------------+ +; Input Transition Times ; ++----------+--------------+-----------------+-----------------+ +; Pin ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ; ++----------+--------------+-----------------+-----------------+ +; SW[0] ; 2.5 V ; 2000 ps ; 2000 ps ; +; SW[1] ; 2.5 V ; 2000 ps ; 2000 ps ; +; SW[2] ; 2.5 V ; 2000 ps ; 2000 ps ; +; SW[3] ; 2.5 V ; 2000 ps ; 2000 ps ; +; SW[4] ; 2.5 V ; 2000 ps ; 2000 ps ; +; SW[5] ; 2.5 V ; 2000 ps ; 2000 ps ; +; SW[6] ; 2.5 V ; 2000 ps ; 2000 ps ; +; SW[7] ; 2.5 V ; 2000 ps ; 2000 ps ; +; SW[8] ; 2.5 V ; 2000 ps ; 2000 ps ; +; SW[9] ; 2.5 V ; 2000 ps ; 2000 ps ; +; CLOCK_50 ; 2.5 V ; 2000 ps ; 2000 ps ; +; ADC_SDO ; 2.5 V ; 2000 ps ; 2000 ps ; ++----------+--------------+-----------------+-----------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Signal Integrity Metrics (Slow 1100mv 0c Model) ; ++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; ++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; HEX0[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.52e-07 V ; 2.42 V ; -0.0568 V ; 0.173 V ; 0.113 V ; 4.5e-10 s ; 4.35e-10 s ; No ; No ; 2.32 V ; 3.52e-07 V ; 2.42 V ; -0.0568 V ; 0.173 V ; 0.113 V ; 4.5e-10 s ; 4.35e-10 s ; No ; No ; +; HEX0[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.6e-07 V ; 2.41 V ; -0.0463 V ; 0.201 V ; 0.131 V ; 4.61e-10 s ; 4.53e-10 s ; No ; Yes ; 2.32 V ; 3.6e-07 V ; 2.41 V ; -0.0463 V ; 0.201 V ; 0.131 V ; 4.61e-10 s ; 4.53e-10 s ; No ; Yes ; +; HEX0[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.52e-07 V ; 2.42 V ; -0.0557 V ; 0.175 V ; 0.114 V ; 4.5e-10 s ; 4.35e-10 s ; No ; No ; 2.32 V ; 3.52e-07 V ; 2.42 V ; -0.0557 V ; 0.175 V ; 0.114 V ; 4.5e-10 s ; 4.35e-10 s ; No ; No ; +; HEX0[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.52e-07 V ; 2.42 V ; -0.0568 V ; 0.173 V ; 0.113 V ; 4.5e-10 s ; 4.35e-10 s ; No ; No ; 2.32 V ; 3.52e-07 V ; 2.42 V ; -0.0568 V ; 0.173 V ; 0.113 V ; 4.5e-10 s ; 4.35e-10 s ; No ; No ; +; HEX0[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.07e-07 V ; 2.36 V ; -0.0231 V ; 0.14 V ; 0.089 V ; 4.52e-10 s ; 4.35e-10 s ; No ; Yes ; 2.32 V ; 3.07e-07 V ; 2.36 V ; -0.0231 V ; 0.14 V ; 0.089 V ; 4.52e-10 s ; 4.35e-10 s ; No ; Yes ; +; HEX0[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.6e-07 V ; 2.41 V ; -0.0463 V ; 0.201 V ; 0.131 V ; 4.61e-10 s ; 4.53e-10 s ; No ; Yes ; 2.32 V ; 3.6e-07 V ; 2.41 V ; -0.0463 V ; 0.201 V ; 0.131 V ; 4.61e-10 s ; 4.53e-10 s ; No ; Yes ; +; HEX0[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.07e-07 V ; 2.36 V ; -0.0231 V ; 0.14 V ; 0.089 V ; 4.52e-10 s ; 4.35e-10 s ; No ; Yes ; 2.32 V ; 3.07e-07 V ; 2.36 V ; -0.0231 V ; 0.14 V ; 0.089 V ; 4.52e-10 s ; 4.35e-10 s ; No ; Yes ; +; HEX1[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.52e-07 V ; 2.42 V ; -0.0568 V ; 0.173 V ; 0.113 V ; 4.5e-10 s ; 4.35e-10 s ; No ; No ; 2.32 V ; 3.52e-07 V ; 2.42 V ; -0.0568 V ; 0.173 V ; 0.113 V ; 4.5e-10 s ; 4.35e-10 s ; No ; No ; +; HEX1[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.52e-07 V ; 2.42 V ; -0.0557 V ; 0.175 V ; 0.114 V ; 4.5e-10 s ; 4.35e-10 s ; No ; No ; 2.32 V ; 3.52e-07 V ; 2.42 V ; -0.0557 V ; 0.175 V ; 0.114 V ; 4.5e-10 s ; 4.35e-10 s ; No ; No ; +; HEX1[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.6e-07 V ; 2.41 V ; -0.0463 V ; 0.201 V ; 0.131 V ; 4.61e-10 s ; 4.53e-10 s ; No ; Yes ; 2.32 V ; 3.6e-07 V ; 2.41 V ; -0.0463 V ; 0.201 V ; 0.131 V ; 4.61e-10 s ; 4.53e-10 s ; No ; Yes ; +; HEX1[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.52e-07 V ; 2.42 V ; -0.0568 V ; 0.173 V ; 0.113 V ; 4.5e-10 s ; 4.35e-10 s ; No ; No ; 2.32 V ; 3.52e-07 V ; 2.42 V ; -0.0568 V ; 0.173 V ; 0.113 V ; 4.5e-10 s ; 4.35e-10 s ; No ; No ; +; HEX1[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.07e-07 V ; 2.36 V ; -0.0231 V ; 0.14 V ; 0.089 V ; 4.52e-10 s ; 4.35e-10 s ; No ; Yes ; 2.32 V ; 3.07e-07 V ; 2.36 V ; -0.0231 V ; 0.14 V ; 0.089 V ; 4.52e-10 s ; 4.35e-10 s ; No ; Yes ; +; HEX1[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.6e-07 V ; 2.41 V ; -0.0463 V ; 0.201 V ; 0.131 V ; 4.61e-10 s ; 4.53e-10 s ; No ; Yes ; 2.32 V ; 3.6e-07 V ; 2.41 V ; -0.0463 V ; 0.201 V ; 0.131 V ; 4.61e-10 s ; 4.53e-10 s ; No ; Yes ; +; HEX1[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.52e-07 V ; 2.42 V ; -0.0557 V ; 0.175 V ; 0.114 V ; 4.5e-10 s ; 4.35e-10 s ; No ; No ; 2.32 V ; 3.52e-07 V ; 2.42 V ; -0.0557 V ; 0.175 V ; 0.114 V ; 4.5e-10 s ; 4.35e-10 s ; No ; No ; +; HEX2[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.52e-07 V ; 2.42 V ; -0.0568 V ; 0.173 V ; 0.113 V ; 4.5e-10 s ; 4.35e-10 s ; No ; No ; 2.32 V ; 3.52e-07 V ; 2.42 V ; -0.0568 V ; 0.173 V ; 0.113 V ; 4.5e-10 s ; 4.35e-10 s ; No ; No ; +; HEX2[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.52e-07 V ; 2.42 V ; -0.0557 V ; 0.175 V ; 0.114 V ; 4.5e-10 s ; 4.35e-10 s ; No ; No ; 2.32 V ; 3.52e-07 V ; 2.42 V ; -0.0557 V ; 0.175 V ; 0.114 V ; 4.5e-10 s ; 4.35e-10 s ; No ; No ; +; HEX2[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.07e-07 V ; 2.36 V ; -0.0231 V ; 0.14 V ; 0.089 V ; 4.52e-10 s ; 4.35e-10 s ; No ; Yes ; 2.32 V ; 3.07e-07 V ; 2.36 V ; -0.0231 V ; 0.14 V ; 0.089 V ; 4.52e-10 s ; 4.35e-10 s ; No ; Yes ; +; HEX2[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.07e-07 V ; 2.36 V ; -0.0231 V ; 0.14 V ; 0.089 V ; 4.52e-10 s ; 4.35e-10 s ; No ; Yes ; 2.32 V ; 3.07e-07 V ; 2.36 V ; -0.0231 V ; 0.14 V ; 0.089 V ; 4.52e-10 s ; 4.35e-10 s ; No ; Yes ; +; HEX2[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.52e-07 V ; 2.42 V ; -0.0557 V ; 0.175 V ; 0.114 V ; 4.5e-10 s ; 4.35e-10 s ; No ; No ; 2.32 V ; 3.52e-07 V ; 2.42 V ; -0.0557 V ; 0.175 V ; 0.114 V ; 4.5e-10 s ; 4.35e-10 s ; No ; No ; +; HEX2[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.6e-07 V ; 2.41 V ; -0.0463 V ; 0.201 V ; 0.131 V ; 4.61e-10 s ; 4.53e-10 s ; No ; Yes ; 2.32 V ; 3.6e-07 V ; 2.41 V ; -0.0463 V ; 0.201 V ; 0.131 V ; 4.61e-10 s ; 4.53e-10 s ; No ; Yes ; +; HEX2[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.52e-07 V ; 2.42 V ; -0.0568 V ; 0.173 V ; 0.113 V ; 4.5e-10 s ; 4.35e-10 s ; No ; No ; 2.32 V ; 3.52e-07 V ; 2.42 V ; -0.0568 V ; 0.173 V ; 0.113 V ; 4.5e-10 s ; 4.35e-10 s ; No ; No ; +; DAC_SDI ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.07e-07 V ; 2.36 V ; -0.0231 V ; 0.14 V ; 0.089 V ; 4.52e-10 s ; 4.35e-10 s ; No ; Yes ; 2.32 V ; 3.07e-07 V ; 2.36 V ; -0.0231 V ; 0.14 V ; 0.089 V ; 4.52e-10 s ; 4.35e-10 s ; No ; Yes ; +; DAC_SCK ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.6e-07 V ; 2.41 V ; -0.0463 V ; 0.201 V ; 0.131 V ; 4.61e-10 s ; 4.53e-10 s ; No ; Yes ; 2.32 V ; 3.6e-07 V ; 2.41 V ; -0.0463 V ; 0.201 V ; 0.131 V ; 4.61e-10 s ; 4.53e-10 s ; No ; Yes ; +; DAC_CS ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.07e-07 V ; 2.36 V ; -0.0231 V ; 0.14 V ; 0.089 V ; 4.52e-10 s ; 4.35e-10 s ; No ; Yes ; 2.32 V ; 3.07e-07 V ; 2.36 V ; -0.0231 V ; 0.14 V ; 0.089 V ; 4.52e-10 s ; 4.35e-10 s ; No ; Yes ; +; DAC_LD ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.52e-07 V ; 2.42 V ; -0.0568 V ; 0.173 V ; 0.113 V ; 4.5e-10 s ; 4.35e-10 s ; No ; No ; 2.32 V ; 3.52e-07 V ; 2.42 V ; -0.0568 V ; 0.173 V ; 0.113 V ; 4.5e-10 s ; 4.35e-10 s ; No ; No ; +; ADC_SDI ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.52e-07 V ; 2.42 V ; -0.0568 V ; 0.173 V ; 0.113 V ; 4.5e-10 s ; 4.35e-10 s ; No ; No ; 2.32 V ; 3.52e-07 V ; 2.42 V ; -0.0568 V ; 0.173 V ; 0.113 V ; 4.5e-10 s ; 4.35e-10 s ; No ; No ; +; ADC_SCK ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.52e-07 V ; 2.42 V ; -0.0557 V ; 0.175 V ; 0.114 V ; 4.5e-10 s ; 4.35e-10 s ; No ; No ; 2.32 V ; 3.52e-07 V ; 2.42 V ; -0.0557 V ; 0.175 V ; 0.114 V ; 4.5e-10 s ; 4.35e-10 s ; No ; No ; +; ADC_CS ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.52e-07 V ; 2.42 V ; -0.0557 V ; 0.175 V ; 0.114 V ; 4.5e-10 s ; 4.35e-10 s ; No ; No ; 2.32 V ; 3.52e-07 V ; 2.42 V ; -0.0557 V ; 0.175 V ; 0.114 V ; 4.5e-10 s ; 4.35e-10 s ; No ; No ; +; PWM_OUT ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.6e-07 V ; 2.41 V ; -0.0463 V ; 0.201 V ; 0.131 V ; 4.61e-10 s ; 4.53e-10 s ; No ; Yes ; 2.32 V ; 3.6e-07 V ; 2.41 V ; -0.0463 V ; 0.201 V ; 0.131 V ; 4.61e-10 s ; 4.53e-10 s ; No ; Yes ; ++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Signal Integrity Metrics (Slow 1100mv 85c Model) ; ++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; ++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; HEX0[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.88e-05 V ; 2.39 V ; -0.0374 V ; 0.189 V ; 0.158 V ; 4.66e-10 s ; 4.67e-10 s ; No ; Yes ; 2.32 V ; 3.88e-05 V ; 2.39 V ; -0.0374 V ; 0.189 V ; 0.158 V ; 4.66e-10 s ; 4.67e-10 s ; No ; Yes ; +; HEX0[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.96e-05 V ; 2.38 V ; -0.0306 V ; 0.23 V ; 0.206 V ; 4.83e-10 s ; 5.01e-10 s ; No ; Yes ; 2.32 V ; 3.96e-05 V ; 2.38 V ; -0.0306 V ; 0.23 V ; 0.206 V ; 4.83e-10 s ; 5.01e-10 s ; No ; Yes ; +; HEX0[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.88e-05 V ; 2.39 V ; -0.037 V ; 0.188 V ; 0.158 V ; 4.67e-10 s ; 4.67e-10 s ; No ; Yes ; 2.32 V ; 3.88e-05 V ; 2.39 V ; -0.037 V ; 0.188 V ; 0.158 V ; 4.67e-10 s ; 4.67e-10 s ; No ; Yes ; +; HEX0[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.88e-05 V ; 2.39 V ; -0.0374 V ; 0.189 V ; 0.158 V ; 4.66e-10 s ; 4.67e-10 s ; No ; Yes ; 2.32 V ; 3.88e-05 V ; 2.39 V ; -0.0374 V ; 0.189 V ; 0.158 V ; 4.66e-10 s ; 4.67e-10 s ; No ; Yes ; +; HEX0[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.49e-05 V ; 2.34 V ; -0.0118 V ; 0.182 V ; 0.051 V ; 4.81e-10 s ; 4.83e-10 s ; Yes ; Yes ; 2.32 V ; 3.49e-05 V ; 2.34 V ; -0.0118 V ; 0.182 V ; 0.051 V ; 4.81e-10 s ; 4.83e-10 s ; Yes ; Yes ; +; HEX0[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.96e-05 V ; 2.38 V ; -0.0306 V ; 0.23 V ; 0.206 V ; 4.83e-10 s ; 5.01e-10 s ; No ; Yes ; 2.32 V ; 3.96e-05 V ; 2.38 V ; -0.0306 V ; 0.23 V ; 0.206 V ; 4.83e-10 s ; 5.01e-10 s ; No ; Yes ; +; HEX0[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.49e-05 V ; 2.34 V ; -0.0118 V ; 0.182 V ; 0.051 V ; 4.81e-10 s ; 4.83e-10 s ; Yes ; Yes ; 2.32 V ; 3.49e-05 V ; 2.34 V ; -0.0118 V ; 0.182 V ; 0.051 V ; 4.81e-10 s ; 4.83e-10 s ; Yes ; Yes ; +; HEX1[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.88e-05 V ; 2.39 V ; -0.0374 V ; 0.189 V ; 0.158 V ; 4.66e-10 s ; 4.67e-10 s ; No ; Yes ; 2.32 V ; 3.88e-05 V ; 2.39 V ; -0.0374 V ; 0.189 V ; 0.158 V ; 4.66e-10 s ; 4.67e-10 s ; No ; Yes ; +; HEX1[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.88e-05 V ; 2.39 V ; -0.037 V ; 0.188 V ; 0.158 V ; 4.67e-10 s ; 4.67e-10 s ; No ; Yes ; 2.32 V ; 3.88e-05 V ; 2.39 V ; -0.037 V ; 0.188 V ; 0.158 V ; 4.67e-10 s ; 4.67e-10 s ; No ; Yes ; +; HEX1[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.96e-05 V ; 2.38 V ; -0.0306 V ; 0.23 V ; 0.206 V ; 4.83e-10 s ; 5.01e-10 s ; No ; Yes ; 2.32 V ; 3.96e-05 V ; 2.38 V ; -0.0306 V ; 0.23 V ; 0.206 V ; 4.83e-10 s ; 5.01e-10 s ; No ; Yes ; +; HEX1[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.88e-05 V ; 2.39 V ; -0.0374 V ; 0.189 V ; 0.158 V ; 4.66e-10 s ; 4.67e-10 s ; No ; Yes ; 2.32 V ; 3.88e-05 V ; 2.39 V ; -0.0374 V ; 0.189 V ; 0.158 V ; 4.66e-10 s ; 4.67e-10 s ; No ; Yes ; +; HEX1[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.49e-05 V ; 2.34 V ; -0.0118 V ; 0.182 V ; 0.051 V ; 4.81e-10 s ; 4.83e-10 s ; Yes ; Yes ; 2.32 V ; 3.49e-05 V ; 2.34 V ; -0.0118 V ; 0.182 V ; 0.051 V ; 4.81e-10 s ; 4.83e-10 s ; Yes ; Yes ; +; HEX1[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.96e-05 V ; 2.38 V ; -0.0306 V ; 0.23 V ; 0.206 V ; 4.83e-10 s ; 5.01e-10 s ; No ; Yes ; 2.32 V ; 3.96e-05 V ; 2.38 V ; -0.0306 V ; 0.23 V ; 0.206 V ; 4.83e-10 s ; 5.01e-10 s ; No ; Yes ; +; HEX1[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.88e-05 V ; 2.39 V ; -0.037 V ; 0.188 V ; 0.158 V ; 4.67e-10 s ; 4.67e-10 s ; No ; Yes ; 2.32 V ; 3.88e-05 V ; 2.39 V ; -0.037 V ; 0.188 V ; 0.158 V ; 4.67e-10 s ; 4.67e-10 s ; No ; Yes ; +; HEX2[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.88e-05 V ; 2.39 V ; -0.0374 V ; 0.189 V ; 0.158 V ; 4.66e-10 s ; 4.67e-10 s ; No ; Yes ; 2.32 V ; 3.88e-05 V ; 2.39 V ; -0.0374 V ; 0.189 V ; 0.158 V ; 4.66e-10 s ; 4.67e-10 s ; No ; Yes ; +; HEX2[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.88e-05 V ; 2.39 V ; -0.037 V ; 0.188 V ; 0.158 V ; 4.67e-10 s ; 4.67e-10 s ; No ; Yes ; 2.32 V ; 3.88e-05 V ; 2.39 V ; -0.037 V ; 0.188 V ; 0.158 V ; 4.67e-10 s ; 4.67e-10 s ; No ; Yes ; +; HEX2[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.49e-05 V ; 2.34 V ; -0.0118 V ; 0.182 V ; 0.051 V ; 4.81e-10 s ; 4.83e-10 s ; Yes ; Yes ; 2.32 V ; 3.49e-05 V ; 2.34 V ; -0.0118 V ; 0.182 V ; 0.051 V ; 4.81e-10 s ; 4.83e-10 s ; Yes ; Yes ; +; HEX2[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.49e-05 V ; 2.34 V ; -0.0118 V ; 0.182 V ; 0.051 V ; 4.81e-10 s ; 4.83e-10 s ; Yes ; Yes ; 2.32 V ; 3.49e-05 V ; 2.34 V ; -0.0118 V ; 0.182 V ; 0.051 V ; 4.81e-10 s ; 4.83e-10 s ; Yes ; Yes ; +; HEX2[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.88e-05 V ; 2.39 V ; -0.037 V ; 0.188 V ; 0.158 V ; 4.67e-10 s ; 4.67e-10 s ; No ; Yes ; 2.32 V ; 3.88e-05 V ; 2.39 V ; -0.037 V ; 0.188 V ; 0.158 V ; 4.67e-10 s ; 4.67e-10 s ; No ; Yes ; +; HEX2[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.96e-05 V ; 2.38 V ; -0.0306 V ; 0.23 V ; 0.206 V ; 4.83e-10 s ; 5.01e-10 s ; No ; Yes ; 2.32 V ; 3.96e-05 V ; 2.38 V ; -0.0306 V ; 0.23 V ; 0.206 V ; 4.83e-10 s ; 5.01e-10 s ; No ; Yes ; +; HEX2[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.88e-05 V ; 2.39 V ; -0.0374 V ; 0.189 V ; 0.158 V ; 4.66e-10 s ; 4.67e-10 s ; No ; Yes ; 2.32 V ; 3.88e-05 V ; 2.39 V ; -0.0374 V ; 0.189 V ; 0.158 V ; 4.66e-10 s ; 4.67e-10 s ; No ; Yes ; +; DAC_SDI ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.49e-05 V ; 2.34 V ; -0.0118 V ; 0.182 V ; 0.051 V ; 4.81e-10 s ; 4.83e-10 s ; Yes ; Yes ; 2.32 V ; 3.49e-05 V ; 2.34 V ; -0.0118 V ; 0.182 V ; 0.051 V ; 4.81e-10 s ; 4.83e-10 s ; Yes ; Yes ; +; DAC_SCK ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.96e-05 V ; 2.38 V ; -0.0306 V ; 0.23 V ; 0.206 V ; 4.83e-10 s ; 5.01e-10 s ; No ; Yes ; 2.32 V ; 3.96e-05 V ; 2.38 V ; -0.0306 V ; 0.23 V ; 0.206 V ; 4.83e-10 s ; 5.01e-10 s ; No ; Yes ; +; DAC_CS ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.49e-05 V ; 2.34 V ; -0.0118 V ; 0.182 V ; 0.051 V ; 4.81e-10 s ; 4.83e-10 s ; Yes ; Yes ; 2.32 V ; 3.49e-05 V ; 2.34 V ; -0.0118 V ; 0.182 V ; 0.051 V ; 4.81e-10 s ; 4.83e-10 s ; Yes ; Yes ; +; DAC_LD ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.88e-05 V ; 2.39 V ; -0.0374 V ; 0.189 V ; 0.158 V ; 4.66e-10 s ; 4.67e-10 s ; No ; Yes ; 2.32 V ; 3.88e-05 V ; 2.39 V ; -0.0374 V ; 0.189 V ; 0.158 V ; 4.66e-10 s ; 4.67e-10 s ; No ; Yes ; +; ADC_SDI ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.88e-05 V ; 2.39 V ; -0.0374 V ; 0.189 V ; 0.158 V ; 4.66e-10 s ; 4.67e-10 s ; No ; Yes ; 2.32 V ; 3.88e-05 V ; 2.39 V ; -0.0374 V ; 0.189 V ; 0.158 V ; 4.66e-10 s ; 4.67e-10 s ; No ; Yes ; +; ADC_SCK ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.88e-05 V ; 2.39 V ; -0.037 V ; 0.188 V ; 0.158 V ; 4.67e-10 s ; 4.67e-10 s ; No ; Yes ; 2.32 V ; 3.88e-05 V ; 2.39 V ; -0.037 V ; 0.188 V ; 0.158 V ; 4.67e-10 s ; 4.67e-10 s ; No ; Yes ; +; ADC_CS ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.88e-05 V ; 2.39 V ; -0.037 V ; 0.188 V ; 0.158 V ; 4.67e-10 s ; 4.67e-10 s ; No ; Yes ; 2.32 V ; 3.88e-05 V ; 2.39 V ; -0.037 V ; 0.188 V ; 0.158 V ; 4.67e-10 s ; 4.67e-10 s ; No ; Yes ; +; PWM_OUT ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.96e-05 V ; 2.38 V ; -0.0306 V ; 0.23 V ; 0.206 V ; 4.83e-10 s ; 5.01e-10 s ; No ; Yes ; 2.32 V ; 3.96e-05 V ; 2.38 V ; -0.0306 V ; 0.23 V ; 0.206 V ; 4.83e-10 s ; 5.01e-10 s ; No ; Yes ; ++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Signal Integrity Metrics (Fast 1100mv 0c Model) ; ++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; ++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; HEX0[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; +; HEX0[1] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.25e-06 V ; 2.9 V ; -0.107 V ; 0.378 V ; 0.16 V ; 2.87e-10 s ; 4.28e-10 s ; No ; No ; 2.75 V ; 4.25e-06 V ; 2.9 V ; -0.107 V ; 0.378 V ; 0.16 V ; 2.87e-10 s ; 4.28e-10 s ; No ; No ; +; HEX0[2] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; +; HEX0[3] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; +; HEX0[4] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 3.54e-06 V ; 2.81 V ; -0.0578 V ; 0.303 V ; 0.28 V ; 2.93e-10 s ; 3.01e-10 s ; No ; No ; 2.75 V ; 3.54e-06 V ; 2.81 V ; -0.0578 V ; 0.303 V ; 0.28 V ; 2.93e-10 s ; 3.01e-10 s ; No ; No ; +; HEX0[5] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.25e-06 V ; 2.9 V ; -0.107 V ; 0.378 V ; 0.16 V ; 2.87e-10 s ; 4.28e-10 s ; No ; No ; 2.75 V ; 4.25e-06 V ; 2.9 V ; -0.107 V ; 0.378 V ; 0.16 V ; 2.87e-10 s ; 4.28e-10 s ; No ; No ; +; HEX0[6] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 3.54e-06 V ; 2.81 V ; -0.0578 V ; 0.303 V ; 0.28 V ; 2.93e-10 s ; 3.01e-10 s ; No ; No ; 2.75 V ; 3.54e-06 V ; 2.81 V ; -0.0578 V ; 0.303 V ; 0.28 V ; 2.93e-10 s ; 3.01e-10 s ; No ; No ; +; HEX1[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; +; HEX1[1] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; +; HEX1[2] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.25e-06 V ; 2.9 V ; -0.107 V ; 0.378 V ; 0.16 V ; 2.87e-10 s ; 4.28e-10 s ; No ; No ; 2.75 V ; 4.25e-06 V ; 2.9 V ; -0.107 V ; 0.378 V ; 0.16 V ; 2.87e-10 s ; 4.28e-10 s ; No ; No ; +; HEX1[3] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; +; HEX1[4] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 3.54e-06 V ; 2.81 V ; -0.0578 V ; 0.303 V ; 0.28 V ; 2.93e-10 s ; 3.01e-10 s ; No ; No ; 2.75 V ; 3.54e-06 V ; 2.81 V ; -0.0578 V ; 0.303 V ; 0.28 V ; 2.93e-10 s ; 3.01e-10 s ; No ; No ; +; HEX1[5] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.25e-06 V ; 2.9 V ; -0.107 V ; 0.378 V ; 0.16 V ; 2.87e-10 s ; 4.28e-10 s ; No ; No ; 2.75 V ; 4.25e-06 V ; 2.9 V ; -0.107 V ; 0.378 V ; 0.16 V ; 2.87e-10 s ; 4.28e-10 s ; No ; No ; +; HEX1[6] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; +; HEX2[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; +; HEX2[1] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; +; HEX2[2] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 3.54e-06 V ; 2.81 V ; -0.0578 V ; 0.303 V ; 0.28 V ; 2.93e-10 s ; 3.01e-10 s ; No ; No ; 2.75 V ; 3.54e-06 V ; 2.81 V ; -0.0578 V ; 0.303 V ; 0.28 V ; 2.93e-10 s ; 3.01e-10 s ; No ; No ; +; HEX2[3] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 3.54e-06 V ; 2.81 V ; -0.0578 V ; 0.303 V ; 0.28 V ; 2.93e-10 s ; 3.01e-10 s ; No ; No ; 2.75 V ; 3.54e-06 V ; 2.81 V ; -0.0578 V ; 0.303 V ; 0.28 V ; 2.93e-10 s ; 3.01e-10 s ; No ; No ; +; HEX2[4] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; +; HEX2[5] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.25e-06 V ; 2.9 V ; -0.107 V ; 0.378 V ; 0.16 V ; 2.87e-10 s ; 4.28e-10 s ; No ; No ; 2.75 V ; 4.25e-06 V ; 2.9 V ; -0.107 V ; 0.378 V ; 0.16 V ; 2.87e-10 s ; 4.28e-10 s ; No ; No ; +; HEX2[6] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; +; DAC_SDI ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 3.54e-06 V ; 2.81 V ; -0.0578 V ; 0.303 V ; 0.28 V ; 2.93e-10 s ; 3.01e-10 s ; No ; No ; 2.75 V ; 3.54e-06 V ; 2.81 V ; -0.0578 V ; 0.303 V ; 0.28 V ; 2.93e-10 s ; 3.01e-10 s ; No ; No ; +; DAC_SCK ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.25e-06 V ; 2.9 V ; -0.107 V ; 0.378 V ; 0.16 V ; 2.87e-10 s ; 4.28e-10 s ; No ; No ; 2.75 V ; 4.25e-06 V ; 2.9 V ; -0.107 V ; 0.378 V ; 0.16 V ; 2.87e-10 s ; 4.28e-10 s ; No ; No ; +; DAC_CS ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 3.54e-06 V ; 2.81 V ; -0.0578 V ; 0.303 V ; 0.28 V ; 2.93e-10 s ; 3.01e-10 s ; No ; No ; 2.75 V ; 3.54e-06 V ; 2.81 V ; -0.0578 V ; 0.303 V ; 0.28 V ; 2.93e-10 s ; 3.01e-10 s ; No ; No ; +; DAC_LD ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; +; ADC_SDI ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; +; ADC_SCK ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; +; ADC_CS ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; +; PWM_OUT ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.25e-06 V ; 2.9 V ; -0.107 V ; 0.378 V ; 0.16 V ; 2.87e-10 s ; 4.28e-10 s ; No ; No ; 2.75 V ; 4.25e-06 V ; 2.9 V ; -0.107 V ; 0.378 V ; 0.16 V ; 2.87e-10 s ; 4.28e-10 s ; No ; No ; ++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Signal Integrity Metrics (Fast 1100mv 85c Model) ; ++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; ++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; HEX0[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ; +; HEX0[1] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000247 V ; 2.85 V ; -0.0711 V ; 0.204 V ; 0.181 V ; 4.55e-10 s ; 4.49e-10 s ; No ; No ; 2.75 V ; 0.000247 V ; 2.85 V ; -0.0711 V ; 0.204 V ; 0.181 V ; 4.55e-10 s ; 4.49e-10 s ; No ; No ; +; HEX0[2] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ; +; HEX0[3] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ; +; HEX0[4] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000213 V ; 2.79 V ; -0.0324 V ; 0.139 V ; 0.119 V ; 4.42e-10 s ; 4.33e-10 s ; No ; Yes ; 2.75 V ; 0.000213 V ; 2.79 V ; -0.0324 V ; 0.139 V ; 0.119 V ; 4.42e-10 s ; 4.33e-10 s ; No ; Yes ; +; HEX0[5] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000247 V ; 2.85 V ; -0.0711 V ; 0.204 V ; 0.181 V ; 4.55e-10 s ; 4.49e-10 s ; No ; No ; 2.75 V ; 0.000247 V ; 2.85 V ; -0.0711 V ; 0.204 V ; 0.181 V ; 4.55e-10 s ; 4.49e-10 s ; No ; No ; +; HEX0[6] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000213 V ; 2.79 V ; -0.0324 V ; 0.139 V ; 0.119 V ; 4.42e-10 s ; 4.33e-10 s ; No ; Yes ; 2.75 V ; 0.000213 V ; 2.79 V ; -0.0324 V ; 0.139 V ; 0.119 V ; 4.42e-10 s ; 4.33e-10 s ; No ; Yes ; +; HEX1[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ; +; HEX1[1] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ; +; HEX1[2] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000247 V ; 2.85 V ; -0.0711 V ; 0.204 V ; 0.181 V ; 4.55e-10 s ; 4.49e-10 s ; No ; No ; 2.75 V ; 0.000247 V ; 2.85 V ; -0.0711 V ; 0.204 V ; 0.181 V ; 4.55e-10 s ; 4.49e-10 s ; No ; No ; +; HEX1[3] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ; +; HEX1[4] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000213 V ; 2.79 V ; -0.0324 V ; 0.139 V ; 0.119 V ; 4.42e-10 s ; 4.33e-10 s ; No ; Yes ; 2.75 V ; 0.000213 V ; 2.79 V ; -0.0324 V ; 0.139 V ; 0.119 V ; 4.42e-10 s ; 4.33e-10 s ; No ; Yes ; +; HEX1[5] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000247 V ; 2.85 V ; -0.0711 V ; 0.204 V ; 0.181 V ; 4.55e-10 s ; 4.49e-10 s ; No ; No ; 2.75 V ; 0.000247 V ; 2.85 V ; -0.0711 V ; 0.204 V ; 0.181 V ; 4.55e-10 s ; 4.49e-10 s ; No ; No ; +; HEX1[6] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ; +; HEX2[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ; +; HEX2[1] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ; +; HEX2[2] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000213 V ; 2.79 V ; -0.0324 V ; 0.139 V ; 0.119 V ; 4.42e-10 s ; 4.33e-10 s ; No ; Yes ; 2.75 V ; 0.000213 V ; 2.79 V ; -0.0324 V ; 0.139 V ; 0.119 V ; 4.42e-10 s ; 4.33e-10 s ; No ; Yes ; +; HEX2[3] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000213 V ; 2.79 V ; -0.0324 V ; 0.139 V ; 0.119 V ; 4.42e-10 s ; 4.33e-10 s ; No ; Yes ; 2.75 V ; 0.000213 V ; 2.79 V ; -0.0324 V ; 0.139 V ; 0.119 V ; 4.42e-10 s ; 4.33e-10 s ; No ; Yes ; +; HEX2[4] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ; +; HEX2[5] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000247 V ; 2.85 V ; -0.0711 V ; 0.204 V ; 0.181 V ; 4.55e-10 s ; 4.49e-10 s ; No ; No ; 2.75 V ; 0.000247 V ; 2.85 V ; -0.0711 V ; 0.204 V ; 0.181 V ; 4.55e-10 s ; 4.49e-10 s ; No ; No ; +; HEX2[6] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ; +; DAC_SDI ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000213 V ; 2.79 V ; -0.0324 V ; 0.139 V ; 0.119 V ; 4.42e-10 s ; 4.33e-10 s ; No ; Yes ; 2.75 V ; 0.000213 V ; 2.79 V ; -0.0324 V ; 0.139 V ; 0.119 V ; 4.42e-10 s ; 4.33e-10 s ; No ; Yes ; +; DAC_SCK ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000247 V ; 2.85 V ; -0.0711 V ; 0.204 V ; 0.181 V ; 4.55e-10 s ; 4.49e-10 s ; No ; No ; 2.75 V ; 0.000247 V ; 2.85 V ; -0.0711 V ; 0.204 V ; 0.181 V ; 4.55e-10 s ; 4.49e-10 s ; No ; No ; +; DAC_CS ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000213 V ; 2.79 V ; -0.0324 V ; 0.139 V ; 0.119 V ; 4.42e-10 s ; 4.33e-10 s ; No ; Yes ; 2.75 V ; 0.000213 V ; 2.79 V ; -0.0324 V ; 0.139 V ; 0.119 V ; 4.42e-10 s ; 4.33e-10 s ; No ; Yes ; +; DAC_LD ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ; +; ADC_SDI ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ; +; ADC_SCK ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ; +; ADC_CS ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ; +; PWM_OUT ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000247 V ; 2.85 V ; -0.0711 V ; 0.204 V ; 0.181 V ; 4.55e-10 s ; 4.49e-10 s ; No ; No ; 2.75 V ; 0.000247 V ; 2.85 V ; -0.0711 V ; 0.204 V ; 0.181 V ; 4.55e-10 s ; 4.49e-10 s ; No ; No ; ++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ + + ++-------------------------------------------------------------------+ +; Setup Transfers ; ++------------+----------+----------+----------+----------+----------+ +; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; ++------------+----------+----------+----------+----------+----------+ +; CLOCK_50 ; CLOCK_50 ; 4354 ; 10 ; 30 ; 9 ; ++------------+----------+----------+----------+----------+----------+ +Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. + + ++-------------------------------------------------------------------+ +; Hold Transfers ; ++------------+----------+----------+----------+----------+----------+ +; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; ++------------+----------+----------+----------+----------+----------+ +; CLOCK_50 ; CLOCK_50 ; 4354 ; 10 ; 30 ; 9 ; ++------------+----------+----------+----------+----------+----------+ +Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. + + +--------------- +; Report TCCS ; +--------------- +No dedicated SERDES Transmitter circuitry present in device or used in design + + +--------------- +; Report RSKM ; +--------------- +No non-DPA dedicated SERDES Receiver circuitry present in device or used in design + + ++------------------------------------------------+ +; Unconstrained Paths Summary ; ++---------------------------------+-------+------+ +; Property ; Setup ; Hold ; ++---------------------------------+-------+------+ +; Illegal Clocks ; 0 ; 0 ; +; Unconstrained Clocks ; 0 ; 0 ; +; Unconstrained Input Ports ; 1 ; 1 ; +; Unconstrained Input Port Paths ; 1 ; 1 ; +; Unconstrained Output Ports ; 28 ; 28 ; +; Unconstrained Output Port Paths ; 88 ; 88 ; ++---------------------------------+-------+------+ + + ++------------------------------------------+ +; Clock Status Summary ; ++----------+----------+------+-------------+ +; Target ; Clock ; Type ; Status ; ++----------+----------+------+-------------+ +; CLOCK_50 ; CLOCK_50 ; Base ; Constrained ; ++----------+----------+------+-------------+ + + ++---------------------------------------------------------------------------------------------------+ +; Unconstrained Input Ports ; ++------------+--------------------------------------------------------------------------------------+ +; Input Port ; Comment ; ++------------+--------------------------------------------------------------------------------------+ +; ADC_SDO ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ++------------+--------------------------------------------------------------------------------------+ + + ++-----------------------------------------------------------------------------------------------------+ +; Unconstrained Output Ports ; ++-------------+---------------------------------------------------------------------------------------+ +; Output Port ; Comment ; ++-------------+---------------------------------------------------------------------------------------+ +; ADC_CS ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; ADC_SCK ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; ADC_SDI ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; DAC_CS ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; DAC_LD ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; DAC_SCK ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; DAC_SDI ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX0[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX0[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX0[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX0[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX0[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX0[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX0[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX1[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX1[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX1[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX1[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX1[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX1[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX1[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX2[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX2[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX2[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX2[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX2[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX2[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; PWM_OUT ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ++-------------+---------------------------------------------------------------------------------------+ + + ++---------------------------------------------------------------------------------------------------+ +; Unconstrained Input Ports ; ++------------+--------------------------------------------------------------------------------------+ +; Input Port ; Comment ; ++------------+--------------------------------------------------------------------------------------+ +; ADC_SDO ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ++------------+--------------------------------------------------------------------------------------+ + + ++-----------------------------------------------------------------------------------------------------+ +; Unconstrained Output Ports ; ++-------------+---------------------------------------------------------------------------------------+ +; Output Port ; Comment ; ++-------------+---------------------------------------------------------------------------------------+ +; ADC_CS ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; ADC_SCK ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; ADC_SDI ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; DAC_CS ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; DAC_LD ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; DAC_SCK ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; DAC_SDI ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX0[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX0[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX0[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX0[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX0[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX0[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX0[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX1[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX1[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX1[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX1[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX1[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX1[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX1[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX2[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX2[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX2[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX2[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX2[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX2[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; PWM_OUT ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ++-------------+---------------------------------------------------------------------------------------+ + + ++------------------------------------+ +; TimeQuest Timing Analyzer Messages ; ++------------------------------------+ +Info: ******************************************************************* +Info: Running Quartus Prime TimeQuest Timing Analyzer + Info: Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition + Info: Processing started: Sat Dec 10 19:03:33 2016 +Info: Command: quartus_sta ex18 -c ex18_top +Info: qsta_default_script.tcl version: #1 +Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. +Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected +Info (21077): Low junction temperature is 0 degrees C +Info (21077): High junction temperature is 85 degrees C +Info (332104): Reading SDC File: 'ex18_top.sdc' +Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty" +Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. +Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON +Info: Analyzing Slow 1100mV 85C Model +Info (332146): Worst-case setup slack is 7.144 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): 7.144 0.000 CLOCK_50 +Info (332146): Worst-case hold slack is 0.372 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): 0.372 0.000 CLOCK_50 +Info (332140): No Recovery paths to report +Info (332140): No Removal paths to report +Info (332146): Worst-case minimum pulse width slack is 8.863 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): 8.863 0.000 CLOCK_50 +Info: Analyzing Slow 1100mV 0C Model +Info (334003): Started post-fitting delay annotation +Info (334004): Delay annotation completed successfully +Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. +Info (332146): Worst-case setup slack is 7.224 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): 7.224 0.000 CLOCK_50 +Info (332146): Worst-case hold slack is 0.372 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): 0.372 0.000 CLOCK_50 +Info (332140): No Recovery paths to report +Info (332140): No Removal paths to report +Info (332146): Worst-case minimum pulse width slack is 8.824 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): 8.824 0.000 CLOCK_50 +Info: Analyzing Fast 1100mV 85C Model +Info (334003): Started post-fitting delay annotation +Info (334004): Delay annotation completed successfully +Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. +Info (332146): Worst-case setup slack is 8.606 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): 8.606 0.000 CLOCK_50 +Info (332146): Worst-case hold slack is 0.180 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): 0.180 0.000 CLOCK_50 +Info (332140): No Recovery paths to report +Info (332140): No Removal paths to report +Info (332146): Worst-case minimum pulse width slack is 8.795 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): 8.795 0.000 CLOCK_50 +Info: Analyzing Fast 1100mV 0C Model +Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. +Info (332146): Worst-case setup slack is 8.770 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): 8.770 0.000 CLOCK_50 +Info (332146): Worst-case hold slack is 0.171 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): 0.171 0.000 CLOCK_50 +Info (332140): No Recovery paths to report +Info (332140): No Removal paths to report +Info (332146): Worst-case minimum pulse width slack is 8.790 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): 8.790 0.000 CLOCK_50 +Info (332102): Design is not fully constrained for setup requirements +Info (332102): Design is not fully constrained for hold requirements +Info: Quartus Prime TimeQuest Timing Analyzer was successful. 0 errors, 1 warning + Info: Peak virtual memory: 1027 megabytes + Info: Processing ended: Sat Dec 10 19:04:49 2016 + Info: Elapsed time: 00:01:16 + Info: Total CPU time (on all processors): 00:00:13 + + diff --git a/part_4/ex19/RAM.v b/part_4/ex19/RAM.v new file mode 100644 index 0000000..e10e60f --- /dev/null +++ b/part_4/ex19/RAM.v @@ -0,0 +1,221 @@ +// megafunction wizard: %RAM: 2-PORT% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altsyncram + +// ============================================================ +// File Name: RAM.v +// Megafunction Name(s): +// altsyncram +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 16.1.0 Build 196 10/24/2016 SJ Lite Edition +// ************************************************************ + + +//Copyright (C) 2016 Intel Corporation. All rights reserved. +//Your use of Intel Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Intel Program License +//Subscription Agreement, the Intel Quartus Prime License Agreement, +//the Intel MegaCore Function License Agreement, or other +//applicable license agreement, including, without limitation, +//that your use is for the sole purpose of programming logic +//devices manufactured by Intel and sold by Intel or its +//authorized distributors. Please refer to the applicable +//agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module RAM ( + clock, + data, + rdaddress, + rden, + wraddress, + wren, + q); + + input clock; + input [8:0] data; + input [12:0] rdaddress; + input rden; + input [12:0] wraddress; + input wren; + output [8:0] q; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_off +`endif + tri1 clock; + tri1 rden; + tri0 wren; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_on +`endif + + wire [8:0] sub_wire0; + wire [8:0] q = sub_wire0[8:0]; + + altsyncram altsyncram_component ( + .address_a (wraddress), + .address_b (rdaddress), + .clock0 (clock), + .data_a (data), + .rden_b (rden), + .wren_a (wren), + .q_b (sub_wire0), + .aclr0 (1'b0), + .aclr1 (1'b0), + .addressstall_a (1'b0), + .addressstall_b (1'b0), + .byteena_a (1'b1), + .byteena_b (1'b1), + .clock1 (1'b1), + .clocken0 (1'b1), + .clocken1 (1'b1), + .clocken2 (1'b1), + .clocken3 (1'b1), + .data_b ({9{1'b1}}), + .eccstatus (), + .q_a (), + .rden_a (1'b1), + .wren_b (1'b0)); + defparam + altsyncram_component.address_aclr_b = "NONE", + altsyncram_component.address_reg_b = "CLOCK0", + altsyncram_component.clock_enable_input_a = "BYPASS", + altsyncram_component.clock_enable_input_b = "BYPASS", + altsyncram_component.clock_enable_output_b = "BYPASS", + altsyncram_component.intended_device_family = "Cyclone V", + altsyncram_component.lpm_type = "altsyncram", + altsyncram_component.numwords_a = 8192, + altsyncram_component.numwords_b = 8192, + altsyncram_component.operation_mode = "DUAL_PORT", + altsyncram_component.outdata_aclr_b = "NONE", + altsyncram_component.outdata_reg_b = "CLOCK0", + altsyncram_component.power_up_uninitialized = "FALSE", + altsyncram_component.rdcontrol_reg_b = "CLOCK0", + altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE", + altsyncram_component.widthad_a = 13, + altsyncram_component.widthad_b = 13, + altsyncram_component.width_a = 9, + altsyncram_component.width_b = 9, + altsyncram_component.width_byteena_a = 1; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" +// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0" +// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0" +// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0" +// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0" +// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0" +// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "9" +// Retrieval info: PRIVATE: BlankMemory NUMERIC "1" +// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" +// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0" +// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" +// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0" +// Retrieval info: PRIVATE: CLRdata NUMERIC "0" +// Retrieval info: PRIVATE: CLRq NUMERIC "0" +// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0" +// Retrieval info: PRIVATE: CLRrren NUMERIC "0" +// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0" +// Retrieval info: PRIVATE: CLRwren NUMERIC "0" +// Retrieval info: PRIVATE: Clock NUMERIC "0" +// Retrieval info: PRIVATE: Clock_A NUMERIC "0" +// Retrieval info: PRIVATE: Clock_B NUMERIC "0" +// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" +// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0" +// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0" +// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B" +// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V" +// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" +// Retrieval info: PRIVATE: JTAG_ID STRING "NONE" +// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" +// Retrieval info: PRIVATE: MEMSIZE NUMERIC "73728" +// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0" +// Retrieval info: PRIVATE: MIFfilename STRING "" +// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2" +// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0" +// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1" +// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" +// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2" +// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3" +// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3" +// Retrieval info: PRIVATE: REGdata NUMERIC "1" +// Retrieval info: PRIVATE: REGq NUMERIC "1" +// Retrieval info: PRIVATE: REGrdaddress NUMERIC "1" +// Retrieval info: PRIVATE: REGrren NUMERIC "1" +// Retrieval info: PRIVATE: REGwraddress NUMERIC "1" +// Retrieval info: PRIVATE: REGwren NUMERIC "1" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0" +// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1" +// Retrieval info: PRIVATE: VarWidth NUMERIC "0" +// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "9" +// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "9" +// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "9" +// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "9" +// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0" +// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0" +// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0" +// Retrieval info: PRIVATE: enable NUMERIC "0" +// Retrieval info: PRIVATE: rden NUMERIC "1" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE" +// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0" +// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" +// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS" +// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" +// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "8192" +// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "8192" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT" +// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE" +// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK0" +// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" +// Retrieval info: CONSTANT: RDCONTROL_REG_B STRING "CLOCK0" +// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE" +// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "13" +// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "13" +// Retrieval info: CONSTANT: WIDTH_A NUMERIC "9" +// Retrieval info: CONSTANT: WIDTH_B NUMERIC "9" +// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" +// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" +// Retrieval info: USED_PORT: data 0 0 9 0 INPUT NODEFVAL "data[8..0]" +// Retrieval info: USED_PORT: q 0 0 9 0 OUTPUT NODEFVAL "q[8..0]" +// Retrieval info: USED_PORT: rdaddress 0 0 13 0 INPUT NODEFVAL "rdaddress[12..0]" +// Retrieval info: USED_PORT: rden 0 0 0 0 INPUT VCC "rden" +// Retrieval info: USED_PORT: wraddress 0 0 13 0 INPUT NODEFVAL "wraddress[12..0]" +// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren" +// Retrieval info: CONNECT: @address_a 0 0 13 0 wraddress 0 0 13 0 +// Retrieval info: CONNECT: @address_b 0 0 13 0 rdaddress 0 0 13 0 +// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 +// Retrieval info: CONNECT: @data_a 0 0 9 0 data 0 0 9 0 +// Retrieval info: CONNECT: @rden_b 0 0 0 0 rden 0 0 0 0 +// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0 +// Retrieval info: CONNECT: q 0 0 9 0 @q_b 0 0 9 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL RAM.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL RAM.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL RAM.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL RAM.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL RAM_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL RAM_bb.v TRUE +// Retrieval info: LIB_FILE: altera_mf diff --git a/part_4/ex19/RAM_bb.v b/part_4/ex19/RAM_bb.v new file mode 100644 index 0000000..9ee0655 --- /dev/null +++ b/part_4/ex19/RAM_bb.v @@ -0,0 +1,166 @@ +// megafunction wizard: %RAM: 2-PORT%VBB% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altsyncram + +// ============================================================ +// File Name: RAM.v +// Megafunction Name(s): +// altsyncram +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 16.1.0 Build 196 10/24/2016 SJ Lite Edition +// ************************************************************ + +//Copyright (C) 2016 Intel Corporation. All rights reserved. +//Your use of Intel Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Intel Program License +//Subscription Agreement, the Intel Quartus Prime License Agreement, +//the Intel MegaCore Function License Agreement, or other +//applicable license agreement, including, without limitation, +//that your use is for the sole purpose of programming logic +//devices manufactured by Intel and sold by Intel or its +//authorized distributors. Please refer to the applicable +//agreement for further details. + +module RAM ( + clock, + data, + rdaddress, + rden, + wraddress, + wren, + q); + + input clock; + input [8:0] data; + input [12:0] rdaddress; + input rden; + input [12:0] wraddress; + input wren; + output [8:0] q; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_off +`endif + tri1 clock; + tri1 rden; + tri0 wren; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_on +`endif + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" +// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0" +// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0" +// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0" +// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0" +// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0" +// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "9" +// Retrieval info: PRIVATE: BlankMemory NUMERIC "1" +// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" +// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0" +// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" +// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0" +// Retrieval info: PRIVATE: CLRdata NUMERIC "0" +// Retrieval info: PRIVATE: CLRq NUMERIC "0" +// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0" +// Retrieval info: PRIVATE: CLRrren NUMERIC "0" +// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0" +// Retrieval info: PRIVATE: CLRwren NUMERIC "0" +// Retrieval info: PRIVATE: Clock NUMERIC "0" +// Retrieval info: PRIVATE: Clock_A NUMERIC "0" +// Retrieval info: PRIVATE: Clock_B NUMERIC "0" +// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" +// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0" +// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0" +// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B" +// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V" +// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" +// Retrieval info: PRIVATE: JTAG_ID STRING "NONE" +// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" +// Retrieval info: PRIVATE: MEMSIZE NUMERIC "73728" +// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0" +// Retrieval info: PRIVATE: MIFfilename STRING "" +// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2" +// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0" +// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1" +// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" +// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2" +// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3" +// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3" +// Retrieval info: PRIVATE: REGdata NUMERIC "1" +// Retrieval info: PRIVATE: REGq NUMERIC "1" +// Retrieval info: PRIVATE: REGrdaddress NUMERIC "1" +// Retrieval info: PRIVATE: REGrren NUMERIC "1" +// Retrieval info: PRIVATE: REGwraddress NUMERIC "1" +// Retrieval info: PRIVATE: REGwren NUMERIC "1" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0" +// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1" +// Retrieval info: PRIVATE: VarWidth NUMERIC "0" +// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "9" +// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "9" +// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "9" +// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "9" +// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0" +// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0" +// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0" +// Retrieval info: PRIVATE: enable NUMERIC "0" +// Retrieval info: PRIVATE: rden NUMERIC "1" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE" +// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0" +// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" +// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS" +// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" +// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "8192" +// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "8192" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT" +// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE" +// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK0" +// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" +// Retrieval info: CONSTANT: RDCONTROL_REG_B STRING "CLOCK0" +// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE" +// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "13" +// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "13" +// Retrieval info: CONSTANT: WIDTH_A NUMERIC "9" +// Retrieval info: CONSTANT: WIDTH_B NUMERIC "9" +// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" +// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" +// Retrieval info: USED_PORT: data 0 0 9 0 INPUT NODEFVAL "data[8..0]" +// Retrieval info: USED_PORT: q 0 0 9 0 OUTPUT NODEFVAL "q[8..0]" +// Retrieval info: USED_PORT: rdaddress 0 0 13 0 INPUT NODEFVAL "rdaddress[12..0]" +// Retrieval info: USED_PORT: rden 0 0 0 0 INPUT VCC "rden" +// Retrieval info: USED_PORT: wraddress 0 0 13 0 INPUT NODEFVAL "wraddress[12..0]" +// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren" +// Retrieval info: CONNECT: @address_a 0 0 13 0 wraddress 0 0 13 0 +// Retrieval info: CONNECT: @address_b 0 0 13 0 rdaddress 0 0 13 0 +// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 +// Retrieval info: CONNECT: @data_a 0 0 9 0 data 0 0 9 0 +// Retrieval info: CONNECT: @rden_b 0 0 0 0 rden 0 0 0 0 +// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0 +// Retrieval info: CONNECT: q 0 0 9 0 @q_b 0 0 9 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL RAM.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL RAM.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL RAM.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL RAM.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL RAM_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL RAM_bb.v TRUE +// Retrieval info: LIB_FILE: altera_mf diff --git a/part_4/ex19/ex19_top.v b/part_4/ex19/ex19_top.v new file mode 100644 index 0000000..cfe1b62 --- /dev/null +++ b/part_4/ex19/ex19_top.v @@ -0,0 +1,45 @@ +module ex19_top (CLOCK_50, SW, HEX0, HEX1, HEX2, + DAC_SDI, DAC_SCK, DAC_CS, DAC_LD, + ADC_SDI, ADC_SCK, ADC_CS, ADC_SDO, PWM_OUT); + + input CLOCK_50; // DE0 50MHz system clock + input [9:0] SW; // 10 slide switches to specify address to ROM + output [6:0] HEX0, HEX1, HEX2; + output DAC_SDI; //Serial data out to SDI of the DAC + output DAC_SCK; //Serial clock signal to both DAC and ADC + output DAC_CS; //Chip select to the DAC, low active + output DAC_LD; //Load new data to DAC, low active + output ADC_SDI; //Serial data out to SDI of the ADC + output ADC_SCK; // ADC Clock signal + output ADC_CS; //Chip select to the ADC, low active + input ADC_SDO; //Converted serial data from ADC + output PWM_OUT; // PWM output to R channel + + wire tick_10k; // internal clock at 10kHz + wire [9:0] data_in; // converted data from ADC + wire [9:0] data_out; // processed data to DAC + wire data_valid; + wire DAC_SCK, ADC_SCK; + + clktick_16 GEN_10K (CLOCK_50, 1'b1, 16'd4999, tick_10k); // generate 10KHz sampling clock ticks + spi2dac SPI_DAC (CLOCK_50, data_out, tick_10k, // send processed sample to DAC + DAC_SDI, DAC_CS, DAC_SCK, DAC_LD); // order of signals matter + pwm PWM_DC(CLOCK_50, data_out, tick_10k, PWM_OUT); // output via PWM - R-channel + + spi2adc SPI_ADC ( // perform a A-to-D conversion + .sysclk (CLOCK_50), // order of parameters do not matter + .channel (1'b1), // use only CH1 + .start (tick_10k), + .data_from_adc (data_in), + .data_valid (data_valid), + .sdata_to_adc (ADC_SDI), + .adc_cs (ADC_CS), + .adc_sck (ADC_SCK), + .sdata_from_adc (ADC_SDO)); + + processor ALLPASS (CLOCK_50, data_in, data_out, data_valid, SW, HEX0, HEX1, HEX2); // do some processing on the data + + +endmodule + + diff --git a/part_4/ex19/output_files/ex19_top.asm.rpt b/part_4/ex19/output_files/ex19_top.asm.rpt new file mode 100644 index 0000000..0e4fe98 --- /dev/null +++ b/part_4/ex19/output_files/ex19_top.asm.rpt @@ -0,0 +1,92 @@ +Assembler report for ex19_top +Sat Dec 10 19:26:58 2016 +Quartus Prime Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Assembler Summary + 3. Assembler Settings + 4. Assembler Generated Files + 5. Assembler Device Options: H:/Year 2/VERI/part_4/ex19/output_files/ex19_top.sof + 6. Assembler Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2016 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel MegaCore Function License Agreement, or other +applicable license agreement, including, without limitation, +that your use is for the sole purpose of programming logic +devices manufactured by Intel and sold by Intel or its +authorized distributors. Please refer to the applicable +agreement for further details. + + + ++---------------------------------------------------------------+ +; Assembler Summary ; ++-----------------------+---------------------------------------+ +; Assembler Status ; Successful - Sat Dec 10 19:26:58 2016 ; +; Revision Name ; ex19_top ; +; Top-level Entity Name ; ex19_top ; +; Family ; Cyclone V ; +; Device ; 5CSEMA5F31C6 ; ++-----------------------+---------------------------------------+ + + ++----------------------------------+ +; Assembler Settings ; ++--------+---------+---------------+ +; Option ; Setting ; Default Value ; ++--------+---------+---------------+ + + ++------------------------------------------------------+ +; Assembler Generated Files ; ++------------------------------------------------------+ +; File Name ; ++------------------------------------------------------+ +; H:/Year 2/VERI/part_4/ex19/output_files/ex19_top.sof ; ++------------------------------------------------------+ + + ++--------------------------------------------------------------------------------+ +; Assembler Device Options: H:/Year 2/VERI/part_4/ex19/output_files/ex19_top.sof ; ++----------------+---------------------------------------------------------------+ +; Option ; Setting ; ++----------------+---------------------------------------------------------------+ +; Device ; 5CSEMA5F31C6 ; +; JTAG usercode ; 0x00E0B678 ; +; Checksum ; 0x00E0B678 ; ++----------------+---------------------------------------------------------------+ + + ++--------------------+ +; Assembler Messages ; ++--------------------+ +Info: ******************************************************************* +Info: Running Quartus Prime Assembler + Info: Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition + Info: Processing started: Sat Dec 10 19:26:02 2016 +Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off ex19 -c ex19_top +Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. +Info (115030): Assembler is generating device programming files +Info: Quartus Prime Assembler was successful. 0 errors, 1 warning + Info: Peak virtual memory: 728 megabytes + Info: Processing ended: Sat Dec 10 19:27:00 2016 + Info: Elapsed time: 00:00:58 + Info: Total CPU time (on all processors): 00:00:13 + + diff --git a/part_4/ex19/output_files/ex19_top.fit.rpt b/part_4/ex19/output_files/ex19_top.fit.rpt new file mode 100644 index 0000000..104f9c1 --- /dev/null +++ b/part_4/ex19/output_files/ex19_top.fit.rpt @@ -0,0 +1,2226 @@ +Fitter report for ex19_top +Sat Dec 10 19:24:58 2016 +Quartus Prime Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Fitter Summary + 3. Fitter Settings + 4. Parallel Compilation + 5. Fitter Netlist Optimizations + 6. Ignored Assignments + 7. Incremental Compilation Preservation Summary + 8. Incremental Compilation Partition Settings + 9. Incremental Compilation Placement Preservation + 10. Pin-Out File + 11. Fitter Resource Usage Summary + 12. Fitter Partition Statistics + 13. Input Pins + 14. Output Pins + 15. I/O Bank Usage + 16. All Package Pins + 17. I/O Assignment Warnings + 18. Fitter Resource Utilization by Entity + 19. Delay Chain Summary + 20. Pad To Core Delay Chain Fanout + 21. Control Signals + 22. Global & Other Fast Signals + 23. Fitter RAM Summary + 24. Routing Usage Summary + 25. I/O Rules Summary + 26. I/O Rules Details + 27. I/O Rules Matrix + 28. Fitter Device Options + 29. Operating Settings and Conditions + 30. Estimated Delay Added for Hold Timing Summary + 31. Estimated Delay Added for Hold Timing Details + 32. Fitter Messages + 33. Fitter Suppressed Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2016 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel MegaCore Function License Agreement, or other +applicable license agreement, including, without limitation, +that your use is for the sole purpose of programming logic +devices manufactured by Intel and sold by Intel or its +authorized distributors. Please refer to the applicable +agreement for further details. + + + ++-------------------------------------------------------------------------------+ +; Fitter Summary ; ++---------------------------------+---------------------------------------------+ +; Fitter Status ; Successful - Sat Dec 10 19:24:58 2016 ; +; Quartus Prime Version ; 16.1.0 Build 196 10/24/2016 SJ Lite Edition ; +; Revision Name ; ex19_top ; +; Top-level Entity Name ; ex19_top ; +; Family ; Cyclone V ; +; Device ; 5CSEMA5F31C6 ; +; Timing Models ; Final ; +; Logic utilization (in ALMs) ; 119 / 32,070 ( < 1 % ) ; +; Total registers ; 139 ; +; Total pins ; 41 / 457 ( 9 % ) ; +; Total virtual pins ; 0 ; +; Total block memory bits ; 73,728 / 4,065,280 ( 2 % ) ; +; Total RAM Blocks ; 9 / 397 ( 2 % ) ; +; Total DSP Blocks ; 0 / 87 ( 0 % ) ; +; Total HSSI RX PCSs ; 0 ; +; Total HSSI PMA RX Deserializers ; 0 ; +; Total HSSI TX PCSs ; 0 ; +; Total HSSI PMA TX Serializers ; 0 ; +; Total PLLs ; 0 / 6 ( 0 % ) ; +; Total DLLs ; 0 / 4 ( 0 % ) ; ++---------------------------------+---------------------------------------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fitter Settings ; ++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+ +; Option ; Setting ; Default Value ; ++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+ +; Device ; 5CSEMA5F31C6 ; ; +; Minimum Core Junction Temperature ; 0 ; ; +; Maximum Core Junction Temperature ; 85 ; ; +; Use smart compilation ; Off ; Off ; +; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ; +; Enable compact report table ; Off ; Off ; +; Router Timing Optimization Level ; Normal ; Normal ; +; Perform Clocking Topology Analysis During Routing ; Off ; Off ; +; Placement Effort Multiplier ; 1.0 ; 1.0 ; +; Device initialization clock source ; INIT_INTOSC ; INIT_INTOSC ; +; Optimize Hold Timing ; All Paths ; All Paths ; +; Optimize Multi-Corner Timing ; On ; On ; +; Auto RAM to MLAB Conversion ; On ; On ; +; Equivalent RAM and MLAB Power Up ; Auto ; Auto ; +; Equivalent RAM and MLAB Paused Read Capabilities ; Care ; Care ; +; PowerPlay Power Optimization During Fitting ; Normal compilation ; Normal compilation ; +; SSN Optimization ; Off ; Off ; +; Optimize Timing ; Normal compilation ; Normal compilation ; +; Optimize Timing for ECOs ; Off ; Off ; +; Regenerate Full Fit Report During ECO Compiles ; Off ; Off ; +; Optimize IOC Register Placement for Timing ; Normal ; Normal ; +; Final Placement Optimizations ; Automatically ; Automatically ; +; Fitter Aggressive Routability Optimizations ; Automatically ; Automatically ; +; Fitter Initial Placement Seed ; 1 ; 1 ; +; Periphery to Core Placement and Routing Optimization ; Off ; Off ; +; Weak Pull-Up Resistor ; Off ; Off ; +; Enable Bus-Hold Circuitry ; Off ; Off ; +; Auto Packed Registers ; Auto ; Auto ; +; Auto Delay Chains ; On ; On ; +; Auto Delay Chains for High Fanout Input Pins ; Off ; Off ; +; Treat Bidirectional Pin as Output Pin ; Off ; Off ; +; Perform Physical Synthesis for Combinational Logic for Fitting ; Off ; Off ; +; Perform Physical Synthesis for Combinational Logic for Performance ; Off ; Off ; +; Perform Register Duplication for Performance ; Off ; Off ; +; Perform Register Retiming for Performance ; Off ; Off ; +; Perform Asynchronous Signal Pipelining ; Off ; Off ; +; Fitter Effort ; Auto Fit ; Auto Fit ; +; Physical Synthesis Effort Level ; Normal ; Normal ; +; Logic Cell Insertion - Logic Duplication ; Auto ; Auto ; +; Auto Register Duplication ; Auto ; Auto ; +; Auto Global Clock ; On ; On ; +; Auto Global Register Control Signals ; On ; On ; +; Reserve all unused pins ; As input tri-stated with weak pull-up ; As input tri-stated with weak pull-up ; +; Synchronizer Identification ; Auto ; Auto ; +; Enable Beneficial Skew Optimization ; On ; On ; +; Optimize Design for Metastability ; On ; On ; +; Active Serial clock source ; FREQ_100MHz ; FREQ_100MHz ; +; Force Fitter to Avoid Periphery Placement Warnings ; Off ; Off ; +; Clamping Diode ; Off ; Off ; +; Enable input tri-state on active configuration pins in user mode ; Off ; Off ; +; Advanced Physical Optimization ; On ; On ; ++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+ + + ++------------------------------------------+ +; Parallel Compilation ; ++----------------------------+-------------+ +; Processors ; Number ; ++----------------------------+-------------+ +; Number detected on machine ; 2 ; +; Maximum allowed ; 2 ; +; ; ; +; Average used ; 1.01 ; +; Maximum used ; 2 ; +; ; ; +; Usage by Processor ; % Time Used ; +; Processor 1 ; 100.0% ; +; Processor 2 ; 0.8% ; ++----------------------------+-------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fitter Netlist Optimizations ; ++-----------------------------------------------+------------+---------------------------------------------------+----------------------------+-----------+----------------+---------------------------------------------------------+------------------+-----------------------+ +; Node ; Action ; Operation ; Reason ; Node Port ; Node Port Name ; Destination Node ; Destination Port ; Destination Port Name ; ++-----------------------------------------------+------------+---------------------------------------------------+----------------------------+-----------+----------------+---------------------------------------------------------+------------------+-----------------------+ +; CLOCK_50~inputCLKENA0 ; Created ; Placement ; Fitter Periphery Placement ; ; ; ; ; ; +; processor:ALLPASS|counter_13:COUNT13|count[1] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; processor:ALLPASS|counter_13:COUNT13|count[1]~DUPLICATE ; ; ; +; processor:ALLPASS|counter_13:COUNT13|count[4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; processor:ALLPASS|counter_13:COUNT13|count[4]~DUPLICATE ; ; ; +; processor:ALLPASS|counter_13:COUNT13|count[6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; processor:ALLPASS|counter_13:COUNT13|count[6]~DUPLICATE ; ; ; +; processor:ALLPASS|data_out[3] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; processor:ALLPASS|data_out[3]~DUPLICATE ; ; ; +; processor:ALLPASS|data_out[6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; processor:ALLPASS|data_out[6]~DUPLICATE ; ; ; +; processor:ALLPASS|data_out[7] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; processor:ALLPASS|data_out[7]~DUPLICATE ; ; ; +; spi2adc:SPI_ADC|clk_1MHz ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; spi2adc:SPI_ADC|clk_1MHz~DUPLICATE ; ; ; +; spi2adc:SPI_ADC|state[0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; spi2adc:SPI_ADC|state[0]~DUPLICATE ; ; ; +; spi2adc:SPI_ADC|state[1] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; spi2adc:SPI_ADC|state[1]~DUPLICATE ; ; ; +; spi2adc:SPI_ADC|state[2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; spi2adc:SPI_ADC|state[2]~DUPLICATE ; ; ; +; spi2adc:SPI_ADC|state[4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; spi2adc:SPI_ADC|state[4]~DUPLICATE ; ; ; +; spi2dac:SPI_DAC|sr_state.WAIT_CSB_FALL ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; spi2dac:SPI_DAC|sr_state.WAIT_CSB_FALL~DUPLICATE ; ; ; +; spi2dac:SPI_DAC|state[1] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; spi2dac:SPI_DAC|state[1]~DUPLICATE ; ; ; +; spi2dac:SPI_DAC|state[4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; spi2dac:SPI_DAC|state[4]~DUPLICATE ; ; ; ++-----------------------------------------------+------------+---------------------------------------------------+----------------------------+-----------+----------------+---------------------------------------------------------+------------------+-----------------------+ + + ++--------------------------------------------------------------------------------------------+ +; Ignored Assignments ; ++--------------+----------------+--------------+------------+---------------+----------------+ +; Name ; Ignored Entity ; Ignored From ; Ignored To ; Ignored Value ; Ignored Source ; ++--------------+----------------+--------------+------------+---------------+----------------+ +; Location ; ; ; HEX3[0] ; PIN_AD26 ; QSF Assignment ; +; Location ; ; ; HEX3[1] ; PIN_AC27 ; QSF Assignment ; +; Location ; ; ; HEX3[2] ; PIN_AD25 ; QSF Assignment ; +; Location ; ; ; HEX3[3] ; PIN_AC25 ; QSF Assignment ; +; Location ; ; ; HEX3[4] ; PIN_AB28 ; QSF Assignment ; +; Location ; ; ; HEX3[5] ; PIN_AB25 ; QSF Assignment ; +; Location ; ; ; HEX3[6] ; PIN_AB22 ; QSF Assignment ; +; Location ; ; ; HEX4[0] ; PIN_AA24 ; QSF Assignment ; +; Location ; ; ; HEX4[1] ; PIN_Y23 ; QSF Assignment ; +; Location ; ; ; HEX4[2] ; PIN_Y24 ; QSF Assignment ; +; Location ; ; ; HEX4[3] ; PIN_W22 ; QSF Assignment ; +; Location ; ; ; HEX4[4] ; PIN_W24 ; QSF Assignment ; +; Location ; ; ; HEX4[5] ; PIN_V23 ; QSF Assignment ; +; Location ; ; ; HEX4[6] ; PIN_W25 ; QSF Assignment ; +; Location ; ; ; HEX5[0] ; PIN_V25 ; QSF Assignment ; +; Location ; ; ; HEX5[1] ; PIN_AA28 ; QSF Assignment ; +; Location ; ; ; HEX5[2] ; PIN_Y27 ; QSF Assignment ; +; Location ; ; ; HEX5[3] ; PIN_AB27 ; QSF Assignment ; +; Location ; ; ; HEX5[4] ; PIN_AB26 ; QSF Assignment ; +; Location ; ; ; HEX5[5] ; PIN_AA26 ; QSF Assignment ; +; Location ; ; ; HEX5[6] ; PIN_AA25 ; QSF Assignment ; +; Location ; ; ; KEY[0] ; PIN_AA14 ; QSF Assignment ; +; Location ; ; ; KEY[1] ; PIN_AA15 ; QSF Assignment ; +; Location ; ; ; KEY[2] ; PIN_W15 ; QSF Assignment ; +; Location ; ; ; KEY[3] ; PIN_Y16 ; QSF Assignment ; +; Location ; ; ; LEDR[0] ; PIN_V16 ; QSF Assignment ; +; Location ; ; ; LEDR[1] ; PIN_W16 ; QSF Assignment ; +; Location ; ; ; LEDR[2] ; PIN_V17 ; QSF Assignment ; +; Location ; ; ; LEDR[3] ; PIN_V18 ; QSF Assignment ; +; Location ; ; ; LEDR[4] ; PIN_W17 ; QSF Assignment ; +; Location ; ; ; LEDR[5] ; PIN_W19 ; QSF Assignment ; +; Location ; ; ; LEDR[6] ; PIN_Y19 ; QSF Assignment ; +; Location ; ; ; LEDR[7] ; PIN_W20 ; QSF Assignment ; +; Location ; ; ; LEDR[8] ; PIN_W21 ; QSF Assignment ; +; Location ; ; ; LEDR[9] ; PIN_Y21 ; QSF Assignment ; +; Location ; ; ; OLED_CLK ; PIN_AJ19 ; QSF Assignment ; +; Location ; ; ; OLED_CS ; PIN_Y17 ; QSF Assignment ; +; Location ; ; ; OLED_DATA ; PIN_AJ16 ; QSF Assignment ; +; Location ; ; ; OLED_DC ; PIN_AK18 ; QSF Assignment ; +; Location ; ; ; OLED_RST ; PIN_Y18 ; QSF Assignment ; +; I/O Standard ; ex19_top ; ; HEX3[0] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ex19_top ; ; HEX3[1] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ex19_top ; ; HEX3[2] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ex19_top ; ; HEX3[3] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ex19_top ; ; HEX3[4] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ex19_top ; ; HEX3[5] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ex19_top ; ; HEX3[6] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ex19_top ; ; HEX4[0] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ex19_top ; ; HEX4[1] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ex19_top ; ; HEX4[2] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ex19_top ; ; HEX4[3] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ex19_top ; ; HEX4[4] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ex19_top ; ; HEX4[5] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ex19_top ; ; HEX4[6] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ex19_top ; ; HEX5[0] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ex19_top ; ; HEX5[1] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ex19_top ; ; HEX5[2] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ex19_top ; ; HEX5[3] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ex19_top ; ; HEX5[4] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ex19_top ; ; HEX5[5] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ex19_top ; ; HEX5[6] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ex19_top ; ; KEY[0] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ex19_top ; ; KEY[1] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ex19_top ; ; KEY[2] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ex19_top ; ; KEY[3] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ex19_top ; ; LEDR[0] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ex19_top ; ; LEDR[1] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ex19_top ; ; LEDR[2] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ex19_top ; ; LEDR[3] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ex19_top ; ; LEDR[4] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ex19_top ; ; LEDR[5] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ex19_top ; ; LEDR[6] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ex19_top ; ; LEDR[7] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ex19_top ; ; LEDR[8] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ex19_top ; ; LEDR[9] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ex19_top ; ; OLED_CLK ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ex19_top ; ; OLED_CS ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ex19_top ; ; OLED_DATA ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ex19_top ; ; OLED_DC ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ex19_top ; ; OLED_RST ; 3.3-V LVTTL ; QSF Assignment ; ++--------------+----------------+--------------+------------+---------------+----------------+ + + ++--------------------------------------------------------------------------------------------------+ +; Incremental Compilation Preservation Summary ; ++---------------------+--------------------+----------------------------+--------------------------+ +; Type ; Total [A + B] ; From Design Partitions [A] ; From Rapid Recompile [B] ; ++---------------------+--------------------+----------------------------+--------------------------+ +; Placement (by node) ; ; ; ; +; -- Requested ; 0.00 % ( 0 / 431 ) ; 0.00 % ( 0 / 431 ) ; 0.00 % ( 0 / 431 ) ; +; -- Achieved ; 0.00 % ( 0 / 431 ) ; 0.00 % ( 0 / 431 ) ; 0.00 % ( 0 / 431 ) ; +; ; ; ; ; +; Routing (by net) ; ; ; ; +; -- Requested ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; +; -- Achieved ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; ++---------------------+--------------------+----------------------------+--------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Incremental Compilation Partition Settings ; ++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+ +; Partition Name ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents ; ++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+ +; Top ; User-created ; Source File ; N/A ; Source File ; N/A ; ; +; hard_block:auto_generated_inst ; Auto-generated ; Source File ; N/A ; Source File ; N/A ; hard_block:auto_generated_inst ; ++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------+ +; Incremental Compilation Placement Preservation ; ++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+ +; Partition Name ; Preservation Achieved ; Preservation Level Used ; Netlist Type Used ; Preservation Method ; Notes ; ++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+ +; Top ; 0.00 % ( 0 / 431 ) ; N/A ; Source File ; N/A ; ; +; hard_block:auto_generated_inst ; 0.00 % ( 0 / 0 ) ; N/A ; Source File ; N/A ; ; ++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+ + + ++--------------+ +; Pin-Out File ; ++--------------+ +The pin-out file can be found in H:/Year 2/VERI/part_4/ex19/output_files/ex19_top.pin. + + ++------------------------------------------------------------------------------------------+ +; Fitter Resource Usage Summary ; ++-------------------------------------------------------------+--------------------+-------+ +; Resource ; Usage ; % ; ++-------------------------------------------------------------+--------------------+-------+ +; Logic utilization (ALMs needed / total ALMs on device) ; 119 / 32,070 ; < 1 % ; +; ALMs needed [=A-B+C] ; 119 ; ; +; [A] ALMs used in final placement [=a+b+c+d] ; 134 / 32,070 ; < 1 % ; +; [a] ALMs used for LUT logic and registers ; 42 ; ; +; [b] ALMs used for LUT logic ; 72 ; ; +; [c] ALMs used for registers ; 20 ; ; +; [d] ALMs used for memory (up to half of total ALMs) ; 0 ; ; +; [B] Estimate of ALMs recoverable by dense packing ; 15 / 32,070 ; < 1 % ; +; [C] Estimate of ALMs unavailable [=a+b+c+d] ; 0 / 32,070 ; 0 % ; +; [a] Due to location constrained logic ; 0 ; ; +; [b] Due to LAB-wide signal conflicts ; 0 ; ; +; [c] Due to LAB input limits ; 0 ; ; +; [d] Due to virtual I/Os ; 0 ; ; +; ; ; ; +; Difficulty packing design ; Low ; ; +; ; ; ; +; Total LABs: partially or completely used ; 18 / 3,207 ; < 1 % ; +; -- Logic LABs ; 18 ; ; +; -- Memory LABs (up to half of total LABs) ; 0 ; ; +; ; ; ; +; Combinational ALUT usage for logic ; 214 ; ; +; -- 7 input functions ; 0 ; ; +; -- 6 input functions ; 11 ; ; +; -- 5 input functions ; 29 ; ; +; -- 4 input functions ; 79 ; ; +; -- <=3 input functions ; 95 ; ; +; Combinational ALUT usage for route-throughs ; 28 ; ; +; ; ; ; +; Dedicated logic registers ; 139 ; ; +; -- By type: ; ; ; +; -- Primary logic registers ; 122 / 64,140 ; < 1 % ; +; -- Secondary logic registers ; 17 / 64,140 ; < 1 % ; +; -- By function: ; ; ; +; -- Design implementation registers ; 125 ; ; +; -- Routing optimization registers ; 14 ; ; +; ; ; ; +; Virtual pins ; 0 ; ; +; I/O pins ; 41 / 457 ; 9 % ; +; -- Clock pins ; 1 / 8 ; 13 % ; +; -- Dedicated input pins ; 0 / 21 ; 0 % ; +; ; ; ; +; Hard processor system peripheral utilization ; ; ; +; -- Boot from FPGA ; 0 / 1 ( 0 % ) ; ; +; -- Clock resets ; 0 / 1 ( 0 % ) ; ; +; -- Cross trigger ; 0 / 1 ( 0 % ) ; ; +; -- S2F AXI ; 0 / 1 ( 0 % ) ; ; +; -- F2S AXI ; 0 / 1 ( 0 % ) ; ; +; -- AXI Lightweight ; 0 / 1 ( 0 % ) ; ; +; -- SDRAM ; 0 / 1 ( 0 % ) ; ; +; -- Interrupts ; 0 / 1 ( 0 % ) ; ; +; -- JTAG ; 0 / 1 ( 0 % ) ; ; +; -- Loan I/O ; 0 / 1 ( 0 % ) ; ; +; -- MPU event standby ; 0 / 1 ( 0 % ) ; ; +; -- MPU general purpose ; 0 / 1 ( 0 % ) ; ; +; -- STM event ; 0 / 1 ( 0 % ) ; ; +; -- TPIU trace ; 0 / 1 ( 0 % ) ; ; +; -- DMA ; 0 / 1 ( 0 % ) ; ; +; -- CAN ; 0 / 2 ( 0 % ) ; ; +; -- EMAC ; 0 / 2 ( 0 % ) ; ; +; -- I2C ; 0 / 4 ( 0 % ) ; ; +; -- NAND Flash ; 0 / 1 ( 0 % ) ; ; +; -- QSPI ; 0 / 1 ( 0 % ) ; ; +; -- SDMMC ; 0 / 1 ( 0 % ) ; ; +; -- SPI Master ; 0 / 2 ( 0 % ) ; ; +; -- SPI Slave ; 0 / 2 ( 0 % ) ; ; +; -- UART ; 0 / 2 ( 0 % ) ; ; +; -- USB ; 0 / 2 ( 0 % ) ; ; +; ; ; ; +; M10K blocks ; 9 / 397 ; 2 % ; +; Total MLAB memory bits ; 0 ; ; +; Total block memory bits ; 73,728 / 4,065,280 ; 2 % ; +; Total block memory implementation bits ; 92,160 / 4,065,280 ; 2 % ; +; ; ; ; +; Total DSP Blocks ; 0 / 87 ; 0 % ; +; ; ; ; +; Fractional PLLs ; 0 / 6 ; 0 % ; +; Global signals ; 1 ; ; +; -- Global clocks ; 1 / 16 ; 6 % ; +; -- Quadrant clocks ; 0 / 66 ; 0 % ; +; -- Horizontal periphery clocks ; 0 / 18 ; 0 % ; +; SERDES Transmitters ; 0 / 100 ; 0 % ; +; SERDES Receivers ; 0 / 100 ; 0 % ; +; JTAGs ; 0 / 1 ; 0 % ; +; ASMI blocks ; 0 / 1 ; 0 % ; +; CRC blocks ; 0 / 1 ; 0 % ; +; Remote update blocks ; 0 / 1 ; 0 % ; +; Oscillator blocks ; 0 / 1 ; 0 % ; +; Impedance control blocks ; 0 / 4 ; 0 % ; +; Hard Memory Controllers ; 0 / 2 ; 0 % ; +; Average interconnect usage (total/H/V) ; 0.2% / 0.2% / 0.1% ; ; +; Peak interconnect usage (total/H/V) ; 3.4% / 4.0% / 1.8% ; ; +; Maximum fan-out ; 131 ; ; +; Highest non-global fan-out ; 39 ; ; +; Total fan-out ; 1438 ; ; +; Average fan-out ; 3.04 ; ; ++-------------------------------------------------------------+--------------------+-------+ + + ++----------------------------------------------------------------------------------------------------------------------+ +; Fitter Partition Statistics ; ++-------------------------------------------------------------+-----------------------+--------------------------------+ +; Statistic ; Top ; hard_block:auto_generated_inst ; ++-------------------------------------------------------------+-----------------------+--------------------------------+ +; Logic utilization (ALMs needed / total ALMs on device) ; 119 / 32070 ( < 1 % ) ; 0 / 32070 ( 0 % ) ; +; ALMs needed [=A-B+C] ; 119 ; 0 ; +; [A] ALMs used in final placement [=a+b+c+d] ; 134 / 32070 ( < 1 % ) ; 0 / 32070 ( 0 % ) ; +; [a] ALMs used for LUT logic and registers ; 42 ; 0 ; +; [b] ALMs used for LUT logic ; 72 ; 0 ; +; [c] ALMs used for registers ; 20 ; 0 ; +; [d] ALMs used for memory (up to half of total ALMs) ; 0 ; 0 ; +; [B] Estimate of ALMs recoverable by dense packing ; 15 / 32070 ( < 1 % ) ; 0 / 32070 ( 0 % ) ; +; [C] Estimate of ALMs unavailable [=a+b+c+d] ; 0 / 32070 ( 0 % ) ; 0 / 32070 ( 0 % ) ; +; [a] Due to location constrained logic ; 0 ; 0 ; +; [b] Due to LAB-wide signal conflicts ; 0 ; 0 ; +; [c] Due to LAB input limits ; 0 ; 0 ; +; [d] Due to virtual I/Os ; 0 ; 0 ; +; ; ; ; +; Difficulty packing design ; Low ; Low ; +; ; ; ; +; Total LABs: partially or completely used ; 18 / 3207 ( < 1 % ) ; 0 / 3207 ( 0 % ) ; +; -- Logic LABs ; 18 ; 0 ; +; -- Memory LABs (up to half of total LABs) ; 0 ; 0 ; +; ; ; ; +; Combinational ALUT usage for logic ; 214 ; 0 ; +; -- 7 input functions ; 0 ; 0 ; +; -- 6 input functions ; 11 ; 0 ; +; -- 5 input functions ; 29 ; 0 ; +; -- 4 input functions ; 79 ; 0 ; +; -- <=3 input functions ; 95 ; 0 ; +; Combinational ALUT usage for route-throughs ; 28 ; 0 ; +; Memory ALUT usage ; 0 ; 0 ; +; -- 64-address deep ; 0 ; 0 ; +; -- 32-address deep ; 0 ; 0 ; +; ; ; ; +; Dedicated logic registers ; 0 ; 0 ; +; -- By type: ; ; ; +; -- Primary logic registers ; 122 / 64140 ( < 1 % ) ; 0 / 64140 ( 0 % ) ; +; -- Secondary logic registers ; 17 / 64140 ( < 1 % ) ; 0 / 64140 ( 0 % ) ; +; -- By function: ; ; ; +; -- Design implementation registers ; 125 ; 0 ; +; -- Routing optimization registers ; 14 ; 0 ; +; ; ; ; +; ; ; ; +; Virtual pins ; 0 ; 0 ; +; I/O pins ; 41 ; 0 ; +; I/O registers ; 0 ; 0 ; +; Total block memory bits ; 73728 ; 0 ; +; Total block memory implementation bits ; 92160 ; 0 ; +; M10K block ; 9 / 397 ( 2 % ) ; 0 / 397 ( 0 % ) ; +; Clock enable block ; 1 / 116 ( < 1 % ) ; 0 / 116 ( 0 % ) ; +; ; ; ; +; Connections ; ; ; +; -- Input Connections ; 0 ; 0 ; +; -- Registered Input Connections ; 0 ; 0 ; +; -- Output Connections ; 0 ; 0 ; +; -- Registered Output Connections ; 0 ; 0 ; +; ; ; ; +; Internal Connections ; ; ; +; -- Total Connections ; 1618 ; 0 ; +; -- Registered Connections ; 544 ; 0 ; +; ; ; ; +; External Connections ; ; ; +; -- Top ; 0 ; 0 ; +; -- hard_block:auto_generated_inst ; 0 ; 0 ; +; ; ; ; +; Partition Interface ; ; ; +; -- Input Ports ; 12 ; 0 ; +; -- Output Ports ; 29 ; 0 ; +; -- Bidir Ports ; 0 ; 0 ; +; ; ; ; +; Registered Ports ; ; ; +; -- Registered Input Ports ; 0 ; 0 ; +; -- Registered Output Ports ; 0 ; 0 ; +; ; ; ; +; Port Connectivity ; ; ; +; -- Input Ports driven by GND ; 0 ; 0 ; +; -- Output Ports driven by GND ; 0 ; 0 ; +; -- Input Ports driven by VCC ; 0 ; 0 ; +; -- Output Ports driven by VCC ; 0 ; 0 ; +; -- Input Ports with no Source ; 0 ; 0 ; +; -- Output Ports with no Source ; 0 ; 0 ; +; -- Input Ports with no Fanout ; 0 ; 0 ; +; -- Output Ports with no Fanout ; 0 ; 0 ; ++-------------------------------------------------------------+-----------------------+--------------------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Input Pins ; ++----------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+ +; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Termination Control Block ; Location assigned by ; Slew Rate ; ++----------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+ +; ADC_SDO ; AJ21 ; 4A ; 62 ; 0 ; 51 ; 1 ; 0 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ; no ; +; CLOCK_50 ; AF14 ; 3B ; 32 ; 0 ; 0 ; 132 ; 0 ; yes ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ; no ; +; SW[0] ; AB12 ; 3A ; 12 ; 0 ; 17 ; 9 ; 0 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ; no ; +; SW[1] ; AC12 ; 3A ; 16 ; 0 ; 0 ; 9 ; 0 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ; no ; +; SW[2] ; AF9 ; 3A ; 8 ; 0 ; 34 ; 9 ; 0 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ; no ; +; SW[3] ; AF10 ; 3A ; 4 ; 0 ; 51 ; 9 ; 0 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ; no ; +; SW[4] ; AD11 ; 3A ; 2 ; 0 ; 40 ; 15 ; 0 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ; no ; +; SW[5] ; AD12 ; 3A ; 16 ; 0 ; 17 ; 14 ; 0 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ; no ; +; SW[6] ; AE11 ; 3A ; 4 ; 0 ; 34 ; 13 ; 0 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ; no ; +; SW[7] ; AC9 ; 3A ; 4 ; 0 ; 0 ; 12 ; 0 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ; no ; +; SW[8] ; AD10 ; 3A ; 4 ; 0 ; 17 ; 7 ; 0 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ; no ; +; SW[9] ; AE12 ; 3A ; 2 ; 0 ; 57 ; 0 ; 0 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ; no ; ++----------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Output Pins ; ++---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+ +; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Output Buffer Delay ; Output Buffer Delay Control ; Location assigned by ; Output Enable Source ; Output Enable Group ; ++---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+ +; ADC_CS ; AG20 ; 4A ; 62 ; 0 ; 17 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; +; ADC_SCK ; AF21 ; 4A ; 70 ; 0 ; 17 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; +; ADC_SDI ; AG21 ; 4A ; 54 ; 0 ; 0 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; +; DAC_CS ; AD20 ; 4A ; 82 ; 0 ; 40 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; +; DAC_LD ; AK21 ; 4A ; 68 ; 0 ; 34 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; +; DAC_SCK ; AF20 ; 4A ; 70 ; 0 ; 0 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; +; DAC_SDI ; AG18 ; 4A ; 58 ; 0 ; 74 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; +; HEX0[0] ; AE26 ; 5A ; 89 ; 8 ; 37 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; +; HEX0[1] ; AE27 ; 5A ; 89 ; 11 ; 77 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; +; HEX0[2] ; AE28 ; 5A ; 89 ; 11 ; 94 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; +; HEX0[3] ; AG27 ; 5A ; 89 ; 4 ; 77 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; +; HEX0[4] ; AF28 ; 5A ; 89 ; 13 ; 54 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; +; HEX0[5] ; AG28 ; 5A ; 89 ; 13 ; 37 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; +; HEX0[6] ; AH28 ; 5A ; 89 ; 4 ; 94 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; +; HEX1[0] ; AJ29 ; 5A ; 89 ; 6 ; 37 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; +; HEX1[1] ; AH29 ; 5A ; 89 ; 6 ; 54 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; +; HEX1[2] ; AH30 ; 5A ; 89 ; 16 ; 37 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; +; HEX1[3] ; AG30 ; 5A ; 89 ; 16 ; 54 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; +; HEX1[4] ; AF29 ; 5A ; 89 ; 15 ; 37 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; +; HEX1[5] ; AF30 ; 5A ; 89 ; 15 ; 54 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; +; HEX1[6] ; AD27 ; 5A ; 89 ; 8 ; 54 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; +; HEX2[0] ; AB23 ; 5A ; 89 ; 9 ; 20 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; +; HEX2[1] ; AE29 ; 5B ; 89 ; 23 ; 37 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; +; HEX2[2] ; AD29 ; 5B ; 89 ; 23 ; 54 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; +; HEX2[3] ; AC28 ; 5B ; 89 ; 20 ; 77 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; +; HEX2[4] ; AD30 ; 5B ; 89 ; 25 ; 37 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; +; HEX2[5] ; AC29 ; 5B ; 89 ; 20 ; 94 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; +; HEX2[6] ; AC30 ; 5B ; 89 ; 25 ; 54 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; +; PWM_OUT ; AJ20 ; 4A ; 62 ; 0 ; 34 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; ++---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+ + + ++----------------------------------------------------------------------------+ +; I/O Bank Usage ; ++----------+------------------+---------------+--------------+---------------+ +; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ; VCCPD Voltage ; ++----------+------------------+---------------+--------------+---------------+ +; B2L ; 0 / 0 ( -- ) ; -- ; -- ; -- ; +; B1L ; 0 / 0 ( -- ) ; -- ; -- ; -- ; +; 3A ; 10 / 32 ( 31 % ) ; 3.3V ; -- ; 3.3V ; +; 3B ; 1 / 48 ( 2 % ) ; 3.3V ; -- ; 3.3V ; +; 4A ; 9 / 80 ( 11 % ) ; 3.3V ; -- ; 3.3V ; +; 5A ; 15 / 32 ( 47 % ) ; 3.3V ; -- ; 3.3V ; +; 5B ; 6 / 16 ( 38 % ) ; 3.3V ; -- ; 3.3V ; +; 6B ; 0 / 44 ( 0 % ) ; 2.5V ; -- ; 2.5V ; +; 6A ; 0 / 56 ( 0 % ) ; 2.5V ; -- ; 2.5V ; +; 7A ; 0 / 19 ( 0 % ) ; 2.5V ; -- ; 2.5V ; +; 7B ; 0 / 22 ( 0 % ) ; 2.5V ; -- ; 2.5V ; +; 7C ; 0 / 12 ( 0 % ) ; 2.5V ; -- ; 2.5V ; +; 7D ; 0 / 14 ( 0 % ) ; 2.5V ; -- ; 2.5V ; +; 8A ; 0 / 80 ( 0 % ) ; 2.5V ; -- ; 2.5V ; ++----------+------------------+---------------+--------------+---------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; All Package Pins ; ++----------+------------+----------------+---------------------------------+--------+--------------+---------------------+--------------+-----------------+----------+--------------+ +; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; I/O Type ; User Assignment ; Bus Hold ; Weak Pull Up ; ++----------+------------+----------------+---------------------------------+--------+--------------+---------------------+--------------+-----------------+----------+--------------+ +; A2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; A3 ; 493 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A4 ; 491 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A5 ; 489 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A6 ; 487 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A7 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; A8 ; 473 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A9 ; 471 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A10 ; 465 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A11 ; 463 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; A13 ; 461 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A14 ; 455 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A15 ; 447 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A16 ; 439 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; A18 ; 425 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A19 ; 423 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A20 ; 415 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A21 ; 411 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; A23 ; 395 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A24 ; 391 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A25 ; 389 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A26 ; 382 ; 7A ; ^GND ; ; ; ; -- ; ; -- ; -- ; +; A27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; A28 ; 380 ; 7A ; ^HPS_TRST ; ; ; ; -- ; ; -- ; -- ; +; A29 ; 378 ; 7A ; ^HPS_TMS ; ; ; ; -- ; ; -- ; -- ; +; AA1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AA2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AA3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AA4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AA5 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; AA6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AA7 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; +; AA8 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AA9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AA10 ; ; 3A ; VCCPD3A ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AA11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AA12 ; 74 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA13 ; 90 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA14 ; 122 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA15 ; 120 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA16 ; 146 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA17 ; ; 4A ; VCCIO4A ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AA18 ; 168 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA19 ; 176 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA20 ; 200 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA21 ; 210 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AA23 ; ; -- ; VCCPGM ; power ; ; 1.8V/2.5V/3.0V/3.3V ; -- ; ; -- ; -- ; +; AA24 ; 228 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AA25 ; 224 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AA26 ; 252 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AA27 ; ; 5B ; VCCIO5B ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AA28 ; 251 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AA29 ; ; 5B ; VREFB5BN0 ; power ; ; ; -- ; ; -- ; -- ; +; AA30 ; 250 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AB1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AB2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AB3 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; +; AB4 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; +; AB5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AB6 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AB7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AB8 ; 43 ; 3A ; ^nCSO, DATA4 ; ; ; ; Weak Pull Up ; ; -- ; On ; +; AB9 ; 42 ; 3A ; #TDO ; output ; ; ; -- ; ; -- ; -- ; +; AB10 ; ; -- ; VCCPGM ; power ; ; 1.8V/2.5V/3.0V/3.3V ; -- ; ; -- ; -- ; +; AB11 ; ; -- ; VCC_AUX ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AB12 ; 72 ; 3A ; SW[0] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; AB13 ; 88 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB14 ; ; 3B ; VCCIO3B ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AB15 ; 106 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB16 ; ; -- ; VCC_AUX ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AB17 ; 144 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB18 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AB19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AB20 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AB21 ; 208 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB22 ; 225 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AB23 ; 227 ; 5A ; HEX2[0] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; AB24 ; ; 5A ; VCCIO5A ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AB25 ; 230 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AB26 ; 226 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AB27 ; 254 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AB28 ; 249 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AB29 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AB30 ; 248 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AC1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AC2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AC3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AC4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AC5 ; 46 ; 3A ; #TCK ; input ; ; ; -- ; ; -- ; -- ; +; AC6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AC7 ; 45 ; 3A ; ^AS_DATA3, DATA3 ; ; ; ; Weak Pull Up ; ; -- ; On ; +; AC8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AC9 ; 58 ; 3A ; SW[7] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; AC10 ; ; 3A ; VCCPD3A ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AC11 ; ; 3A ; VCCIO3A ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AC12 ; 82 ; 3A ; SW[1] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; AC13 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AC14 ; 104 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AC15 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AC16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AC17 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AC18 ; 162 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AC19 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AC20 ; 186 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AC21 ; ; 4A ; VCCIO4A ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AC22 ; 207 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AC23 ; 205 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AC24 ; ; 5A ; VREFB5AN0 ; power ; ; ; -- ; ; -- ; -- ; +; AC25 ; 215 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AC26 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AC27 ; 242 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AC28 ; 245 ; 5B ; HEX2[3] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; AC29 ; 247 ; 5B ; HEX2[5] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; AC30 ; 259 ; 5B ; HEX2[6] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; AD1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AD2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AD3 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; +; AD4 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; +; AD5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AD6 ; ; 3A ; VREFB3AN0 ; power ; ; ; -- ; ; -- ; -- ; +; AD7 ; 62 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AD8 ; ; 3A ; VCCIO3A ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AD9 ; 55 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AD10 ; 56 ; 3A ; SW[8] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; AD11 ; 54 ; 3A ; SW[4] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; AD12 ; 80 ; 3A ; SW[5] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; AD13 ; ; 3B ; VCCIO3B ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AD14 ; 98 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AD15 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; +; AD16 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AD17 ; 160 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AD18 ; ; 4A ; VCCIO4A ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AD19 ; 184 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AD20 ; 199 ; 4A ; DAC_CS ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; AD21 ; 197 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AD22 ; ; -- ; VCC_AUX ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AD23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AD24 ; 211 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AD25 ; 213 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AD26 ; 240 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AD27 ; 222 ; 5A ; HEX1[6] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; AD28 ; ; 5A ; VCCIO5A ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AD29 ; 255 ; 5B ; HEX2[2] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; AD30 ; 257 ; 5B ; HEX2[4] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; AE1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AE2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AE3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AE4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AE5 ; 49 ; 3A ; ^AS_DATA1, DATA1 ; ; ; ; Weak Pull Up ; ; -- ; On ; +; AE6 ; 51 ; 3A ; ^AS_DATA0, ASDO, DATA0 ; ; ; ; Weak Pull Up ; ; -- ; On ; +; AE7 ; 60 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AE8 ; 47 ; 3A ; ^AS_DATA2, DATA2 ; ; ; ; Weak Pull Up ; ; -- ; On ; +; AE9 ; 53 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AE10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AE11 ; 59 ; 3A ; SW[6] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; AE12 ; 52 ; 3A ; SW[9] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; AE13 ; 95 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AE14 ; 96 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AE15 ; ; 3B ; VCCIO3B ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AE16 ; 139 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AE17 ; 135 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AE18 ; 167 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AE19 ; 165 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AE20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AE21 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AE22 ; 191 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AE23 ; 189 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AE24 ; 209 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AE25 ; ; 4A ; VCCIO4A ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AE26 ; 220 ; 5A ; HEX0[0] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; AE27 ; 229 ; 5A ; HEX0[1] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; AE28 ; 231 ; 5A ; HEX0[2] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; AE29 ; 253 ; 5B ; HEX2[1] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; AE30 ; ; 5B ; VCCIO5B ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AF1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AF2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AF3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AF4 ; 66 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF5 ; 64 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF6 ; 75 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF7 ; ; 3A ; VCCIO3A ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AF8 ; 70 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF9 ; 67 ; 3A ; SW[2] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; AF10 ; 57 ; 3A ; SW[3] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; AF11 ; 87 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AF13 ; 93 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF14 ; 114 ; 3B ; CLOCK_50 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; AF15 ; 112 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF16 ; 137 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AF18 ; 133 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF19 ; 159 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF20 ; 175 ; 4A ; DAC_SCK ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; AF21 ; 173 ; 4A ; ADC_SCK ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; AF22 ; ; 4A ; VCCIO4A ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AF23 ; 183 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF24 ; 181 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF25 ; 206 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF26 ; 204 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AF28 ; 235 ; 5A ; HEX0[4] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; AF29 ; 237 ; 5A ; HEX1[4] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; AF30 ; 239 ; 5A ; HEX1[5] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; AG1 ; 71 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AG2 ; 83 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AG3 ; 63 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AG4 ; ; 3A ; VCCIO3A ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AG5 ; 78 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AG6 ; 73 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AG7 ; 68 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AG8 ; 65 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AG9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AG10 ; 86 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AG11 ; 85 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AG12 ; 103 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AG13 ; 101 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AG14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AG15 ; 127 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AG16 ; 134 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AG17 ; 132 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AG18 ; 150 ; 4A ; DAC_SDI ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; AG19 ; ; 4A ; VCCIO4A ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AG20 ; 157 ; 4A ; ADC_CS ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; AG21 ; 143 ; 4A ; ADC_SDI ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; AG22 ; 166 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AG23 ; 163 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AG24 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AG25 ; 190 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AG26 ; 203 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AG27 ; 212 ; 5A ; HEX0[3] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; AG28 ; 233 ; 5A ; HEX0[5] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; AG29 ; ; 5A ; VCCIO5A ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AG30 ; 243 ; 5A ; HEX1[3] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; AH1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AH2 ; 69 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AH3 ; 81 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AH4 ; 61 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AH5 ; 76 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AH6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AH7 ; 115 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AH8 ; 113 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AH9 ; 84 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AH10 ; 118 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AH11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AH12 ; 126 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AH13 ; 111 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AH14 ; 109 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AH15 ; 125 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AH16 ; ; 4A ; VCCIO4A ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AH17 ; 147 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AH18 ; 145 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AH19 ; 148 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AH20 ; 141 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AH21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AH22 ; 164 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AH23 ; 174 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AH24 ; 161 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AH25 ; 188 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AH26 ; ; 4A ; VCCIO4A ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AH27 ; 201 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AH28 ; 214 ; 5A ; HEX0[6] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; AH29 ; 218 ; 5A ; HEX1[1] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; AH30 ; 241 ; 5A ; HEX1[2] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; AJ1 ; 79 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AJ2 ; 77 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AJ3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AJ4 ; 94 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AJ5 ; 99 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AJ6 ; 102 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AJ7 ; 100 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AJ8 ; ; 3B ; VCCIO3B ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AJ9 ; 110 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AJ10 ; 116 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AJ11 ; 119 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AJ12 ; 124 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AJ13 ; ; 3B ; VCCIO3B ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AJ14 ; 131 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AJ15 ; ; 3B ; VREFB3BN0 ; power ; ; ; -- ; ; -- ; -- ; +; AJ16 ; 142 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AJ17 ; 151 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AJ18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AJ19 ; 155 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AJ20 ; 158 ; 4A ; PWM_OUT ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; AJ21 ; 156 ; 4A ; ADC_SDO ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; AJ22 ; 172 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AJ23 ; ; 4A ; VCCIO4A ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AJ24 ; 182 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AJ25 ; 180 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AJ26 ; 187 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AJ27 ; 195 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AJ28 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AJ29 ; 216 ; 5A ; HEX1[0] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; AJ30 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AK2 ; 91 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AK3 ; 89 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AK4 ; 92 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AK5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AK6 ; 97 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AK7 ; 107 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AK8 ; 105 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AK9 ; 108 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AK10 ; ; 3B ; VCCIO3B ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AK11 ; 117 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AK12 ; 123 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AK13 ; 121 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AK14 ; 129 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AK15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AK16 ; 140 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AK17 ; ; 4A ; VREFB4AN0 ; power ; ; ; -- ; ; -- ; -- ; +; AK18 ; 149 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AK19 ; 153 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AK20 ; ; 4A ; VCCIO4A ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AK21 ; 171 ; 4A ; DAC_LD ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; AK22 ; 169 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AK23 ; 179 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AK24 ; 177 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AK25 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AK26 ; 185 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AK27 ; 193 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AK28 ; 198 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AK29 ; 196 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B1 ; 509 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B2 ; 507 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B3 ; 513 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B4 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; B5 ; 512 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B6 ; 510 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B7 ; 477 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B8 ; 481 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B10 ; ; 8A ; VREFB8AN0 ; power ; ; ; -- ; ; -- ; -- ; +; B11 ; 469 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B12 ; 464 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B13 ; 459 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B15 ; 451 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B16 ; 441 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B17 ; 431 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B18 ; 418 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B20 ; 417 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B21 ; 413 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B22 ; 399 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B23 ; 397 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B24 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B25 ; 387 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B26 ; 386 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B27 ; 381 ; 7A ; ^HPS_TDI ; ; ; ; -- ; ; -- ; -- ; +; B28 ; 376 ; 7A ; ^HPS_TDO ; ; ; ; -- ; ; -- ; -- ; +; B29 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B30 ; 365 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; C1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; C2 ; 517 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C3 ; 511 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C4 ; 501 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C5 ; 497 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; C7 ; 475 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C8 ; 479 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C9 ; 485 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C10 ; 483 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C11 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; C12 ; 467 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C13 ; 462 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C14 ; 448 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C15 ; 453 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; C17 ; 433 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C18 ; 435 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C19 ; 427 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C20 ; 421 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; C22 ; 396 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C23 ; 401 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C24 ; 393 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C25 ; 388 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C26 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; C27 ; 374 ; 7A ; ^HPS_nRST ; ; ; ; -- ; ; -- ; -- ; +; C28 ; 369 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; C29 ; 367 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; C30 ; 363 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; D1 ; 529 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D2 ; 515 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; D4 ; 521 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D5 ; 499 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D6 ; 495 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D7 ; 505 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D8 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; D9 ; 480 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D10 ; 472 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D11 ; 470 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D12 ; 496 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; D14 ; 446 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D15 ; 449 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D16 ; 445 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D17 ; 440 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D18 ; ; 7C ; VCCIO7C_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; D19 ; 426 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D20 ; 420 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D21 ; 419 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D22 ; 402 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; D24 ; 404 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D25 ; 384 ; 7A ; ^HPS_CLK1 ; ; ; ; -- ; ; -- ; -- ; +; D26 ; 373 ; 7A ; ^GND ; ; ; ; -- ; ; -- ; -- ; +; D27 ; 371 ; 6A ; HPS_RZQ_0 ; ; ; ; -- ; ; no ; On ; +; D28 ; ; 6A ; VCCIO6A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; D29 ; 361 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; D30 ; 359 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E1 ; 527 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E2 ; 525 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E3 ; 523 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E4 ; 519 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E5 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; E6 ; 533 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E7 ; 531 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E8 ; 503 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E9 ; 478 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; E11 ; 504 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E12 ; 494 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E13 ; 488 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E14 ; 454 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E15 ; ; 7D ; VCCIO7D_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; E16 ; 443 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E17 ; 438 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E18 ; 437 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E19 ; 424 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E20 ; ; 7B ; VCCIO7B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; E21 ; 412 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E22 ; ; 7A, 7B, 7C, 7D ; VREFB7A7B7C7DN0_HPS ; power ; ; ; -- ; ; -- ; -- ; +; E23 ; 394 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E24 ; 403 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E25 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; E26 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; +; E27 ; 357 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E28 ; 351 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E29 ; 353 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E30 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; F1 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; +; F2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; F3 ; 539 ; 9A ; ^CONF_DONE ; ; ; ; -- ; ; -- ; -- ; +; F4 ; 541 ; 9A ; ^nSTATUS ; ; ; ; -- ; ; -- ; -- ; +; F5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; F6 ; 537 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; F8 ; 536 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F9 ; 534 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F10 ; 528 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F11 ; 502 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F12 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; F13 ; 486 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F14 ; 468 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F15 ; 466 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F16 ; 442 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; F18 ; 430 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F19 ; 410 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F20 ; 407 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F21 ; 409 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F22 ; ; 7A ; VCCIO7A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; F23 ; 375 ; 7A ; ^HPS_nPOR ; ; ; ; -- ; ; -- ; -- ; +; F24 ; 383 ; 7A ; ^HPS_PORSEL ; ; ; ; -- ; ; -- ; -- ; +; F25 ; 385 ; 7A ; ^HPS_CLK2 ; ; ; ; -- ; ; -- ; -- ; +; F26 ; 341 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; F28 ; 345 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F29 ; 349 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F30 ; 347 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G1 ; ; ; GND ; ; ; ; -- ; ; -- ; -- ; +; G2 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; +; G3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; G4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; G5 ; 542 ; 9A ; ^nCE ; ; ; ; -- ; ; -- ; -- ; +; G6 ; 543 ; 9A ; ^MSEL2 ; ; ; ; -- ; ; -- ; -- ; +; G7 ; 535 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; G8 ; 492 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; G9 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; G10 ; 526 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; G11 ; 520 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; G12 ; 518 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; G13 ; 484 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; G14 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; G15 ; 460 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; G16 ; 444 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; G17 ; 436 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; G18 ; 432 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; G19 ; ; 7B ; VCCIO7B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; G20 ; 416 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; G21 ; 392 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; G22 ; 400 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; G23 ; 377 ; 7A ; ^VCCRSTCLK_HPS ; ; ; ; -- ; ; -- ; -- ; +; G24 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; G25 ; 370 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G26 ; 362 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G27 ; 339 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ; +; G28 ; 335 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G29 ; ; 6A ; VCCIO6A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; G30 ; 343 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; H2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; H3 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; +; H4 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; +; H5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; H6 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; H7 ; 508 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H8 ; 490 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H9 ; ; -- ; VCCBAT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; H10 ; ; -- ; VCC_AUX ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; H11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; H12 ; 500 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H13 ; 498 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H14 ; 482 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H15 ; 458 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H16 ; ; 7D ; VCCIO7D_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; H17 ; 434 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H18 ; 422 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H19 ; 406 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H20 ; 398 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H21 ; ; 7A ; VCCIO7A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; H22 ; 379 ; 7A ; ^HPS_TCK ; ; ; ; -- ; ; -- ; -- ; +; H23 ; 390 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H24 ; 364 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H25 ; 368 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H26 ; ; 6A ; VCCIO6A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; H27 ; 360 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H28 ; 333 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H29 ; 331 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H30 ; 337 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J5 ; 545 ; 9A ; ^nCONFIG ; ; ; ; -- ; ; -- ; -- ; +; J6 ; 547 ; 9A ; ^GND ; ; ; ; -- ; ; -- ; -- ; +; J7 ; 506 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; J8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J9 ; 532 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; J10 ; 530 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; J11 ; ; -- ; VCCPGM ; power ; ; 1.8V/2.5V/3.0V/3.3V ; -- ; ; -- ; -- ; +; J12 ; 516 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; J13 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; J14 ; 476 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; J15 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; +; J16 ; ; -- ; VCC_AUX ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; J17 ; ; 7C ; VCCPD7C_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; J18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J19 ; 408 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; J20 ; ; -- ; VCCRSTCLK_HPS ; power ; ; 1.8V/2.5V/3.0V/3.3V ; -- ; ; -- ; -- ; +; J21 ; ; -- ; VCC_AUX_SHARED ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; J22 ; 372 ; 7A ; ^GND ; ; ; ; -- ; ; -- ; -- ; +; J23 ; 354 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J24 ; 352 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J25 ; 344 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J26 ; 323 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J27 ; 346 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J28 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J29 ; 327 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J30 ; 329 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K3 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; +; K4 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; +; K5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K6 ; 540 ; 9A ; ^MSEL1 ; ; ; ; -- ; ; -- ; -- ; +; K7 ; 522 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; K8 ; 524 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; K9 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; K10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K11 ; ; 8A ; VCCPD8A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; K12 ; 514 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; K13 ; ; 8A ; VCCPD8A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; K14 ; 474 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; K15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K16 ; ; 7D ; VCCPD7D_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; K17 ; 414 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; K18 ; ; 7B ; VCCPD7B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; K19 ; ; 7A ; VCCPD7A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; K20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K21 ; 366 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K22 ; 336 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K23 ; 338 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K24 ; ; 6A ; VCCIO6A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; K25 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K26 ; 322 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K27 ; 319 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K28 ; 325 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K29 ; 321 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K30 ; ; 6A ; VCCIO6A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; L1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L5 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; L6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L7 ; 544 ; 9A ; ^MSEL3 ; ; ; ; -- ; ; -- ; -- ; +; L8 ; 538 ; 9A ; ^MSEL0 ; ; ; ; -- ; ; -- ; -- ; +; L9 ; 546 ; 9A ; ^MSEL4 ; ; ; ; -- ; ; -- ; -- ; +; L10 ; ; 8A ; VCCPD8A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; L11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L12 ; ; 8A ; VCCPD8A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; L13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L14 ; ; 8A ; VCCPD8A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; L15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L16 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; L17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L18 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; L19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L20 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; L21 ; ; -- ; VCCPLL_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; L22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L23 ; 350 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L24 ; 328 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L25 ; 330 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L26 ; 320 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L27 ; ; 6A ; VCCIO6A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; L28 ; 313 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L29 ; 315 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L30 ; 317 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M3 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; +; M4 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; +; M5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M6 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; M7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M9 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; M10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M11 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; M12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M13 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; M14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M15 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; M16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M17 ; 450 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; M18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M19 ; 334 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M21 ; ; 6A, 6B ; VCCPD6A6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; M22 ; 308 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M23 ; 348 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M24 ; ; 6A ; VCCIO6A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; M25 ; 324 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M26 ; 314 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M27 ; 312 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M28 ; 309 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M29 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M30 ; 311 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N5 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; N6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N7 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; N8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N10 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; N11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N12 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; N13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N14 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; N15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N16 ; 452 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; N17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N18 ; 332 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N20 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; N21 ; ; 6A ; VCCIO6A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; N22 ; ; 6A, 6B ; VCCPD6A6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; N23 ; 310 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N24 ; 318 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N25 ; 316 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N26 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N27 ; 297 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N28 ; 303 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N29 ; 305 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N30 ; 307 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P3 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; +; P4 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; +; P5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P6 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; P7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P11 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; P12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P13 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; P14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P15 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; P16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P17 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; P18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P19 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; P20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P21 ; ; 6A, 6B ; VCCPD6A6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; P22 ; 294 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P23 ; ; 6B ; VCCIO6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; P24 ; 290 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P25 ; 288 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P26 ; 298 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P27 ; 296 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P28 ; ; 6B ; VCCIO6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; P29 ; 299 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P30 ; 301 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; R2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; R3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; R4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; R5 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; R6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; R7 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; R8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; R9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; R10 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; R11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; R12 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; R13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; R14 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; R15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; R16 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; R17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; R18 ; 302 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R19 ; 300 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R20 ; ; 6A, 6B ; VCCPD6A6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; R21 ; 286 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R22 ; 284 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R23 ; ; 6A, 6B ; VCCPD6A6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; R24 ; 272 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R25 ; ; 6B ; VCCIO6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; R26 ; 280 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R27 ; 282 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R28 ; 293 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R29 ; 295 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R30 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T3 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; +; T4 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; +; T5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T6 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; T7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T11 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; T12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T13 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; T14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T17 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; T18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T19 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; T20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T21 ; 278 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T22 ; ; 6B ; VCCIO6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; T23 ; 270 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T24 ; 268 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T25 ; 266 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T26 ; 304 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T28 ; 287 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T29 ; 289 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T30 ; 291 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; U2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; U3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; U4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; U5 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; U6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; U7 ; 50 ; 3A ; ^DCLK ; ; ; ; Weak Pull Up ; ; -- ; On ; +; U8 ; 48 ; 3A ; #TDI ; input ; ; ; -- ; ; -- ; -- ; +; U9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; U10 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; U11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; U12 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; U13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; U14 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; U15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; U16 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; U17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; U18 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; U19 ; ; 6B ; VCCIO6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; U20 ; 276 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U21 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; U22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; U23 ; ; 5B ; VCCPD5B ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; U24 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; U25 ; 264 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U26 ; 306 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U27 ; 273 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U28 ; 285 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U29 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; U30 ; 283 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ; +; V1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; V2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; V3 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; +; V4 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; +; V5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; V6 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; V7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; V8 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; V9 ; 44 ; 3A ; #TMS ; input ; ; ; -- ; ; -- ; -- ; +; V10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; V11 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; V12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; V13 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; V14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; V15 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; V16 ; 138 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V17 ; 154 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V18 ; 194 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; V20 ; 292 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; V22 ; ; 5A ; VCCPD5A ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; V23 ; 236 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V24 ; ; 5A ; VCCPD5A ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; V25 ; 246 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V26 ; ; 6B ; VCCIO6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; V27 ; 265 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V28 ; 271 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V29 ; 275 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V30 ; 281 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; W1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; W2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; W3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; W4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; W5 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; W6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; W7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; W8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; W9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; W10 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; W11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; W12 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; W13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; W14 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; W15 ; 130 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W16 ; 136 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W17 ; 152 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; W19 ; 192 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W20 ; 217 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; W21 ; 221 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; W22 ; 223 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; W23 ; ; 5A ; VCCIO5A ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; W24 ; 238 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; W25 ; 244 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; W26 ; 274 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; W27 ; 261 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; W28 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; W29 ; 279 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; W30 ; 277 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; Y1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y3 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; +; Y4 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; +; Y5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y6 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; Y7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y9 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; Y10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y11 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; Y12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y13 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; Y14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y16 ; 128 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y17 ; 170 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y18 ; 178 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y19 ; 202 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y21 ; 219 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; Y22 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; Y23 ; 232 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; Y24 ; 234 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; Y25 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y26 ; 256 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; Y27 ; 258 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; Y28 ; 269 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; Y29 ; 263 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; Y30 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ++----------+------------+----------------+---------------------------------+--------+--------------+---------------------+--------------+-----------------+----------+--------------+ +Note: Pin directions (input, output or bidir) are based on device operating in user mode. + + ++-------------------------------------------------+ +; I/O Assignment Warnings ; ++----------+--------------------------------------+ +; Pin Name ; Reason ; ++----------+--------------------------------------+ +; HEX0[0] ; Missing drive strength and slew rate ; +; HEX0[1] ; Missing drive strength and slew rate ; +; HEX0[2] ; Missing drive strength and slew rate ; +; HEX0[3] ; Missing drive strength and slew rate ; +; HEX0[4] ; Missing drive strength and slew rate ; +; HEX0[5] ; Missing drive strength and slew rate ; +; HEX0[6] ; Missing drive strength and slew rate ; +; HEX1[0] ; Missing drive strength and slew rate ; +; HEX1[1] ; Missing drive strength and slew rate ; +; HEX1[2] ; Missing drive strength and slew rate ; +; HEX1[3] ; Missing drive strength and slew rate ; +; HEX1[4] ; Missing drive strength and slew rate ; +; HEX1[5] ; Missing drive strength and slew rate ; +; HEX1[6] ; Missing drive strength and slew rate ; +; HEX2[0] ; Missing drive strength and slew rate ; +; HEX2[1] ; Missing drive strength and slew rate ; +; HEX2[2] ; Missing drive strength and slew rate ; +; HEX2[3] ; Missing drive strength and slew rate ; +; HEX2[4] ; Missing drive strength and slew rate ; +; HEX2[5] ; Missing drive strength and slew rate ; +; HEX2[6] ; Missing drive strength and slew rate ; +; DAC_SDI ; Missing drive strength and slew rate ; +; DAC_SCK ; Missing drive strength and slew rate ; +; DAC_CS ; Missing drive strength and slew rate ; +; DAC_LD ; Missing drive strength and slew rate ; +; ADC_SDI ; Missing drive strength and slew rate ; +; ADC_SCK ; Missing drive strength and slew rate ; +; ADC_CS ; Missing drive strength and slew rate ; +; PWM_OUT ; Missing drive strength and slew rate ; ++----------+--------------------------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fitter Resource Utilization by Entity ; ++------------------------------------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------+--------------+ +; Compilation Hierarchy Node ; ALMs needed [=A-B+C] ; [A] ALMs used in final placement ; [B] Estimate of ALMs recoverable by dense packing ; [C] Estimate of ALMs unavailable ; ALMs used for memory ; Combinational ALUTs ; Dedicated Logic Registers ; I/O Registers ; Block Memory Bits ; M10Ks ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name ; Entity Name ; Library Name ; ++------------------------------------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------+--------------+ +; |ex19_top ; 118.5 (0.5) ; 132.5 (0.5) ; 14.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 214 (1) ; 139 (0) ; 0 (0) ; 73728 ; 9 ; 0 ; 41 ; 0 ; |ex19_top ; ex19_top ; work ; +; |clktick_16:GEN_10K| ; 11.5 (11.5) ; 12.0 (12.0) ; 0.5 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 20 (20) ; 17 (17) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex19_top|clktick_16:GEN_10K ; clktick_16 ; work ; +; |processor:ALLPASS| ; 69.5 (10.0) ; 73.3 (13.3) ; 3.9 (3.4) ; 0.0 (0.0) ; 0.0 (0.0) ; 136 (23) ; 31 (13) ; 0 (0) ; 73728 ; 9 ; 0 ; 0 ; 0 ; |ex19_top|processor:ALLPASS ; processor ; work ; +; |RAM:DELAY1024| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 73728 ; 9 ; 0 ; 0 ; 0 ; |ex19_top|processor:ALLPASS|RAM:DELAY1024 ; RAM ; work ; +; |altsyncram:altsyncram_component| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 73728 ; 9 ; 0 ; 0 ; 0 ; |ex19_top|processor:ALLPASS|RAM:DELAY1024|altsyncram:altsyncram_component ; altsyncram ; work ; +; |altsyncram_ip02:auto_generated| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 73728 ; 9 ; 0 ; 0 ; 0 ; |ex19_top|processor:ALLPASS|RAM:DELAY1024|altsyncram:altsyncram_component|altsyncram_ip02:auto_generated ; altsyncram_ip02 ; work ; +; |bin2bcd_16:BIN0| ; 21.0 (0.0) ; 21.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 38 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex19_top|processor:ALLPASS|bin2bcd_16:BIN0 ; bin2bcd_16 ; work ; +; |add3_ge5:A12| ; 0.5 (0.5) ; 0.5 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex19_top|processor:ALLPASS|bin2bcd_16:BIN0|add3_ge5:A12 ; add3_ge5 ; work ; +; |add3_ge5:A15| ; 2.0 (2.0) ; 2.0 (2.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex19_top|processor:ALLPASS|bin2bcd_16:BIN0|add3_ge5:A15 ; add3_ge5 ; work ; +; |add3_ge5:A18| ; 2.0 (2.0) ; 2.0 (2.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex19_top|processor:ALLPASS|bin2bcd_16:BIN0|add3_ge5:A18 ; add3_ge5 ; work ; +; |add3_ge5:A21| ; 0.5 (0.5) ; 0.5 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex19_top|processor:ALLPASS|bin2bcd_16:BIN0|add3_ge5:A21 ; add3_ge5 ; work ; +; |add3_ge5:A22| ; 2.0 (2.0) ; 2.0 (2.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex19_top|processor:ALLPASS|bin2bcd_16:BIN0|add3_ge5:A22 ; add3_ge5 ; work ; +; |add3_ge5:A25| ; 4.0 (4.0) ; 4.0 (4.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex19_top|processor:ALLPASS|bin2bcd_16:BIN0|add3_ge5:A25 ; add3_ge5 ; work ; +; |add3_ge5:A26| ; 2.0 (2.0) ; 2.0 (2.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex19_top|processor:ALLPASS|bin2bcd_16:BIN0|add3_ge5:A26 ; add3_ge5 ; work ; +; |add3_ge5:A29| ; 2.0 (2.0) ; 2.0 (2.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex19_top|processor:ALLPASS|bin2bcd_16:BIN0|add3_ge5:A29 ; add3_ge5 ; work ; +; |add3_ge5:A30| ; 2.0 (2.0) ; 2.0 (2.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex19_top|processor:ALLPASS|bin2bcd_16:BIN0|add3_ge5:A30 ; add3_ge5 ; work ; +; |add3_ge5:A34| ; 2.0 (2.0) ; 2.0 (2.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex19_top|processor:ALLPASS|bin2bcd_16:BIN0|add3_ge5:A34 ; add3_ge5 ; work ; +; |add3_ge5:A35| ; 2.0 (2.0) ; 2.0 (2.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex19_top|processor:ALLPASS|bin2bcd_16:BIN0|add3_ge5:A35 ; add3_ge5 ; work ; +; |counter_13:COUNT13| ; 6.5 (6.5) ; 7.0 (7.0) ; 0.5 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 13 (13) ; 16 (16) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex19_top|processor:ALLPASS|counter_13:COUNT13 ; counter_13 ; work ; +; |hex_to_7seg:SEG0| ; 3.5 (3.5) ; 3.5 (3.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 7 (7) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex19_top|processor:ALLPASS|hex_to_7seg:SEG0 ; hex_to_7seg ; work ; +; |hex_to_7seg:SEG1| ; 3.5 (3.5) ; 3.5 (3.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 7 (7) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex19_top|processor:ALLPASS|hex_to_7seg:SEG1 ; hex_to_7seg ; work ; +; |hex_to_7seg:SEG2| ; 7.5 (7.5) ; 7.5 (7.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 13 (13) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex19_top|processor:ALLPASS|hex_to_7seg:SEG2 ; hex_to_7seg ; work ; +; |multiply_k:MULTK| ; 16.5 (0.0) ; 16.5 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 33 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex19_top|processor:ALLPASS|multiply_k:MULTK ; multiply_k ; work ; +; |lpm_mult:lpm_mult_component| ; 16.5 (0.0) ; 16.5 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 33 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex19_top|processor:ALLPASS|multiply_k:MULTK|lpm_mult:lpm_mult_component ; lpm_mult ; work ; +; |multcore:mult_core| ; 16.5 (3.5) ; 16.5 (3.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 33 (7) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex19_top|processor:ALLPASS|multiply_k:MULTK|lpm_mult:lpm_mult_component|multcore:mult_core ; multcore ; work ; +; |mpar_add:padder| ; 13.0 (0.0) ; 13.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 26 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex19_top|processor:ALLPASS|multiply_k:MULTK|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder ; mpar_add ; work ; +; |lpm_add_sub:adder[0]| ; 7.5 (0.0) ; 7.5 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 15 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex19_top|processor:ALLPASS|multiply_k:MULTK|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0] ; lpm_add_sub ; work ; +; |add_sub_a9h:auto_generated| ; 7.5 (7.5) ; 7.5 (7.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 15 (15) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex19_top|processor:ALLPASS|multiply_k:MULTK|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_a9h:auto_generated ; add_sub_a9h ; work ; +; |mpar_add:sub_par_add| ; 5.5 (0.0) ; 5.5 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 11 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex19_top|processor:ALLPASS|multiply_k:MULTK|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add ; mpar_add ; work ; +; |lpm_add_sub:adder[0]| ; 5.5 (0.0) ; 5.5 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 11 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex19_top|processor:ALLPASS|multiply_k:MULTK|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0] ; lpm_add_sub ; work ; +; |add_sub_e9h:auto_generated| ; 5.5 (5.5) ; 5.5 (5.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 11 (11) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex19_top|processor:ALLPASS|multiply_k:MULTK|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|add_sub_e9h:auto_generated ; add_sub_e9h ; work ; +; |pulse_gen:PULSE0| ; 1.0 (1.0) ; 1.0 (1.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 2 (2) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex19_top|processor:ALLPASS|pulse_gen:PULSE0 ; pulse_gen ; work ; +; |pwm:PWM_DC| ; 9.6 (9.6) ; 10.7 (10.7) ; 1.2 (1.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 16 (16) ; 21 (21) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex19_top|pwm:PWM_DC ; pwm ; work ; +; |spi2adc:SPI_ADC| ; 14.0 (14.0) ; 22.3 (22.3) ; 8.3 (8.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 24 (24) ; 45 (45) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex19_top|spi2adc:SPI_ADC ; spi2adc ; work ; +; |spi2dac:SPI_DAC| ; 13.4 (13.4) ; 13.6 (13.6) ; 0.1 (0.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 25 (25) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex19_top|spi2dac:SPI_DAC ; spi2dac ; work ; ++------------------------------------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------+--------------+ +Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. + + ++-------------------------------------------------------------------------------------------------------------------------+ +; Delay Chain Summary ; ++----------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+ +; Name ; Pin Type ; D1 ; D3_0 ; D3_1 ; D4 ; D5 ; D5 OE ; D5 OCT ; T11 (Postamble Gating) ; T11 (Postamble Ungating) ; ++----------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+ +; SW[9] ; Input ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; +; HEX0[0] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; HEX0[1] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; HEX0[2] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; HEX0[3] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; HEX0[4] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; HEX0[5] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; HEX0[6] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; HEX1[0] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; HEX1[1] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; HEX1[2] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; HEX1[3] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; HEX1[4] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; HEX1[5] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; HEX1[6] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; HEX2[0] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; HEX2[1] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; HEX2[2] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; HEX2[3] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; HEX2[4] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; HEX2[5] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; HEX2[6] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; DAC_SDI ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; DAC_SCK ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; DAC_CS ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; DAC_LD ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; ADC_SDI ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; ADC_SCK ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; ADC_CS ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; PWM_OUT ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; SW[8] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; +; CLOCK_50 ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; +; SW[6] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; +; SW[5] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; +; SW[4] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; +; SW[3] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; +; SW[2] ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; +; SW[1] ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; +; SW[0] ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; +; SW[7] ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; +; ADC_SDO ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; ++----------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Pad To Core Delay Chain Fanout ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+---------+ +; Source Pin / Fanout ; Pad To Core Index ; Setting ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+---------+ +; SW[9] ; ; ; +; SW[8] ; ; ; +; - processor:ALLPASS|multiply_k:MULTK|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|add_sub_e9h:auto_generated|op_1~42 ; 1 ; 0 ; +; - processor:ALLPASS|multiply_k:MULTK|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|add_sub_e9h:auto_generated|op_1~1 ; 1 ; 0 ; +; - processor:ALLPASS|multiply_k:MULTK|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|add_sub_e9h:auto_generated|op_1~13 ; 1 ; 0 ; +; - processor:ALLPASS|multiply_k:MULTK|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|add_sub_e9h:auto_generated|op_1~17 ; 1 ; 0 ; +; - processor:ALLPASS|multiply_k:MULTK|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|add_sub_e9h:auto_generated|op_1~29 ; 1 ; 0 ; +; - processor:ALLPASS|multiply_k:MULTK|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|add_sub_e9h:auto_generated|op_1~33 ; 1 ; 0 ; +; - processor:ALLPASS|Add2~33 ; 1 ; 0 ; +; CLOCK_50 ; ; ; +; - spi2adc:SPI_ADC|adc_cs ; 0 ; 0 ; +; SW[6] ; ; ; +; - processor:ALLPASS|multiply_k:MULTK|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_a9h:auto_generated|op_1~46 ; 1 ; 0 ; +; - processor:ALLPASS|multiply_k:MULTK|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_a9h:auto_generated|op_1~1 ; 1 ; 0 ; +; - processor:ALLPASS|multiply_k:MULTK|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_a9h:auto_generated|op_1~5 ; 1 ; 0 ; +; - processor:ALLPASS|multiply_k:MULTK|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_a9h:auto_generated|op_1~9 ; 1 ; 0 ; +; - processor:ALLPASS|multiply_k:MULTK|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_a9h:auto_generated|op_1~13 ; 1 ; 0 ; +; - processor:ALLPASS|multiply_k:MULTK|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_a9h:auto_generated|op_1~17 ; 1 ; 0 ; +; - processor:ALLPASS|multiply_k:MULTK|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_a9h:auto_generated|op_1~21 ; 1 ; 0 ; +; - processor:ALLPASS|multiply_k:MULTK|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_a9h:auto_generated|op_1~25 ; 1 ; 0 ; +; - processor:ALLPASS|multiply_k:MULTK|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_a9h:auto_generated|op_1~29 ; 1 ; 0 ; +; - processor:ALLPASS|multiply_k:MULTK|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_a9h:auto_generated|op_1~33 ; 1 ; 0 ; +; - processor:ALLPASS|Add2~25 ; 1 ; 0 ; +; - processor:ALLPASS|multiply_k:MULTK|lpm_mult:lpm_mult_component|multcore:mult_core|romout[1][9]~5 ; 1 ; 0 ; +; - processor:ALLPASS|multiply_k:MULTK|lpm_mult:lpm_mult_component|multcore:mult_core|romout[1][4]~6 ; 1 ; 0 ; +; SW[5] ; ; ; +; - processor:ALLPASS|multiply_k:MULTK|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_a9h:auto_generated|op_1~50 ; 1 ; 0 ; +; - processor:ALLPASS|multiply_k:MULTK|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_a9h:auto_generated|op_1~46 ; 1 ; 0 ; +; - processor:ALLPASS|multiply_k:MULTK|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_a9h:auto_generated|op_1~1 ; 1 ; 0 ; +; - processor:ALLPASS|multiply_k:MULTK|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_a9h:auto_generated|op_1~5 ; 1 ; 0 ; +; - processor:ALLPASS|multiply_k:MULTK|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_a9h:auto_generated|op_1~9 ; 1 ; 0 ; +; - processor:ALLPASS|multiply_k:MULTK|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_a9h:auto_generated|op_1~13 ; 1 ; 0 ; +; - processor:ALLPASS|multiply_k:MULTK|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_a9h:auto_generated|op_1~17 ; 1 ; 0 ; +; - processor:ALLPASS|multiply_k:MULTK|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_a9h:auto_generated|op_1~21 ; 1 ; 0 ; +; - processor:ALLPASS|multiply_k:MULTK|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_a9h:auto_generated|op_1~25 ; 1 ; 0 ; +; - processor:ALLPASS|multiply_k:MULTK|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_a9h:auto_generated|op_1~29 ; 1 ; 0 ; +; - processor:ALLPASS|multiply_k:MULTK|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_a9h:auto_generated|op_1~33 ; 1 ; 0 ; +; - processor:ALLPASS|Add2~21 ; 1 ; 0 ; +; - processor:ALLPASS|multiply_k:MULTK|lpm_mult:lpm_mult_component|multcore:mult_core|romout[1][9]~5 ; 1 ; 0 ; +; - processor:ALLPASS|multiply_k:MULTK|lpm_mult:lpm_mult_component|multcore:mult_core|romout[1][4]~6 ; 1 ; 0 ; +; SW[4] ; ; ; +; - processor:ALLPASS|multiply_k:MULTK|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_a9h:auto_generated|op_1~54 ; 1 ; 0 ; +; - processor:ALLPASS|multiply_k:MULTK|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_a9h:auto_generated|op_1~50 ; 1 ; 0 ; +; - processor:ALLPASS|multiply_k:MULTK|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_a9h:auto_generated|op_1~46 ; 1 ; 0 ; +; - processor:ALLPASS|multiply_k:MULTK|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_a9h:auto_generated|op_1~1 ; 1 ; 0 ; +; - processor:ALLPASS|multiply_k:MULTK|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_a9h:auto_generated|op_1~5 ; 1 ; 0 ; +; - processor:ALLPASS|multiply_k:MULTK|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_a9h:auto_generated|op_1~9 ; 1 ; 0 ; +; - processor:ALLPASS|multiply_k:MULTK|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_a9h:auto_generated|op_1~13 ; 1 ; 0 ; +; - processor:ALLPASS|multiply_k:MULTK|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_a9h:auto_generated|op_1~17 ; 1 ; 0 ; +; - processor:ALLPASS|multiply_k:MULTK|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_a9h:auto_generated|op_1~21 ; 1 ; 0 ; +; - processor:ALLPASS|multiply_k:MULTK|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_a9h:auto_generated|op_1~25 ; 1 ; 0 ; +; - processor:ALLPASS|multiply_k:MULTK|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_a9h:auto_generated|op_1~29 ; 1 ; 0 ; +; - processor:ALLPASS|multiply_k:MULTK|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_a9h:auto_generated|op_1~33 ; 1 ; 0 ; +; - processor:ALLPASS|Add2~17 ; 1 ; 0 ; +; - processor:ALLPASS|multiply_k:MULTK|lpm_mult:lpm_mult_component|multcore:mult_core|romout[1][9]~5 ; 1 ; 0 ; +; - processor:ALLPASS|multiply_k:MULTK|lpm_mult:lpm_mult_component|multcore:mult_core|romout[1][4]~6 ; 1 ; 0 ; +; SW[3] ; ; ; +; - processor:ALLPASS|multiply_k:MULTK|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_a9h:auto_generated|op_1~54 ; 1 ; 0 ; +; - processor:ALLPASS|multiply_k:MULTK|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_a9h:auto_generated|op_1~42 ; 1 ; 0 ; +; - processor:ALLPASS|multiply_k:MULTK|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_a9h:auto_generated|op_1~37 ; 1 ; 0 ; +; - processor:ALLPASS|Add2~13 ; 1 ; 0 ; +; - processor:ALLPASS|multiply_k:MULTK|lpm_mult:lpm_mult_component|multcore:mult_core|romout[0][10]~0 ; 1 ; 0 ; +; - processor:ALLPASS|multiply_k:MULTK|lpm_mult:lpm_mult_component|multcore:mult_core|romout[0][11]~1 ; 1 ; 0 ; +; - processor:ALLPASS|multiply_k:MULTK|lpm_mult:lpm_mult_component|multcore:mult_core|romout[0][12]~2 ; 1 ; 0 ; +; - processor:ALLPASS|multiply_k:MULTK|lpm_mult:lpm_mult_component|multcore:mult_core|romout[0][13]~3 ; 1 ; 0 ; +; - processor:ALLPASS|multiply_k:MULTK|lpm_mult:lpm_mult_component|multcore:mult_core|romout[0][14]~4 ; 1 ; 0 ; +; SW[2] ; ; ; +; - processor:ALLPASS|multiply_k:MULTK|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_a9h:auto_generated|op_1~54 ; 0 ; 0 ; +; - processor:ALLPASS|multiply_k:MULTK|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_a9h:auto_generated|op_1~42 ; 0 ; 0 ; +; - processor:ALLPASS|multiply_k:MULTK|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_a9h:auto_generated|op_1~37 ; 0 ; 0 ; +; - processor:ALLPASS|Add2~9 ; 0 ; 0 ; +; - processor:ALLPASS|multiply_k:MULTK|lpm_mult:lpm_mult_component|multcore:mult_core|romout[0][10]~0 ; 0 ; 0 ; +; - processor:ALLPASS|multiply_k:MULTK|lpm_mult:lpm_mult_component|multcore:mult_core|romout[0][11]~1 ; 0 ; 0 ; +; - processor:ALLPASS|multiply_k:MULTK|lpm_mult:lpm_mult_component|multcore:mult_core|romout[0][12]~2 ; 0 ; 0 ; +; - processor:ALLPASS|multiply_k:MULTK|lpm_mult:lpm_mult_component|multcore:mult_core|romout[0][13]~3 ; 0 ; 0 ; +; - processor:ALLPASS|multiply_k:MULTK|lpm_mult:lpm_mult_component|multcore:mult_core|romout[0][14]~4 ; 0 ; 0 ; +; SW[1] ; ; ; +; - processor:ALLPASS|multiply_k:MULTK|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_a9h:auto_generated|op_1~54 ; 0 ; 0 ; +; - processor:ALLPASS|multiply_k:MULTK|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_a9h:auto_generated|op_1~42 ; 0 ; 0 ; +; - processor:ALLPASS|multiply_k:MULTK|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_a9h:auto_generated|op_1~37 ; 0 ; 0 ; +; - processor:ALLPASS|Add2~5 ; 0 ; 0 ; +; - processor:ALLPASS|multiply_k:MULTK|lpm_mult:lpm_mult_component|multcore:mult_core|romout[0][10]~0 ; 0 ; 0 ; +; - processor:ALLPASS|multiply_k:MULTK|lpm_mult:lpm_mult_component|multcore:mult_core|romout[0][11]~1 ; 0 ; 0 ; +; - processor:ALLPASS|multiply_k:MULTK|lpm_mult:lpm_mult_component|multcore:mult_core|romout[0][12]~2 ; 0 ; 0 ; +; - processor:ALLPASS|multiply_k:MULTK|lpm_mult:lpm_mult_component|multcore:mult_core|romout[0][13]~3 ; 0 ; 0 ; +; - processor:ALLPASS|multiply_k:MULTK|lpm_mult:lpm_mult_component|multcore:mult_core|romout[0][14]~4 ; 0 ; 0 ; +; SW[0] ; ; ; +; - processor:ALLPASS|multiply_k:MULTK|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_a9h:auto_generated|op_1~54 ; 0 ; 0 ; +; - processor:ALLPASS|multiply_k:MULTK|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_a9h:auto_generated|op_1~42 ; 0 ; 0 ; +; - processor:ALLPASS|multiply_k:MULTK|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_a9h:auto_generated|op_1~37 ; 0 ; 0 ; +; - processor:ALLPASS|Add2~1 ; 0 ; 0 ; +; - processor:ALLPASS|multiply_k:MULTK|lpm_mult:lpm_mult_component|multcore:mult_core|romout[0][10]~0 ; 0 ; 0 ; +; - processor:ALLPASS|multiply_k:MULTK|lpm_mult:lpm_mult_component|multcore:mult_core|romout[0][11]~1 ; 0 ; 0 ; +; - processor:ALLPASS|multiply_k:MULTK|lpm_mult:lpm_mult_component|multcore:mult_core|romout[0][12]~2 ; 0 ; 0 ; +; - processor:ALLPASS|multiply_k:MULTK|lpm_mult:lpm_mult_component|multcore:mult_core|romout[0][13]~3 ; 0 ; 0 ; +; - processor:ALLPASS|multiply_k:MULTK|lpm_mult:lpm_mult_component|multcore:mult_core|romout[0][14]~4 ; 0 ; 0 ; +; SW[7] ; ; ; +; - processor:ALLPASS|multiply_k:MULTK|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_a9h:auto_generated|op_1~1 ; 0 ; 0 ; +; - processor:ALLPASS|multiply_k:MULTK|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_a9h:auto_generated|op_1~5 ; 0 ; 0 ; +; - processor:ALLPASS|multiply_k:MULTK|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_a9h:auto_generated|op_1~9 ; 0 ; 0 ; +; - processor:ALLPASS|multiply_k:MULTK|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_a9h:auto_generated|op_1~13 ; 0 ; 0 ; +; - processor:ALLPASS|multiply_k:MULTK|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_a9h:auto_generated|op_1~17 ; 0 ; 0 ; +; - processor:ALLPASS|multiply_k:MULTK|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_a9h:auto_generated|op_1~21 ; 0 ; 0 ; +; - processor:ALLPASS|multiply_k:MULTK|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_a9h:auto_generated|op_1~25 ; 0 ; 0 ; +; - processor:ALLPASS|multiply_k:MULTK|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_a9h:auto_generated|op_1~29 ; 0 ; 0 ; +; - processor:ALLPASS|multiply_k:MULTK|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_a9h:auto_generated|op_1~33 ; 0 ; 0 ; +; - processor:ALLPASS|Add2~29 ; 0 ; 0 ; +; - processor:ALLPASS|multiply_k:MULTK|lpm_mult:lpm_mult_component|multcore:mult_core|romout[1][9]~5 ; 0 ; 0 ; +; - processor:ALLPASS|multiply_k:MULTK|lpm_mult:lpm_mult_component|multcore:mult_core|romout[1][4]~6 ; 0 ; 0 ; +; ADC_SDO ; ; ; +; - spi2adc:SPI_ADC|shift_reg[0]~feeder ; 1 ; 0 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+---------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Control Signals ; ++------------------------------------------+--------------------+---------+----------------------------+--------+----------------------+------------------+---------------------------+ +; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ; ++------------------------------------------+--------------------+---------+----------------------------+--------+----------------------+------------------+---------------------------+ +; CLOCK_50 ; PIN_AF14 ; 2 ; Clock ; no ; -- ; -- ; -- ; +; CLOCK_50 ; PIN_AF14 ; 131 ; Clock ; yes ; Global Clock ; GCLK6 ; -- ; +; clktick_16:GEN_10K|Equal0~3 ; LABCELL_X51_Y2_N15 ; 10 ; Sync. clear ; no ; -- ; -- ; -- ; +; clktick_16:GEN_10K|tick ; FF_X51_Y2_N32 ; 15 ; Clock enable ; no ; -- ; -- ; -- ; +; processor:ALLPASS|pulse_gen:PULSE0|pulse ; FF_X51_Y1_N49 ; 9 ; Clock enable, Write enable ; no ; -- ; -- ; -- ; +; spi2adc:SPI_ADC|adc_cs ; FF_X50_Y1_N32 ; 25 ; Clock ; no ; -- ; -- ; -- ; +; spi2adc:SPI_ADC|adc_done ; FF_X53_Y1_N22 ; 10 ; Clock enable ; no ; -- ; -- ; -- ; +; spi2adc:SPI_ADC|always3~0 ; LABCELL_X53_Y1_N54 ; 10 ; Clock enable ; no ; -- ; -- ; -- ; +; spi2adc:SPI_ADC|tick ; FF_X56_Y1_N29 ; 39 ; Clock enable ; no ; -- ; -- ; -- ; +; spi2dac:SPI_DAC|always5~0 ; LABCELL_X50_Y1_N33 ; 9 ; Sync. load ; no ; -- ; -- ; -- ; ++------------------------------------------+--------------------+---------+----------------------------+--------+----------------------+------------------+---------------------------+ + + ++-----------------------------------------------------------------------------------------------------+ +; Global & Other Fast Signals ; ++----------+----------+---------+----------------------+------------------+---------------------------+ +; Name ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ; ++----------+----------+---------+----------------------+------------------+---------------------------+ +; CLOCK_50 ; PIN_AF14 ; 131 ; Global Clock ; GCLK6 ; -- ; ++----------+----------+---------+----------------------+------------------+---------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fitter RAM Summary ; ++-----------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+-------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+-------------+------------+------+------------------------------------------------------------------------------------------------------------------------------------------------+----------------------+-----------------+-----------------+----------+------------------------+-----------------------+ +; Name ; Type ; Mode ; Clock Mode ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Port A Input Registers ; Port A Output Registers ; Port B Input Registers ; Port B Output Registers ; Size ; Implementation Port A Depth ; Implementation Port A Width ; Implementation Port B Depth ; Implementation Port B Width ; Implementation Bits ; M10K blocks ; MLAB cells ; MIF ; Location ; Mixed Width RDW Mode ; Port A RDW Mode ; Port B RDW Mode ; ECC Mode ; ECC Pipeline Registers ; Fits in MLABs ; ++-----------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+-------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+-------------+------------+------+------------------------------------------------------------------------------------------------------------------------------------------------+----------------------+-----------------+-----------------+----------+------------------------+-----------------------+ +; processor:ALLPASS|RAM:DELAY1024|altsyncram:altsyncram_component|altsyncram_ip02:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Single Clock ; 8192 ; 9 ; 8192 ; 9 ; yes ; no ; yes ; yes ; 73728 ; 8192 ; 9 ; 8192 ; 9 ; 73728 ; 9 ; 0 ; None ; M10K_X49_Y3_N0, M10K_X58_Y4_N0, M10K_X58_Y3_N0, M10K_X58_Y1_N0, M10K_X49_Y1_N0, M10K_X58_Y2_N0, M10K_X49_Y4_N0, M10K_X49_Y2_N0, M10K_X49_Y5_N0 ; Don't care ; New data ; New data ; Off ; No ; No - Address Too Wide ; ++-----------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+-------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+-------------+------------+------+------------------------------------------------------------------------------------------------------------------------------------------------+----------------------+-----------------+-----------------+----------+------------------------+-----------------------+ +Note: Fitter may spread logical memories into multiple blocks to improve timing. The actual required RAM blocks can be found in the Fitter Resource Usage section. + + ++-----------------------------------------------------------------------+ +; Routing Usage Summary ; ++---------------------------------------------+-------------------------+ +; Routing Resource Type ; Usage ; ++---------------------------------------------+-------------------------+ +; Block interconnects ; 470 / 289,320 ( < 1 % ) ; +; C12 interconnects ; 11 / 13,420 ( < 1 % ) ; +; C2 interconnects ; 112 / 119,108 ( < 1 % ) ; +; C4 interconnects ; 79 / 56,300 ( < 1 % ) ; +; DQS bus muxes ; 0 / 25 ( 0 % ) ; +; DQS-18 I/O buses ; 0 / 25 ( 0 % ) ; +; DQS-9 I/O buses ; 0 / 25 ( 0 % ) ; +; Direct links ; 41 / 289,320 ( < 1 % ) ; +; Global clocks ; 1 / 16 ( 6 % ) ; +; HPS SDRAM PLL inputs ; 0 / 1 ( 0 % ) ; +; HPS SDRAM PLL outputs ; 0 / 1 ( 0 % ) ; +; HPS_INTERFACE_BOOT_FROM_FPGA_INPUTs ; 0 / 9 ( 0 % ) ; +; HPS_INTERFACE_CLOCKS_RESETS_INPUTs ; 0 / 7 ( 0 % ) ; +; HPS_INTERFACE_CLOCKS_RESETS_OUTPUTs ; 0 / 6 ( 0 % ) ; +; HPS_INTERFACE_CROSS_TRIGGER_INPUTs ; 0 / 18 ( 0 % ) ; +; HPS_INTERFACE_CROSS_TRIGGER_OUTPUTs ; 0 / 24 ( 0 % ) ; +; HPS_INTERFACE_DBG_APB_INPUTs ; 0 / 37 ( 0 % ) ; +; HPS_INTERFACE_DBG_APB_OUTPUTs ; 0 / 55 ( 0 % ) ; +; HPS_INTERFACE_DMA_INPUTs ; 0 / 16 ( 0 % ) ; +; HPS_INTERFACE_DMA_OUTPUTs ; 0 / 8 ( 0 % ) ; +; HPS_INTERFACE_FPGA2HPS_INPUTs ; 0 / 287 ( 0 % ) ; +; HPS_INTERFACE_FPGA2HPS_OUTPUTs ; 0 / 154 ( 0 % ) ; +; HPS_INTERFACE_FPGA2SDRAM_INPUTs ; 0 / 852 ( 0 % ) ; +; HPS_INTERFACE_FPGA2SDRAM_OUTPUTs ; 0 / 408 ( 0 % ) ; +; HPS_INTERFACE_HPS2FPGA_INPUTs ; 0 / 165 ( 0 % ) ; +; HPS_INTERFACE_HPS2FPGA_LIGHT_WEIGHT_INPUTs ; 0 / 67 ( 0 % ) ; +; HPS_INTERFACE_HPS2FPGA_LIGHT_WEIGHT_OUTPUTs ; 0 / 156 ( 0 % ) ; +; HPS_INTERFACE_HPS2FPGA_OUTPUTs ; 0 / 282 ( 0 % ) ; +; HPS_INTERFACE_INTERRUPTS_INPUTs ; 0 / 64 ( 0 % ) ; +; HPS_INTERFACE_INTERRUPTS_OUTPUTs ; 0 / 42 ( 0 % ) ; +; HPS_INTERFACE_JTAG_OUTPUTs ; 0 / 5 ( 0 % ) ; +; HPS_INTERFACE_LOAN_IO_INPUTs ; 0 / 142 ( 0 % ) ; +; HPS_INTERFACE_LOAN_IO_OUTPUTs ; 0 / 85 ( 0 % ) ; +; HPS_INTERFACE_MPU_EVENT_STANDBY_INPUTs ; 0 / 1 ( 0 % ) ; +; HPS_INTERFACE_MPU_EVENT_STANDBY_OUTPUTs ; 0 / 5 ( 0 % ) ; +; HPS_INTERFACE_MPU_GENERAL_PURPOSE_INPUTs ; 0 / 32 ( 0 % ) ; +; HPS_INTERFACE_MPU_GENERAL_PURPOSE_OUTPUTs ; 0 / 32 ( 0 % ) ; +; HPS_INTERFACE_PERIPHERAL_CAN_INPUTs ; 0 / 2 ( 0 % ) ; +; HPS_INTERFACE_PERIPHERAL_CAN_OUTPUTs ; 0 / 2 ( 0 % ) ; +; HPS_INTERFACE_PERIPHERAL_EMAC_INPUTs ; 0 / 32 ( 0 % ) ; +; HPS_INTERFACE_PERIPHERAL_EMAC_OUTPUTs ; 0 / 34 ( 0 % ) ; +; HPS_INTERFACE_PERIPHERAL_I2C_INPUTs ; 0 / 8 ( 0 % ) ; +; HPS_INTERFACE_PERIPHERAL_I2C_OUTPUTs ; 0 / 8 ( 0 % ) ; +; HPS_INTERFACE_PERIPHERAL_NAND_INPUTs ; 0 / 12 ( 0 % ) ; +; HPS_INTERFACE_PERIPHERAL_NAND_OUTPUTs ; 0 / 18 ( 0 % ) ; +; HPS_INTERFACE_PERIPHERAL_QSPI_INPUTs ; 0 / 4 ( 0 % ) ; +; HPS_INTERFACE_PERIPHERAL_QSPI_OUTPUTs ; 0 / 13 ( 0 % ) ; +; HPS_INTERFACE_PERIPHERAL_SDMMC_INPUTs ; 0 / 13 ( 0 % ) ; +; HPS_INTERFACE_PERIPHERAL_SDMMC_OUTPUTs ; 0 / 22 ( 0 % ) ; +; HPS_INTERFACE_PERIPHERAL_SPI_MASTER_INPUTs ; 0 / 4 ( 0 % ) ; +; HPS_INTERFACE_PERIPHERAL_SPI_MASTER_OUTPUTs ; 0 / 14 ( 0 % ) ; +; HPS_INTERFACE_PERIPHERAL_SPI_SLAVE_INPUTs ; 0 / 6 ( 0 % ) ; +; HPS_INTERFACE_PERIPHERAL_SPI_SLAVE_OUTPUTs ; 0 / 4 ( 0 % ) ; +; HPS_INTERFACE_PERIPHERAL_UART_INPUTs ; 0 / 10 ( 0 % ) ; +; HPS_INTERFACE_PERIPHERAL_UART_OUTPUTs ; 0 / 10 ( 0 % ) ; +; HPS_INTERFACE_PERIPHERAL_USB_INPUTs ; 0 / 22 ( 0 % ) ; +; HPS_INTERFACE_PERIPHERAL_USB_OUTPUTs ; 0 / 34 ( 0 % ) ; +; HPS_INTERFACE_STM_EVENT_INPUTs ; 0 / 28 ( 0 % ) ; +; HPS_INTERFACE_TEST_INPUTs ; 0 / 610 ( 0 % ) ; +; HPS_INTERFACE_TEST_OUTPUTs ; 0 / 513 ( 0 % ) ; +; HPS_INTERFACE_TPIU_TRACE_INPUTs ; 0 / 2 ( 0 % ) ; +; HPS_INTERFACE_TPIU_TRACE_OUTPUTs ; 0 / 33 ( 0 % ) ; +; Horizontal periphery clocks ; 0 / 72 ( 0 % ) ; +; Local interconnects ; 107 / 84,580 ( < 1 % ) ; +; Quadrant clocks ; 0 / 66 ( 0 % ) ; +; R14 interconnects ; 39 / 12,676 ( < 1 % ) ; +; R14/C12 interconnect drivers ; 41 / 20,720 ( < 1 % ) ; +; R3 interconnects ; 174 / 130,992 ( < 1 % ) ; +; R6 interconnects ; 344 / 266,960 ( < 1 % ) ; +; Spine clocks ; 1 / 360 ( < 1 % ) ; +; Wire stub REs ; 0 / 15,858 ( 0 % ) ; ++---------------------------------------------+-------------------------+ + + ++------------------------------------------+ +; I/O Rules Summary ; ++----------------------------------+-------+ +; I/O Rules Statistic ; Total ; ++----------------------------------+-------+ +; Total I/O Rules ; 28 ; +; Number of I/O Rules Passed ; 6 ; +; Number of I/O Rules Failed ; 0 ; +; Number of I/O Rules Unchecked ; 0 ; +; Number of I/O Rules Inapplicable ; 22 ; ++----------------------------------+-------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; I/O Rules Details ; ++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+------+-------------------+ +; Status ; ID ; Category ; Rule Description ; Severity ; Information ; Area ; Extra Information ; ++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+------+-------------------+ +; Pass ; IO_000001 ; Capacity Checks ; Number of pins in an I/O bank should not exceed the number of locations available. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000002 ; Capacity Checks ; Number of clocks in an I/O bank should not exceed the number of clocks available. ; Critical ; No Global Signal assignments found. ; I/O ; ; +; Pass ; IO_000003 ; Capacity Checks ; Number of pins in a Vrefgroup should not exceed the number of locations available. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000004 ; Voltage Compatibility Checks ; The I/O bank should support the requested VCCIO. ; Critical ; No IOBANK_VCCIO assignments found. ; I/O ; ; +; Inapplicable ; IO_000005 ; Voltage Compatibility Checks ; The I/O bank should not have competing VREF values. ; Critical ; No VREF I/O Standard assignments found. ; I/O ; ; +; Pass ; IO_000006 ; Voltage Compatibility Checks ; The I/O bank should not have competing VCCIO values. ; Critical ; 0 such failures found. ; I/O ; ; +; Pass ; IO_000007 ; Valid Location Checks ; Checks for unavailable locations. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000008 ; Valid Location Checks ; Checks for reserved locations. ; Critical ; No reserved LogicLock region found. ; I/O ; ; +; Pass ; IO_000009 ; I/O Properties Checks for One I/O ; The location should support the requested I/O standard. ; Critical ; 0 such failures found. ; I/O ; ; +; Pass ; IO_000010 ; I/O Properties Checks for One I/O ; The location should support the requested I/O direction. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000011 ; I/O Properties Checks for One I/O ; The location should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ; +; Inapplicable ; IO_000012 ; I/O Properties Checks for One I/O ; The location should support the requested On Chip Termination value. ; Critical ; No Termination assignments found. ; I/O ; ; +; Inapplicable ; IO_000013 ; I/O Properties Checks for One I/O ; The location should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ; +; Inapplicable ; IO_000014 ; I/O Properties Checks for One I/O ; The location should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ; +; Inapplicable ; IO_000015 ; I/O Properties Checks for One I/O ; The location should support the requested PCI Clamp Diode. ; Critical ; No Clamping Diode assignments found. ; I/O ; ; +; Inapplicable ; IO_000018 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ; +; Inapplicable ; IO_000019 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested On Chip Termination value. ; Critical ; No Termination assignments found. ; I/O ; ; +; Inapplicable ; IO_000020 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested PCI Clamp Diode. ; Critical ; No Clamping Diode assignments found. ; I/O ; ; +; Inapplicable ; IO_000021 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ; +; Inapplicable ; IO_000022 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ; +; Inapplicable ; IO_000023 ; I/O Properties Checks for One I/O ; The I/O standard should support the Open Drain value. ; Critical ; No open drain assignments found. ; I/O ; ; +; Inapplicable ; IO_000024 ; I/O Properties Checks for One I/O ; The I/O direction should support the On Chip Termination value. ; Critical ; No Termination assignments found. ; I/O ; ; +; Inapplicable ; IO_000026 ; I/O Properties Checks for One I/O ; On Chip Termination and Current Strength should not be used at the same time. ; Critical ; No Current Strength or Termination assignments found. ; I/O ; ; +; Inapplicable ; IO_000027 ; I/O Properties Checks for One I/O ; Weak Pull Up and Bus Hold should not be used at the same time. ; Critical ; No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found. ; I/O ; ; +; Inapplicable ; IO_000045 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ; +; Inapplicable ; IO_000046 ; I/O Properties Checks for One I/O ; The location should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ; +; Inapplicable ; IO_000047 ; I/O Properties Checks for One I/O ; On Chip Termination and Slew Rate should not be used at the same time. ; Critical ; No Slew Rate assignments found. ; I/O ; ; +; Inapplicable ; IO_000034 ; SI Related Distance Checks ; Single-ended outputs should be 0 LAB row(s) away from a differential I/O. ; High ; No Differential I/O Standard assignments found. ; I/O ; ; ++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+------+-------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; I/O Rules Matrix ; ++--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+ +; Pin/Rules ; IO_000001 ; IO_000002 ; IO_000003 ; IO_000004 ; IO_000005 ; IO_000006 ; IO_000007 ; IO_000008 ; IO_000009 ; IO_000010 ; IO_000011 ; IO_000012 ; IO_000013 ; IO_000014 ; IO_000015 ; IO_000018 ; IO_000019 ; IO_000020 ; IO_000021 ; IO_000022 ; IO_000023 ; IO_000024 ; IO_000026 ; IO_000027 ; IO_000045 ; IO_000046 ; IO_000047 ; IO_000034 ; ++--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+ +; Total Pass ; 41 ; 0 ; 41 ; 0 ; 0 ; 41 ; 41 ; 0 ; 41 ; 41 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; Total Unchecked ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; Total Inapplicable ; 0 ; 41 ; 0 ; 41 ; 41 ; 0 ; 0 ; 41 ; 0 ; 0 ; 41 ; 41 ; 41 ; 41 ; 41 ; 41 ; 41 ; 41 ; 41 ; 41 ; 41 ; 41 ; 41 ; 41 ; 41 ; 41 ; 41 ; 41 ; +; Total Fail ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; SW[9] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; HEX0[0] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; HEX0[1] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; HEX0[2] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; HEX0[3] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; HEX0[4] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; HEX0[5] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; HEX0[6] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; HEX1[0] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; HEX1[1] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; HEX1[2] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; HEX1[3] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; HEX1[4] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; HEX1[5] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; HEX1[6] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; HEX2[0] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; HEX2[1] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; HEX2[2] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; HEX2[3] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; HEX2[4] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; HEX2[5] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; HEX2[6] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; DAC_SDI ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; DAC_SCK ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; DAC_CS ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; DAC_LD ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; ADC_SDI ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; ADC_SCK ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; ADC_CS ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; PWM_OUT ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; SW[8] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; CLOCK_50 ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; SW[6] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; SW[5] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; SW[4] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; SW[3] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; SW[2] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; SW[1] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; SW[0] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; SW[7] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; ADC_SDO ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; ++--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+ + + ++------------------------------------------------------------------------------------------------+ +; Fitter Device Options ; ++------------------------------------------------------------------+-----------------------------+ +; Option ; Setting ; ++------------------------------------------------------------------+-----------------------------+ +; Enable user-supplied start-up clock (CLKUSR) ; Off ; +; Enable device-wide reset (DEV_CLRn) ; Off ; +; Enable device-wide output enable (DEV_OE) ; Off ; +; Enable INIT_DONE output ; Off ; +; Configuration scheme ; Passive Serial ; +; Enable Error Detection CRC_ERROR pin ; Off ; +; Enable CvP_CONFDONE pin ; Off ; +; Enable open drain on CRC_ERROR pin ; On ; +; Enable open drain on CvP_CONFDONE pin ; On ; +; Enable open drain on INIT_DONE pin ; On ; +; Enable open drain on Partial Reconfiguration pins ; Off ; +; Enable open drain on nCEO pin ; On ; +; Enable Partial Reconfiguration pins ; Off ; +; Enable input tri-state on active configuration pins in user mode ; Off ; +; Enable internal scrubbing ; Off ; +; Active Serial clock source ; 100 MHz Internal Oscillator ; +; Device initialization clock source ; Internal Oscillator ; +; Configuration via Protocol ; Off ; +; Configuration Voltage Level ; Auto ; +; Force Configuration Voltage Level ; Off ; +; Enable nCEO output ; Off ; +; Data[15..8] ; Unreserved ; +; Data[7..5] ; Unreserved ; +; Base pin-out file on sameframe device ; Off ; ++------------------------------------------------------------------+-----------------------------+ + + ++------------------------------------+ +; Operating Settings and Conditions ; ++---------------------------+--------+ +; Setting ; Value ; ++---------------------------+--------+ +; Nominal Core Voltage ; 1.10 V ; +; Low Junction Temperature ; 0 °C ; +; High Junction Temperature ; 85 °C ; ++---------------------------+--------+ + + ++------------------------------------------------------------+ +; Estimated Delay Added for Hold Timing Summary ; ++-----------------+----------------------+-------------------+ +; Source Clock(s) ; Destination Clock(s) ; Delay Added in ns ; ++-----------------+----------------------+-------------------+ +; CLOCK_50 ; CLOCK_50 ; 36.1 ; +; CLOCK_50 ; CLOCK_50,I/O ; 1.3 ; ++-----------------+----------------------+-------------------+ +Note: For more information on problematic transfers, consider running the Fitter again with the Optimize hold timing option (Settings Menu) turned off. +This will disable optimization of problematic paths and expose them for further analysis using the TimeQuest Timing Analyzer. + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Estimated Delay Added for Hold Timing Details ; ++-------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------+-------------------+ +; Source Register ; Destination Register ; Delay Added in ns ; ++-------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------+-------------------+ +; spi2adc:SPI_ADC|adc_start ; spi2adc:SPI_ADC|adc_cs ; 1.181 ; +; spi2adc:SPI_ADC|state[1] ; spi2adc:SPI_ADC|adc_cs ; 1.176 ; +; spi2adc:SPI_ADC|state[4] ; spi2adc:SPI_ADC|adc_cs ; 1.167 ; +; spi2adc:SPI_ADC|state[0] ; spi2adc:SPI_ADC|adc_cs ; 1.130 ; +; spi2adc:SPI_ADC|state[2] ; spi2adc:SPI_ADC|adc_din ; 1.007 ; +; spi2adc:SPI_ADC|state[3] ; spi2adc:SPI_ADC|adc_din ; 0.987 ; +; spi2adc:SPI_ADC|tick ; spi2adc:SPI_ADC|adc_cs ; 0.692 ; +; spi2dac:SPI_DAC|state[2] ; spi2dac:SPI_DAC|state[0] ; 0.402 ; +; pwm:PWM_DC|d[8] ; pwm:PWM_DC|pwm_out ; 0.401 ; +; spi2dac:SPI_DAC|state[1] ; spi2dac:SPI_DAC|state[0] ; 0.399 ; +; pwm:PWM_DC|count[9] ; pwm:PWM_DC|pwm_out ; 0.385 ; +; spi2adc:SPI_ADC|shift_reg[8] ; spi2adc:SPI_ADC|shift_reg[9] ; 0.370 ; +; spi2adc:SPI_ADC|shift_reg[4] ; spi2adc:SPI_ADC|shift_reg[5] ; 0.370 ; +; spi2dac:SPI_DAC|state[0] ; spi2dac:SPI_DAC|state[4] ; 0.367 ; +; spi2adc:SPI_ADC|shift_reg[3] ; spi2adc:SPI_ADC|shift_reg[4] ; 0.357 ; +; spi2adc:SPI_ADC|shift_reg[0] ; spi2adc:SPI_ADC|shift_reg[1] ; 0.357 ; +; spi2adc:SPI_ADC|shift_reg[7] ; spi2adc:SPI_ADC|shift_reg[8] ; 0.352 ; +; spi2adc:SPI_ADC|shift_reg[5] ; spi2adc:SPI_ADC|shift_reg[6] ; 0.352 ; +; processor:ALLPASS|pulse_gen:PULSE0|state.IDLE ; processor:ALLPASS|pulse_gen:PULSE0|pulse ; 0.347 ; +; spi2adc:SPI_ADC|ctr[3] ; spi2adc:SPI_ADC|ctr[4] ; 0.347 ; +; spi2dac:SPI_DAC|state[4] ; spi2dac:SPI_DAC|state[0] ; 0.339 ; +; spi2adc:SPI_ADC|sr_state.IDLE ; spi2adc:SPI_ADC|sr_state.WAIT_CSB_FALL ; 0.337 ; +; spi2adc:SPI_ADC|ctr[1] ; spi2adc:SPI_ADC|ctr[2] ; 0.337 ; +; spi2dac:SPI_DAC|sr_state.IDLE ; spi2dac:SPI_DAC|sr_state.WAIT_CSB_FALL ; 0.333 ; +; spi2adc:SPI_ADC|sr_state.WAIT_CSB_HIGH ; spi2adc:SPI_ADC|sr_state.IDLE ; 0.333 ; +; pwm:PWM_DC|d[9] ; pwm:PWM_DC|pwm_out ; 0.332 ; +; spi2dac:SPI_DAC|shift_reg[13] ; spi2dac:SPI_DAC|shift_reg[14] ; 0.315 ; +; spi2dac:SPI_DAC|shift_reg[11] ; spi2dac:SPI_DAC|shift_reg[12] ; 0.315 ; +; spi2dac:SPI_DAC|sr_state.WAIT_CSB_FALL ; spi2dac:SPI_DAC|sr_state.IDLE ; 0.309 ; +; processor:ALLPASS|data_out[0] ; spi2dac:SPI_DAC|shift_reg[2] ; 0.307 ; +; spi2dac:SPI_DAC|state[3] ; spi2dac:SPI_DAC|state[4] ; 0.307 ; +; spi2dac:SPI_DAC|sr_state.WAIT_CSB_HIGH ; spi2dac:SPI_DAC|sr_state.WAIT_CSB_FALL ; 0.304 ; +; spi2dac:SPI_DAC|shift_reg[12] ; spi2dac:SPI_DAC|shift_reg[13] ; 0.300 ; +; spi2adc:SPI_ADC|adc_cs ; processor:ALLPASS|pulse_gen:PULSE0|pulse ; 0.295 ; +; spi2adc:SPI_ADC|sr_state.WAIT_CSB_FALL ; spi2adc:SPI_ADC|adc_start ; 0.287 ; +; spi2dac:SPI_DAC|shift_reg[14] ; spi2dac:SPI_DAC|shift_reg[15] ; 0.278 ; +; spi2adc:SPI_ADC|ctr[0] ; spi2adc:SPI_ADC|ctr[1] ; 0.262 ; +; spi2adc:SPI_ADC|data_from_adc[4] ; processor:ALLPASS|RAM:DELAY1024|altsyncram:altsyncram_component|altsyncram_ip02:auto_generated|ram_block1a3~porta_datain_reg0 ; 0.258 ; +; pwm:PWM_DC|d[7] ; pwm:PWM_DC|pwm_out ; 0.235 ; +; pwm:PWM_DC|count[7] ; pwm:PWM_DC|pwm_out ; 0.235 ; +; clktick_16:GEN_10K|count[14] ; clktick_16:GEN_10K|tick ; 0.226 ; +; clktick_16:GEN_10K|count[13] ; clktick_16:GEN_10K|tick ; 0.226 ; +; clktick_16:GEN_10K|count[12] ; clktick_16:GEN_10K|tick ; 0.226 ; +; clktick_16:GEN_10K|count[11] ; clktick_16:GEN_10K|tick ; 0.226 ; +; clktick_16:GEN_10K|count[10] ; clktick_16:GEN_10K|tick ; 0.226 ; +; clktick_16:GEN_10K|count[9] ; clktick_16:GEN_10K|tick ; 0.226 ; +; clktick_16:GEN_10K|count[8] ; clktick_16:GEN_10K|tick ; 0.226 ; +; clktick_16:GEN_10K|count[7] ; clktick_16:GEN_10K|tick ; 0.226 ; +; clktick_16:GEN_10K|count[5] ; clktick_16:GEN_10K|tick ; 0.226 ; +; clktick_16:GEN_10K|count[4] ; clktick_16:GEN_10K|tick ; 0.226 ; +; clktick_16:GEN_10K|count[3] ; clktick_16:GEN_10K|tick ; 0.226 ; +; clktick_16:GEN_10K|count[2] ; clktick_16:GEN_10K|tick ; 0.226 ; +; clktick_16:GEN_10K|count[1] ; clktick_16:GEN_10K|tick ; 0.226 ; +; clktick_16:GEN_10K|count[0] ; clktick_16:GEN_10K|tick ; 0.226 ; +; clktick_16:GEN_10K|count[15] ; clktick_16:GEN_10K|tick ; 0.226 ; +; clktick_16:GEN_10K|count[6] ; clktick_16:GEN_10K|tick ; 0.226 ; +; processor:ALLPASS|data_out[6] ; spi2dac:SPI_DAC|shift_reg[8] ; 0.212 ; +; processor:ALLPASS|data_out[9] ; spi2dac:SPI_DAC|shift_reg[11] ; 0.201 ; +; processor:ALLPASS|data_out[3] ; spi2dac:SPI_DAC|shift_reg[5] ; 0.201 ; +; processor:ALLPASS|data_out[1] ; spi2dac:SPI_DAC|shift_reg[3] ; 0.201 ; +; processor:ALLPASS|data_out[7] ; spi2dac:SPI_DAC|shift_reg[9] ; 0.199 ; +; pwm:PWM_DC|count[8] ; pwm:PWM_DC|pwm_out ; 0.189 ; +; pwm:PWM_DC|d[6] ; pwm:PWM_DC|pwm_out ; 0.166 ; +; pwm:PWM_DC|d[5] ; pwm:PWM_DC|pwm_out ; 0.166 ; +; pwm:PWM_DC|d[4] ; pwm:PWM_DC|pwm_out ; 0.166 ; +; pwm:PWM_DC|d[3] ; pwm:PWM_DC|pwm_out ; 0.166 ; +; pwm:PWM_DC|d[2] ; pwm:PWM_DC|pwm_out ; 0.166 ; +; pwm:PWM_DC|d[1] ; pwm:PWM_DC|pwm_out ; 0.166 ; +; pwm:PWM_DC|d[0] ; pwm:PWM_DC|pwm_out ; 0.166 ; +; pwm:PWM_DC|count[6] ; pwm:PWM_DC|pwm_out ; 0.166 ; +; pwm:PWM_DC|count[5] ; pwm:PWM_DC|pwm_out ; 0.166 ; +; pwm:PWM_DC|count[4] ; pwm:PWM_DC|pwm_out ; 0.166 ; +; pwm:PWM_DC|count[3] ; pwm:PWM_DC|pwm_out ; 0.166 ; +; pwm:PWM_DC|count[2] ; pwm:PWM_DC|pwm_out ; 0.166 ; +; pwm:PWM_DC|count[1] ; pwm:PWM_DC|pwm_out ; 0.166 ; +; pwm:PWM_DC|count[0] ; pwm:PWM_DC|pwm_out ; 0.166 ; +; processor:ALLPASS|pulse_gen:PULSE0|pulse ; processor:ALLPASS|RAM:DELAY1024|altsyncram:altsyncram_component|altsyncram_ip02:auto_generated|ram_block1a2~porta_we_reg ; 0.102 ; +; spi2adc:SPI_ADC|data_from_adc[5] ; processor:ALLPASS|data_out[9] ; 0.064 ; +; processor:ALLPASS|RAM:DELAY1024|altsyncram:altsyncram_component|altsyncram_ip02:auto_generated|q_b[3] ; processor:ALLPASS|RAM:DELAY1024|altsyncram:altsyncram_component|altsyncram_ip02:auto_generated|ram_block1a2~porta_datain_reg0 ; 0.057 ; +; spi2adc:SPI_ADC|data_from_adc[3] ; processor:ALLPASS|RAM:DELAY1024|altsyncram:altsyncram_component|altsyncram_ip02:auto_generated|ram_block1a2~porta_datain_reg0 ; 0.057 ; +; processor:ALLPASS|RAM:DELAY1024|altsyncram:altsyncram_component|altsyncram_ip02:auto_generated|q_b[2] ; processor:ALLPASS|RAM:DELAY1024|altsyncram:altsyncram_component|altsyncram_ip02:auto_generated|ram_block1a2~porta_datain_reg0 ; 0.057 ; +; spi2adc:SPI_ADC|data_from_adc[2] ; processor:ALLPASS|RAM:DELAY1024|altsyncram:altsyncram_component|altsyncram_ip02:auto_generated|ram_block1a2~porta_datain_reg0 ; 0.057 ; +; processor:ALLPASS|RAM:DELAY1024|altsyncram:altsyncram_component|altsyncram_ip02:auto_generated|q_b[1] ; processor:ALLPASS|RAM:DELAY1024|altsyncram:altsyncram_component|altsyncram_ip02:auto_generated|ram_block1a2~porta_datain_reg0 ; 0.057 ; +; spi2adc:SPI_ADC|data_from_adc[1] ; processor:ALLPASS|RAM:DELAY1024|altsyncram:altsyncram_component|altsyncram_ip02:auto_generated|ram_block1a2~porta_datain_reg0 ; 0.057 ; +; processor:ALLPASS|RAM:DELAY1024|altsyncram:altsyncram_component|altsyncram_ip02:auto_generated|q_b[0] ; processor:ALLPASS|RAM:DELAY1024|altsyncram:altsyncram_component|altsyncram_ip02:auto_generated|ram_block1a2~porta_datain_reg0 ; 0.057 ; +; spi2adc:SPI_ADC|data_from_adc[0] ; processor:ALLPASS|RAM:DELAY1024|altsyncram:altsyncram_component|altsyncram_ip02:auto_generated|ram_block1a2~porta_datain_reg0 ; 0.057 ; +; processor:ALLPASS|data_out[4] ; pwm:PWM_DC|d[4] ; 0.042 ; +; processor:ALLPASS|data_out[2] ; pwm:PWM_DC|d[2] ; 0.042 ; +; spi2adc:SPI_ADC|data_from_adc[6] ; processor:ALLPASS|data_out[9] ; 0.031 ; +; spi2dac:SPI_DAC|shift_reg[2] ; spi2dac:SPI_DAC|shift_reg[3] ; 0.026 ; +; spi2dac:SPI_DAC|shift_reg[4] ; spi2dac:SPI_DAC|shift_reg[5] ; 0.026 ; +; spi2dac:SPI_DAC|shift_reg[6] ; spi2dac:SPI_DAC|shift_reg[7] ; 0.026 ; +; spi2dac:SPI_DAC|shift_reg[10] ; spi2dac:SPI_DAC|shift_reg[11] ; 0.026 ; +; spi2dac:SPI_DAC|shift_reg[3] ; spi2dac:SPI_DAC|shift_reg[4] ; 0.024 ; +; spi2dac:SPI_DAC|shift_reg[5] ; spi2dac:SPI_DAC|shift_reg[6] ; 0.024 ; +; processor:ALLPASS|RAM:DELAY1024|altsyncram:altsyncram_component|altsyncram_ip02:auto_generated|q_b[4] ; processor:ALLPASS|RAM:DELAY1024|altsyncram:altsyncram_component|altsyncram_ip02:auto_generated|ram_block1a3~porta_datain_reg0 ; 0.018 ; +; spi2dac:SPI_DAC|shift_reg[8] ; spi2dac:SPI_DAC|shift_reg[9] ; 0.018 ; ++-------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------+-------------------+ +Note: This table only shows the top 97 path(s) that have the largest delay added for hold. + + ++-----------------+ +; Fitter Messages ; ++-----------------+ +Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. +Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected +Info (119006): Selected device 5CSEMA5F31C6 for design "ex19_top" +Info (21077): Low junction temperature is 0 degrees C +Info (21077): High junction temperature is 85 degrees C +Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time +Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature. +Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details +Info (176045): Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements. +Info (184020): Starting Fitter periphery placement operations +Info (11191): Automatically promoted 1 clock (1 global) + Info (11162): CLOCK_50~inputCLKENA0 with 120 fanout uses global clock CLKCTRL_G6 +Info (184021): Fitter periphery placement operations ending: elapsed time is 00:00:00 +Info (176233): Starting register packing +Info (332104): Reading SDC File: 'ex19_top.sdc' +Warning (332060): Node: spi2adc:SPI_ADC|adc_cs was determined to be a clock but was found without an associated clock assignment. + Info (13166): Register processor:ALLPASS|counter_13:COUNT13|count[12] is being clocked by spi2adc:SPI_ADC|adc_cs +Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty" +Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. +Info (332129): Detected timing requirements -- optimizing circuit to achieve only the specified requirements +Info (332111): Found 1 clocks + Info (332111): Period Clock Name + Info (332111): ======== ============ + Info (332111): 20.000 CLOCK_50 +Info (176235): Finished register packing + Extra Info (176219): No registers were packed into other blocks +Warning (15705): Ignored locations or region assignments to the following nodes + Warning (15706): Node "HEX3[0]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HEX3[1]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HEX3[2]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HEX3[3]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HEX3[4]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HEX3[5]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HEX3[6]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HEX4[0]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HEX4[1]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HEX4[2]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HEX4[3]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HEX4[4]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HEX4[5]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HEX4[6]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HEX5[0]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HEX5[1]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HEX5[2]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HEX5[3]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HEX5[4]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HEX5[5]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HEX5[6]" is assigned to location or region, but does not exist in design + Warning (15706): Node "KEY[0]" is assigned to location or region, but does not exist in design + Warning (15706): Node "KEY[1]" is assigned to location or region, but does not exist in design + Warning (15706): Node "KEY[2]" is assigned to location or region, but does not exist in design + Warning (15706): Node "KEY[3]" is assigned to location or region, but does not exist in design + Warning (15706): Node "LEDR[0]" is assigned to location or region, but does not exist in design + Warning (15706): Node "LEDR[1]" is assigned to location or region, but does not exist in design + Warning (15706): Node "LEDR[2]" is assigned to location or region, but does not exist in design + Warning (15706): Node "LEDR[3]" is assigned to location or region, but does not exist in design + Warning (15706): Node "LEDR[4]" is assigned to location or region, but does not exist in design + Warning (15706): Node "LEDR[5]" is assigned to location or region, but does not exist in design + Warning (15706): Node "LEDR[6]" is assigned to location or region, but does not exist in design + Warning (15706): Node "LEDR[7]" is assigned to location or region, but does not exist in design + Warning (15706): Node "LEDR[8]" is assigned to location or region, but does not exist in design + Warning (15706): Node "LEDR[9]" is assigned to location or region, but does not exist in design + Warning (15706): Node "OLED_CLK" is assigned to location or region, but does not exist in design + Warning (15706): Node "OLED_CS" is assigned to location or region, but does not exist in design + Warning (15706): Node "OLED_DATA" is assigned to location or region, but does not exist in design + Warning (15706): Node "OLED_DC" is assigned to location or region, but does not exist in design + Warning (15706): Node "OLED_RST" is assigned to location or region, but does not exist in design +Info (11798): Fitter preparation operations ending: elapsed time is 00:00:39 +Info (170189): Fitter placement preparation operations beginning +Info (14951): The Fitter is using Advanced Physical Optimization. +Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:06 +Info (170191): Fitter placement operations beginning +Info (170137): Fitter placement was successful +Info (170192): Fitter placement operations ending: elapsed time is 00:00:01 +Info (170193): Fitter routing operations beginning +Info (170195): Router estimated average interconnect usage is 0% of the available device resources + Info (170196): Router estimated peak interconnect usage is 3% of the available device resources in the region that extends from location X45_Y0 to location X55_Y10 +Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time. + Info (170201): Optimizations that may affect the design's routability were skipped + Info (170200): Optimizations that may affect the design's timing were skipped +Info (170194): Fitter routing operations ending: elapsed time is 00:00:03 +Info (11888): Total time spent on timing analysis during the Fitter is 1.85 seconds. +Info (334003): Started post-fitting delay annotation +Info (334004): Delay annotation completed successfully +Info (334003): Started post-fitting delay annotation +Info (334004): Delay annotation completed successfully +Info (11801): Fitter post-fit operations ending: elapsed time is 00:01:12 +Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information. +Info (144001): Generated suppressed messages file H:/Year 2/VERI/part_4/ex19/output_files/ex19_top.fit.smsg +Info: Quartus Prime Fitter was successful. 0 errors, 46 warnings + Info: Peak virtual memory: 2197 megabytes + Info: Processing ended: Sat Dec 10 19:25:21 2016 + Info: Elapsed time: 00:03:41 + Info: Total CPU time (on all processors): 00:02:15 + + ++----------------------------+ +; Fitter Suppressed Messages ; ++----------------------------+ +The suppressed messages can be found in H:/Year 2/VERI/part_4/ex19/output_files/ex19_top.fit.smsg. + + diff --git a/part_4/ex19/output_files/ex19_top.flow.rpt b/part_4/ex19/output_files/ex19_top.flow.rpt new file mode 100644 index 0000000..6153b78 --- /dev/null +++ b/part_4/ex19/output_files/ex19_top.flow.rpt @@ -0,0 +1,127 @@ +Flow report for ex19_top +Sat Dec 10 19:28:13 2016 +Quartus Prime Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Flow Summary + 3. Flow Settings + 4. Flow Non-Default Global Settings + 5. Flow Elapsed Time + 6. Flow OS Summary + 7. Flow Log + 8. Flow Messages + 9. Flow Suppressed Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2016 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel MegaCore Function License Agreement, or other +applicable license agreement, including, without limitation, +that your use is for the sole purpose of programming logic +devices manufactured by Intel and sold by Intel or its +authorized distributors. Please refer to the applicable +agreement for further details. + + + ++-------------------------------------------------------------------------------+ +; Flow Summary ; ++---------------------------------+---------------------------------------------+ +; Flow Status ; Successful - Sat Dec 10 19:26:58 2016 ; +; Quartus Prime Version ; 16.1.0 Build 196 10/24/2016 SJ Lite Edition ; +; Revision Name ; ex19_top ; +; Top-level Entity Name ; ex19_top ; +; Family ; Cyclone V ; +; Device ; 5CSEMA5F31C6 ; +; Timing Models ; Final ; +; Logic utilization (in ALMs) ; 119 / 32,070 ( < 1 % ) ; +; Total registers ; 139 ; +; Total pins ; 41 / 457 ( 9 % ) ; +; Total virtual pins ; 0 ; +; Total block memory bits ; 73,728 / 4,065,280 ( 2 % ) ; +; Total DSP Blocks ; 0 / 87 ( 0 % ) ; +; Total HSSI RX PCSs ; 0 ; +; Total HSSI PMA RX Deserializers ; 0 ; +; Total HSSI TX PCSs ; 0 ; +; Total HSSI PMA TX Serializers ; 0 ; +; Total PLLs ; 0 / 6 ( 0 % ) ; +; Total DLLs ; 0 / 4 ( 0 % ) ; ++---------------------------------+---------------------------------------------+ + + ++-----------------------------------------+ +; Flow Settings ; ++-------------------+---------------------+ +; Option ; Setting ; ++-------------------+---------------------+ +; Start date & time ; 12/10/2016 19:20:05 ; +; Main task ; Compilation ; +; Revision Name ; ex19_top ; ++-------------------+---------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------+ +; Flow Non-Default Global Settings ; ++-------------------------------------+----------------------------------------+---------------+-------------+------------+ +; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ; ++-------------------------------------+----------------------------------------+---------------+-------------+------------+ +; COMPILER_SIGNATURE_ID ; 147774608559.148139760403284 ; -- ; -- ; -- ; +; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ; +; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ; +; MISC_FILE ; RAM_bb.v ; -- ; -- ; -- ; +; PARTITION_COLOR ; -- (Not supported for targeted family) ; -- ; -- ; Top ; +; PARTITION_FITTER_PRESERVATION_LEVEL ; -- (Not supported for targeted family) ; -- ; -- ; Top ; +; PARTITION_NETLIST_TYPE ; -- (Not supported for targeted family) ; -- ; -- ; Top ; +; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ; ++-------------------------------------+----------------------------------------+---------------+-------------+------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------+ +; Flow Elapsed Time ; ++---------------------------+--------------+-------------------------+---------------------+------------------------------------+ +; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; ++---------------------------+--------------+-------------------------+---------------------+------------------------------------+ +; Analysis & Synthesis ; 00:01:07 ; 1.0 ; 718 MB ; 00:00:39 ; +; Fitter ; 00:03:18 ; 1.0 ; 2197 MB ; 00:02:14 ; +; Assembler ; 00:00:56 ; 1.0 ; 727 MB ; 00:00:13 ; +; TimeQuest Timing Analyzer ; 00:01:07 ; 1.0 ; 1035 MB ; 00:00:13 ; +; Total ; 00:06:28 ; -- ; -- ; 00:03:19 ; ++---------------------------+--------------+-------------------------+---------------------+------------------------------------+ + + ++-----------------------------------------------------------------------------------------+ +; Flow OS Summary ; ++---------------------------+------------------+------------+------------+----------------+ +; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ; ++---------------------------+------------------+------------+------------+----------------+ +; Analysis & Synthesis ; Xav-Laptop ; Windows 10 ; 10.0 ; x86_64 ; +; Fitter ; Xav-Laptop ; Windows 10 ; 10.0 ; x86_64 ; +; Assembler ; Xav-Laptop ; Windows 10 ; 10.0 ; x86_64 ; +; TimeQuest Timing Analyzer ; Xav-Laptop ; Windows 10 ; 10.0 ; x86_64 ; ++---------------------------+------------------+------------+------------+----------------+ + + +------------ +; Flow Log ; +------------ +quartus_map --read_settings_files=on --write_settings_files=off ex19 -c ex19_top +quartus_fit --read_settings_files=off --write_settings_files=off ex19 -c ex19_top +quartus_asm --read_settings_files=off --write_settings_files=off ex19 -c ex19_top +quartus_sta ex19 -c ex19_top + + + diff --git a/part_4/ex19/output_files/ex19_top.map.rpt b/part_4/ex19/output_files/ex19_top.map.rpt new file mode 100644 index 0000000..9fbc49b --- /dev/null +++ b/part_4/ex19/output_files/ex19_top.map.rpt @@ -0,0 +1,946 @@ +Analysis & Synthesis report for ex19_top +Sat Dec 10 19:21:21 2016 +Quartus Prime Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Analysis & Synthesis Summary + 3. Analysis & Synthesis Settings + 4. Parallel Compilation + 5. Analysis & Synthesis Source Files Read + 6. Analysis & Synthesis Resource Usage Summary + 7. Analysis & Synthesis Resource Utilization by Entity + 8. Analysis & Synthesis RAM Summary + 9. Analysis & Synthesis IP Cores Summary + 10. State Machine - |ex19_top|processor:ALLPASS|pulse_gen:PULSE0|state + 11. State Machine - |ex19_top|spi2adc:SPI_ADC|sr_state + 12. State Machine - |ex19_top|spi2dac:SPI_DAC|sr_state + 13. Registers Removed During Synthesis + 14. Removed Registers Triggering Further Register Optimizations + 15. General Register Statistics + 16. Inverted Register Statistics + 17. Multiplexer Restructuring Statistics (Restructuring Performed) + 18. Source assignments for processor:ALLPASS|RAM:DELAY1024|altsyncram:altsyncram_component|altsyncram_ip02:auto_generated + 19. Parameter Settings for User Entity Instance: clktick_16:GEN_10K + 20. Parameter Settings for User Entity Instance: spi2dac:SPI_DAC + 21. Parameter Settings for User Entity Instance: spi2adc:SPI_ADC + 22. Parameter Settings for User Entity Instance: processor:ALLPASS + 23. Parameter Settings for User Entity Instance: processor:ALLPASS|pulse_gen:PULSE0 + 24. Parameter Settings for User Entity Instance: processor:ALLPASS|counter_13:COUNT13 + 25. Parameter Settings for User Entity Instance: processor:ALLPASS|RAM:DELAY1024|altsyncram:altsyncram_component + 26. Parameter Settings for User Entity Instance: processor:ALLPASS|multiply_k:MULTK|lpm_mult:lpm_mult_component + 27. altsyncram Parameter Settings by Entity Instance + 28. lpm_mult Parameter Settings by Entity Instance + 29. Port Connectivity Checks: "processor:ALLPASS|bin2bcd_16:BIN0|add3_ge5:A31" + 30. Port Connectivity Checks: "processor:ALLPASS|bin2bcd_16:BIN0|add3_ge5:A19" + 31. Port Connectivity Checks: "processor:ALLPASS|bin2bcd_16:BIN0|add3_ge5:A10" + 32. Port Connectivity Checks: "processor:ALLPASS|bin2bcd_16:BIN0|add3_ge5:A4" + 33. Port Connectivity Checks: "processor:ALLPASS|bin2bcd_16:BIN0|add3_ge5:A1" + 34. Port Connectivity Checks: "processor:ALLPASS|bin2bcd_16:BIN0" + 35. Port Connectivity Checks: "processor:ALLPASS|multiply_k:MULTK" + 36. Port Connectivity Checks: "processor:ALLPASS|counter_13:COUNT13" + 37. Port Connectivity Checks: "processor:ALLPASS" + 38. Port Connectivity Checks: "spi2adc:SPI_ADC" + 39. Port Connectivity Checks: "clktick_16:GEN_10K" + 40. Post-Synthesis Netlist Statistics for Top Partition + 41. Elapsed Time Per Partition + 42. Analysis & Synthesis Messages + 43. Analysis & Synthesis Suppressed Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2016 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel MegaCore Function License Agreement, or other +applicable license agreement, including, without limitation, +that your use is for the sole purpose of programming logic +devices manufactured by Intel and sold by Intel or its +authorized distributors. Please refer to the applicable +agreement for further details. + + + ++-------------------------------------------------------------------------------+ +; Analysis & Synthesis Summary ; ++---------------------------------+---------------------------------------------+ +; Analysis & Synthesis Status ; Successful - Sat Dec 10 19:21:19 2016 ; +; Quartus Prime Version ; 16.1.0 Build 196 10/24/2016 SJ Lite Edition ; +; Revision Name ; ex19_top ; +; Top-level Entity Name ; ex19_top ; +; Family ; Cyclone V ; +; Logic utilization (in ALMs) ; N/A ; +; Total registers ; 125 ; +; Total pins ; 41 ; +; Total virtual pins ; 0 ; +; Total block memory bits ; 73,728 ; +; Total DSP Blocks ; 0 ; +; Total HSSI RX PCSs ; 0 ; +; Total HSSI PMA RX Deserializers ; 0 ; +; Total HSSI TX PCSs ; 0 ; +; Total HSSI PMA TX Serializers ; 0 ; +; Total PLLs ; 0 ; +; Total DLLs ; 0 ; ++---------------------------------+---------------------------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Settings ; ++---------------------------------------------------------------------------------+--------------------+--------------------+ +; Option ; Setting ; Default Value ; ++---------------------------------------------------------------------------------+--------------------+--------------------+ +; Device ; 5CSEMA5F31C6 ; ; +; Top-level entity name ; ex19_top ; ex19_top ; +; Family name ; Cyclone V ; Cyclone V ; +; Use smart compilation ; Off ; Off ; +; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ; +; Enable compact report table ; Off ; Off ; +; Restructure Multiplexers ; Auto ; Auto ; +; MLAB Add Timing Constraints For Mixed-Port Feed-Through Mode Setting Don't Care ; Off ; Off ; +; Create Debugging Nodes for IP Cores ; Off ; Off ; +; Preserve fewer node names ; On ; On ; +; OpenCore Plus hardware evaluation ; Enable ; Enable ; +; Verilog Version ; Verilog_2001 ; Verilog_2001 ; +; VHDL Version ; VHDL_1993 ; VHDL_1993 ; +; State Machine Processing ; Auto ; Auto ; +; Safe State Machine ; Off ; Off ; +; Extract Verilog State Machines ; On ; On ; +; Extract VHDL State Machines ; On ; On ; +; Ignore Verilog initial constructs ; Off ; Off ; +; Iteration limit for constant Verilog loops ; 5000 ; 5000 ; +; Iteration limit for non-constant Verilog loops ; 250 ; 250 ; +; Add Pass-Through Logic to Inferred RAMs ; On ; On ; +; Infer RAMs from Raw Logic ; On ; On ; +; Parallel Synthesis ; On ; On ; +; DSP Block Balancing ; Auto ; Auto ; +; NOT Gate Push-Back ; On ; On ; +; Power-Up Don't Care ; On ; On ; +; Remove Redundant Logic Cells ; Off ; Off ; +; Remove Duplicate Registers ; On ; On ; +; Ignore CARRY Buffers ; Off ; Off ; +; Ignore CASCADE Buffers ; Off ; Off ; +; Ignore GLOBAL Buffers ; Off ; Off ; +; Ignore ROW GLOBAL Buffers ; Off ; Off ; +; Ignore LCELL Buffers ; Off ; Off ; +; Ignore SOFT Buffers ; On ; On ; +; Limit AHDL Integers to 32 Bits ; Off ; Off ; +; Optimization Technique ; Balanced ; Balanced ; +; Carry Chain Length ; 70 ; 70 ; +; Auto Carry Chains ; On ; On ; +; Auto Open-Drain Pins ; On ; On ; +; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ; +; Auto ROM Replacement ; On ; On ; +; Auto RAM Replacement ; On ; On ; +; Auto DSP Block Replacement ; On ; On ; +; Auto Shift Register Replacement ; Auto ; Auto ; +; Allow Shift Register Merging across Hierarchies ; Auto ; Auto ; +; Auto Clock Enable Replacement ; On ; On ; +; Strict RAM Replacement ; Off ; Off ; +; Allow Synchronous Control Signals ; On ; On ; +; Force Use of Synchronous Clear Signals ; Off ; Off ; +; Auto Resource Sharing ; Off ; Off ; +; Allow Any RAM Size For Recognition ; Off ; Off ; +; Allow Any ROM Size For Recognition ; Off ; Off ; +; Allow Any Shift Register Size For Recognition ; Off ; Off ; +; Use LogicLock Constraints during Resource Balancing ; On ; On ; +; Ignore translate_off and synthesis_off directives ; Off ; Off ; +; Timing-Driven Synthesis ; On ; On ; +; Report Parameter Settings ; On ; On ; +; Report Source Assignments ; On ; On ; +; Report Connectivity Checks ; On ; On ; +; Ignore Maximum Fan-Out Assignments ; Off ; Off ; +; Synchronization Register Chain Length ; 3 ; 3 ; +; PowerPlay Power Optimization During Synthesis ; Normal compilation ; Normal compilation ; +; HDL message level ; Level2 ; Level2 ; +; Suppress Register Optimization Related Messages ; Off ; Off ; +; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ; +; Number of Swept Nodes Reported in Synthesis Report ; 5000 ; 5000 ; +; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ; +; Clock MUX Protection ; On ; On ; +; Auto Gated Clock Conversion ; Off ; Off ; +; Block Design Naming ; Auto ; Auto ; +; SDC constraint protection ; Off ; Off ; +; Synthesis Effort ; Auto ; Auto ; +; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ; +; Pre-Mapping Resynthesis Optimization ; Off ; Off ; +; Analysis & Synthesis Message Level ; Medium ; Medium ; +; Disable Register Merging Across Hierarchies ; Auto ; Auto ; +; Resource Aware Inference For Block RAM ; On ; On ; +; Automatic Parallel Synthesis ; On ; On ; +; Partial Reconfiguration Bitstream ID ; Off ; Off ; ++---------------------------------------------------------------------------------+--------------------+--------------------+ + + ++------------------------------------------+ +; Parallel Compilation ; ++----------------------------+-------------+ +; Processors ; Number ; ++----------------------------+-------------+ +; Number detected on machine ; 2 ; +; Maximum allowed ; 2 ; +; ; ; +; Average used ; 1.00 ; +; Maximum used ; 2 ; +; ; ; +; Usage by Processor ; % Time Used ; +; Processor 1 ; 100.0% ; +; Processor 2 ; 0.0% ; ++----------------------------+-------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Source Files Read ; ++----------------------------------+-----------------+------------------------------+--------------------------------------------------------------------------------+---------+ +; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ; ++----------------------------------+-----------------+------------------------------+--------------------------------------------------------------------------------+---------+ +; variable_echo.v ; yes ; User Verilog HDL File ; H:/Year 2/VERI/part_4/ex19/variable_echo.v ; ; +; ex19_top.v ; yes ; User Verilog HDL File ; H:/Year 2/VERI/part_4/ex19/ex19_top.v ; ; +; ../mylib/spi2dac.v ; yes ; User Verilog HDL File ; H:/Year 2/VERI/part_4/mylib/spi2dac.v ; ; +; ../mylib/spi2adc.v ; yes ; User Verilog HDL File ; H:/Year 2/VERI/part_4/mylib/spi2adc.v ; ; +; ../mylib/pwm.v ; yes ; User Verilog HDL File ; H:/Year 2/VERI/part_4/mylib/pwm.v ; ; +; ../mylib/pulse_gen.v ; yes ; User Verilog HDL File ; H:/Year 2/VERI/part_4/mylib/pulse_gen.v ; ; +; ../mylib/multiply_k.v ; yes ; User Wizard-Generated File ; H:/Year 2/VERI/part_4/mylib/multiply_k.v ; ; +; ../mylib/hex_to_7seg.v ; yes ; User Verilog HDL File ; H:/Year 2/VERI/part_4/mylib/hex_to_7seg.v ; ; +; ../mylib/counter_13.v ; yes ; User Verilog HDL File ; H:/Year 2/VERI/part_4/mylib/counter_13.v ; ; +; ../mylib/clktick_16.v ; yes ; User Verilog HDL File ; H:/Year 2/VERI/part_4/mylib/clktick_16.v ; ; +; ../mylib/bin2bcd_16.v ; yes ; User Verilog HDL File ; H:/Year 2/VERI/part_4/mylib/bin2bcd_16.v ; ; +; ../mylib/add3_ge5.v ; yes ; User Verilog HDL File ; H:/Year 2/VERI/part_4/mylib/add3_ge5.v ; ; +; RAM.v ; yes ; User Wizard-Generated File ; H:/Year 2/VERI/part_4/ex19/RAM.v ; ; +; altsyncram.tdf ; yes ; Megafunction ; c:/intelfpga_lite/16.1/quartus/libraries/megafunctions/altsyncram.tdf ; ; +; stratix_ram_block.inc ; yes ; Megafunction ; c:/intelfpga_lite/16.1/quartus/libraries/megafunctions/stratix_ram_block.inc ; ; +; lpm_mux.inc ; yes ; Megafunction ; c:/intelfpga_lite/16.1/quartus/libraries/megafunctions/lpm_mux.inc ; ; +; lpm_decode.inc ; yes ; Megafunction ; c:/intelfpga_lite/16.1/quartus/libraries/megafunctions/lpm_decode.inc ; ; +; aglobal161.inc ; yes ; Megafunction ; c:/intelfpga_lite/16.1/quartus/libraries/megafunctions/aglobal161.inc ; ; +; a_rdenreg.inc ; yes ; Megafunction ; c:/intelfpga_lite/16.1/quartus/libraries/megafunctions/a_rdenreg.inc ; ; +; altrom.inc ; yes ; Megafunction ; c:/intelfpga_lite/16.1/quartus/libraries/megafunctions/altrom.inc ; ; +; altram.inc ; yes ; Megafunction ; c:/intelfpga_lite/16.1/quartus/libraries/megafunctions/altram.inc ; ; +; altdpram.inc ; yes ; Megafunction ; c:/intelfpga_lite/16.1/quartus/libraries/megafunctions/altdpram.inc ; ; +; db/altsyncram_ip02.tdf ; yes ; Auto-Generated Megafunction ; H:/Year 2/VERI/part_4/ex19/db/altsyncram_ip02.tdf ; ; +; lpm_mult.tdf ; yes ; Megafunction ; c:/intelfpga_lite/16.1/quartus/libraries/megafunctions/lpm_mult.tdf ; ; +; lpm_add_sub.inc ; yes ; Megafunction ; c:/intelfpga_lite/16.1/quartus/libraries/megafunctions/lpm_add_sub.inc ; ; +; multcore.inc ; yes ; Megafunction ; c:/intelfpga_lite/16.1/quartus/libraries/megafunctions/multcore.inc ; ; +; bypassff.inc ; yes ; Megafunction ; c:/intelfpga_lite/16.1/quartus/libraries/megafunctions/bypassff.inc ; ; +; altshift.inc ; yes ; Megafunction ; c:/intelfpga_lite/16.1/quartus/libraries/megafunctions/altshift.inc ; ; +; multcore.tdf ; yes ; Megafunction ; c:/intelfpga_lite/16.1/quartus/libraries/megafunctions/multcore.tdf ; ; +; csa_add.inc ; yes ; Megafunction ; c:/intelfpga_lite/16.1/quartus/libraries/megafunctions/csa_add.inc ; ; +; mpar_add.inc ; yes ; Megafunction ; c:/intelfpga_lite/16.1/quartus/libraries/megafunctions/mpar_add.inc ; ; +; muleabz.inc ; yes ; Megafunction ; c:/intelfpga_lite/16.1/quartus/libraries/megafunctions/muleabz.inc ; ; +; mul_lfrg.inc ; yes ; Megafunction ; c:/intelfpga_lite/16.1/quartus/libraries/megafunctions/mul_lfrg.inc ; ; +; mul_boothc.inc ; yes ; Megafunction ; c:/intelfpga_lite/16.1/quartus/libraries/megafunctions/mul_boothc.inc ; ; +; alt_ded_mult.inc ; yes ; Megafunction ; c:/intelfpga_lite/16.1/quartus/libraries/megafunctions/alt_ded_mult.inc ; ; +; alt_ded_mult_y.inc ; yes ; Megafunction ; c:/intelfpga_lite/16.1/quartus/libraries/megafunctions/alt_ded_mult_y.inc ; ; +; dffpipe.inc ; yes ; Megafunction ; c:/intelfpga_lite/16.1/quartus/libraries/megafunctions/dffpipe.inc ; ; +; mpar_add.tdf ; yes ; Megafunction ; c:/intelfpga_lite/16.1/quartus/libraries/megafunctions/mpar_add.tdf ; ; +; lpm_add_sub.tdf ; yes ; Megafunction ; c:/intelfpga_lite/16.1/quartus/libraries/megafunctions/lpm_add_sub.tdf ; ; +; addcore.inc ; yes ; Megafunction ; c:/intelfpga_lite/16.1/quartus/libraries/megafunctions/addcore.inc ; ; +; look_add.inc ; yes ; Megafunction ; c:/intelfpga_lite/16.1/quartus/libraries/megafunctions/look_add.inc ; ; +; alt_stratix_add_sub.inc ; yes ; Megafunction ; c:/intelfpga_lite/16.1/quartus/libraries/megafunctions/alt_stratix_add_sub.inc ; ; +; db/add_sub_a9h.tdf ; yes ; Auto-Generated Megafunction ; H:/Year 2/VERI/part_4/ex19/db/add_sub_a9h.tdf ; ; +; db/add_sub_e9h.tdf ; yes ; Auto-Generated Megafunction ; H:/Year 2/VERI/part_4/ex19/db/add_sub_e9h.tdf ; ; +; altshift.tdf ; yes ; Megafunction ; c:/intelfpga_lite/16.1/quartus/libraries/megafunctions/altshift.tdf ; ; ++----------------------------------+-----------------+------------------------------+--------------------------------------------------------------------------------+---------+ + + ++--------------------------------------------------------------+ +; Analysis & Synthesis Resource Usage Summary ; ++---------------------------------------------+----------------+ +; Resource ; Usage ; ++---------------------------------------------+----------------+ +; Estimate of Logic utilization (ALMs needed) ; 120 ; +; ; ; +; Combinational ALUT usage for logic ; 213 ; +; -- 7 input functions ; 0 ; +; -- 6 input functions ; 11 ; +; -- 5 input functions ; 29 ; +; -- 4 input functions ; 79 ; +; -- <=3 input functions ; 94 ; +; ; ; +; Dedicated logic registers ; 125 ; +; ; ; +; I/O pins ; 41 ; +; Total MLAB memory bits ; 0 ; +; Total block memory bits ; 73728 ; +; ; ; +; Total DSP Blocks ; 0 ; +; ; ; +; Maximum fan-out node ; CLOCK_50~input ; +; Maximum fan-out ; 121 ; +; Total fan-out ; 1377 ; +; Average fan-out ; 3.21 ; ++---------------------------------------------+----------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Resource Utilization by Entity ; ++------------------------------------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------+--------------+ +; Compilation Hierarchy Node ; Combinational ALUTs ; Dedicated Logic Registers ; Block Memory Bits ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name ; Entity Name ; Library Name ; ++------------------------------------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------+--------------+ +; |ex19_top ; 213 (0) ; 125 (0) ; 73728 ; 0 ; 41 ; 0 ; |ex19_top ; ex19_top ; work ; +; |clktick_16:GEN_10K| ; 20 (20) ; 17 (17) ; 0 ; 0 ; 0 ; 0 ; |ex19_top|clktick_16:GEN_10K ; clktick_16 ; work ; +; |processor:ALLPASS| ; 136 (23) ; 25 (10) ; 73728 ; 0 ; 0 ; 0 ; |ex19_top|processor:ALLPASS ; processor ; work ; +; |RAM:DELAY1024| ; 0 (0) ; 0 (0) ; 73728 ; 0 ; 0 ; 0 ; |ex19_top|processor:ALLPASS|RAM:DELAY1024 ; RAM ; work ; +; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 73728 ; 0 ; 0 ; 0 ; |ex19_top|processor:ALLPASS|RAM:DELAY1024|altsyncram:altsyncram_component ; altsyncram ; work ; +; |altsyncram_ip02:auto_generated| ; 0 (0) ; 0 (0) ; 73728 ; 0 ; 0 ; 0 ; |ex19_top|processor:ALLPASS|RAM:DELAY1024|altsyncram:altsyncram_component|altsyncram_ip02:auto_generated ; altsyncram_ip02 ; work ; +; |bin2bcd_16:BIN0| ; 38 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex19_top|processor:ALLPASS|bin2bcd_16:BIN0 ; bin2bcd_16 ; work ; +; |add3_ge5:A12| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex19_top|processor:ALLPASS|bin2bcd_16:BIN0|add3_ge5:A12 ; add3_ge5 ; work ; +; |add3_ge5:A15| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex19_top|processor:ALLPASS|bin2bcd_16:BIN0|add3_ge5:A15 ; add3_ge5 ; work ; +; |add3_ge5:A18| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex19_top|processor:ALLPASS|bin2bcd_16:BIN0|add3_ge5:A18 ; add3_ge5 ; work ; +; |add3_ge5:A21| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex19_top|processor:ALLPASS|bin2bcd_16:BIN0|add3_ge5:A21 ; add3_ge5 ; work ; +; |add3_ge5:A22| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex19_top|processor:ALLPASS|bin2bcd_16:BIN0|add3_ge5:A22 ; add3_ge5 ; work ; +; |add3_ge5:A25| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex19_top|processor:ALLPASS|bin2bcd_16:BIN0|add3_ge5:A25 ; add3_ge5 ; work ; +; |add3_ge5:A26| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex19_top|processor:ALLPASS|bin2bcd_16:BIN0|add3_ge5:A26 ; add3_ge5 ; work ; +; |add3_ge5:A29| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex19_top|processor:ALLPASS|bin2bcd_16:BIN0|add3_ge5:A29 ; add3_ge5 ; work ; +; |add3_ge5:A30| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex19_top|processor:ALLPASS|bin2bcd_16:BIN0|add3_ge5:A30 ; add3_ge5 ; work ; +; |add3_ge5:A34| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex19_top|processor:ALLPASS|bin2bcd_16:BIN0|add3_ge5:A34 ; add3_ge5 ; work ; +; |add3_ge5:A35| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex19_top|processor:ALLPASS|bin2bcd_16:BIN0|add3_ge5:A35 ; add3_ge5 ; work ; +; |counter_13:COUNT13| ; 13 (13) ; 13 (13) ; 0 ; 0 ; 0 ; 0 ; |ex19_top|processor:ALLPASS|counter_13:COUNT13 ; counter_13 ; work ; +; |hex_to_7seg:SEG0| ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex19_top|processor:ALLPASS|hex_to_7seg:SEG0 ; hex_to_7seg ; work ; +; |hex_to_7seg:SEG1| ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex19_top|processor:ALLPASS|hex_to_7seg:SEG1 ; hex_to_7seg ; work ; +; |hex_to_7seg:SEG2| ; 13 (13) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex19_top|processor:ALLPASS|hex_to_7seg:SEG2 ; hex_to_7seg ; work ; +; |multiply_k:MULTK| ; 33 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex19_top|processor:ALLPASS|multiply_k:MULTK ; multiply_k ; work ; +; |lpm_mult:lpm_mult_component| ; 33 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex19_top|processor:ALLPASS|multiply_k:MULTK|lpm_mult:lpm_mult_component ; lpm_mult ; work ; +; |multcore:mult_core| ; 33 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex19_top|processor:ALLPASS|multiply_k:MULTK|lpm_mult:lpm_mult_component|multcore:mult_core ; multcore ; work ; +; |mpar_add:padder| ; 26 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex19_top|processor:ALLPASS|multiply_k:MULTK|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder ; mpar_add ; work ; +; |lpm_add_sub:adder[0]| ; 15 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex19_top|processor:ALLPASS|multiply_k:MULTK|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0] ; lpm_add_sub ; work ; +; |add_sub_a9h:auto_generated| ; 15 (15) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex19_top|processor:ALLPASS|multiply_k:MULTK|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_a9h:auto_generated ; add_sub_a9h ; work ; +; |mpar_add:sub_par_add| ; 11 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex19_top|processor:ALLPASS|multiply_k:MULTK|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add ; mpar_add ; work ; +; |lpm_add_sub:adder[0]| ; 11 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex19_top|processor:ALLPASS|multiply_k:MULTK|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0] ; lpm_add_sub ; work ; +; |add_sub_e9h:auto_generated| ; 11 (11) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex19_top|processor:ALLPASS|multiply_k:MULTK|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|add_sub_e9h:auto_generated ; add_sub_e9h ; work ; +; |pulse_gen:PULSE0| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; |ex19_top|processor:ALLPASS|pulse_gen:PULSE0 ; pulse_gen ; work ; +; |pwm:PWM_DC| ; 16 (16) ; 21 (21) ; 0 ; 0 ; 0 ; 0 ; |ex19_top|pwm:PWM_DC ; pwm ; work ; +; |spi2adc:SPI_ADC| ; 24 (24) ; 40 (40) ; 0 ; 0 ; 0 ; 0 ; |ex19_top|spi2adc:SPI_ADC ; spi2adc ; work ; +; |spi2dac:SPI_DAC| ; 17 (17) ; 22 (22) ; 0 ; 0 ; 0 ; 0 ; |ex19_top|spi2dac:SPI_DAC ; spi2dac ; work ; ++------------------------------------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------+--------------+ +Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis RAM Summary ; ++-----------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+-------+------+ +; Name ; Type ; Mode ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size ; MIF ; ++-----------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+-------+------+ +; processor:ALLPASS|RAM:DELAY1024|altsyncram:altsyncram_component|altsyncram_ip02:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 8192 ; 9 ; 8192 ; 9 ; 73728 ; None ; ++-----------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+-------+------+ + + ++-----------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis IP Cores Summary ; ++--------+--------------+---------+--------------+--------------+-------------------------------------------+-----------------+ +; Vendor ; IP Core Name ; Version ; Release Date ; License Type ; Entity Instance ; IP Include File ; ++--------+--------------+---------+--------------+--------------+-------------------------------------------+-----------------+ +; Altera ; RAM: 2-PORT ; 16.1 ; N/A ; N/A ; |ex19_top|processor:ALLPASS|RAM:DELAY1024 ; RAM.v ; ++--------+--------------+---------+--------------+--------------+-------------------------------------------+-----------------+ + + +Encoding Type: One-Hot ++--------------------------------------------------------------------+ +; State Machine - |ex19_top|processor:ALLPASS|pulse_gen:PULSE0|state ; ++----------------+------------+----------------+---------------------+ +; Name ; state.IDLE ; state.WAIT_LOW ; state.IN_HIGH ; ++----------------+------------+----------------+---------------------+ +; state.IDLE ; 0 ; 0 ; 0 ; +; state.IN_HIGH ; 1 ; 0 ; 1 ; +; state.WAIT_LOW ; 1 ; 1 ; 0 ; ++----------------+------------+----------------+---------------------+ + + +Encoding Type: One-Hot ++------------------------------------------------------------------------------------------+ +; State Machine - |ex19_top|spi2adc:SPI_ADC|sr_state ; ++------------------------+---------------+------------------------+------------------------+ +; Name ; sr_state.IDLE ; sr_state.WAIT_CSB_HIGH ; sr_state.WAIT_CSB_FALL ; ++------------------------+---------------+------------------------+------------------------+ +; sr_state.IDLE ; 0 ; 0 ; 0 ; +; sr_state.WAIT_CSB_FALL ; 1 ; 0 ; 1 ; +; sr_state.WAIT_CSB_HIGH ; 1 ; 1 ; 0 ; ++------------------------+---------------+------------------------+------------------------+ + + +Encoding Type: One-Hot ++------------------------------------------------------------------------------------------+ +; State Machine - |ex19_top|spi2dac:SPI_DAC|sr_state ; ++------------------------+---------------+------------------------+------------------------+ +; Name ; sr_state.IDLE ; sr_state.WAIT_CSB_HIGH ; sr_state.WAIT_CSB_FALL ; ++------------------------+---------------+------------------------+------------------------+ +; sr_state.IDLE ; 0 ; 0 ; 0 ; +; sr_state.WAIT_CSB_FALL ; 1 ; 0 ; 1 ; +; sr_state.WAIT_CSB_HIGH ; 1 ; 1 ; 0 ; ++------------------------+---------------+------------------------+------------------------+ + + ++--------------------------------------------------------------------------------------------+ +; Registers Removed During Synthesis ; ++---------------------------------------------------+----------------------------------------+ +; Register name ; Reason for Removal ; ++---------------------------------------------------+----------------------------------------+ +; spi2dac:SPI_DAC|clk_1MHz ; Merged with spi2adc:SPI_ADC|clk_1MHz ; +; spi2dac:SPI_DAC|tick ; Merged with spi2adc:SPI_ADC|tick ; +; spi2dac:SPI_DAC|ctr[4] ; Merged with spi2adc:SPI_ADC|ctr[4] ; +; spi2dac:SPI_DAC|ctr[3] ; Merged with spi2adc:SPI_ADC|ctr[3] ; +; spi2dac:SPI_DAC|ctr[2] ; Merged with spi2adc:SPI_ADC|ctr[2] ; +; spi2dac:SPI_DAC|ctr[1] ; Merged with spi2adc:SPI_ADC|ctr[1] ; +; spi2dac:SPI_DAC|ctr[0] ; Merged with spi2adc:SPI_ADC|ctr[0] ; +; spi2dac:SPI_DAC|shift_reg[0,1] ; Stuck at GND due to stuck port data_in ; +; processor:ALLPASS|pulse_gen:PULSE0|state.IN_HIGH ; Lost fanout ; +; processor:ALLPASS|pulse_gen:PULSE0|state.WAIT_LOW ; Lost fanout ; +; Total Number of Removed Registers = 11 ; ; ++---------------------------------------------------+----------------------------------------+ + + ++---------------------------------------------------------------------------------------------------+ +; Removed Registers Triggering Further Register Optimizations ; ++------------------------------+---------------------------+----------------------------------------+ +; Register name ; Reason for Removal ; Registers Removed due to This Register ; ++------------------------------+---------------------------+----------------------------------------+ +; spi2dac:SPI_DAC|shift_reg[0] ; Stuck at GND ; spi2dac:SPI_DAC|shift_reg[1] ; +; ; due to stuck port data_in ; ; ++------------------------------+---------------------------+----------------------------------------+ + + ++------------------------------------------------------+ +; General Register Statistics ; ++----------------------------------------------+-------+ +; Statistic ; Value ; ++----------------------------------------------+-------+ +; Total registers ; 125 ; +; Number of registers using Synchronous Clear ; 9 ; +; Number of registers using Synchronous Load ; 9 ; +; Number of registers using Asynchronous Clear ; 0 ; +; Number of registers using Asynchronous Load ; 0 ; +; Number of registers using Clock Enable ; 54 ; +; Number of registers using Preset ; 0 ; ++----------------------------------------------+-------+ + + ++--------------------------------------------------+ +; Inverted Register Statistics ; ++----------------------------------------+---------+ +; Inverted Register ; Fan out ; ++----------------------------------------+---------+ +; spi2adc:SPI_ADC|adc_cs ; 22 ; +; Total number of inverted registers = 1 ; ; ++----------------------------------------+---------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Multiplexer Restructuring Statistics (Restructuring Performed) ; ++--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------------------+ +; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ; ++--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------------------+ +; 3:1 ; 3 bits ; 6 LEs ; 3 LEs ; 3 LEs ; Yes ; |ex19_top|spi2dac:SPI_DAC|shift_reg[14] ; +; 3:1 ; 9 bits ; 18 LEs ; 0 LEs ; 18 LEs ; Yes ; |ex19_top|spi2dac:SPI_DAC|shift_reg[11] ; +; 6:1 ; 3 bits ; 12 LEs ; 6 LEs ; 6 LEs ; No ; |ex19_top|spi2dac:SPI_DAC|Selector2 ; ++--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------+ +; Source assignments for processor:ALLPASS|RAM:DELAY1024|altsyncram:altsyncram_component|altsyncram_ip02:auto_generated ; ++---------------------------------+--------------------+------+---------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++---------------------------------+--------------------+------+---------------------------------------------------------+ +; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ; ++---------------------------------+--------------------+------+---------------------------------------------------------+ + + ++-----------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: clktick_16:GEN_10K ; ++----------------+-------+----------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+-------+----------------------------------------+ +; N_BIT ; 16 ; Signed Integer ; ++----------------+-------+----------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++--------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: spi2dac:SPI_DAC ; ++----------------+-------+-------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+-------+-------------------------------------+ +; BUF ; 1 ; Unsigned Binary ; +; GA_N ; 1 ; Unsigned Binary ; +; SHDN_N ; 1 ; Unsigned Binary ; +; TC ; 11000 ; Unsigned Binary ; +; IDLE ; 00 ; Unsigned Binary ; +; WAIT_CSB_FALL ; 01 ; Unsigned Binary ; +; WAIT_CSB_HIGH ; 10 ; Unsigned Binary ; ++----------------+-------+-------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++--------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: spi2adc:SPI_ADC ; ++----------------+-------+-------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+-------+-------------------------------------+ +; SGL ; 1 ; Unsigned Binary ; +; MSBF ; 1 ; Unsigned Binary ; +; TIME_CONSTANT ; 11000 ; Unsigned Binary ; +; IDLE ; 00 ; Unsigned Binary ; +; WAIT_CSB_FALL ; 01 ; Unsigned Binary ; +; WAIT_CSB_HIGH ; 10 ; Unsigned Binary ; ++----------------+-------+-------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++----------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: processor:ALLPASS ; ++----------------+------------+----------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+------------+----------------------------------+ +; ADC_OFFSET ; 0110000001 ; Unsigned Binary ; +; DAC_OFFSET ; 1000000000 ; Unsigned Binary ; ++----------------+------------+----------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++---------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: processor:ALLPASS|pulse_gen:PULSE0 ; ++----------------+-------+--------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+-------+--------------------------------------------------------+ +; IDLE ; 00 ; Unsigned Binary ; +; IN_HIGH ; 01 ; Unsigned Binary ; +; WAIT_LOW ; 10 ; Unsigned Binary ; ++----------------+-------+--------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++-----------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: processor:ALLPASS|counter_13:COUNT13 ; ++----------------+-------+----------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+-------+----------------------------------------------------------+ +; BIT_SZ ; 13 ; Signed Integer ; ++----------------+-------+----------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++--------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: processor:ALLPASS|RAM:DELAY1024|altsyncram:altsyncram_component ; ++------------------------------------+----------------------+--------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------------------+----------------------+--------------------------------------------------+ +; BYTE_SIZE_BLOCK ; 8 ; Untyped ; +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; +; WIDTH_BYTEENA ; 1 ; Untyped ; +; OPERATION_MODE ; DUAL_PORT ; Untyped ; +; WIDTH_A ; 9 ; Signed Integer ; +; WIDTHAD_A ; 13 ; Signed Integer ; +; NUMWORDS_A ; 8192 ; Signed Integer ; +; OUTDATA_REG_A ; UNREGISTERED ; Untyped ; +; ADDRESS_ACLR_A ; NONE ; Untyped ; +; OUTDATA_ACLR_A ; NONE ; Untyped ; +; WRCONTROL_ACLR_A ; NONE ; Untyped ; +; INDATA_ACLR_A ; NONE ; Untyped ; +; BYTEENA_ACLR_A ; NONE ; Untyped ; +; WIDTH_B ; 9 ; Signed Integer ; +; WIDTHAD_B ; 13 ; Signed Integer ; +; NUMWORDS_B ; 8192 ; Signed Integer ; +; INDATA_REG_B ; CLOCK1 ; Untyped ; +; WRCONTROL_WRADDRESS_REG_B ; CLOCK1 ; Untyped ; +; RDCONTROL_REG_B ; CLOCK0 ; Untyped ; +; ADDRESS_REG_B ; CLOCK0 ; Untyped ; +; OUTDATA_REG_B ; CLOCK0 ; Untyped ; +; BYTEENA_REG_B ; CLOCK1 ; Untyped ; +; INDATA_ACLR_B ; NONE ; Untyped ; +; WRCONTROL_ACLR_B ; NONE ; Untyped ; +; ADDRESS_ACLR_B ; NONE ; Untyped ; +; OUTDATA_ACLR_B ; NONE ; Untyped ; +; RDCONTROL_ACLR_B ; NONE ; Untyped ; +; BYTEENA_ACLR_B ; NONE ; Untyped ; +; WIDTH_BYTEENA_A ; 1 ; Signed Integer ; +; WIDTH_BYTEENA_B ; 1 ; Untyped ; +; RAM_BLOCK_TYPE ; AUTO ; Untyped ; +; BYTE_SIZE ; 8 ; Untyped ; +; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; Untyped ; +; READ_DURING_WRITE_MODE_PORT_A ; NEW_DATA_NO_NBE_READ ; Untyped ; +; READ_DURING_WRITE_MODE_PORT_B ; NEW_DATA_NO_NBE_READ ; Untyped ; +; INIT_FILE ; UNUSED ; Untyped ; +; INIT_FILE_LAYOUT ; PORT_A ; Untyped ; +; MAXIMUM_DEPTH ; 0 ; Untyped ; +; CLOCK_ENABLE_INPUT_A ; BYPASS ; Untyped ; +; CLOCK_ENABLE_INPUT_B ; BYPASS ; Untyped ; +; CLOCK_ENABLE_OUTPUT_A ; NORMAL ; Untyped ; +; CLOCK_ENABLE_OUTPUT_B ; BYPASS ; Untyped ; +; CLOCK_ENABLE_CORE_A ; USE_INPUT_CLKEN ; Untyped ; +; CLOCK_ENABLE_CORE_B ; USE_INPUT_CLKEN ; Untyped ; +; ENABLE_ECC ; FALSE ; Untyped ; +; ECC_PIPELINE_STAGE_ENABLED ; FALSE ; Untyped ; +; WIDTH_ECCSTATUS ; 3 ; Untyped ; +; DEVICE_FAMILY ; Cyclone V ; Untyped ; +; CBXI_PARAMETER ; altsyncram_ip02 ; Untyped ; ++------------------------------------+----------------------+--------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++-------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: processor:ALLPASS|multiply_k:MULTK|lpm_mult:lpm_mult_component ; ++------------------------------------------------+-----------+------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------------------------------+-----------+------------------------------------------------+ +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; +; LPM_WIDTHA ; 9 ; Signed Integer ; +; LPM_WIDTHB ; 11 ; Signed Integer ; +; LPM_WIDTHP ; 20 ; Signed Integer ; +; LPM_WIDTHR ; 0 ; Untyped ; +; LPM_WIDTHS ; 1 ; Untyped ; +; LPM_REPRESENTATION ; UNSIGNED ; Untyped ; +; LPM_PIPELINE ; 0 ; Untyped ; +; LATENCY ; 0 ; Untyped ; +; INPUT_A_IS_CONSTANT ; NO ; Untyped ; +; INPUT_B_IS_CONSTANT ; YES ; Untyped ; +; USE_EAB ; OFF ; Untyped ; +; MAXIMIZE_SPEED ; 5 ; Untyped ; +; DEVICE_FAMILY ; Cyclone V ; Untyped ; +; CARRY_CHAIN ; MANUAL ; Untyped ; +; APEX20K_TECHNOLOGY_MAPPER ; LUT ; TECH_MAPPER_APEX20K ; +; DEDICATED_MULTIPLIER_CIRCUITRY ; AUTO ; Untyped ; +; DEDICATED_MULTIPLIER_MIN_INPUT_WIDTH_FOR_AUTO ; 0 ; Untyped ; +; DEDICATED_MULTIPLIER_MIN_OUTPUT_WIDTH_FOR_AUTO ; 0 ; Untyped ; +; CBXI_PARAMETER ; NOTHING ; Untyped ; +; INPUT_A_FIXED_VALUE ; Bx ; Untyped ; +; INPUT_B_FIXED_VALUE ; Bx ; Untyped ; +; USE_AHDL_IMPLEMENTATION ; OFF ; Untyped ; ++------------------------------------------------+-----------+------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++-------------------------------------------------------------------------------------------------------------+ +; altsyncram Parameter Settings by Entity Instance ; ++-------------------------------------------+-----------------------------------------------------------------+ +; Name ; Value ; ++-------------------------------------------+-----------------------------------------------------------------+ +; Number of entity instances ; 1 ; +; Entity Instance ; processor:ALLPASS|RAM:DELAY1024|altsyncram:altsyncram_component ; +; -- OPERATION_MODE ; DUAL_PORT ; +; -- WIDTH_A ; 9 ; +; -- NUMWORDS_A ; 8192 ; +; -- OUTDATA_REG_A ; UNREGISTERED ; +; -- WIDTH_B ; 9 ; +; -- NUMWORDS_B ; 8192 ; +; -- ADDRESS_REG_B ; CLOCK0 ; +; -- OUTDATA_REG_B ; CLOCK0 ; +; -- RAM_BLOCK_TYPE ; AUTO ; +; -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; ++-------------------------------------------+-----------------------------------------------------------------+ + + ++--------------------------------------------------------------------------------------------------------+ +; lpm_mult Parameter Settings by Entity Instance ; ++---------------------------------------+----------------------------------------------------------------+ +; Name ; Value ; ++---------------------------------------+----------------------------------------------------------------+ +; Number of entity instances ; 1 ; +; Entity Instance ; processor:ALLPASS|multiply_k:MULTK|lpm_mult:lpm_mult_component ; +; -- LPM_WIDTHA ; 9 ; +; -- LPM_WIDTHB ; 11 ; +; -- LPM_WIDTHP ; 20 ; +; -- LPM_REPRESENTATION ; UNSIGNED ; +; -- INPUT_A_IS_CONSTANT ; NO ; +; -- INPUT_B_IS_CONSTANT ; YES ; +; -- USE_EAB ; OFF ; +; -- DEDICATED_MULTIPLIER_CIRCUITRY ; AUTO ; +; -- INPUT_A_FIXED_VALUE ; Bx ; +; -- INPUT_B_FIXED_VALUE ; Bx ; ++---------------------------------------+----------------------------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "processor:ALLPASS|bin2bcd_16:BIN0|add3_ge5:A31" ; ++------+--------+----------+-------------------------------------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++------+--------+----------+-------------------------------------------------------------------------------------+ +; w[3] ; Input ; Info ; Stuck at GND ; +; a[3] ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; ++------+--------+----------+-------------------------------------------------------------------------------------+ + + ++----------------------------------------------------------------------------+ +; Port Connectivity Checks: "processor:ALLPASS|bin2bcd_16:BIN0|add3_ge5:A19" ; ++------+-------+----------+--------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++------+-------+----------+--------------------------------------------------+ +; w[3] ; Input ; Info ; Stuck at GND ; ++------+-------+----------+--------------------------------------------------+ + + ++----------------------------------------------------------------------------+ +; Port Connectivity Checks: "processor:ALLPASS|bin2bcd_16:BIN0|add3_ge5:A10" ; ++------+-------+----------+--------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++------+-------+----------+--------------------------------------------------+ +; w[3] ; Input ; Info ; Stuck at GND ; ++------+-------+----------+--------------------------------------------------+ + + ++---------------------------------------------------------------------------+ +; Port Connectivity Checks: "processor:ALLPASS|bin2bcd_16:BIN0|add3_ge5:A4" ; ++------+-------+----------+-------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++------+-------+----------+-------------------------------------------------+ +; w[3] ; Input ; Info ; Stuck at GND ; ++------+-------+----------+-------------------------------------------------+ + + ++---------------------------------------------------------------------------+ +; Port Connectivity Checks: "processor:ALLPASS|bin2bcd_16:BIN0|add3_ge5:A1" ; ++------+-------+----------+-------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++------+-------+----------+-------------------------------------------------+ +; w[3] ; Input ; Info ; Stuck at GND ; ++------+-------+----------+-------------------------------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "processor:ALLPASS|bin2bcd_16:BIN0" ; ++-------+--------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++-------+--------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------+ +; B ; Input ; Warning ; Input port expression (10 bits) is smaller than the input port (16 bits) it drives. Extra input bit(s) "B[15..10]" will be connected to GND. ; +; BCD_3 ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; +; BCD_4 ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; ++-------+--------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------+ + + ++------------------------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "processor:ALLPASS|multiply_k:MULTK" ; ++--------------+--------+----------+-------------------------------------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++--------------+--------+----------+-------------------------------------------------------------------------------------+ +; result[9..0] ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; ++--------------+--------+----------+-------------------------------------------------------------------------------------+ + + ++------------------------------------------------------------------+ +; Port Connectivity Checks: "processor:ALLPASS|counter_13:COUNT13" ; ++--------+-------+----------+--------------------------------------+ +; Port ; Type ; Severity ; Details ; ++--------+-------+----------+--------------------------------------+ +; enable ; Input ; Info ; Stuck at GND ; +; reset ; Input ; Info ; Stuck at VCC ; ++--------+-------+----------+--------------------------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "processor:ALLPASS" ; ++------+-------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++------+-------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; SW ; Input ; Warning ; Input port expression (10 bits) is wider than the input port (9 bits) it drives. The 1 most-significant bit(s) in the expression will be dangling if they have no other fanouts. ; ++------+-------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + + ++---------------------------------------------+ +; Port Connectivity Checks: "spi2adc:SPI_ADC" ; ++---------+-------+----------+----------------+ +; Port ; Type ; Severity ; Details ; ++---------+-------+----------+----------------+ +; channel ; Input ; Info ; Stuck at VCC ; ++---------+-------+----------+----------------+ + + ++------------------------------------------------+ +; Port Connectivity Checks: "clktick_16:GEN_10K" ; ++-----------+-------+----------+-----------------+ +; Port ; Type ; Severity ; Details ; ++-----------+-------+----------+-----------------+ +; enable ; Input ; Info ; Stuck at VCC ; +; N[9..7] ; Input ; Info ; Stuck at VCC ; +; N[2..0] ; Input ; Info ; Stuck at VCC ; +; N[15..13] ; Input ; Info ; Stuck at GND ; +; N[11..10] ; Input ; Info ; Stuck at GND ; +; N[6..3] ; Input ; Info ; Stuck at GND ; +; N[12] ; Input ; Info ; Stuck at VCC ; ++-----------+-------+----------+-----------------+ + + ++-----------------------------------------------------+ +; Post-Synthesis Netlist Statistics for Top Partition ; ++-----------------------+-----------------------------+ +; Type ; Count ; ++-----------------------+-----------------------------+ +; arriav_ff ; 125 ; +; ENA ; 45 ; +; ENA SLD ; 9 ; +; SCLR ; 9 ; +; plain ; 62 ; +; arriav_lcell_comb ; 224 ; +; arith ; 85 ; +; 0 data inputs ; 2 ; +; 1 data inputs ; 42 ; +; 2 data inputs ; 27 ; +; 3 data inputs ; 1 ; +; 4 data inputs ; 5 ; +; 5 data inputs ; 8 ; +; normal ; 139 ; +; 1 data inputs ; 15 ; +; 2 data inputs ; 10 ; +; 3 data inputs ; 8 ; +; 4 data inputs ; 74 ; +; 5 data inputs ; 21 ; +; 6 data inputs ; 11 ; +; boundary_port ; 41 ; +; stratixv_ram_block ; 9 ; +; ; ; +; Max LUT depth ; 13.30 ; +; Average LUT depth ; 5.01 ; ++-----------------------+-----------------------------+ + + ++-------------------------------+ +; Elapsed Time Per Partition ; ++----------------+--------------+ +; Partition Name ; Elapsed Time ; ++----------------+--------------+ +; Top ; 00:00:02 ; ++----------------+--------------+ + + ++-------------------------------+ +; Analysis & Synthesis Messages ; ++-------------------------------+ +Info: ******************************************************************* +Info: Running Quartus Prime Analysis & Synthesis + Info: Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition + Info: Processing started: Sat Dec 10 19:20:02 2016 +Info: Command: quartus_map --read_settings_files=on --write_settings_files=off ex19 -c ex19_top +Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. +Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected +Info (12021): Found 1 design units, including 1 entities, in source file variable_echo.v + Info (12023): Found entity 1: processor File: H:/Year 2/VERI/part_4/ex19/variable_echo.v Line: 1 +Info (12021): Found 1 design units, including 1 entities, in source file ex19_top.v + Info (12023): Found entity 1: ex19_top File: H:/Year 2/VERI/part_4/ex19/ex19_top.v Line: 1 +Info (12021): Found 1 design units, including 1 entities, in source file /year 2/veri/part_4/mylib/spi2dac.v + Info (12023): Found entity 1: spi2dac File: H:/Year 2/VERI/part_4/mylib/spi2dac.v Line: 9 +Info (12021): Found 1 design units, including 1 entities, in source file /year 2/veri/part_4/mylib/spi2adc.v + Info (12023): Found entity 1: spi2adc File: H:/Year 2/VERI/part_4/mylib/spi2adc.v Line: 9 +Info (12021): Found 1 design units, including 1 entities, in source file /year 2/veri/part_4/mylib/pwm.v + Info (12023): Found entity 1: pwm File: H:/Year 2/VERI/part_4/mylib/pwm.v Line: 1 +Info (12021): Found 1 design units, including 1 entities, in source file /year 2/veri/part_4/mylib/pulse_gen.v + Info (12023): Found entity 1: pulse_gen File: H:/Year 2/VERI/part_4/mylib/pulse_gen.v Line: 9 +Info (12021): Found 1 design units, including 1 entities, in source file /year 2/veri/part_4/mylib/multiply_k.v + Info (12023): Found entity 1: multiply_k File: H:/Year 2/VERI/part_4/mylib/multiply_k.v Line: 39 +Info (12021): Found 1 design units, including 1 entities, in source file /year 2/veri/part_4/mylib/multiply_4.v + Info (12023): Found entity 1: multiply_4 File: H:/Year 2/VERI/part_4/mylib/multiply_4.v Line: 39 +Info (12021): Found 1 design units, including 1 entities, in source file /year 2/veri/part_4/mylib/hex_to_7seg.v + Info (12023): Found entity 1: hex_to_7seg File: H:/Year 2/VERI/part_4/mylib/hex_to_7seg.v Line: 10 +Info (12021): Found 1 design units, including 1 entities, in source file /year 2/veri/part_4/mylib/counter_13.v + Info (12023): Found entity 1: counter_13 File: H:/Year 2/VERI/part_4/mylib/counter_13.v Line: 3 +Info (12021): Found 1 design units, including 1 entities, in source file /year 2/veri/part_4/mylib/clktick_16.v + Info (12023): Found entity 1: clktick_16 File: H:/Year 2/VERI/part_4/mylib/clktick_16.v Line: 6 +Info (12021): Found 1 design units, including 1 entities, in source file /year 2/veri/part_4/mylib/bin2bcd_16.v + Info (12023): Found entity 1: bin2bcd_16 File: H:/Year 2/VERI/part_4/mylib/bin2bcd_16.v Line: 12 +Info (12021): Found 1 design units, including 1 entities, in source file /year 2/veri/part_4/mylib/add3_ge5.v + Info (12023): Found entity 1: add3_ge5 File: H:/Year 2/VERI/part_4/mylib/add3_ge5.v Line: 9 +Info (12021): Found 1 design units, including 1 entities, in source file ram.v + Info (12023): Found entity 1: RAM File: H:/Year 2/VERI/part_4/ex19/RAM.v Line: 40 +Info (12127): Elaborating entity "ex19_top" for the top level hierarchy +Info (12128): Elaborating entity "clktick_16" for hierarchy "clktick_16:GEN_10K" File: H:/Year 2/VERI/part_4/ex19/ex19_top.v Line: 24 +Info (12128): Elaborating entity "spi2dac" for hierarchy "spi2dac:SPI_DAC" File: H:/Year 2/VERI/part_4/ex19/ex19_top.v Line: 26 +Info (12128): Elaborating entity "pwm" for hierarchy "pwm:PWM_DC" File: H:/Year 2/VERI/part_4/ex19/ex19_top.v Line: 27 +Info (12128): Elaborating entity "spi2adc" for hierarchy "spi2adc:SPI_ADC" File: H:/Year 2/VERI/part_4/ex19/ex19_top.v Line: 38 +Info (12128): Elaborating entity "processor" for hierarchy "processor:ALLPASS" File: H:/Year 2/VERI/part_4/ex19/ex19_top.v Line: 40 +Info (12128): Elaborating entity "pulse_gen" for hierarchy "processor:ALLPASS|pulse_gen:PULSE0" File: H:/Year 2/VERI/part_4/ex19/variable_echo.v Line: 27 +Info (12128): Elaborating entity "counter_13" for hierarchy "processor:ALLPASS|counter_13:COUNT13" File: H:/Year 2/VERI/part_4/ex19/variable_echo.v Line: 34 +Info (12128): Elaborating entity "RAM" for hierarchy "processor:ALLPASS|RAM:DELAY1024" File: H:/Year 2/VERI/part_4/ex19/variable_echo.v Line: 44 +Info (12128): Elaborating entity "altsyncram" for hierarchy "processor:ALLPASS|RAM:DELAY1024|altsyncram:altsyncram_component" File: H:/Year 2/VERI/part_4/ex19/RAM.v Line: 92 +Info (12130): Elaborated megafunction instantiation "processor:ALLPASS|RAM:DELAY1024|altsyncram:altsyncram_component" File: H:/Year 2/VERI/part_4/ex19/RAM.v Line: 92 +Info (12133): Instantiated megafunction "processor:ALLPASS|RAM:DELAY1024|altsyncram:altsyncram_component" with the following parameter: File: H:/Year 2/VERI/part_4/ex19/RAM.v Line: 92 + Info (12134): Parameter "address_aclr_b" = "NONE" + Info (12134): Parameter "address_reg_b" = "CLOCK0" + Info (12134): Parameter "clock_enable_input_a" = "BYPASS" + Info (12134): Parameter "clock_enable_input_b" = "BYPASS" + Info (12134): Parameter "clock_enable_output_b" = "BYPASS" + Info (12134): Parameter "intended_device_family" = "Cyclone V" + Info (12134): Parameter "lpm_type" = "altsyncram" + Info (12134): Parameter "numwords_a" = "8192" + Info (12134): Parameter "numwords_b" = "8192" + Info (12134): Parameter "operation_mode" = "DUAL_PORT" + Info (12134): Parameter "outdata_aclr_b" = "NONE" + Info (12134): Parameter "outdata_reg_b" = "CLOCK0" + Info (12134): Parameter "power_up_uninitialized" = "FALSE" + Info (12134): Parameter "rdcontrol_reg_b" = "CLOCK0" + Info (12134): Parameter "read_during_write_mode_mixed_ports" = "DONT_CARE" + Info (12134): Parameter "widthad_a" = "13" + Info (12134): Parameter "widthad_b" = "13" + Info (12134): Parameter "width_a" = "9" + Info (12134): Parameter "width_b" = "9" + Info (12134): Parameter "width_byteena_a" = "1" +Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_ip02.tdf + Info (12023): Found entity 1: altsyncram_ip02 File: H:/Year 2/VERI/part_4/ex19/db/altsyncram_ip02.tdf Line: 28 +Info (12128): Elaborating entity "altsyncram_ip02" for hierarchy "processor:ALLPASS|RAM:DELAY1024|altsyncram:altsyncram_component|altsyncram_ip02:auto_generated" File: c:/intelfpga_lite/16.1/quartus/libraries/megafunctions/altsyncram.tdf Line: 792 +Info (12128): Elaborating entity "multiply_k" for hierarchy "processor:ALLPASS|multiply_k:MULTK" File: H:/Year 2/VERI/part_4/ex19/variable_echo.v Line: 46 +Info (12128): Elaborating entity "lpm_mult" for hierarchy "processor:ALLPASS|multiply_k:MULTK|lpm_mult:lpm_mult_component" File: H:/Year 2/VERI/part_4/mylib/multiply_k.v Line: 57 +Info (12130): Elaborated megafunction instantiation "processor:ALLPASS|multiply_k:MULTK|lpm_mult:lpm_mult_component" File: H:/Year 2/VERI/part_4/mylib/multiply_k.v Line: 57 +Info (12133): Instantiated megafunction "processor:ALLPASS|multiply_k:MULTK|lpm_mult:lpm_mult_component" with the following parameter: File: H:/Year 2/VERI/part_4/mylib/multiply_k.v Line: 57 + Info (12134): Parameter "lpm_hint" = "INPUT_B_IS_CONSTANT=YES,MAXIMIZE_SPEED=5" + Info (12134): Parameter "lpm_representation" = "UNSIGNED" + Info (12134): Parameter "lpm_type" = "LPM_MULT" + Info (12134): Parameter "lpm_widtha" = "9" + Info (12134): Parameter "lpm_widthb" = "11" + Info (12134): Parameter "lpm_widthp" = "20" +Info (12128): Elaborating entity "multcore" for hierarchy "processor:ALLPASS|multiply_k:MULTK|lpm_mult:lpm_mult_component|multcore:mult_core" File: c:/intelfpga_lite/16.1/quartus/libraries/megafunctions/lpm_mult.tdf Line: 309 +Info (12131): Elaborated megafunction instantiation "processor:ALLPASS|multiply_k:MULTK|lpm_mult:lpm_mult_component|multcore:mult_core", which is child of megafunction instantiation "processor:ALLPASS|multiply_k:MULTK|lpm_mult:lpm_mult_component" File: c:/intelfpga_lite/16.1/quartus/libraries/megafunctions/lpm_mult.tdf Line: 309 +Info (12128): Elaborating entity "mpar_add" for hierarchy "processor:ALLPASS|multiply_k:MULTK|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder" File: c:/intelfpga_lite/16.1/quartus/libraries/megafunctions/multcore.tdf Line: 229 +Info (12131): Elaborated megafunction instantiation "processor:ALLPASS|multiply_k:MULTK|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder", which is child of megafunction instantiation "processor:ALLPASS|multiply_k:MULTK|lpm_mult:lpm_mult_component" File: c:/intelfpga_lite/16.1/quartus/libraries/megafunctions/multcore.tdf Line: 229 +Info (12128): Elaborating entity "lpm_add_sub" for hierarchy "processor:ALLPASS|multiply_k:MULTK|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]" File: c:/intelfpga_lite/16.1/quartus/libraries/megafunctions/mpar_add.tdf Line: 78 +Info (12131): Elaborated megafunction instantiation "processor:ALLPASS|multiply_k:MULTK|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]", which is child of megafunction instantiation "processor:ALLPASS|multiply_k:MULTK|lpm_mult:lpm_mult_component" File: c:/intelfpga_lite/16.1/quartus/libraries/megafunctions/mpar_add.tdf Line: 78 +Info (12021): Found 1 design units, including 1 entities, in source file db/add_sub_a9h.tdf + Info (12023): Found entity 1: add_sub_a9h File: H:/Year 2/VERI/part_4/ex19/db/add_sub_a9h.tdf Line: 23 +Info (12128): Elaborating entity "add_sub_a9h" for hierarchy "processor:ALLPASS|multiply_k:MULTK|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_a9h:auto_generated" File: c:/intelfpga_lite/16.1/quartus/libraries/megafunctions/lpm_add_sub.tdf Line: 119 +Info (12128): Elaborating entity "mpar_add" for hierarchy "processor:ALLPASS|multiply_k:MULTK|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add" File: c:/intelfpga_lite/16.1/quartus/libraries/megafunctions/mpar_add.tdf Line: 138 +Info (12131): Elaborated megafunction instantiation "processor:ALLPASS|multiply_k:MULTK|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add", which is child of megafunction instantiation "processor:ALLPASS|multiply_k:MULTK|lpm_mult:lpm_mult_component" File: c:/intelfpga_lite/16.1/quartus/libraries/megafunctions/mpar_add.tdf Line: 138 +Info (12128): Elaborating entity "lpm_add_sub" for hierarchy "processor:ALLPASS|multiply_k:MULTK|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]" File: c:/intelfpga_lite/16.1/quartus/libraries/megafunctions/mpar_add.tdf Line: 78 +Info (12131): Elaborated megafunction instantiation "processor:ALLPASS|multiply_k:MULTK|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]", which is child of megafunction instantiation "processor:ALLPASS|multiply_k:MULTK|lpm_mult:lpm_mult_component" File: c:/intelfpga_lite/16.1/quartus/libraries/megafunctions/mpar_add.tdf Line: 78 +Info (12021): Found 1 design units, including 1 entities, in source file db/add_sub_e9h.tdf + Info (12023): Found entity 1: add_sub_e9h File: H:/Year 2/VERI/part_4/ex19/db/add_sub_e9h.tdf Line: 23 +Info (12128): Elaborating entity "add_sub_e9h" for hierarchy "processor:ALLPASS|multiply_k:MULTK|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|add_sub_e9h:auto_generated" File: c:/intelfpga_lite/16.1/quartus/libraries/megafunctions/lpm_add_sub.tdf Line: 119 +Info (12128): Elaborating entity "altshift" for hierarchy "processor:ALLPASS|multiply_k:MULTK|lpm_mult:lpm_mult_component|altshift:external_latency_ffs" File: c:/intelfpga_lite/16.1/quartus/libraries/megafunctions/lpm_mult.tdf Line: 352 +Info (12131): Elaborated megafunction instantiation "processor:ALLPASS|multiply_k:MULTK|lpm_mult:lpm_mult_component|altshift:external_latency_ffs", which is child of megafunction instantiation "processor:ALLPASS|multiply_k:MULTK|lpm_mult:lpm_mult_component" File: c:/intelfpga_lite/16.1/quartus/libraries/megafunctions/lpm_mult.tdf Line: 352 +Info (12128): Elaborating entity "bin2bcd_16" for hierarchy "processor:ALLPASS|bin2bcd_16:BIN0" File: H:/Year 2/VERI/part_4/ex19/variable_echo.v Line: 48 +Info (12128): Elaborating entity "add3_ge5" for hierarchy "processor:ALLPASS|bin2bcd_16:BIN0|add3_ge5:A1" File: H:/Year 2/VERI/part_4/mylib/bin2bcd_16.v Line: 26 +Info (12128): Elaborating entity "hex_to_7seg" for hierarchy "processor:ALLPASS|hex_to_7seg:SEG0" File: H:/Year 2/VERI/part_4/ex19/variable_echo.v Line: 50 +Warning (12241): 2 hierarchies have connectivity warnings - see the Connectivity Checks report folder +Info (286030): Timing-Driven Synthesis is running +Info (17049): 2 registers lost all their fanouts during netlist optimizations. +Info (144001): Generated suppressed messages file H:/Year 2/VERI/part_4/ex19/output_files/ex19_top.map.smsg +Info (16010): Generating hard_block partition "hard_block:auto_generated_inst" + Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL +Warning (21074): Design contains 1 input pin(s) that do not drive logic + Warning (15610): No output dependent on input pin "SW[9]" File: H:/Year 2/VERI/part_4/ex19/ex19_top.v Line: 6 +Info (21057): Implemented 311 device resources after synthesis - the final resource count might be different + Info (21058): Implemented 12 input pins + Info (21059): Implemented 29 output pins + Info (21061): Implemented 261 logic cells + Info (21064): Implemented 9 RAM segments +Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 4 warnings + Info: Peak virtual memory: 722 megabytes + Info: Processing ended: Sat Dec 10 19:21:22 2016 + Info: Elapsed time: 00:01:20 + Info: Total CPU time (on all processors): 00:00:39 + + ++------------------------------------------+ +; Analysis & Synthesis Suppressed Messages ; ++------------------------------------------+ +The suppressed messages can be found in H:/Year 2/VERI/part_4/ex19/output_files/ex19_top.map.smsg. + + diff --git a/part_4/ex19/output_files/ex19_top.sta.rpt b/part_4/ex19/output_files/ex19_top.sta.rpt new file mode 100644 index 0000000..fc18c29 --- /dev/null +++ b/part_4/ex19/output_files/ex19_top.sta.rpt @@ -0,0 +1,820 @@ +TimeQuest Timing Analyzer report for ex19_top +Sat Dec 10 19:28:16 2016 +Quartus Prime Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. TimeQuest Timing Analyzer Summary + 3. Parallel Compilation + 4. SDC File List + 5. Clocks + 6. Slow 1100mV 85C Model Fmax Summary + 7. Timing Closure Recommendations + 8. Slow 1100mV 85C Model Setup Summary + 9. Slow 1100mV 85C Model Hold Summary + 10. Slow 1100mV 85C Model Recovery Summary + 11. Slow 1100mV 85C Model Removal Summary + 12. Slow 1100mV 85C Model Minimum Pulse Width Summary + 13. Slow 1100mV 85C Model Metastability Summary + 14. Slow 1100mV 0C Model Fmax Summary + 15. Slow 1100mV 0C Model Setup Summary + 16. Slow 1100mV 0C Model Hold Summary + 17. Slow 1100mV 0C Model Recovery Summary + 18. Slow 1100mV 0C Model Removal Summary + 19. Slow 1100mV 0C Model Minimum Pulse Width Summary + 20. Slow 1100mV 0C Model Metastability Summary + 21. Fast 1100mV 85C Model Setup Summary + 22. Fast 1100mV 85C Model Hold Summary + 23. Fast 1100mV 85C Model Recovery Summary + 24. Fast 1100mV 85C Model Removal Summary + 25. Fast 1100mV 85C Model Minimum Pulse Width Summary + 26. Fast 1100mV 85C Model Metastability Summary + 27. Fast 1100mV 0C Model Setup Summary + 28. Fast 1100mV 0C Model Hold Summary + 29. Fast 1100mV 0C Model Recovery Summary + 30. Fast 1100mV 0C Model Removal Summary + 31. Fast 1100mV 0C Model Minimum Pulse Width Summary + 32. Fast 1100mV 0C Model Metastability Summary + 33. Multicorner Timing Analysis Summary + 34. Board Trace Model Assignments + 35. Input Transition Times + 36. Signal Integrity Metrics (Slow 1100mv 0c Model) + 37. Signal Integrity Metrics (Slow 1100mv 85c Model) + 38. Signal Integrity Metrics (Fast 1100mv 0c Model) + 39. Signal Integrity Metrics (Fast 1100mv 85c Model) + 40. Setup Transfers + 41. Hold Transfers + 42. Report TCCS + 43. Report RSKM + 44. Unconstrained Paths Summary + 45. Clock Status Summary + 46. Unconstrained Input Ports + 47. Unconstrained Output Ports + 48. Unconstrained Input Ports + 49. Unconstrained Output Ports + 50. TimeQuest Timing Analyzer Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2016 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel MegaCore Function License Agreement, or other +applicable license agreement, including, without limitation, +that your use is for the sole purpose of programming logic +devices manufactured by Intel and sold by Intel or its +authorized distributors. Please refer to the applicable +agreement for further details. + + + ++-----------------------------------------------------------------------------+ +; TimeQuest Timing Analyzer Summary ; ++-----------------------+-----------------------------------------------------+ +; Quartus Prime Version ; Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition ; +; Timing Analyzer ; TimeQuest ; +; Revision Name ; ex19_top ; +; Device Family ; Cyclone V ; +; Device Name ; 5CSEMA5F31C6 ; +; Timing Models ; Final ; +; Delay Model ; Combined ; +; Rise/Fall Delays ; Enabled ; ++-----------------------+-----------------------------------------------------+ + + ++------------------------------------------+ +; Parallel Compilation ; ++----------------------------+-------------+ +; Processors ; Number ; ++----------------------------+-------------+ +; Number detected on machine ; 2 ; +; Maximum allowed ; 2 ; +; ; ; +; Average used ; 1.02 ; +; Maximum used ; 2 ; +; ; ; +; Usage by Processor ; % Time Used ; +; Processor 1 ; 100.0% ; +; Processor 2 ; 2.2% ; ++----------------------------+-------------+ + + ++---------------------------------------------------+ +; SDC File List ; ++---------------+--------+--------------------------+ +; SDC File Path ; Status ; Read at ; ++---------------+--------+--------------------------+ +; ex19_top.sdc ; OK ; Sat Dec 10 19:27:14 2016 ; ++---------------+--------+--------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Clocks ; ++------------+------+--------+-----------+-------+--------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+--------------+ +; Clock Name ; Type ; Period ; Frequency ; Rise ; Fall ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets ; ++------------+------+--------+-----------+-------+--------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+--------------+ +; CLOCK_50 ; Base ; 20.000 ; 50.0 MHz ; 0.000 ; 10.000 ; ; ; ; ; ; ; ; ; ; ; { CLOCK_50 } ; ++------------+------+--------+-----------+-------+--------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+--------------+ + + ++--------------------------------------------------+ +; Slow 1100mV 85C Model Fmax Summary ; ++------------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++------------+-----------------+------------+------+ +; 153.75 MHz ; 153.75 MHz ; CLOCK_50 ; ; ++------------+-----------------+------------+------+ +This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis. + + +---------------------------------- +; Timing Closure Recommendations ; +---------------------------------- +HTML report is unavailable in plain text report export. + + ++-------------------------------------+ +; Slow 1100mV 85C Model Setup Summary ; ++----------+-------+------------------+ +; Clock ; Slack ; End Point TNS ; ++----------+-------+------------------+ +; CLOCK_50 ; 6.748 ; 0.000 ; ++----------+-------+------------------+ + + ++------------------------------------+ +; Slow 1100mV 85C Model Hold Summary ; ++----------+-------+-----------------+ +; Clock ; Slack ; End Point TNS ; ++----------+-------+-----------------+ +; CLOCK_50 ; 0.362 ; 0.000 ; ++----------+-------+-----------------+ + + +------------------------------------------ +; Slow 1100mV 85C Model Recovery Summary ; +------------------------------------------ +No paths to report. + + +----------------------------------------- +; Slow 1100mV 85C Model Removal Summary ; +----------------------------------------- +No paths to report. + + ++---------------------------------------------------+ +; Slow 1100mV 85C Model Minimum Pulse Width Summary ; ++----------+-------+--------------------------------+ +; Clock ; Slack ; End Point TNS ; ++----------+-------+--------------------------------+ +; CLOCK_50 ; 8.774 ; 0.000 ; ++----------+-------+--------------------------------+ + + +----------------------------------------------- +; Slow 1100mV 85C Model Metastability Summary ; +----------------------------------------------- +No synchronizer chains to report. + + ++--------------------------------------------------+ +; Slow 1100mV 0C Model Fmax Summary ; ++------------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++------------+-----------------+------------+------+ +; 156.27 MHz ; 156.27 MHz ; CLOCK_50 ; ; ++------------+-----------------+------------+------+ +This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis. + + ++------------------------------------+ +; Slow 1100mV 0C Model Setup Summary ; ++----------+-------+-----------------+ +; Clock ; Slack ; End Point TNS ; ++----------+-------+-----------------+ +; CLOCK_50 ; 7.062 ; 0.000 ; ++----------+-------+-----------------+ + + ++-----------------------------------+ +; Slow 1100mV 0C Model Hold Summary ; ++----------+-------+----------------+ +; Clock ; Slack ; End Point TNS ; ++----------+-------+----------------+ +; CLOCK_50 ; 0.173 ; 0.000 ; ++----------+-------+----------------+ + + +----------------------------------------- +; Slow 1100mV 0C Model Recovery Summary ; +----------------------------------------- +No paths to report. + + +---------------------------------------- +; Slow 1100mV 0C Model Removal Summary ; +---------------------------------------- +No paths to report. + + ++--------------------------------------------------+ +; Slow 1100mV 0C Model Minimum Pulse Width Summary ; ++----------+-------+-------------------------------+ +; Clock ; Slack ; End Point TNS ; ++----------+-------+-------------------------------+ +; CLOCK_50 ; 8.756 ; 0.000 ; ++----------+-------+-------------------------------+ + + +---------------------------------------------- +; Slow 1100mV 0C Model Metastability Summary ; +---------------------------------------------- +No synchronizer chains to report. + + ++-------------------------------------+ +; Fast 1100mV 85C Model Setup Summary ; ++----------+-------+------------------+ +; Clock ; Slack ; End Point TNS ; ++----------+-------+------------------+ +; CLOCK_50 ; 8.262 ; 0.000 ; ++----------+-------+------------------+ + + ++------------------------------------+ +; Fast 1100mV 85C Model Hold Summary ; ++----------+-------+-----------------+ +; Clock ; Slack ; End Point TNS ; ++----------+-------+-----------------+ +; CLOCK_50 ; 0.164 ; 0.000 ; ++----------+-------+-----------------+ + + +------------------------------------------ +; Fast 1100mV 85C Model Recovery Summary ; +------------------------------------------ +No paths to report. + + +----------------------------------------- +; Fast 1100mV 85C Model Removal Summary ; +----------------------------------------- +No paths to report. + + ++---------------------------------------------------+ +; Fast 1100mV 85C Model Minimum Pulse Width Summary ; ++----------+-------+--------------------------------+ +; Clock ; Slack ; End Point TNS ; ++----------+-------+--------------------------------+ +; CLOCK_50 ; 8.476 ; 0.000 ; ++----------+-------+--------------------------------+ + + +----------------------------------------------- +; Fast 1100mV 85C Model Metastability Summary ; +----------------------------------------------- +No synchronizer chains to report. + + ++------------------------------------+ +; Fast 1100mV 0C Model Setup Summary ; ++----------+-------+-----------------+ +; Clock ; Slack ; End Point TNS ; ++----------+-------+-----------------+ +; CLOCK_50 ; 8.301 ; 0.000 ; ++----------+-------+-----------------+ + + ++-----------------------------------+ +; Fast 1100mV 0C Model Hold Summary ; ++----------+-------+----------------+ +; Clock ; Slack ; End Point TNS ; ++----------+-------+----------------+ +; CLOCK_50 ; 0.064 ; 0.000 ; ++----------+-------+----------------+ + + +----------------------------------------- +; Fast 1100mV 0C Model Recovery Summary ; +----------------------------------------- +No paths to report. + + +---------------------------------------- +; Fast 1100mV 0C Model Removal Summary ; +---------------------------------------- +No paths to report. + + ++--------------------------------------------------+ +; Fast 1100mV 0C Model Minimum Pulse Width Summary ; ++----------+-------+-------------------------------+ +; Clock ; Slack ; End Point TNS ; ++----------+-------+-------------------------------+ +; CLOCK_50 ; 8.431 ; 0.000 ; ++----------+-------+-------------------------------+ + + +---------------------------------------------- +; Fast 1100mV 0C Model Metastability Summary ; +---------------------------------------------- +No synchronizer chains to report. + + ++-----------------------------------------------------------------------------+ +; Multicorner Timing Analysis Summary ; ++------------------+-------+-------+----------+---------+---------------------+ +; Clock ; Setup ; Hold ; Recovery ; Removal ; Minimum Pulse Width ; ++------------------+-------+-------+----------+---------+---------------------+ +; Worst-case Slack ; 6.748 ; 0.064 ; N/A ; N/A ; 8.431 ; +; CLOCK_50 ; 6.748 ; 0.064 ; N/A ; N/A ; 8.431 ; +; Design-wide TNS ; 0.0 ; 0.0 ; 0.0 ; 0.0 ; 0.0 ; +; CLOCK_50 ; 0.000 ; 0.000 ; N/A ; N/A ; 0.000 ; ++------------------+-------+-------+----------+---------+---------------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Board Trace Model Assignments ; ++---------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ +; Pin ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ; ++---------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ +; HEX0[0] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX0[1] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX0[2] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX0[3] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX0[4] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX0[5] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX0[6] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX1[0] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX1[1] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX1[2] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX1[3] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX1[4] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX1[5] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX1[6] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX2[0] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX2[1] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX2[2] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX2[3] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX2[4] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX2[5] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX2[6] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DAC_SDI ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DAC_SCK ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DAC_CS ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DAC_LD ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; ADC_SDI ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; ADC_SCK ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; ADC_CS ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; PWM_OUT ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; ++---------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ + + ++-------------------------------------------------------------+ +; Input Transition Times ; ++----------+--------------+-----------------+-----------------+ +; Pin ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ; ++----------+--------------+-----------------+-----------------+ +; SW[9] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; SW[8] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; CLOCK_50 ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; SW[6] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; SW[5] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; SW[4] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; SW[3] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; SW[2] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; SW[1] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; SW[0] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; SW[7] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; ADC_SDO ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; ++----------+--------------+-----------------+-----------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Signal Integrity Metrics (Slow 1100mv 0c Model) ; ++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; ++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; HEX0[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; +; HEX0[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; +; HEX0[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; +; HEX0[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; +; HEX0[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; +; HEX0[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; +; HEX0[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; +; HEX1[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; +; HEX1[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; +; HEX1[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; +; HEX1[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; +; HEX1[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; +; HEX1[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; +; HEX1[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; +; HEX2[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ; +; HEX2[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; +; HEX2[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; +; HEX2[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; +; HEX2[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; +; HEX2[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; +; HEX2[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; +; DAC_SDI ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; +; DAC_SCK ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ; +; DAC_CS ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ; +; DAC_LD ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; +; ADC_SDI ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ; +; ADC_SCK ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ; +; ADC_CS ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ; +; PWM_OUT ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; ++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Signal Integrity Metrics (Slow 1100mv 85c Model) ; ++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; ++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; HEX0[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; +; HEX0[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; +; HEX0[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; +; HEX0[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; +; HEX0[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; +; HEX0[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; +; HEX0[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; +; HEX1[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; +; HEX1[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; +; HEX1[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; +; HEX1[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; +; HEX1[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; +; HEX1[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; +; HEX1[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; +; HEX2[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ; +; HEX2[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; +; HEX2[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; +; HEX2[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; +; HEX2[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; +; HEX2[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; +; HEX2[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; +; DAC_SDI ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; +; DAC_SCK ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ; +; DAC_CS ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ; +; DAC_LD ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; +; ADC_SDI ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ; +; ADC_SCK ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ; +; ADC_CS ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ; +; PWM_OUT ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; ++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Signal Integrity Metrics (Fast 1100mv 0c Model) ; ++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; ++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; HEX0[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; +; HEX0[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; +; HEX0[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; +; HEX0[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; +; HEX0[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; +; HEX0[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; +; HEX0[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; +; HEX1[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; +; HEX1[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; +; HEX1[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; +; HEX1[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; +; HEX1[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; +; HEX1[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; +; HEX1[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; +; HEX2[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ; +; HEX2[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; +; HEX2[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; +; HEX2[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; +; HEX2[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; +; HEX2[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; +; HEX2[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; +; DAC_SDI ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; +; DAC_SCK ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ; +; DAC_CS ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ; +; DAC_LD ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; +; ADC_SDI ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ; +; ADC_SCK ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ; +; ADC_CS ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ; +; PWM_OUT ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; ++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Signal Integrity Metrics (Fast 1100mv 85c Model) ; ++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; ++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; HEX0[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; +; HEX0[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; +; HEX0[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; +; HEX0[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; +; HEX0[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; +; HEX0[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; +; HEX0[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; +; HEX1[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; +; HEX1[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; +; HEX1[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; +; HEX1[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; +; HEX1[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; +; HEX1[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; +; HEX1[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; +; HEX2[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ; +; HEX2[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; +; HEX2[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; +; HEX2[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; +; HEX2[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; +; HEX2[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; +; HEX2[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; +; DAC_SDI ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; +; DAC_SCK ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ; +; DAC_CS ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ; +; DAC_LD ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; +; ADC_SDI ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ; +; ADC_SCK ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ; +; ADC_CS ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ; +; PWM_OUT ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; ++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ + + ++-------------------------------------------------------------------+ +; Setup Transfers ; ++------------+----------+----------+----------+----------+----------+ +; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; ++------------+----------+----------+----------+----------+----------+ +; CLOCK_50 ; CLOCK_50 ; 3511 ; 10 ; 30 ; 9 ; ++------------+----------+----------+----------+----------+----------+ +Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. + + ++-------------------------------------------------------------------+ +; Hold Transfers ; ++------------+----------+----------+----------+----------+----------+ +; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; ++------------+----------+----------+----------+----------+----------+ +; CLOCK_50 ; CLOCK_50 ; 3511 ; 10 ; 30 ; 9 ; ++------------+----------+----------+----------+----------+----------+ +Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. + + +--------------- +; Report TCCS ; +--------------- +No dedicated SERDES Transmitter circuitry present in device or used in design + + +--------------- +; Report RSKM ; +--------------- +No non-DPA dedicated SERDES Receiver circuitry present in device or used in design + + ++------------------------------------------------+ +; Unconstrained Paths Summary ; ++---------------------------------+-------+------+ +; Property ; Setup ; Hold ; ++---------------------------------+-------+------+ +; Illegal Clocks ; 0 ; 0 ; +; Unconstrained Clocks ; 1 ; 1 ; +; Unconstrained Input Ports ; 10 ; 10 ; +; Unconstrained Input Port Paths ; 595 ; 595 ; +; Unconstrained Output Ports ; 29 ; 29 ; +; Unconstrained Output Port Paths ; 211 ; 211 ; ++---------------------------------+-------+------+ + + ++----------------------------------------------------------+ +; Clock Status Summary ; ++------------------------+----------+------+---------------+ +; Target ; Clock ; Type ; Status ; ++------------------------+----------+------+---------------+ +; CLOCK_50 ; CLOCK_50 ; Base ; Constrained ; +; spi2adc:SPI_ADC|adc_cs ; ; Base ; Unconstrained ; ++------------------------+----------+------+---------------+ + + ++---------------------------------------------------------------------------------------------------+ +; Unconstrained Input Ports ; ++------------+--------------------------------------------------------------------------------------+ +; Input Port ; Comment ; ++------------+--------------------------------------------------------------------------------------+ +; ADC_SDO ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SW[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SW[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SW[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SW[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SW[4] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SW[5] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SW[6] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SW[7] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SW[8] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ++------------+--------------------------------------------------------------------------------------+ + + ++-----------------------------------------------------------------------------------------------------+ +; Unconstrained Output Ports ; ++-------------+---------------------------------------------------------------------------------------+ +; Output Port ; Comment ; ++-------------+---------------------------------------------------------------------------------------+ +; ADC_CS ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; ADC_SCK ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; ADC_SDI ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; DAC_CS ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; DAC_LD ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; DAC_SCK ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; DAC_SDI ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX0[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX0[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX0[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX0[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX0[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX0[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX0[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX1[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX1[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX1[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX1[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX1[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX1[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX1[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX2[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX2[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX2[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX2[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX2[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX2[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX2[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; PWM_OUT ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ++-------------+---------------------------------------------------------------------------------------+ + + ++---------------------------------------------------------------------------------------------------+ +; Unconstrained Input Ports ; ++------------+--------------------------------------------------------------------------------------+ +; Input Port ; Comment ; ++------------+--------------------------------------------------------------------------------------+ +; ADC_SDO ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SW[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SW[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SW[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SW[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SW[4] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SW[5] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SW[6] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SW[7] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SW[8] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ++------------+--------------------------------------------------------------------------------------+ + + ++-----------------------------------------------------------------------------------------------------+ +; Unconstrained Output Ports ; ++-------------+---------------------------------------------------------------------------------------+ +; Output Port ; Comment ; ++-------------+---------------------------------------------------------------------------------------+ +; ADC_CS ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; ADC_SCK ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; ADC_SDI ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; DAC_CS ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; DAC_LD ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; DAC_SCK ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; DAC_SDI ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX0[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX0[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX0[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX0[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX0[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX0[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX0[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX1[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX1[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX1[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX1[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX1[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX1[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX1[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX2[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX2[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX2[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX2[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX2[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX2[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX2[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; PWM_OUT ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ++-------------+---------------------------------------------------------------------------------------+ + + ++------------------------------------+ +; TimeQuest Timing Analyzer Messages ; ++------------------------------------+ +Info: ******************************************************************* +Info: Running Quartus Prime TimeQuest Timing Analyzer + Info: Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition + Info: Processing started: Sat Dec 10 19:27:05 2016 +Info: Command: quartus_sta ex19 -c ex19_top +Info: qsta_default_script.tcl version: #1 +Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. +Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected +Info (21077): Low junction temperature is 0 degrees C +Info (21077): High junction temperature is 85 degrees C +Info (332104): Reading SDC File: 'ex19_top.sdc' +Warning (332060): Node: spi2adc:SPI_ADC|adc_cs was determined to be a clock but was found without an associated clock assignment. + Info (13166): Register processor:ALLPASS|counter_13:COUNT13|count[2] is being clocked by spi2adc:SPI_ADC|adc_cs +Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty" +Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. +Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON +Info: Analyzing Slow 1100mV 85C Model +Info (332146): Worst-case setup slack is 6.748 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): 6.748 0.000 CLOCK_50 +Info (332146): Worst-case hold slack is 0.362 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): 0.362 0.000 CLOCK_50 +Info (332140): No Recovery paths to report +Info (332140): No Removal paths to report +Info (332146): Worst-case minimum pulse width slack is 8.774 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): 8.774 0.000 CLOCK_50 +Info: Analyzing Slow 1100mV 0C Model +Info (334003): Started post-fitting delay annotation +Info (334004): Delay annotation completed successfully +Warning (332060): Node: spi2adc:SPI_ADC|adc_cs was determined to be a clock but was found without an associated clock assignment. + Info (13166): Register processor:ALLPASS|counter_13:COUNT13|count[2] is being clocked by spi2adc:SPI_ADC|adc_cs +Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. +Info (332146): Worst-case setup slack is 7.062 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): 7.062 0.000 CLOCK_50 +Info (332146): Worst-case hold slack is 0.173 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): 0.173 0.000 CLOCK_50 +Info (332140): No Recovery paths to report +Info (332140): No Removal paths to report +Info (332146): Worst-case minimum pulse width slack is 8.756 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): 8.756 0.000 CLOCK_50 +Info: Analyzing Fast 1100mV 85C Model +Info (334003): Started post-fitting delay annotation +Info (334004): Delay annotation completed successfully +Warning (332060): Node: spi2adc:SPI_ADC|adc_cs was determined to be a clock but was found without an associated clock assignment. + Info (13166): Register processor:ALLPASS|counter_13:COUNT13|count[2] is being clocked by spi2adc:SPI_ADC|adc_cs +Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. +Info (332146): Worst-case setup slack is 8.262 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): 8.262 0.000 CLOCK_50 +Info (332146): Worst-case hold slack is 0.164 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): 0.164 0.000 CLOCK_50 +Info (332140): No Recovery paths to report +Info (332140): No Removal paths to report +Info (332146): Worst-case minimum pulse width slack is 8.476 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): 8.476 0.000 CLOCK_50 +Info: Analyzing Fast 1100mV 0C Model +Warning (332060): Node: spi2adc:SPI_ADC|adc_cs was determined to be a clock but was found without an associated clock assignment. + Info (13166): Register processor:ALLPASS|counter_13:COUNT13|count[2] is being clocked by spi2adc:SPI_ADC|adc_cs +Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. +Info (332146): Worst-case setup slack is 8.301 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): 8.301 0.000 CLOCK_50 +Info (332146): Worst-case hold slack is 0.064 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): 0.064 0.000 CLOCK_50 +Info (332140): No Recovery paths to report +Info (332140): No Removal paths to report +Info (332146): Worst-case minimum pulse width slack is 8.431 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): 8.431 0.000 CLOCK_50 +Info (332102): Design is not fully constrained for setup requirements +Info (332102): Design is not fully constrained for hold requirements +Info: Quartus Prime TimeQuest Timing Analyzer was successful. 0 errors, 5 warnings + Info: Peak virtual memory: 1035 megabytes + Info: Processing ended: Sat Dec 10 19:28:16 2016 + Info: Elapsed time: 00:01:11 + Info: Total CPU time (on all processors): 00:00:13 + + diff --git a/part_4/ex19/variable_echo.v b/part_4/ex19/variable_echo.v new file mode 100644 index 0000000..9b86f02 --- /dev/null +++ b/part_4/ex19/variable_echo.v @@ -0,0 +1,59 @@ +module processor (sysclk, data_in, data_out, data_valid, SW, HEX0, HEX1, HEX2); + + input sysclk; // system clock + input data_valid; + input [9:0] data_in; // 10-bit input data + input [8:0] SW; + output [9:0] data_out; // 10-bit output data + output [6:0] HEX0, HEX1, HEX2; + + wire sysclk; + wire [9:0] data_in; + reg [9:0] data_out; + wire [9:0] x,y; + wire [8:0] RAM_out; + wire pulse; + wire [19:0] segnum; + wire [12:0] count_13; + wire [3:0] BCD_0, BCD_1, BCD_2, BCD_3, BCD_4; + + parameter ADC_OFFSET = 10'h181; + parameter DAC_OFFSET = 10'h200; + + assign x = data_in[9:0] - ADC_OFFSET; // x is input in 2's complement + + assign y = x - {RAM_out[8],RAM_out[8:0]}; + + pulse_gen PULSE0 (pulse, data_valid, sysclk); + + counter_13 COUNT13 ( + .clock(~data_valid), + .enable(1'b0), + .count(count_13), + .reset(1'b1) + ); + + RAM DELAY1024 ( + .clock(sysclk), + .data(y[9:1]), + .wren(pulse), + .rden(pulse), + .rdaddress(count_13), + .wraddress(count_13 + {SW[8:0],4'b0000}), + .q(RAM_out) + ); + + multiply_k MULTK (SW,segnum); + + bin2bcd_16 BIN0 (segnum[19:10], BCD_0, BCD_1, BCD_2, BCD_3, BCD_4); + + hex_to_7seg SEG0 (HEX0, BCD_0); + hex_to_7seg SEG1 (HEX1, BCD_1); + hex_to_7seg SEG2 (HEX2, BCD_2); + + // Now clock y output with system clock + always @(posedge sysclk) + data_out <= y + DAC_OFFSET; + +endmodule + \ No newline at end of file diff --git a/part_4/mylib/add3_ge5.v b/part_4/mylib/add3_ge5.v new file mode 100644 index 0000000..0daf78a --- /dev/null +++ b/part_4/mylib/add3_ge5.v @@ -0,0 +1,31 @@ +//------------------------------ +// Module name: add3_ge5 +// Function: Add 3 to input if it is 5 or above +// Creator: Peter Cheung +// Version: 1.0 +// Date: 21 Jan 2014 +//------------------------------ + +module add3_ge5(w,a); + input [3:0] w; + output [3:0] a; + reg [3:0] a; + + always @ (w) + case (w) + 4'b0000: a <= 4'b0000; + 4'b0001: a <= 4'b0001; + 4'b0010: a <= 4'b0010; + 4'b0011: a <= 4'b0011; + 4'b0100: a <= 4'b0100; + 4'b0101: a <= 4'b1000; + 4'b0110: a <= 4'b1001; + 4'b0111: a <= 4'b1010; + 4'b1000: a <= 4'b1011; + 4'b1001: a <= 4'b1100; + 4'b1010: a <= 4'b1101; + 4'b1011: a <= 4'b1110; + 4'b1100: a <= 4'b1111; + default: a <= 4'b0000; // a cannot be 13 or larger, else overflow + endcase +endmodule \ No newline at end of file diff --git a/part_4/mylib/bin2bcd_16.v b/part_4/mylib/bin2bcd_16.v new file mode 100644 index 0000000..b25d0bd --- /dev/null +++ b/part_4/mylib/bin2bcd_16.v @@ -0,0 +1,109 @@ +//------------------------------ +// Module name: bin2bcd_16 +// Function: Converts a 16-bit binary number to 5 digits BCD +// .... it uses a shift-and-add3 algorithm +// Creator: Peter Cheung +// Version: 2.0 (Correct mistake - problem with numbers 0x5000 or larger) +// Date: 24 Nov 2016 +//------------------------------ +// For more explanation of how this work, see +// ... instructions on wwww.ee.ic.ac.uk/pcheung/teaching/E2_experiment + +module bin2bcd_16 (B, BCD_0, BCD_1, BCD_2, BCD_3, BCD_4); + + input [15:0] B; // binary input number + output [3:0] BCD_0, BCD_1, BCD_2, BCD_3, BCD_4; // BCD digit LSD to MSD + + wire [3:0] w1,w2,w3,w4,w5,w6,w7,w8,w9,w10,w11,w12,w13; + wire [3:0] w14,w15,w16,w17,w18,w19,w20,w21,w22,w23,w24,w25; + wire [3:0] w26,w27,w28,w29,w30,w31,w32,w33,w34,w35; + wire [3:0] a0,a1,a2,a3,a4,a5,a6,a7,a8,a9,a10,a11,a12,a13; + wire [3:0] a14,a15,a16,a17,a18,a19,a20,a21,a22,a23,a24,a25; + wire [3:0] a26,a27,a28,a29,a30,a31,a32,a33,a34,a35; + + // Instantiate a tree of add3-if-greater than or equal to 5 cells + // ... input is w_n, and output is a_n + add3_ge5 A1 (w1,a1); + add3_ge5 A2 (w2,a2); + add3_ge5 A3 (w3,a3); + add3_ge5 A4 (w4,a4); + add3_ge5 A5 (w5,a5); + add3_ge5 A6 (w6,a6); + add3_ge5 A7 (w7,a7); + add3_ge5 A8 (w8,a8); + add3_ge5 A9 (w9,a9); + add3_ge5 A10 (w10,a10); + add3_ge5 A11 (w11,a11); + add3_ge5 A12 (w12,a12); + add3_ge5 A13 (w13,a13); + add3_ge5 A14 (w14,a14); + add3_ge5 A15 (w15,a15); + add3_ge5 A16 (w16,a16); + add3_ge5 A17 (w17,a17); + add3_ge5 A18 (w18,a18); + add3_ge5 A19 (w19,a19); + add3_ge5 A20 (w20,a20); + add3_ge5 A21 (w21,a21); + add3_ge5 A22 (w22,a22); + add3_ge5 A23 (w23,a23); + add3_ge5 A24 (w24,a24); + add3_ge5 A25 (w25,a25); + add3_ge5 A26 (w26,a26); + add3_ge5 A27 (w27,a27); + add3_ge5 A28 (w28,a28); + add3_ge5 A29 (w29,a29); + add3_ge5 A30 (w30,a30); + add3_ge5 A31 (w31,a31); + add3_ge5 A32 (w32,a32); + add3_ge5 A33 (w33,a33); + add3_ge5 A34 (w34,a34); + add3_ge5 A35 (w35,a35); + + // wire the tree of add3 modules together + assign w1 = {1'b0,B[15:13]}; // w_n is the input port to module a_n + assign w2 = {a1[2:0], B[12]}; + assign w3 = {a2[2:0], B[11]}; + assign w4 = {1'b0,a1[3],a2[3],a3[3]}; + assign w5 = {a3[2:0], B[10]}; + assign w6 = {a4[2:0], a5[3]}; + assign w7 = {a5[2:0], B[9]}; + assign w8 = {a6[2:0], a7[3]}; + assign w9 = {a7[2:0], B[8]}; + assign w10 = {1'b0, a4[3], a6[3], a8[3]}; + assign w11 = {a8[2:0], a9[3]}; + assign w12 = {a9[2:0], B[7]}; + assign w13 = {a10[2:0], a11[3]}; + assign w14 = {a11[2:0], a12[3]}; + assign w15 = {a12[2:0], B[6]}; + assign w16 = {a13[2:0], a14[3]}; + assign w17 = {a14[2:0], a15[3]}; + assign w18 = {a15[2:0], B[5]}; + assign w19 = {1'b0, a10[3], a13[3], a16[3]}; + assign w20 = {a16[2:0], a17[3]}; + assign w21 = {a17[2:0], a18[3]}; + assign w22 = {a18[2:0], B[4]}; + assign w23 = {a19[2:0], a20[3]}; + assign w24 = {a20[2:0], a21[3]}; + assign w25 = {a21[2:0], a22[3]}; + assign w26 = {a22[2:0], B[3]}; + assign w27 = {a23[2:0], a24[3]}; + assign w28 = {a24[2:0], a25[3]}; + assign w29 = {a25[2:0], a26[3]}; + assign w30 = {a26[2:0], B[2]}; + assign w31 = {1'b0,a19[3], a23[3], a27[3]}; + assign w32 = {a27[2:0], a28[3]}; + assign w33 = {a28[2:0], a29[3]}; + assign w34 = {a29[2:0], a30[3]}; + assign w35 = {a30[2:0], B[1]}; + + // connect up to four BCD digit outputs + assign BCD_0 = {a35[2:0],B[0]}; + assign BCD_1 = {a34[2:0],a35[3]}; + assign BCD_2 = {a33[2:0],a34[3]}; + assign BCD_3 = {a32[2:0],a33[3]}; + assign BCD_4 = {a31[2:0],a32[3]}; +endmodule + + + + diff --git a/part_4/mylib/clktick_16.v b/part_4/mylib/clktick_16.v new file mode 100644 index 0000000..e6b99eb --- /dev/null +++ b/part_4/mylib/clktick_16.v @@ -0,0 +1,42 @@ +// Design Name : clktick_16 +// File Name : clktick.v +// Function : divide an input clock signal by n+1 +//----------------------------------------------------- + +module clktick_16 ( + clkin, // Clock input to the design + enable, // enable clk divider + N, // Clock division factor is N+1 + tick // pulse_out goes high for one cycle (n+1) clock cycles +); // End of port list + +parameter N_BIT = 16; +//-------------Input Ports----------------------------- +input clkin; +input enable; +input [N_BIT-1:0] N; + +//-------------Output Ports---------------------------- +output tick; + +//-------------Output Ports Data Type------------------ +// Output port can be a storage element (reg) or a wire +reg [N_BIT-1:0] count; +reg tick; + +initial tick = 1'b0; + +//------------ Main Body of the module ------------------------ + + always @ (posedge clkin) + if (enable == 1'b1) + if (count == 0) begin + tick <= 1'b1; + count <= N; + end + else begin + tick <= 1'b0; + count <= count - 1'b1; + end + +endmodule // End of Module clktick \ No newline at end of file diff --git a/part_4/mylib/counter_13.v b/part_4/mylib/counter_13.v new file mode 100644 index 0000000..59ad089 --- /dev/null +++ b/part_4/mylib/counter_13.v @@ -0,0 +1,24 @@ +`timescale 1ns / 100ps + +module counter_13 ( + clock, + enable, + count, + reset + ); + + parameter BIT_SZ = 13; + input clock; + input enable; + input reset; + output reg [BIT_SZ-1:0] count; + + + initial count = 0; + + always @ (posedge clock) + if (reset == 1'b0) + count <= 0; + else if (enable == 1'b0) + count <= count + 1'b1; +endmodule diff --git a/part_4/mylib/hex_to_7seg.v b/part_4/mylib/hex_to_7seg.v new file mode 100644 index 0000000..1c39f02 --- /dev/null +++ b/part_4/mylib/hex_to_7seg.v @@ -0,0 +1,38 @@ +//------------------------------ +// Module name: hex_to_7seg +// Function: convert 4-bit hex value to drive 7 segment display +// output is low active - using case statement +// Creator: Peter Cheung +// Version: 1.1 +// Date: 23 Oct 2011 +//------------------------------ + +module hex_to_7seg (out,in); + + output [6:0] out; // low-active output to drive 7 segment display + input [3:0] in; // 4-bit binary input of a hexademical number + + reg [6:0] out; // make out a variable for use in procedural assignment + + always @ (in) + case (in) + 4'h0: out = 7'b1000000; + 4'h1: out = 7'b1111001; // -- 0 --- + 4'h2: out = 7'b0100100; // | | + 4'h3: out = 7'b0110000; // 5 1 + 4'h4: out = 7'b0011001; // | | + 4'h5: out = 7'b0010010; // -- 6 --- + 4'h6: out = 7'b0000010; // | | + 4'h7: out = 7'b1111000; // 4 2 + 4'h8: out = 7'b0000000; // | | + 4'h9: out = 7'b0011000; // -- 3 --- + 4'ha: out = 7'b0001000; + 4'hb: out = 7'b0000011; + 4'hc: out = 7'b1000110; + 4'hd: out = 7'b0100001; + 4'he: out = 7'b0000110; + 4'hf: out = 7'b0001110; + endcase +endmodule + + diff --git a/part_4/mylib/multiply_4.v b/part_4/mylib/multiply_4.v new file mode 100644 index 0000000..863b6c1 --- /dev/null +++ b/part_4/mylib/multiply_4.v @@ -0,0 +1,107 @@ +// megafunction wizard: %LPM_MULT% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: lpm_mult + +// ============================================================ +// File Name: multiply_k.v +// Megafunction Name(s): +// lpm_mult +// +// Simulation Library Files(s): +// lpm +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 13.1.0 Build 162 10/23/2013 SJ Web Edition +// ************************************************************ + + +//Copyright (C) 1991-2013 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module multiply_4 ( + dataa, + result); + + input [8:0] dataa; + output [19:0] result; + + wire [19:0] sub_wire0; + wire [10:0] sub_wire1 = 11'h4; + wire [19:0] result = sub_wire0[19:0]; + + lpm_mult lpm_mult_component ( + .dataa (dataa), + .datab (sub_wire1), + .result (sub_wire0), + .aclr (1'b0), + .clken (1'b1), + .clock (1'b0), + .sum (1'b0)); + defparam + lpm_mult_component.lpm_hint = "INPUT_B_IS_CONSTANT=YES,MAXIMIZE_SPEED=5", + lpm_mult_component.lpm_representation = "UNSIGNED", + lpm_mult_component.lpm_type = "LPM_MULT", + lpm_mult_component.lpm_widtha = 9, + lpm_mult_component.lpm_widthb = 11, + lpm_mult_component.lpm_widthp = 20; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: AutoSizeResult NUMERIC "1" +// Retrieval info: PRIVATE: B_isConstant NUMERIC "1" +// Retrieval info: PRIVATE: ConstantB NUMERIC "1638" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +// Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "0" +// Retrieval info: PRIVATE: Latency NUMERIC "0" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: SignedMult NUMERIC "0" +// Retrieval info: PRIVATE: USE_MULT NUMERIC "1" +// Retrieval info: PRIVATE: ValidConstant NUMERIC "1" +// Retrieval info: PRIVATE: WidthA NUMERIC "9" +// Retrieval info: PRIVATE: WidthB NUMERIC "11" +// Retrieval info: PRIVATE: WidthP NUMERIC "20" +// Retrieval info: PRIVATE: aclr NUMERIC "0" +// Retrieval info: PRIVATE: clken NUMERIC "0" +// Retrieval info: PRIVATE: new_diagram STRING "1" +// Retrieval info: PRIVATE: optimize NUMERIC "0" +// Retrieval info: LIBRARY: lpm lpm.lpm_components.all +// Retrieval info: CONSTANT: LPM_HINT STRING "INPUT_B_IS_CONSTANT=YES,MAXIMIZE_SPEED=5" +// Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "UNSIGNED" +// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MULT" +// Retrieval info: CONSTANT: LPM_WIDTHA NUMERIC "9" +// Retrieval info: CONSTANT: LPM_WIDTHB NUMERIC "11" +// Retrieval info: CONSTANT: LPM_WIDTHP NUMERIC "20" +// Retrieval info: USED_PORT: dataa 0 0 9 0 INPUT NODEFVAL "dataa[8..0]" +// Retrieval info: USED_PORT: result 0 0 20 0 OUTPUT NODEFVAL "result[19..0]" +// Retrieval info: CONNECT: @dataa 0 0 9 0 dataa 0 0 9 0 +// Retrieval info: CONNECT: @datab 0 0 11 0 1638 0 0 11 0 +// Retrieval info: CONNECT: result 0 0 20 0 @result 0 0 20 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL multiply_k.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL multiply_k.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL multiply_k.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL multiply_k.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL multiply_k_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL multiply_k_bb.v TRUE +// Retrieval info: LIB_FILE: lpm diff --git a/part_4/mylib/multiply_k.v b/part_4/mylib/multiply_k.v new file mode 100644 index 0000000..8292b58 --- /dev/null +++ b/part_4/mylib/multiply_k.v @@ -0,0 +1,107 @@ +// megafunction wizard: %LPM_MULT% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: lpm_mult + +// ============================================================ +// File Name: multiply_k.v +// Megafunction Name(s): +// lpm_mult +// +// Simulation Library Files(s): +// lpm +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 13.1.0 Build 162 10/23/2013 SJ Web Edition +// ************************************************************ + + +//Copyright (C) 1991-2013 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module multiply_k ( + dataa, + result); + + input [8:0] dataa; + output [19:0] result; + + wire [19:0] sub_wire0; + wire [10:0] sub_wire1 = 11'h666; + wire [19:0] result = sub_wire0[19:0]; + + lpm_mult lpm_mult_component ( + .dataa (dataa), + .datab (sub_wire1), + .result (sub_wire0), + .aclr (1'b0), + .clken (1'b1), + .clock (1'b0), + .sum (1'b0)); + defparam + lpm_mult_component.lpm_hint = "INPUT_B_IS_CONSTANT=YES,MAXIMIZE_SPEED=5", + lpm_mult_component.lpm_representation = "UNSIGNED", + lpm_mult_component.lpm_type = "LPM_MULT", + lpm_mult_component.lpm_widtha = 9, + lpm_mult_component.lpm_widthb = 11, + lpm_mult_component.lpm_widthp = 20; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: AutoSizeResult NUMERIC "1" +// Retrieval info: PRIVATE: B_isConstant NUMERIC "1" +// Retrieval info: PRIVATE: ConstantB NUMERIC "1638" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +// Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "0" +// Retrieval info: PRIVATE: Latency NUMERIC "0" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: SignedMult NUMERIC "0" +// Retrieval info: PRIVATE: USE_MULT NUMERIC "1" +// Retrieval info: PRIVATE: ValidConstant NUMERIC "1" +// Retrieval info: PRIVATE: WidthA NUMERIC "9" +// Retrieval info: PRIVATE: WidthB NUMERIC "11" +// Retrieval info: PRIVATE: WidthP NUMERIC "20" +// Retrieval info: PRIVATE: aclr NUMERIC "0" +// Retrieval info: PRIVATE: clken NUMERIC "0" +// Retrieval info: PRIVATE: new_diagram STRING "1" +// Retrieval info: PRIVATE: optimize NUMERIC "0" +// Retrieval info: LIBRARY: lpm lpm.lpm_components.all +// Retrieval info: CONSTANT: LPM_HINT STRING "INPUT_B_IS_CONSTANT=YES,MAXIMIZE_SPEED=5" +// Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "UNSIGNED" +// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MULT" +// Retrieval info: CONSTANT: LPM_WIDTHA NUMERIC "9" +// Retrieval info: CONSTANT: LPM_WIDTHB NUMERIC "11" +// Retrieval info: CONSTANT: LPM_WIDTHP NUMERIC "20" +// Retrieval info: USED_PORT: dataa 0 0 9 0 INPUT NODEFVAL "dataa[8..0]" +// Retrieval info: USED_PORT: result 0 0 20 0 OUTPUT NODEFVAL "result[19..0]" +// Retrieval info: CONNECT: @dataa 0 0 9 0 dataa 0 0 9 0 +// Retrieval info: CONNECT: @datab 0 0 11 0 1638 0 0 11 0 +// Retrieval info: CONNECT: result 0 0 20 0 @result 0 0 20 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL multiply_k.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL multiply_k.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL multiply_k.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL multiply_k.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL multiply_k_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL multiply_k_bb.v TRUE +// Retrieval info: LIB_FILE: lpm diff --git a/part_4/mylib/pulse_gen.v b/part_4/mylib/pulse_gen.v new file mode 100644 index 0000000..d82fe49 --- /dev/null +++ b/part_4/mylib/pulse_gen.v @@ -0,0 +1,43 @@ +//------------------------------ +// Module name: pulse_gen (Moore) +// Function: Generate one clock pulse on +ve edge of input +// Creator: Peter Cheung +// Version: 1.0 +// Date: 29 Jan 2014 +//------------------------------ + +module pulse_gen(pulse, in, clk); + + output pulse; // output pulse lasting one clk cycle + input in; // input, +ve edge to be detected + input clk; // clock signal + + reg [1:0] state; + reg pulse; + + parameter IDLE = 2'b0; // state coding for IDLE state + parameter IN_HIGH = 2'b01; + parameter WAIT_LOW = 2'b10; + + initial state = IDLE; + + always @ (posedge clk) + begin + pulse <= 0; // default output + case (state) + IDLE: if (in == 1'b1) begin + state <= IN_HIGH; pulse <= 1'b1; end + else + state <= IDLE; + IN_HIGH: if (in == 1'b1) + state <= WAIT_LOW; + else + state <= IDLE; + WAIT_LOW: if (in == 1'b1) + state <= WAIT_LOW; + else + state <= IDLE; + default: ; + endcase + end //... always +endmodule diff --git a/part_4/mylib/pwm.v b/part_4/mylib/pwm.v new file mode 100644 index 0000000..c3b34d9 --- /dev/null +++ b/part_4/mylib/pwm.v @@ -0,0 +1,25 @@ +module pwm (clk, data_in, load, pwm_out); + + input clk; // system clock + input [9:0] data_in; // input data for conversion + input load; // high pulse to load new data + output pwm_out; // PWM output + + reg [9:0] d; // internal register + reg [9:0] count; // internal 10-bit counter + reg pwm_out; + + always @ (posedge clk) + if (load == 1'b1) d <= data_in; + + initial count = 10'b0; + + always @ (posedge clk) begin + count <= count + 1'b1; + if (count > d) + pwm_out <= 1'b0; + else + pwm_out <= 1'b1; + end + +endmodule diff --git a/part_4/mylib/spi2adc.v b/part_4/mylib/spi2adc.v new file mode 100644 index 0000000..41be7ad --- /dev/null +++ b/part_4/mylib/spi2adc.v @@ -0,0 +1,157 @@ +//------------------------------ +// Module name: spi2adc +// Function: SPI interface for MCP3002 ADC +// Creator: Peter Cheung +// Version: 3.0 +// Date: 8 Dec 2016 +//------------------------------ + +module spi2adc (sysclk, start, channel, data_from_adc, data_valid, + sdata_to_adc, adc_cs, adc_sck, sdata_from_adc); + + input sysclk; // 50MHz system clock of DE0 + input start; // Pulse to start ADC, minimum wide = clock period + input channel; // channel 0 or 1 to be converted + output [9:0] data_from_adc; // 10-bit ADC result + output data_valid; // High indicates that converted data valid + output sdata_to_adc; // Serial commands send to adc chip + output adc_cs; // chip select - low when converting + output adc_sck; // SPI clock - active during conversion + input sdata_from_adc; // Converted serial data from ADC, MSB first + +//-------------Input Ports----------------------------- +// All the input ports should be wires + wire sysclk, start, sdata_from_adc; + +//-------------Output Ports----------------------------- +// Output port can be a storage element (reg) or a wire + reg [9:0] data_from_adc; + reg adc_cs; + wire sdata_to_adc, adc_sck, data_valid; + +//-------------Configuration parameters for ADC -------- + parameter SGL=1'b1; // 0:diff i/p, 1:single-ended + parameter MSBF=1'b1; // 0:LSB first, 1:MSB first + +// --- Submodule: Generate internal clock at 1 MHz ----- + reg clk_1MHz; // 1Mhz clock derived from 50MHz + reg [4:0] ctr; // internal counter + reg tick; // 1MHz clock tick lasting 20ns, i.e. one 50MHz cycle + parameter TIME_CONSTANT = 5'd24; // change this for diff clk freq + initial begin + clk_1MHz = 0; // don't need to reset - don't care if it is 1 or 0 to start + ctr = 5'b0; // ... to start. Initialise to make simulation easier + tick = 1'b0; + end + + always @ (posedge sysclk) // + if (ctr==0) begin + ctr <= TIME_CONSTANT; + if (clk_1MHz==1'b0) + tick <= 1'b1; + clk_1MHz <= ~clk_1MHz; // toggle the output clock for squarewave + end + else begin + ctr <= ctr - 1'b1; + tick <= 1'b0; + end +// ---- end internal clock generator ---------- + +// ---- Detect start is asserted with a small state machine + // .... FF set on positive edge of start + // .... reset when adc_cs goes high again + reg [1:0] sr_state; + parameter IDLE = 2'b00,WAIT_CSB_FALL = 2'b01, WAIT_CSB_HIGH = 2'b10; + reg adc_start; + + initial begin + sr_state = IDLE; + adc_start = 1'b0; // set while sending data to ADC + end + + always @ (posedge sysclk) + case (sr_state) + IDLE: if (start==1'b0) sr_state <= IDLE; + else begin + sr_state <= WAIT_CSB_FALL; + adc_start <= 1'b1; + end + WAIT_CSB_FALL: if (adc_cs==1'b1) sr_state <= WAIT_CSB_FALL; + else sr_state <= WAIT_CSB_HIGH; + + WAIT_CSB_HIGH: if (adc_cs==1'b0) sr_state <= WAIT_CSB_HIGH; + else begin + sr_state <= IDLE; + adc_start <= 1'b0; + end + default: sr_state <= IDLE; + endcase +//------- End circuit to detect start and end of conversion + + +// spi controller designed as a state machine +// .... with 16 states (idle, and S1-S15 indicated by state value + + reg [4:0] state; + reg adc_done, adc_din, shift_ena; + + initial begin + state = 5'b0; adc_cs = 1'b1; adc_done = 1'b0; + adc_din = 1'b0; shift_ena <= 1'b0; + end + + always @(posedge sysclk) + if (tick==1'b1) begin + + // default outputs and state transition + adc_cs <= 1'b0; adc_done <= 1'b0; adc_din <= 1'b0; shift_ena <= 1'b0; + state <= state + 1'b1; + case (state) + 5'd0: begin + if (adc_start==1'b0) begin + state <= 5'd0; // still idle + adc_cs <= 1'b1; // chip select not active + end + else begin + state <= 5'd1; // start converting + adc_din <= 1'b1; // start bit is 1 + end + end + 5'd1: adc_din <= SGL; // SGL bit + 5'd2: adc_din <= channel; // CH bit + 5'd3: adc_din <= MSBF; // MSB first bit + 5'd4: shift_ena <= 1'b1; // start shifting data from adc + 5'd15: begin + shift_ena <= 1'b0; + adc_done <= 1'b1; + end + 5'd16: begin + adc_cs <= 1'b1; // last state - disable chip select + state <= 5'd0; // go back to idle state + end + default: + shift_ena <= 1'b1; // unspecified states are covered by default above + endcase + end // ... always + + // shift register for output data + reg [9:0] shift_reg; + initial begin + shift_reg = 10'b0; + data_from_adc = 10'b0; + end + + always @(negedge sysclk) + if((adc_cs==1'b0)&&(shift_ena==1'b1)&&(tick==1'b1)) // start shifting data_in + shift_reg <= {shift_reg[8:0],sdata_from_adc}; + + // Latch converted output data + always @(posedge sysclk) + if(adc_done) + data_from_adc = shift_reg; + + // Assign outputs to drive SPI interface to DAC + assign adc_sck = !clk_1MHz & !adc_cs; + assign sdata_to_adc = adc_din; + assign data_valid = adc_cs; +endmodule \ No newline at end of file diff --git a/part_4/mylib/spi2dac.v b/part_4/mylib/spi2dac.v new file mode 100644 index 0000000..6b8bbbd --- /dev/null +++ b/part_4/mylib/spi2dac.v @@ -0,0 +1,135 @@ +//------------------------------ +// Module name: spi2dac +// Function: SPI interface for MPC4911 DAC +// Creator: Peter Cheung +// Version: 3.0 +// Date: 8 Dec 2016 +//------------------------------ + +module spi2dac (sysclk, data_in, load, dac_sdi, dac_cs, dac_sck, dac_ld); + + input sysclk; // 50MHz system clock of DE1 + input [9:0] data_in; // input data to DAC + input load; // Pulse to load data to dac + output dac_sdi; // SPI serial data out + output dac_cs; // chip select - low when sending data to dac + output dac_sck; // SPI clock, 16 cycles at half sysclk freq + output dac_ld; + +//-------------Input Ports----------------------------- +// All the input ports should be wires + wire sysclk, load; + wire [9:0] data_in; + +//-------------Output Ports----------------------------- +// Output port can be a storage element (reg) or a wire + reg dac_cs, dac_ld; + wire dac_sck, dac_sdi; + + parameter BUF=1'b1; // 0:no buffer, 1:Vref buffered + parameter GA_N=1'b1; // 0:gain = 2x, 1:gain = 1x + parameter SHDN_N=1'b1; // 0:power down, 1:dac active + + wire [3:0] cmd = {1'b0,BUF,GA_N,SHDN_N}; // wire to VDD or GND + + // --- internal 1MHz symmetical clock generator ----- + reg clk_1MHz; // 1Mhz clock derived from 50MHz + reg [4:0] ctr; // internal counter + reg tick; // 1MHz clock tick (1 cycle of 20ns every 1 usec) + + parameter TC = 5'd24; // Terminal count - change this for diff clk freq + initial begin + clk_1MHz = 0; // don't need to reset - don't care if it is 1 or 0 to start + ctr = 5'b0; // ... Initialise when FPGA is configured + tick = 1'b0; + end + + always @ (posedge sysclk) + if (ctr==0) begin + ctr <= TC; + if (clk_1MHz==1'b0) + tick <= 1'b1; + clk_1MHz <= ~clk_1MHz; // toggle the output clock for squarewave + end + else begin + ctr <= ctr - 1'b1; + tick <= 1'b0; + end + // ---- end internal 1MHz symmetical clock generator ---------- + + // ---- FSM to detect rising edge of load and falling edge of dac_cs + // .... sr_state set on posedge of load + // .... sr_state reset when dac_cs goes high at the end of DAC output cycle + reg [1:0] sr_state; + parameter IDLE = 2'b00,WAIT_CSB_FALL = 2'b01, WAIT_CSB_HIGH = 2'b10; + reg dac_start; // set if a DAC write is detected + + initial begin + sr_state = IDLE; + dac_start = 1'b0; // set while sending data to DAC + end + + always @ (posedge sysclk) // state transition + case (sr_state) + IDLE: if (load==1'b1) sr_state <= WAIT_CSB_FALL; + WAIT_CSB_FALL: if (dac_cs==1'b0) sr_state <= WAIT_CSB_HIGH; + WAIT_CSB_HIGH: if (dac_cs==1'b1) sr_state <= IDLE; + default: sr_state <= IDLE; + endcase + + always @ (*) + case (sr_state) + IDLE: dac_start = 1'b0; + WAIT_CSB_FALL: dac_start = 1'b1; + WAIT_CSB_HIGH: dac_start = 1'b0; + default: dac_start = 1'b0; + endcase + + //------- End circuit to detect start and end of conversion state machine + + //------- spi controller FSM + // .... with 17 states (idle, and S1-S16 + // .... for the 16 cycles each sending 1-bit to dac) + reg [4:0] state; + + initial begin + state = 5'b0; dac_ld = 1'b0; dac_cs = 1'b1; + end + + always @(posedge sysclk) // FSM state transition + if (tick==1'b1) + case (state) + 5'd0: if (dac_start == 1'b1) // waiting to start + state <= state + 1'b1; + else + state <= 5'b0; + 5'd17: state <= 5'd0; // go back to idle state + default: state <= state + 1'b1; // default go to next state + endcase + + always @ (*) begin // FSM output + dac_cs = 1'b0; dac_ld = 1'b1; + case (state) + 5'd0: dac_cs = 1'b1; + 5'd17: begin dac_cs = 1'b1; dac_ld = 1'b0; end + default: begin dac_cs = 1'b0; dac_ld = 1'b1; end + endcase + end //always + // --------- END of spi controller FSM + + // shift register for output data + reg [15:0] shift_reg; + initial begin + shift_reg = 16'b0; + end + + always @(posedge sysclk) + if((dac_start==1'b1)&&(dac_cs==1'b1)&&(tick==1'b1)) // parallel load data to shift reg + shift_reg <= {cmd,data_in,2'b00}; + else if (tick==1'b1) // .. else start shifting + shift_reg <= {shift_reg[14:0],1'b0}; + + // Assign outputs to drive SPI interface to DAC + assign dac_sck = !clk_1MHz&!dac_cs; + assign dac_sdi = shift_reg[15]; +endmodule \ No newline at end of file -- cgit v1.2.3-54-g00ecf