module delay(
	input CLOCK,
	input [13:0] DELAY,
	input START_DELAY,
	output reg TIME_OUT
);
	reg [13:0] COUNT;

	always @ (posedge CLOCK)
	begin
		if (START_DELAY == 1'b1)
		begin
			if (COUNT < DELAY+14'd24)
				begin
				COUNT <= COUNT + 1'b1;
				TIME_OUT <= 1'b0;
				end
			else
				begin
				COUNT <= 0;
				TIME_OUT <= 1'b1;
				end
		end 
		
	end
endmodule