module lfsr(
	input CLOCK,
	input ENABLE,
	output reg [13:0] SHIFT
);

	initial SHIFT = 13'd1;
	
	always @ (posedge CLOCK)
	begin
		if (ENABLE == 1'b1)
			SHIFT <= {SHIFT[12:0],(SHIFT[13] ^ SHIFT[11]) ^ SHIFT[3]};
	end
endmodule