`timescale 1ns / 100ps


module timer (
		input clock,
		input count,
		input count_clear,
		output reg [15:0] tim
		);
		
		always @ (posedge clock)
		begin
			if (count_clear)
				tim <= 0;
			else if (count)
				tim <= tim + 16'b1;
		end
endmodule