EDA Netlist Writer report for ex10_top
Mon Dec 05 10:45:30 2016
Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition


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; Table of Contents ;
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  1. Legal Notice
  2. EDA Netlist Writer Summary
  3. Simulation Settings
  4. Simulation Generated Files
  5. EDA Netlist Writer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, the Altera Quartus Prime License Agreement,
the Altera MegaCore Function License Agreement, or other 
applicable license agreement, including, without limitation, 
that your use is for the sole purpose of programming logic 
devices manufactured by Altera and sold by Altera or its 
authorized distributors.  Please refer to the applicable 
agreement for further details.



+-------------------------------------------------------------------+
; EDA Netlist Writer Summary                                        ;
+---------------------------+---------------------------------------+
; EDA Netlist Writer Status ; Successful - Mon Dec 05 10:45:30 2016 ;
; Revision Name             ; ex10_top                              ;
; Top-level Entity Name     ; ex10_top                              ;
; Family                    ; Cyclone V                             ;
; Simulation Files Creation ; Successful                            ;
+---------------------------+---------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------+
; Simulation Settings                                                                                                           ;
+---------------------------------------------------------------------------------------------------+---------------------------+
; Option                                                                                            ; Setting                   ;
+---------------------------------------------------------------------------------------------------+---------------------------+
; Tool Name                                                                                         ; ModelSim-Altera (Verilog) ;
; Generate functional simulation netlist                                                            ; Off                       ;
; Time scale                                                                                        ; 1 ps                      ;
; Truncate long hierarchy paths                                                                     ; Off                       ;
; Map illegal HDL characters                                                                        ; Off                       ;
; Flatten buses into individual nodes                                                               ; Off                       ;
; Maintain hierarchy                                                                                ; Off                       ;
; Bring out device-wide set/reset signals as ports                                                  ; Off                       ;
; Enable glitch filtering                                                                           ; Off                       ;
; Do not write top level VHDL entity                                                                ; Off                       ;
; Disable detection of setup and hold time violations in the input registers of bi-directional pins ; Off                       ;
; Architecture name in VHDL output netlist                                                          ; structure                 ;
; Generate third-party EDA tool command script for RTL functional simulation                        ; Off                       ;
; Generate third-party EDA tool command script for gate-level simulation                            ; Off                       ;
+---------------------------------------------------------------------------------------------------+---------------------------+


+-----------------------------------------------------+
; Simulation Generated Files                          ;
+-----------------------------------------------------+
; Generated Files                                     ;
+-----------------------------------------------------+
; C:/VERI/part_3/ex10/simulation/modelsim/ex10_top.vo ;
+-----------------------------------------------------+


+-----------------------------+
; EDA Netlist Writer Messages ;
+-----------------------------+
Info: *******************************************************************
Info: Running Quartus Prime EDA Netlist Writer
    Info: Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
    Info: Processing started: Mon Dec 05 10:45:29 2016
Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off ex10 -c ex10_top
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Warning (10905): Generated the EDA functional simulation netlist because it is the only supported netlist type for this device.
Info (204019): Generated file ex10_top.vo in folder "C:/VERI/part_3/ex10/simulation/modelsim/" for EDA simulation tool
Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 2 warnings
    Info: Peak virtual memory: 801 megabytes
    Info: Processing ended: Mon Dec 05 10:45:30 2016
    Info: Elapsed time: 00:00:01
    Info: Total CPU time (on all processors): 00:00:01