TimeQuest Timing Analyzer report for ex10_top Mon Dec 05 10:51:05 2016 Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition --------------------- ; Table of Contents ; --------------------- 1. Legal Notice 2. TimeQuest Timing Analyzer Summary 3. Parallel Compilation 4. SDC File List 5. Clocks 6. Slow 1100mV 85C Model Fmax Summary 7. Timing Closure Recommendations 8. Slow 1100mV 85C Model Setup Summary 9. Slow 1100mV 85C Model Hold Summary 10. Slow 1100mV 85C Model Recovery Summary 11. Slow 1100mV 85C Model Removal Summary 12. Slow 1100mV 85C Model Minimum Pulse Width Summary 13. Slow 1100mV 85C Model Metastability Summary 14. Slow 1100mV 0C Model Fmax Summary 15. Slow 1100mV 0C Model Setup Summary 16. Slow 1100mV 0C Model Hold Summary 17. Slow 1100mV 0C Model Recovery Summary 18. Slow 1100mV 0C Model Removal Summary 19. Slow 1100mV 0C Model Minimum Pulse Width Summary 20. Slow 1100mV 0C Model Metastability Summary 21. Fast 1100mV 85C Model Setup Summary 22. Fast 1100mV 85C Model Hold Summary 23. Fast 1100mV 85C Model Recovery Summary 24. Fast 1100mV 85C Model Removal Summary 25. Fast 1100mV 85C Model Minimum Pulse Width Summary 26. Fast 1100mV 85C Model Metastability Summary 27. Fast 1100mV 0C Model Setup Summary 28. Fast 1100mV 0C Model Hold Summary 29. Fast 1100mV 0C Model Recovery Summary 30. Fast 1100mV 0C Model Removal Summary 31. Fast 1100mV 0C Model Minimum Pulse Width Summary 32. Fast 1100mV 0C Model Metastability Summary 33. Multicorner Timing Analysis Summary 34. Board Trace Model Assignments 35. Input Transition Times 36. Signal Integrity Metrics (Slow 1100mv 0c Model) 37. Signal Integrity Metrics (Slow 1100mv 85c Model) 38. Signal Integrity Metrics (Fast 1100mv 0c Model) 39. Signal Integrity Metrics (Fast 1100mv 85c Model) 40. Setup Transfers 41. Hold Transfers 42. Report TCCS 43. Report RSKM 44. Unconstrained Paths Summary 45. Clock Status Summary 46. Unconstrained Input Ports 47. Unconstrained Output Ports 48. Unconstrained Input Ports 49. Unconstrained Output Ports 50. TimeQuest Timing Analyzer Messages ---------------- ; Legal Notice ; ---------------- Copyright (C) 1991-2016 Altera Corporation. All rights reserved. Your use of Altera Corporation's design tools, logic functions and other software and tools, and its AMPP partner logic functions, and any output files from any of the foregoing (including device programming or simulation files), and any associated documentation or information are expressly subject to the terms and conditions of the Altera Program License Subscription Agreement, the Altera Quartus Prime License Agreement, the Altera MegaCore Function License Agreement, or other applicable license agreement, including, without limitation, that your use is for the sole purpose of programming logic devices manufactured by Altera and sold by Altera or its authorized distributors. Please refer to the applicable agreement for further details. +---------------------------------------------------------------------------------+ ; TimeQuest Timing Analyzer Summary ; +-----------------------+---------------------------------------------------------+ ; Quartus Prime Version ; Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition ; ; Timing Analyzer ; TimeQuest ; ; Revision Name ; ex10_top ; ; Device Family ; Cyclone V ; ; Device Name ; 5CSEMA5F31C6 ; ; Timing Models ; Final ; ; Delay Model ; Combined ; ; Rise/Fall Delays ; Enabled ; +-----------------------+---------------------------------------------------------+ +------------------------------------------+ ; Parallel Compilation ; +----------------------------+-------------+ ; Processors ; Number ; +----------------------------+-------------+ ; Number detected on machine ; 8 ; ; Maximum allowed ; 4 ; ; ; ; ; Average used ; 1.07 ; ; Maximum used ; 4 ; ; ; ; ; Usage by Processor ; % Time Used ; ; Processor 1 ; 100.0% ; ; Processor 2 ; 2.2% ; ; Processor 3 ; 2.2% ; ; Processor 4 ; 2.2% ; +----------------------------+-------------+ +---------------------------------------------------+ ; SDC File List ; +---------------+--------+--------------------------+ ; SDC File Path ; Status ; Read at ; +---------------+--------+--------------------------+ ; ex10_top.sdc ; OK ; Mon Dec 05 10:51:03 2016 ; +---------------+--------+--------------------------+ +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Clocks ; +------------+------+--------+-----------+-------+--------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+--------------+ ; Clock Name ; Type ; Period ; Frequency ; Rise ; Fall ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets ; +------------+------+--------+-----------+-------+--------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+--------------+ ; CLOCK_50 ; Base ; 20.000 ; 50.0 MHz ; 0.000 ; 10.000 ; ; ; ; ; ; ; ; ; ; ; { CLOCK_50 } ; +------------+------+--------+-----------+-------+--------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+--------------+ +--------------------------------------------------+ ; Slow 1100mV 85C Model Fmax Summary ; +------------+-----------------+------------+------+ ; Fmax ; Restricted Fmax ; Clock Name ; Note ; +------------+-----------------+------------+------+ ; 259.61 MHz ; 259.61 MHz ; CLOCK_50 ; ; +------------+-----------------+------------+------+ This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis. ---------------------------------- ; Timing Closure Recommendations ; ---------------------------------- HTML report is unavailable in plain text report export. +-------------------------------------+ ; Slow 1100mV 85C Model Setup Summary ; +----------+--------+-----------------+ ; Clock ; Slack ; End Point TNS ; +----------+--------+-----------------+ ; CLOCK_50 ; 16.148 ; 0.000 ; +----------+--------+-----------------+ +------------------------------------+ ; Slow 1100mV 85C Model Hold Summary ; +----------+-------+-----------------+ ; Clock ; Slack ; End Point TNS ; +----------+-------+-----------------+ ; CLOCK_50 ; 0.362 ; 0.000 ; +----------+-------+-----------------+ ------------------------------------------ ; Slow 1100mV 85C Model Recovery Summary ; ------------------------------------------ No paths to report. ----------------------------------------- ; Slow 1100mV 85C Model Removal Summary ; ----------------------------------------- No paths to report. +---------------------------------------------------+ ; Slow 1100mV 85C Model Minimum Pulse Width Summary ; +----------+-------+--------------------------------+ ; Clock ; Slack ; End Point TNS ; +----------+-------+--------------------------------+ ; CLOCK_50 ; 8.815 ; 0.000 ; +----------+-------+--------------------------------+ ----------------------------------------------- ; Slow 1100mV 85C Model Metastability Summary ; ----------------------------------------------- No synchronizer chains to report. +--------------------------------------------------+ ; Slow 1100mV 0C Model Fmax Summary ; +------------+-----------------+------------+------+ ; Fmax ; Restricted Fmax ; Clock Name ; Note ; +------------+-----------------+------------+------+ ; 251.45 MHz ; 251.45 MHz ; CLOCK_50 ; ; +------------+-----------------+------------+------+ This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis. +------------------------------------+ ; Slow 1100mV 0C Model Setup Summary ; +----------+--------+----------------+ ; Clock ; Slack ; End Point TNS ; +----------+--------+----------------+ ; CLOCK_50 ; 16.023 ; 0.000 ; +----------+--------+----------------+ +-----------------------------------+ ; Slow 1100mV 0C Model Hold Summary ; +----------+-------+----------------+ ; Clock ; Slack ; End Point TNS ; +----------+-------+----------------+ ; CLOCK_50 ; 0.343 ; 0.000 ; +----------+-------+----------------+ ----------------------------------------- ; Slow 1100mV 0C Model Recovery Summary ; ----------------------------------------- No paths to report. ---------------------------------------- ; Slow 1100mV 0C Model Removal Summary ; ---------------------------------------- No paths to report. +--------------------------------------------------+ ; Slow 1100mV 0C Model Minimum Pulse Width Summary ; +----------+-------+-------------------------------+ ; Clock ; Slack ; End Point TNS ; +----------+-------+-------------------------------+ ; CLOCK_50 ; 8.805 ; 0.000 ; +----------+-------+-------------------------------+ ---------------------------------------------- ; Slow 1100mV 0C Model Metastability Summary ; ---------------------------------------------- No synchronizer chains to report. +-------------------------------------+ ; Fast 1100mV 85C Model Setup Summary ; +----------+--------+-----------------+ ; Clock ; Slack ; End Point TNS ; +----------+--------+-----------------+ ; CLOCK_50 ; 17.543 ; 0.000 ; +----------+--------+-----------------+ +------------------------------------+ ; Fast 1100mV 85C Model Hold Summary ; +----------+-------+-----------------+ ; Clock ; Slack ; End Point TNS ; +----------+-------+-----------------+ ; CLOCK_50 ; 0.183 ; 0.000 ; +----------+-------+-----------------+ ------------------------------------------ ; Fast 1100mV 85C Model Recovery Summary ; ------------------------------------------ No paths to report. ----------------------------------------- ; Fast 1100mV 85C Model Removal Summary ; ----------------------------------------- No paths to report. +---------------------------------------------------+ ; Fast 1100mV 85C Model Minimum Pulse Width Summary ; +----------+-------+--------------------------------+ ; Clock ; Slack ; End Point TNS ; +----------+-------+--------------------------------+ ; CLOCK_50 ; 8.762 ; 0.000 ; +----------+-------+--------------------------------+ ----------------------------------------------- ; Fast 1100mV 85C Model Metastability Summary ; ----------------------------------------------- No synchronizer chains to report. +------------------------------------+ ; Fast 1100mV 0C Model Setup Summary ; +----------+--------+----------------+ ; Clock ; Slack ; End Point TNS ; +----------+--------+----------------+ ; CLOCK_50 ; 17.666 ; 0.000 ; +----------+--------+----------------+ +-----------------------------------+ ; Fast 1100mV 0C Model Hold Summary ; +----------+-------+----------------+ ; Clock ; Slack ; End Point TNS ; +----------+-------+----------------+ ; CLOCK_50 ; 0.172 ; 0.000 ; +----------+-------+----------------+ ----------------------------------------- ; Fast 1100mV 0C Model Recovery Summary ; ----------------------------------------- No paths to report. ---------------------------------------- ; Fast 1100mV 0C Model Removal Summary ; ---------------------------------------- No paths to report. +--------------------------------------------------+ ; Fast 1100mV 0C Model Minimum Pulse Width Summary ; +----------+-------+-------------------------------+ ; Clock ; Slack ; End Point TNS ; +----------+-------+-------------------------------+ ; CLOCK_50 ; 8.741 ; 0.000 ; +----------+-------+-------------------------------+ ---------------------------------------------- ; Fast 1100mV 0C Model Metastability Summary ; ---------------------------------------------- No synchronizer chains to report. +------------------------------------------------------------------------------+ ; Multicorner Timing Analysis Summary ; +------------------+--------+-------+----------+---------+---------------------+ ; Clock ; Setup ; Hold ; Recovery ; Removal ; Minimum Pulse Width ; +------------------+--------+-------+----------+---------+---------------------+ ; Worst-case Slack ; 16.023 ; 0.172 ; N/A ; N/A ; 8.741 ; ; CLOCK_50 ; 16.023 ; 0.172 ; N/A ; N/A ; 8.741 ; ; Design-wide TNS ; 0.0 ; 0.0 ; 0.0 ; 0.0 ; 0.0 ; ; CLOCK_50 ; 0.000 ; 0.000 ; N/A ; N/A ; 0.000 ; +------------------+--------+-------+----------+---------+---------------------+ +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Board Trace Model Assignments ; +---------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ ; Pin ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ; +---------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ ; DAC_SDI ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; ; DAC_CS ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; ; DAC_LD ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; ; DAC_SCK ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +---------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ +-------------------------------------------------------------+ ; Input Transition Times ; +----------+--------------+-----------------+-----------------+ ; Pin ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ; +----------+--------------+-----------------+-----------------+ ; CLOCK_50 ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; ; SW[9] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; ; SW[8] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; ; SW[7] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; ; SW[6] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; ; SW[5] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; ; SW[4] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; ; SW[3] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; ; SW[2] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; ; SW[1] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; ; SW[0] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +----------+--------------+-----------------+-----------------+ +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Signal Integrity Metrics (Slow 1100mv 0c Model) ; +---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ ; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; +---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ ; DAC_SDI ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; ; DAC_CS ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ; ; DAC_LD ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; ; DAC_SCK ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ; +---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Signal Integrity Metrics (Slow 1100mv 85c Model) ; +---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ ; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; +---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ ; DAC_SDI ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; ; DAC_CS ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ; ; DAC_LD ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; ; DAC_SCK ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ; +---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Signal Integrity Metrics (Fast 1100mv 0c Model) ; +---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ ; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; +---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ ; DAC_SDI ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; ; DAC_CS ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ; ; DAC_LD ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; ; DAC_SCK ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ; +---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Signal Integrity Metrics (Fast 1100mv 85c Model) ; +---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ ; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; +---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ ; DAC_SDI ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; ; DAC_CS ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ; ; DAC_LD ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; ; DAC_SCK ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ; +---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +-------------------------------------------------------------------+ ; Setup Transfers ; +------------+----------+----------+----------+----------+----------+ ; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; +------------+----------+----------+----------+----------+----------+ ; CLOCK_50 ; CLOCK_50 ; 497 ; 0 ; 0 ; 0 ; +------------+----------+----------+----------+----------+----------+ Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. +-------------------------------------------------------------------+ ; Hold Transfers ; +------------+----------+----------+----------+----------+----------+ ; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; +------------+----------+----------+----------+----------+----------+ ; CLOCK_50 ; CLOCK_50 ; 497 ; 0 ; 0 ; 0 ; +------------+----------+----------+----------+----------+----------+ Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. --------------- ; Report TCCS ; --------------- No dedicated SERDES Transmitter circuitry present in device or used in design --------------- ; Report RSKM ; --------------- No non-DPA dedicated SERDES Receiver circuitry present in device or used in design +------------------------------------------------+ ; Unconstrained Paths Summary ; +---------------------------------+-------+------+ ; Property ; Setup ; Hold ; +---------------------------------+-------+------+ ; Illegal Clocks ; 0 ; 0 ; ; Unconstrained Clocks ; 1 ; 1 ; ; Unconstrained Input Ports ; 10 ; 10 ; ; Unconstrained Input Port Paths ; 10 ; 10 ; ; Unconstrained Output Ports ; 4 ; 4 ; ; Unconstrained Output Port Paths ; 17 ; 17 ; +---------------------------------+-------+------+ +---------------------------------------------------------+ ; Clock Status Summary ; +-----------------------+----------+------+---------------+ ; Target ; Clock ; Type ; Status ; +-----------------------+----------+------+---------------+ ; CLOCK_50 ; CLOCK_50 ; Base ; Constrained ; ; spi2dac:SPI0|clk_1MHz ; ; Base ; Unconstrained ; +-----------------------+----------+------+---------------+ +---------------------------------------------------------------------------------------------------+ ; Unconstrained Input Ports ; +------------+--------------------------------------------------------------------------------------+ ; Input Port ; Comment ; +------------+--------------------------------------------------------------------------------------+ ; SW[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ; SW[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ; SW[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ; SW[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ; SW[4] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ; SW[5] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ; SW[6] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ; SW[7] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ; SW[8] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ; SW[9] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +------------+--------------------------------------------------------------------------------------+ +-----------------------------------------------------------------------------------------------------+ ; Unconstrained Output Ports ; +-------------+---------------------------------------------------------------------------------------+ ; Output Port ; Comment ; +-------------+---------------------------------------------------------------------------------------+ ; DAC_CS ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ; DAC_LD ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ; DAC_SCK ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ; DAC_SDI ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +-------------+---------------------------------------------------------------------------------------+ +---------------------------------------------------------------------------------------------------+ ; Unconstrained Input Ports ; +------------+--------------------------------------------------------------------------------------+ ; Input Port ; Comment ; +------------+--------------------------------------------------------------------------------------+ ; SW[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ; SW[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ; SW[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ; SW[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ; SW[4] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ; SW[5] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ; SW[6] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ; SW[7] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ; SW[8] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ; SW[9] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +------------+--------------------------------------------------------------------------------------+ +-----------------------------------------------------------------------------------------------------+ ; Unconstrained Output Ports ; +-------------+---------------------------------------------------------------------------------------+ ; Output Port ; Comment ; +-------------+---------------------------------------------------------------------------------------+ ; DAC_CS ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ; DAC_LD ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ; DAC_SCK ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ; DAC_SDI ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +-------------+---------------------------------------------------------------------------------------+ +------------------------------------+ ; TimeQuest Timing Analyzer Messages ; +------------------------------------+ Info: ******************************************************************* Info: Running Quartus Prime TimeQuest Timing Analyzer Info: Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition Info: Processing started: Mon Dec 05 10:51:01 2016 Info: Command: quartus_sta ex10 -c ex10_top Info: qsta_default_script.tcl version: #1 Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected Info (21077): Low junction temperature is 0 degrees C Info (21077): High junction temperature is 85 degrees C Info (332104): Reading SDC File: 'ex10_top.sdc' Warning (332060): Node: spi2dac:SPI0|clk_1MHz was determined to be a clock but was found without an associated clock assignment. Info (13166): Register spi2dac:SPI0|shift_reg[11] is being clocked by spi2dac:SPI0|clk_1MHz Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty" Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON Info: Analyzing Slow 1100mV 85C Model Info (332146): Worst-case setup slack is 16.148 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 16.148 0.000 CLOCK_50 Info (332146): Worst-case hold slack is 0.362 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 0.362 0.000 CLOCK_50 Info (332140): No Recovery paths to report Info (332140): No Removal paths to report Info (332146): Worst-case minimum pulse width slack is 8.815 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 8.815 0.000 CLOCK_50 Info: Analyzing Slow 1100mV 0C Model Info (334003): Started post-fitting delay annotation Info (334004): Delay annotation completed successfully Warning (332060): Node: spi2dac:SPI0|clk_1MHz was determined to be a clock but was found without an associated clock assignment. Info (13166): Register spi2dac:SPI0|shift_reg[11] is being clocked by spi2dac:SPI0|clk_1MHz Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. Info (332146): Worst-case setup slack is 16.023 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 16.023 0.000 CLOCK_50 Info (332146): Worst-case hold slack is 0.343 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 0.343 0.000 CLOCK_50 Info (332140): No Recovery paths to report Info (332140): No Removal paths to report Info (332146): Worst-case minimum pulse width slack is 8.805 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 8.805 0.000 CLOCK_50 Info: Analyzing Fast 1100mV 85C Model Info (334003): Started post-fitting delay annotation Info (334004): Delay annotation completed successfully Warning (332060): Node: spi2dac:SPI0|clk_1MHz was determined to be a clock but was found without an associated clock assignment. Info (13166): Register spi2dac:SPI0|shift_reg[11] is being clocked by spi2dac:SPI0|clk_1MHz Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. Info (332146): Worst-case setup slack is 17.543 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 17.543 0.000 CLOCK_50 Info (332146): Worst-case hold slack is 0.183 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 0.183 0.000 CLOCK_50 Info (332140): No Recovery paths to report Info (332140): No Removal paths to report Info (332146): Worst-case minimum pulse width slack is 8.762 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 8.762 0.000 CLOCK_50 Info: Analyzing Fast 1100mV 0C Model Warning (332060): Node: spi2dac:SPI0|clk_1MHz was determined to be a clock but was found without an associated clock assignment. Info (13166): Register spi2dac:SPI0|shift_reg[11] is being clocked by spi2dac:SPI0|clk_1MHz Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. Info (332146): Worst-case setup slack is 17.666 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 17.666 0.000 CLOCK_50 Info (332146): Worst-case hold slack is 0.172 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 0.172 0.000 CLOCK_50 Info (332140): No Recovery paths to report Info (332140): No Removal paths to report Info (332146): Worst-case minimum pulse width slack is 8.741 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 8.741 0.000 CLOCK_50 Info (332102): Design is not fully constrained for setup requirements Info (332102): Design is not fully constrained for hold requirements Info: Quartus Prime TimeQuest Timing Analyzer was successful. 0 errors, 5 warnings Info: Peak virtual memory: 1183 megabytes Info: Processing ended: Mon Dec 05 10:51:05 2016 Info: Elapsed time: 00:00:04 Info: Total CPU time (on all processors): 00:00:04