module ex15_top (
	CLOCK_50,
	DAC_SDI,
	DAC_CS,
	DAC_LD,
	DAC_SCK,
	PWM_OUT,
	HEX0,
	HEX1,
	HEX2,
	HEX3
);
	input CLOCK_50;
	output DAC_SDI,DAC_CS,DAC_SCK,DAC_LD,PWM_OUT;
	output [6:0] HEX0,HEX1,HEX2,HEX3;

	wire CLOCK_DIVIDED;
	reg [9:0] A;
	wire [9:0] D;
	wire [23:0] MULTRESULT;
	wire [9:0] ADC_RESULT;
	wire ADC_VALID;
	wire [3:0] BCD0,BCD1,BCD2,BCD3;
	
	divider_5000 DIV0 (CLOCK_50, CLOCK_DIVIDED);
	
	spi2adc SPI1 (
	.sysclk(CLOCK_50), 
	.start(CLOCK_DIVIDED),
	.channel(1'b0), //Channel 0 is the Potentiometer 
	.data_from_adc(ADC_RESULT), 
	.data_valid(ADC_VALID), //Assume data is always valid
	.sdata_to_adc(ADC_SDO), 
	.adc_cs(ADC_CS), 
	.adc_sck(ADC_SCK), 
	.sdata_from_adc(ADC_SDI)
	);
	
	
	always @ (posedge CLOCK_DIVIDED)
	begin
		A <= A + ADC_RESULT;
	end
	
	MULT_accum_u5f MULT10K (
		.clock(CLOCK_50),
		.sload(CLOCK_DIVIDED),
		.data(ADC_RESULT[9:0]),
		.result(MULTRESULT)
	);
	
	bin2bcd_16 BIN0 (
		.B(MULTRESULT[23:10]),
		.BCD_0(BCD0),
		.BCD_1(BCD1),
		.BCD_2(BCD2),
		.BCD_3(BCD3)
	);
	
	hex_to_7seg SEG0 (.out(HEX0),.in(BCD0));
	hex_to_7seg SEG1 (.out(HEX1),.in(BCD1));
	hex_to_7seg SEG2 (.out(HEX2),.in(BCD2));
	hex_to_7seg SEG3 (.out(HEX3),.in(BCD3));
	
	ROM ROM0 (
		.address(A),
		.clock(CLOCK_DIVIDED),
		.q(D[9:0])
	);
	
	spi2dac SPI0 (
		.sysclk(CLOCK_50), 
		.data_in(D[9:0]), 
		.load(CLOCK_DIVIDED), 
		.dac_sdi(DAC_SDI), 
		.dac_cs(DAC_CS), 
		.dac_sck(DAC_SCK), 
		.dac_ld(DAC_LD)
	);
		
	pwm PWM0 (
		.clk(CLOCK_50), 
		.data_in(D[9:0]), 
		.load(CLOCK_DIVIDED), 
		.pwm_out(PWM_OUT)
	);
	
endmodule