`timescale 1ns / 100ps


module divider_5000 (
		clock,
		out
		);
		
		parameter BIT_SZ = 16;
		input clock;
		reg [BIT_SZ-1:0] count;
		
		initial count = 0;
		
		output reg out;
		
		
		always @ (posedge clock)
		begin
			if (count < 16'd5000)
				begin
				count <= count + 1'b1;
				out <= 1'b0;
				end
			else
				begin
				out <= 1'b1;
				count <= 1'b0;		
				end
		end
endmodule