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| author | Vasil Zlatanov <v@skozl.com> | 2016-12-12 21:51:10 +0000 |
|---|---|---|
| committer | Vasil Zlatanov <v@skozl.com> | 2016-12-12 21:51:10 +0000 |
| commit | 4b6e0102d20d9ab060ce930e4b846c8be446bb06 (patch) | |
| tree | e475eab3716738f2928f0b2063956e9b155f94ab /part_1/ex4/bin2bcd_8.v | |
| download | e2-verilab-4b6e0102d20d9ab060ce930e4b846c8be446bb06.tar.gz e2-verilab-4b6e0102d20d9ab060ce930e4b846c8be446bb06.tar.bz2 e2-verilab-4b6e0102d20d9ab060ce930e4b846c8be446bb06.zip | |
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Diffstat (limited to 'part_1/ex4/bin2bcd_8.v')
| -rw-r--r-- | part_1/ex4/bin2bcd_8.v | 48 |
1 files changed, 48 insertions, 0 deletions
diff --git a/part_1/ex4/bin2bcd_8.v b/part_1/ex4/bin2bcd_8.v new file mode 100644 index 0000000..dc382b9 --- /dev/null +++ b/part_1/ex4/bin2bcd_8.v @@ -0,0 +1,48 @@ +//------------------------------
+// Module name: bin2bcd_8
+// Function: Converts an 8-bit binary number to 3 digits BCD
+// .... it uses a shift-and-add3 algorithm
+// Creator: Peter Cheung
+// Version: 1.0
+// Date: 17 Sept 2016
+//------------------------------
+// For more explanation of how this work, see
+// ... instructions on wwww.ee.ic.ac.uk/pcheung/teaching/E2_experiment
+
+module bin2bcd_8 (B, BCD_0, BCD_1, BCD_2);
+
+ input [7:0] B; // binary input number
+ output [3:0] BCD_0, BCD_1, BCD_2; // BCD digit LSD to MSD
+
+ wire [3:0] w1,w2,w3,w4,w5,w6,w7;
+ wire [3:0] a1,a2,a3,a4,a5,a6,a7;
+
+ // Instantiate a tree of add3-if-greater than or equal to 5 cells
+ // ... input is w_n, and output is a_n
+ add3_ge5 A1 (w1,a1);
+ add3_ge5 A2 (w2,a2);
+ add3_ge5 A3 (w3,a3);
+ add3_ge5 A4 (w4,a4);
+ add3_ge5 A5 (w5,a5);
+ add3_ge5 A6 (w6,a6);
+ add3_ge5 A7 (w7,a7);
+
+ // wire the tree of add3 modules together
+ assign w1 = {1'b0, B[7:5]}; // wn is the input port to module An
+ assign w2 = {a1[2:0], B[4]};
+ assign w3 = {a2[2:0], B[3]};
+ assign w4 = {1'b0, a1[3], a2[3], a3[3]};
+ assign w5 = {a3[2:0], B[2]};
+ assign w6 = {a4[2:0], a5[3]};
+ assign w7 = {a5[2:0], B[1]};
+
+ // connect up to four BCD digit outputs
+ assign BCD_0 = {a7[2:0],B[0]};
+ assign BCD_1 = {a6[2:0],a7[3]};
+ assign BCD_2 = {2'b0,a4[3],a6[3]};
+
+endmodule
+
+
+
+
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