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| author | Vasil Zlatanov <v@skozl.com> | 2016-12-12 21:51:10 +0000 |
|---|---|---|
| committer | Vasil Zlatanov <v@skozl.com> | 2016-12-12 21:51:10 +0000 |
| commit | 4b6e0102d20d9ab060ce930e4b846c8be446bb06 (patch) | |
| tree | e475eab3716738f2928f0b2063956e9b155f94ab /part_2/ex9/delay.v | |
| download | e2-verilab-4b6e0102d20d9ab060ce930e4b846c8be446bb06.tar.gz e2-verilab-4b6e0102d20d9ab060ce930e4b846c8be446bb06.tar.bz2 e2-verilab-4b6e0102d20d9ab060ce930e4b846c8be446bb06.zip | |
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Diffstat (limited to 'part_2/ex9/delay.v')
| -rw-r--r-- | part_2/ex9/delay.v | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/part_2/ex9/delay.v b/part_2/ex9/delay.v new file mode 100644 index 0000000..71bee21 --- /dev/null +++ b/part_2/ex9/delay.v @@ -0,0 +1,26 @@ +module delay(
+ input CLOCK,
+ input [13:0] DELAY,
+ input START_DELAY,
+ output reg TIME_OUT
+);
+ reg [13:0] COUNT;
+
+ always @ (posedge CLOCK)
+ begin
+ if (START_DELAY == 1'b1)
+ begin
+ if (COUNT < DELAY+14'd24)
+ begin
+ COUNT <= COUNT + 1'b1;
+ TIME_OUT <= 1'b0;
+ end
+ else
+ begin
+ COUNT <= 0;
+ TIME_OUT <= 1'b1;
+ end
+ end
+
+ end
+endmodule
|