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| author | Vasil Zlatanov <v@skozl.com> | 2016-12-12 21:51:10 +0000 |
|---|---|---|
| committer | Vasil Zlatanov <v@skozl.com> | 2016-12-12 21:51:10 +0000 |
| commit | 4b6e0102d20d9ab060ce930e4b846c8be446bb06 (patch) | |
| tree | e475eab3716738f2928f0b2063956e9b155f94ab /part_2/ex9/ex9_top.v | |
| download | e2-verilab-4b6e0102d20d9ab060ce930e4b846c8be446bb06.tar.gz e2-verilab-4b6e0102d20d9ab060ce930e4b846c8be446bb06.tar.bz2 e2-verilab-4b6e0102d20d9ab060ce930e4b846c8be446bb06.zip | |
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Diffstat (limited to 'part_2/ex9/ex9_top.v')
| -rw-r--r-- | part_2/ex9/ex9_top.v | 50 |
1 files changed, 50 insertions, 0 deletions
diff --git a/part_2/ex9/ex9_top.v b/part_2/ex9/ex9_top.v new file mode 100644 index 0000000..b894df2 --- /dev/null +++ b/part_2/ex9/ex9_top.v @@ -0,0 +1,50 @@ +module ex9_top (
+ input CLOCK_50,
+
+ input [3:0] KEY,
+
+ output [6:0] HEX0,
+ output [6:0] HEX1,
+ output [6:0] HEX2,
+ output [6:0] HEX3,
+ output [6:0] HEX4,
+ output [9:0] LEDR
+);
+ // Define 1ms and 0.5s (half-second)
+ wire CLOCK_MS;
+ wire CLOCK_HS;
+
+ wire [15:0] B;
+ wire [3:0] BCD_0;
+ wire [3:0] BCD_1;
+ wire [3:0] BCD_2;
+ wire [3:0] BCD_3;
+ wire [3:0] BCD_4;
+
+ wire TIME_OUT;
+ wire START_DELAY;
+ wire EN_LFSR;
+ wire [13:0] PRBS;
+ wire COUNT;
+ wire [15:0] TIME;
+ wire COUNT_CLEAR;
+
+ divider_50000 DIV0 (CLOCK_50, CLOCK_MS);
+ divider_2500 DIV1 (CLOCK_50, CLOCK_MS, CLOCK_HS);
+
+ fsm FSM0 (CLOCK_MS, CLOCK_HS, KEY[3], TIME_OUT, START_DELAY, EN_LFSR, LEDR, COUNT, COUNT_CLEAR);
+
+ delay DELAY0 (CLOCK_MS, PRBS, START_DELAY, TIME_OUT);
+
+ lfsr LSFR0 (CLOCK_MS, EN_LFSR, PRBS);
+
+ timer TIME0 (CLOCK_MS, COUNT, COUNT_CLEAR, TIME);
+
+ bin2bcd_16 BIN0 (TIME, BCD_0, BCD_1, BCD_2, BCD_3, BCD_4);
+
+ hex_to_7seg SEG0 (HEX0,BCD_0);
+ hex_to_7seg SEG1 (HEX1,BCD_1);
+ hex_to_7seg SEG2 (HEX2,BCD_2);
+ hex_to_7seg SEG3 (HEX3,BCD_3);
+ hex_to_7seg SEG4 (HEX4,BCD_4);
+endmodule
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