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authorVasil Zlatanov <v@skozl.com>2016-12-12 21:51:10 +0000
committerVasil Zlatanov <v@skozl.com>2016-12-12 21:51:10 +0000
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+module lfsr(
+ input CLOCK,
+ input ENABLE,
+ output reg [13:0] SHIFT
+);
+
+ initial SHIFT = 13'd1;
+
+ always @ (posedge CLOCK)
+ begin
+ if (ENABLE == 1'b1)
+ SHIFT <= {SHIFT[12:0],(SHIFT[13] ^ SHIFT[11]) ^ SHIFT[3]};
+ end
+endmodule