diff options
| author | Vasil Zlatanov <v@skozl.com> | 2016-12-12 21:51:10 +0000 |
|---|---|---|
| committer | Vasil Zlatanov <v@skozl.com> | 2016-12-12 21:51:10 +0000 |
| commit | 4b6e0102d20d9ab060ce930e4b846c8be446bb06 (patch) | |
| tree | e475eab3716738f2928f0b2063956e9b155f94ab /part_2/ex9/timer.v | |
| download | e2-verilab-4b6e0102d20d9ab060ce930e4b846c8be446bb06.tar.gz e2-verilab-4b6e0102d20d9ab060ce930e4b846c8be446bb06.tar.bz2 e2-verilab-4b6e0102d20d9ab060ce930e4b846c8be446bb06.zip | |
public push
Diffstat (limited to 'part_2/ex9/timer.v')
| -rw-r--r-- | part_2/ex9/timer.v | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/part_2/ex9/timer.v b/part_2/ex9/timer.v new file mode 100644 index 0000000..4974ca2 --- /dev/null +++ b/part_2/ex9/timer.v @@ -0,0 +1,18 @@ +`timescale 1ns / 100ps
+
+
+module timer (
+ input clock,
+ input count,
+ input count_clear,
+ output reg [15:0] tim
+ );
+
+ always @ (posedge clock)
+ begin
+ if (count_clear)
+ tim <= 0;
+ else if (count)
+ tim <= tim + 16'b1;
+ end
+endmodule
|