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| author | Vasil Zlatanov <v@skozl.com> | 2016-12-12 21:51:10 +0000 |
|---|---|---|
| committer | Vasil Zlatanov <v@skozl.com> | 2016-12-12 21:51:10 +0000 |
| commit | 4b6e0102d20d9ab060ce930e4b846c8be446bb06 (patch) | |
| tree | e475eab3716738f2928f0b2063956e9b155f94ab /part_3/ex10/ex10_top.v | |
| download | e2-verilab-4b6e0102d20d9ab060ce930e4b846c8be446bb06.tar.gz e2-verilab-4b6e0102d20d9ab060ce930e4b846c8be446bb06.tar.bz2 e2-verilab-4b6e0102d20d9ab060ce930e4b846c8be446bb06.zip | |
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Diffstat (limited to 'part_3/ex10/ex10_top.v')
| -rw-r--r-- | part_3/ex10/ex10_top.v | 29 |
1 files changed, 29 insertions, 0 deletions
diff --git a/part_3/ex10/ex10_top.v b/part_3/ex10/ex10_top.v new file mode 100644 index 0000000..730c3ca --- /dev/null +++ b/part_3/ex10/ex10_top.v @@ -0,0 +1,29 @@ +
+
+module ex10_top (
+ SW,
+ CLOCK_50,
+ DAC_SDI,
+ DAC_CS,
+ DAC_LD,
+ DAC_SCK
+);
+ input CLOCK_50;
+ input [9:0] SW;
+ output DAC_SDI,DAC_CS,DAC_SCK,DAC_LD;
+
+ wire CLOCK_DIVIDED;
+
+ divider_5000 COUNT0 (CLOCK_50, CLOCK_DIVIDED);
+
+ spi2dac SPI0 (
+ .sysclk(CLOCK_50),
+ .data_in(SW[9:0]),
+ .load(CLOCK_DIVIDED),
+ .dac_sdi(DAC_SDI),
+ .dac_cs(DAC_CS),
+ .dac_sck(DAC_SCK),
+ .dac_ld(DAC_LD)
+ );
+
+endmodule
\ No newline at end of file |