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| author | Vasil Zlatanov <v@skozl.com> | 2016-12-12 21:51:10 +0000 |
|---|---|---|
| committer | Vasil Zlatanov <v@skozl.com> | 2016-12-12 21:51:10 +0000 |
| commit | 4b6e0102d20d9ab060ce930e4b846c8be446bb06 (patch) | |
| tree | e475eab3716738f2928f0b2063956e9b155f94ab /part_3/ex10/ex10_top_nativelink_simulation.rpt | |
| download | e2-verilab-4b6e0102d20d9ab060ce930e4b846c8be446bb06.tar.gz e2-verilab-4b6e0102d20d9ab060ce930e4b846c8be446bb06.tar.bz2 e2-verilab-4b6e0102d20d9ab060ce930e4b846c8be446bb06.zip | |
public push
Diffstat (limited to 'part_3/ex10/ex10_top_nativelink_simulation.rpt')
| -rw-r--r-- | part_3/ex10/ex10_top_nativelink_simulation.rpt | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/part_3/ex10/ex10_top_nativelink_simulation.rpt b/part_3/ex10/ex10_top_nativelink_simulation.rpt new file mode 100644 index 0000000..269b5a5 --- /dev/null +++ b/part_3/ex10/ex10_top_nativelink_simulation.rpt @@ -0,0 +1,22 @@ +Info: Start Nativelink Simulation process
+Info: NativeLink has detected Verilog design -- Verilog simulation models will be used
+
+========= EDA Simulation Settings =====================
+
+Sim Mode : RTL
+Family : cyclonev
+Quartus root : c:/altera/16.0/quartus/bin64/
+Quartus sim root : c:/altera/16.0/quartus/eda/sim_lib
+Simulation Tool : modelsim-altera
+Simulation Language : verilog
+Simulation Mode : GUI
+Sim Output File :
+Sim SDF file :
+Sim dir : simulation\modelsim
+
+=======================================================
+
+Info: Starting NativeLink simulation with ModelSim-Altera software
+Sourced NativeLink script c:/altera/16.0/quartus/common/tcl/internal/nativelink/modelsim.tcl
+Warning: File ex10_top_run_msim_rtl_verilog.do already exists - backing up current file as ex10_top_run_msim_rtl_verilog.do.bak2
+Info: Spawning ModelSim-Altera Simulation software
|