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| author | Vasil Zlatanov <v@skozl.com> | 2016-12-12 21:51:10 +0000 |
|---|---|---|
| committer | Vasil Zlatanov <v@skozl.com> | 2016-12-12 21:51:10 +0000 |
| commit | 4b6e0102d20d9ab060ce930e4b846c8be446bb06 (patch) | |
| tree | e475eab3716738f2928f0b2063956e9b155f94ab /part_3/ex15/ex15_top.v | |
| download | e2-verilab-4b6e0102d20d9ab060ce930e4b846c8be446bb06.tar.gz e2-verilab-4b6e0102d20d9ab060ce930e4b846c8be446bb06.tar.bz2 e2-verilab-4b6e0102d20d9ab060ce930e4b846c8be446bb06.zip | |
public push
Diffstat (limited to 'part_3/ex15/ex15_top.v')
| -rw-r--r-- | part_3/ex15/ex15_top.v | 88 |
1 files changed, 88 insertions, 0 deletions
diff --git a/part_3/ex15/ex15_top.v b/part_3/ex15/ex15_top.v new file mode 100644 index 0000000..54aeb09 --- /dev/null +++ b/part_3/ex15/ex15_top.v @@ -0,0 +1,88 @@ +module ex15_top (
+ CLOCK_50,
+ DAC_SDI,
+ DAC_CS,
+ DAC_LD,
+ DAC_SCK,
+ PWM_OUT,
+ HEX0,
+ HEX1,
+ HEX2,
+ HEX3
+);
+ input CLOCK_50;
+ output DAC_SDI,DAC_CS,DAC_SCK,DAC_LD,PWM_OUT;
+ output [6:0] HEX0,HEX1,HEX2,HEX3;
+
+ wire CLOCK_DIVIDED;
+ reg [9:0] A;
+ wire [9:0] D;
+ wire [23:0] MULTRESULT;
+ wire [9:0] ADC_RESULT;
+ wire ADC_VALID;
+ wire [3:0] BCD0,BCD1,BCD2,BCD3;
+
+ divider_5000 DIV0 (CLOCK_50, CLOCK_DIVIDED);
+
+ spi2adc SPI1 (
+ .sysclk(CLOCK_50),
+ .start(CLOCK_DIVIDED),
+ .channel(1'b0), //Channel 0 is the Potentiometer
+ .data_from_adc(ADC_RESULT),
+ .data_valid(ADC_VALID), //Assume data is always valid
+ .sdata_to_adc(ADC_SDO),
+ .adc_cs(ADC_CS),
+ .adc_sck(ADC_SCK),
+ .sdata_from_adc(ADC_SDI)
+ );
+
+
+ always @ (posedge CLOCK_DIVIDED)
+ begin
+ A <= A + ADC_RESULT;
+ end
+
+ MULT_accum_u5f MULT10K (
+ .clock(CLOCK_50),
+ .sload(CLOCK_DIVIDED),
+ .data(ADC_RESULT[9:0]),
+ .result(MULTRESULT)
+ );
+
+ bin2bcd_16 BIN0 (
+ .B(MULTRESULT[23:10]),
+ .BCD_0(BCD0),
+ .BCD_1(BCD1),
+ .BCD_2(BCD2),
+ .BCD_3(BCD3)
+ );
+
+ hex_to_7seg SEG0 (.out(HEX0),.in(BCD0));
+ hex_to_7seg SEG1 (.out(HEX1),.in(BCD1));
+ hex_to_7seg SEG2 (.out(HEX2),.in(BCD2));
+ hex_to_7seg SEG3 (.out(HEX3),.in(BCD3));
+
+ ROM ROM0 (
+ .address(A),
+ .clock(CLOCK_DIVIDED),
+ .q(D[9:0])
+ );
+
+ spi2dac SPI0 (
+ .sysclk(CLOCK_50),
+ .data_in(D[9:0]),
+ .load(CLOCK_DIVIDED),
+ .dac_sdi(DAC_SDI),
+ .dac_cs(DAC_CS),
+ .dac_sck(DAC_SCK),
+ .dac_ld(DAC_LD)
+ );
+
+ pwm PWM0 (
+ .clk(CLOCK_50),
+ .data_in(D[9:0]),
+ .load(CLOCK_DIVIDED),
+ .pwm_out(PWM_OUT)
+ );
+
+endmodule
\ No newline at end of file |