diff options
| author | Vasil Zlatanov <v@skozl.com> | 2016-12-12 21:51:10 +0000 |
|---|---|---|
| committer | Vasil Zlatanov <v@skozl.com> | 2016-12-12 21:51:10 +0000 |
| commit | 4b6e0102d20d9ab060ce930e4b846c8be446bb06 (patch) | |
| tree | e475eab3716738f2928f0b2063956e9b155f94ab /part_3/ex15/output_files/ex15_top.flow.rpt | |
| download | e2-verilab-4b6e0102d20d9ab060ce930e4b846c8be446bb06.tar.gz e2-verilab-4b6e0102d20d9ab060ce930e4b846c8be446bb06.tar.bz2 e2-verilab-4b6e0102d20d9ab060ce930e4b846c8be446bb06.zip | |
public push
Diffstat (limited to 'part_3/ex15/output_files/ex15_top.flow.rpt')
| -rw-r--r-- | part_3/ex15/output_files/ex15_top.flow.rpt | 130 |
1 files changed, 130 insertions, 0 deletions
diff --git a/part_3/ex15/output_files/ex15_top.flow.rpt b/part_3/ex15/output_files/ex15_top.flow.rpt new file mode 100644 index 0000000..5b2f3d6 --- /dev/null +++ b/part_3/ex15/output_files/ex15_top.flow.rpt @@ -0,0 +1,130 @@ +Flow report for ex15_top
+Mon Dec 05 14:43:57 2016
+Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+ 1. Legal Notice
+ 2. Flow Summary
+ 3. Flow Settings
+ 4. Flow Non-Default Global Settings
+ 5. Flow Elapsed Time
+ 6. Flow OS Summary
+ 7. Flow Log
+ 8. Flow Messages
+ 9. Flow Suppressed Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+Your use of Altera Corporation's design tools, logic functions
+and other software and tools, and its AMPP partner logic
+functions, and any output files from any of the foregoing
+(including device programming or simulation files), and any
+associated documentation or information are expressly subject
+to the terms and conditions of the Altera Program License
+Subscription Agreement, the Altera Quartus Prime License Agreement,
+the Altera MegaCore Function License Agreement, or other
+applicable license agreement, including, without limitation,
+that your use is for the sole purpose of programming logic
+devices manufactured by Altera and sold by Altera or its
+authorized distributors. Please refer to the applicable
+agreement for further details.
+
+
+
++-----------------------------------------------------------------------------------+
+; Flow Summary ;
++---------------------------------+-------------------------------------------------+
+; Flow Status ; Successful - Mon Dec 05 14:43:46 2016 ;
+; Quartus Prime Version ; 16.0.0 Build 211 04/27/2016 SJ Standard Edition ;
+; Revision Name ; ex15_top ;
+; Top-level Entity Name ; ex15_top ;
+; Family ; Cyclone V ;
+; Device ; 5CSEMA5F31C6 ;
+; Timing Models ; Final ;
+; Logic utilization (in ALMs) ; 89 / 32,070 ( < 1 % ) ;
+; Total registers ; 90 ;
+; Total pins ; 34 / 457 ( 7 % ) ;
+; Total virtual pins ; 0 ;
+; Total block memory bits ; 0 / 4,065,280 ( 0 % ) ;
+; Total DSP Blocks ; 0 / 87 ( 0 % ) ;
+; Total HSSI RX PCSs ; 0 ;
+; Total HSSI PMA RX Deserializers ; 0 ;
+; Total HSSI TX PCSs ; 0 ;
+; Total HSSI PMA TX Serializers ; 0 ;
+; Total PLLs ; 0 / 6 ( 0 % ) ;
+; Total DLLs ; 0 / 4 ( 0 % ) ;
++---------------------------------+-------------------------------------------------+
+
+
++-----------------------------------------+
+; Flow Settings ;
++-------------------+---------------------+
+; Option ; Setting ;
++-------------------+---------------------+
+; Start date & time ; 12/05/2016 14:42:19 ;
+; Main task ; Compilation ;
+; Revision Name ; ex15_top ;
++-------------------+---------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------+
+; Flow Non-Default Global Settings ;
++-------------------------------------+---------------------------------------+---------------+-------------+------------+
+; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
++-------------------------------------+---------------------------------------+---------------+-------------+------------+
+; COMPILER_SIGNATURE_ID ; 48549626425810.148094893807912 ; -- ; -- ; -- ;
+; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
+; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
+; MISC_FILE ; ROM_bb.v ; -- ; -- ; -- ;
+; MISC_FILE ; MULT_bb.v ; -- ; -- ; -- ;
+; PARTITION_COLOR ; 16764057 ; -- ; -- ; Top ;
+; PARTITION_FITTER_PRESERVATION_LEVEL ; PLACEMENT_AND_ROUTING ; -- ; -- ; Top ;
+; PARTITION_NETLIST_TYPE ; SOURCE ; -- ; -- ; Top ;
+; POWER_BOARD_THERMAL_MODEL ; None (CONSERVATIVE) ; -- ; -- ; -- ;
+; POWER_PRESET_COOLING_SOLUTION ; 23 MM HEAT SINK WITH 200 LFPM AIRFLOW ; -- ; -- ; -- ;
+; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ;
++-------------------------------------+---------------------------------------+---------------+-------------+------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------+
+; Flow Elapsed Time ;
++---------------------------+--------------+-------------------------+---------------------+------------------------------------+
+; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
++---------------------------+--------------+-------------------------+---------------------+------------------------------------+
+; Analysis & Synthesis ; 00:00:14 ; 1.0 ; 901 MB ; 00:00:28 ;
+; Fitter ; 00:00:59 ; 1.0 ; 3154 MB ; 00:01:21 ;
+; Assembler ; 00:00:10 ; 1.0 ; 895 MB ; 00:00:08 ;
+; TimeQuest Timing Analyzer ; 00:00:10 ; 1.1 ; 1444 MB ; 00:00:09 ;
+; Total ; 00:01:33 ; -- ; -- ; 00:02:06 ;
++---------------------------+--------------+-------------------------+---------------------+------------------------------------+
+
+
++----------------------------------------------------------------------------------------+
+; Flow OS Summary ;
++---------------------------+------------------+-----------+------------+----------------+
+; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ;
++---------------------------+------------------+-----------+------------+----------------+
+; Analysis & Synthesis ; eews305-071 ; Windows 7 ; 6.1 ; x86_64 ;
+; Fitter ; eews305-071 ; Windows 7 ; 6.1 ; x86_64 ;
+; Assembler ; eews305-071 ; Windows 7 ; 6.1 ; x86_64 ;
+; TimeQuest Timing Analyzer ; eews305-071 ; Windows 7 ; 6.1 ; x86_64 ;
++---------------------------+------------------+-----------+------------+----------------+
+
+
+------------
+; Flow Log ;
+------------
+quartus_map --read_settings_files=on --write_settings_files=off ex15 -c ex15_top
+quartus_fit --read_settings_files=off --write_settings_files=off ex15 -c ex15_top
+quartus_asm --read_settings_files=off --write_settings_files=off ex15 -c ex15_top
+quartus_sta ex15 -c ex15_top
+
+
+
|