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| author | Vasil Zlatanov <v@skozl.com> | 2016-12-12 21:51:10 +0000 |
|---|---|---|
| committer | Vasil Zlatanov <v@skozl.com> | 2016-12-12 21:51:10 +0000 |
| commit | 4b6e0102d20d9ab060ce930e4b846c8be446bb06 (patch) | |
| tree | e475eab3716738f2928f0b2063956e9b155f94ab /part_4/ex16/clktick_16.v | |
| download | e2-verilab-4b6e0102d20d9ab060ce930e4b846c8be446bb06.tar.gz e2-verilab-4b6e0102d20d9ab060ce930e4b846c8be446bb06.tar.bz2 e2-verilab-4b6e0102d20d9ab060ce930e4b846c8be446bb06.zip | |
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Diffstat (limited to 'part_4/ex16/clktick_16.v')
| -rw-r--r-- | part_4/ex16/clktick_16.v | 42 |
1 files changed, 42 insertions, 0 deletions
diff --git a/part_4/ex16/clktick_16.v b/part_4/ex16/clktick_16.v new file mode 100644 index 0000000..e6b99eb --- /dev/null +++ b/part_4/ex16/clktick_16.v @@ -0,0 +1,42 @@ +// Design Name : clktick_16
+// File Name : clktick.v
+// Function : divide an input clock signal by n+1
+//-----------------------------------------------------
+
+module clktick_16 (
+ clkin, // Clock input to the design
+ enable, // enable clk divider
+ N, // Clock division factor is N+1
+ tick // pulse_out goes high for one cycle (n+1) clock cycles
+); // End of port list
+
+parameter N_BIT = 16;
+//-------------Input Ports-----------------------------
+input clkin;
+input enable;
+input [N_BIT-1:0] N;
+
+//-------------Output Ports----------------------------
+output tick;
+
+//-------------Output Ports Data Type------------------
+// Output port can be a storage element (reg) or a wire
+reg [N_BIT-1:0] count;
+reg tick;
+
+initial tick = 1'b0;
+
+//------------ Main Body of the module ------------------------
+
+ always @ (posedge clkin)
+ if (enable == 1'b1)
+ if (count == 0) begin
+ tick <= 1'b1;
+ count <= N;
+ end
+ else begin
+ tick <= 1'b0;
+ count <= count - 1'b1;
+ end
+
+endmodule // End of Module clktick
\ No newline at end of file |