diff options
| author | Vasil Zlatanov <v@skozl.com> | 2016-12-12 21:51:10 +0000 |
|---|---|---|
| committer | Vasil Zlatanov <v@skozl.com> | 2016-12-12 21:51:10 +0000 |
| commit | 4b6e0102d20d9ab060ce930e4b846c8be446bb06 (patch) | |
| tree | e475eab3716738f2928f0b2063956e9b155f94ab /part_4/ex16/simulation/modelsim/init_adc.do | |
| download | e2-verilab-4b6e0102d20d9ab060ce930e4b846c8be446bb06.tar.gz e2-verilab-4b6e0102d20d9ab060ce930e4b846c8be446bb06.tar.bz2 e2-verilab-4b6e0102d20d9ab060ce930e4b846c8be446bb06.zip | |
public push
Diffstat (limited to 'part_4/ex16/simulation/modelsim/init_adc.do')
| -rw-r--r-- | part_4/ex16/simulation/modelsim/init_adc.do | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/part_4/ex16/simulation/modelsim/init_adc.do b/part_4/ex16/simulation/modelsim/init_adc.do new file mode 100644 index 0000000..1269f00 --- /dev/null +++ b/part_4/ex16/simulation/modelsim/init_adc.do @@ -0,0 +1,23 @@ +add wave sysclk +add wave clk_1MHz +add wave start +add wave data_from_adc +add wave data_valid +add wave -hexadecimal data_out +add wave adc_cs +add wave adc_sck +add wave adc_done +add wave adc_din +add wave -hexadecimal shift_reg +add wave -hexadecimal state +add wave shift_ena +force sysclk 1 0, 0 {10 ns} -r 20 ns +force start 0 +run 200ns +force start 1 +run 200ns +force start 0 +force data_from_adc 0 @ 1us, 1 @ 6us, 0 @ 8us, 1 @ 10us, 0 @ 13us, 1 @ 15us + +run 20us + |