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| author | Vasil Zlatanov <v@skozl.com> | 2016-12-12 21:51:10 +0000 |
|---|---|---|
| committer | Vasil Zlatanov <v@skozl.com> | 2016-12-12 21:51:10 +0000 |
| commit | 4b6e0102d20d9ab060ce930e4b846c8be446bb06 (patch) | |
| tree | e475eab3716738f2928f0b2063956e9b155f94ab /part_4/mylib/pwm.v | |
| download | e2-verilab-4b6e0102d20d9ab060ce930e4b846c8be446bb06.tar.gz e2-verilab-4b6e0102d20d9ab060ce930e4b846c8be446bb06.tar.bz2 e2-verilab-4b6e0102d20d9ab060ce930e4b846c8be446bb06.zip | |
public push
Diffstat (limited to 'part_4/mylib/pwm.v')
| -rw-r--r-- | part_4/mylib/pwm.v | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/part_4/mylib/pwm.v b/part_4/mylib/pwm.v new file mode 100644 index 0000000..c3b34d9 --- /dev/null +++ b/part_4/mylib/pwm.v @@ -0,0 +1,25 @@ +module pwm (clk, data_in, load, pwm_out);
+
+ input clk; // system clock
+ input [9:0] data_in; // input data for conversion
+ input load; // high pulse to load new data
+ output pwm_out; // PWM output
+
+ reg [9:0] d; // internal register
+ reg [9:0] count; // internal 10-bit counter
+ reg pwm_out;
+
+ always @ (posedge clk)
+ if (load == 1'b1) d <= data_in;
+
+ initial count = 10'b0;
+
+ always @ (posedge clk) begin
+ count <= count + 1'b1;
+ if (count > d)
+ pwm_out <= 1'b0;
+ else
+ pwm_out <= 1'b1;
+ end
+
+endmodule
|