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-rw-r--r--part_3/ex12/ex12_top.v39
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diff --git a/part_3/ex12/ex12_top.v b/part_3/ex12/ex12_top.v
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+module ex12_top (
+ SW,
+ CLOCK_50,
+ HEX0,
+ HEX1,
+ HEX2,
+ HEX3
+
+);
+ input [9:0] SW;
+ input CLOCK_50;
+ output [6:0] HEX0,HEX1,HEX2,HEX3;
+ wire [9:0] DATA;
+ wire [3:0] BCD0,BCD1,BCD2,BCD3;
+
+ ROM ROM0 (
+ .address(SW[9:0]),
+ .clock(CLOCK_50),
+ .q(DATA)
+ );
+
+ bin2bcd_16 BIN0 (
+ .B(DATA),
+ .BCD_0(BCD0),
+ .BCD_1(BCD1),
+ .BCD_2(BCD2),
+ .BCD_3(BCD3)
+ );
+
+
+
+ hex_to_7seg SEG0 (.out(HEX0),.in(BCD0));
+ hex_to_7seg SEG1 (.out(HEX1),.in(BCD1));
+ hex_to_7seg SEG2 (.out(HEX2),.in(BCD2));
+ hex_to_7seg SEG3 (.out(HEX3),.in(BCD3));
+
+
+
+endmodule \ No newline at end of file