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-rw-r--r--part_3/ex13/ex13_top.v47
1 files changed, 47 insertions, 0 deletions
diff --git a/part_3/ex13/ex13_top.v b/part_3/ex13/ex13_top.v
new file mode 100644
index 0000000..d73043a
--- /dev/null
+++ b/part_3/ex13/ex13_top.v
@@ -0,0 +1,47 @@
+module ex13_top (
+ CLOCK_50,
+ DAC_SDI,
+ DAC_CS,
+ DAC_LD,
+ DAC_SCK,
+ PWM_OUT
+);
+ input CLOCK_50;
+ output DAC_SDI,DAC_CS,DAC_SCK,DAC_LD,PWM_OUT;
+
+ wire CLOCK_DIVIDED;
+ wire [9:0] A,D;
+
+ divider_5000 DIV0 (CLOCK_50, CLOCK_DIVIDED);
+
+ counter_16 COUNT0 (
+ .clock(CLOCK_50),
+ .enable(CLOCK_DIVIDED),
+ .reset(1'b1),
+ .count(A[9:0])
+ );
+
+ ROM ROM0 (
+ .address(A),
+ .clock(CLOCK_DIVIDED),
+ .q(D[9:0])
+ );
+
+ spi2dac SPI0 (
+ .sysclk(CLOCK_50),
+ .data_in(D[9:0]),
+ .load(CLOCK_DIVIDED),
+ .dac_sdi(DAC_SDI),
+ .dac_cs(DAC_CS),
+ .dac_sck(DAC_SCK),
+ .dac_ld(DAC_LD)
+ );
+
+ pwm PWM0 (
+ .clk(CLOCK_50),
+ .data_in(D[9:0]),
+ .load(CLOCK_DIVIDED),
+ .pwm_out(PWM_OUT)
+ );
+
+endmodule \ No newline at end of file