diff options
Diffstat (limited to 'part_4/ex16/ex16_top.eda.rpt')
| -rw-r--r-- | part_4/ex16/ex16_top.eda.rpt | 96 |
1 files changed, 96 insertions, 0 deletions
diff --git a/part_4/ex16/ex16_top.eda.rpt b/part_4/ex16/ex16_top.eda.rpt new file mode 100644 index 0000000..1421f53 --- /dev/null +++ b/part_4/ex16/ex16_top.eda.rpt @@ -0,0 +1,96 @@ +EDA Netlist Writer report for ex16_top
+Sat Dec 10 18:30:59 2016
+Quartus Prime Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+ 1. Legal Notice
+ 2. EDA Netlist Writer Summary
+ 3. Simulation Settings
+ 4. Simulation Generated Files
+ 5. EDA Netlist Writer Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 2016 Intel Corporation. All rights reserved.
+Your use of Intel Corporation's design tools, logic functions
+and other software and tools, and its AMPP partner logic
+functions, and any output files from any of the foregoing
+(including device programming or simulation files), and any
+associated documentation or information are expressly subject
+to the terms and conditions of the Intel Program License
+Subscription Agreement, the Intel Quartus Prime License Agreement,
+the Intel MegaCore Function License Agreement, or other
+applicable license agreement, including, without limitation,
+that your use is for the sole purpose of programming logic
+devices manufactured by Intel and sold by Intel or its
+authorized distributors. Please refer to the applicable
+agreement for further details.
+
+
+
++-------------------------------------------------------------------+
+; EDA Netlist Writer Summary ;
++---------------------------+---------------------------------------+
+; EDA Netlist Writer Status ; Successful - Sat Dec 10 18:30:59 2016 ;
+; Revision Name ; ex16_top ;
+; Top-level Entity Name ; ex16_top ;
+; Family ; Cyclone V ;
+; Simulation Files Creation ; Successful ;
++---------------------------+---------------------------------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------+
+; Simulation Settings ;
++---------------------------------------------------------------------------------------------------+---------------------------+
+; Option ; Setting ;
++---------------------------------------------------------------------------------------------------+---------------------------+
+; Tool Name ; ModelSim-Altera (Verilog) ;
+; Generate functional simulation netlist ; Off ;
+; Time scale ; 1 ps ;
+; Truncate long hierarchy paths ; Off ;
+; Map illegal HDL characters ; Off ;
+; Flatten buses into individual nodes ; Off ;
+; Maintain hierarchy ; Off ;
+; Bring out device-wide set/reset signals as ports ; Off ;
+; Enable glitch filtering ; Off ;
+; Do not write top level VHDL entity ; Off ;
+; Disable detection of setup and hold time violations in the input registers of bi-directional pins ; Off ;
+; Architecture name in VHDL output netlist ; structure ;
+; Generate third-party EDA tool command script for RTL functional simulation ; Off ;
+; Generate third-party EDA tool command script for gate-level simulation ; Off ;
++---------------------------------------------------------------------------------------------------+---------------------------+
+
+
++------------------------------------------------------------+
+; Simulation Generated Files ;
++------------------------------------------------------------+
+; Generated Files ;
++------------------------------------------------------------+
+; H:/Year 2/VERI/part_4/ex16/simulation/modelsim/ex16_top.vo ;
++------------------------------------------------------------+
+
+
++-----------------------------+
+; EDA Netlist Writer Messages ;
++-----------------------------+
+Info: *******************************************************************
+Info: Running Quartus Prime EDA Netlist Writer
+ Info: Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition
+ Info: Processing started: Sat Dec 10 18:30:46 2016
+Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off ex16 -c ex16_top
+Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
+Warning (10905): Generated the EDA functional simulation netlist because it is the only supported netlist type for this device.
+Info (204019): Generated file ex16_top.vo in folder "H:/Year 2/VERI/part_4/ex16/simulation/modelsim/" for EDA simulation tool
+Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 2 warnings
+ Info: Peak virtual memory: 628 megabytes
+ Info: Processing ended: Sat Dec 10 18:31:01 2016
+ Info: Elapsed time: 00:00:15
+ Info: Total CPU time (on all processors): 00:00:03
+
+
|