1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
|
Analysis & Synthesis report for ex4_top
Thu Nov 17 11:14:11 2016
Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Analysis & Synthesis Summary
3. Analysis & Synthesis Settings
4. Parallel Compilation
5. Analysis & Synthesis Source Files Read
6. Analysis & Synthesis Resource Usage Summary
7. Analysis & Synthesis Resource Utilization by Entity
8. General Register Statistics
9. Port Connectivity Checks: "hex_to_7seg:SEG3"
10. Post-Synthesis Netlist Statistics for Top Partition
11. Elapsed Time Per Partition
12. Analysis & Synthesis Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, the Altera Quartus Prime License Agreement,
the Altera MegaCore Function License Agreement, or other
applicable license agreement, including, without limitation,
that your use is for the sole purpose of programming logic
devices manufactured by Altera and sold by Altera or its
authorized distributors. Please refer to the applicable
agreement for further details.
+-----------------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+---------------------------------+-------------------------------------------------+
; Analysis & Synthesis Status ; Successful - Thu Nov 17 11:14:11 2016 ;
; Quartus Prime Version ; 16.0.0 Build 211 04/27/2016 SJ Standard Edition ;
; Revision Name ; ex4_top ;
; Top-level Entity Name ; ex4_top ;
; Family ; Cyclone V ;
; Logic utilization (in ALMs) ; N/A ;
; Total registers ; 0 ;
; Total pins ; 38 ;
; Total virtual pins ; 0 ;
; Total block memory bits ; 0 ;
; Total DSP Blocks ; 0 ;
; Total HSSI RX PCSs ; 0 ;
; Total HSSI PMA RX Deserializers ; 0 ;
; Total HSSI TX PCSs ; 0 ;
; Total HSSI PMA TX Serializers ; 0 ;
; Total PLLs ; 0 ;
; Total DLLs ; 0 ;
+---------------------------------+-------------------------------------------------+
+---------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings ;
+---------------------------------------------------------------------------------+--------------------+--------------------+
; Option ; Setting ; Default Value ;
+---------------------------------------------------------------------------------+--------------------+--------------------+
; Device ; 5CSEMA5F31C6 ; ;
; Top-level entity name ; ex4_top ; ex4_top ;
; Family name ; Cyclone V ; Cyclone V ;
; Use smart compilation ; Off ; Off ;
; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ;
; Enable compact report table ; Off ; Off ;
; Restructure Multiplexers ; Auto ; Auto ;
; MLAB Add Timing Constraints For Mixed-Port Feed-Through Mode Setting Don't Care ; Off ; Off ;
; Create Debugging Nodes for IP Cores ; Off ; Off ;
; Preserve fewer node names ; On ; On ;
; Disable OpenCore Plus hardware evaluation ; Off ; Off ;
; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
; VHDL Version ; VHDL_1993 ; VHDL_1993 ;
; State Machine Processing ; Auto ; Auto ;
; Safe State Machine ; Off ; Off ;
; Extract Verilog State Machines ; On ; On ;
; Extract VHDL State Machines ; On ; On ;
; Ignore Verilog initial constructs ; Off ; Off ;
; Iteration limit for constant Verilog loops ; 5000 ; 5000 ;
; Iteration limit for non-constant Verilog loops ; 250 ; 250 ;
; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
; Infer RAMs from Raw Logic ; On ; On ;
; Parallel Synthesis ; On ; On ;
; DSP Block Balancing ; Auto ; Auto ;
; NOT Gate Push-Back ; On ; On ;
; Power-Up Don't Care ; On ; On ;
; Remove Redundant Logic Cells ; Off ; Off ;
; Remove Duplicate Registers ; On ; On ;
; Ignore CARRY Buffers ; Off ; Off ;
; Ignore CASCADE Buffers ; Off ; Off ;
; Ignore GLOBAL Buffers ; Off ; Off ;
; Ignore ROW GLOBAL Buffers ; Off ; Off ;
; Ignore LCELL Buffers ; Off ; Off ;
; Ignore SOFT Buffers ; On ; On ;
; Limit AHDL Integers to 32 Bits ; Off ; Off ;
; Optimization Technique ; Balanced ; Balanced ;
; Carry Chain Length ; 70 ; 70 ;
; Auto Carry Chains ; On ; On ;
; Auto Open-Drain Pins ; On ; On ;
; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ;
; Auto ROM Replacement ; On ; On ;
; Auto RAM Replacement ; On ; On ;
; Auto DSP Block Replacement ; On ; On ;
; Auto Shift Register Replacement ; Auto ; Auto ;
; Allow Shift Register Merging across Hierarchies ; Auto ; Auto ;
; Auto Clock Enable Replacement ; On ; On ;
; Strict RAM Replacement ; Off ; Off ;
; Allow Synchronous Control Signals ; On ; On ;
; Force Use of Synchronous Clear Signals ; Off ; Off ;
; Auto Resource Sharing ; Off ; Off ;
; Allow Any RAM Size For Recognition ; Off ; Off ;
; Allow Any ROM Size For Recognition ; Off ; Off ;
; Allow Any Shift Register Size For Recognition ; Off ; Off ;
; Use LogicLock Constraints during Resource Balancing ; On ; On ;
; Ignore translate_off and synthesis_off directives ; Off ; Off ;
; Timing-Driven Synthesis ; On ; On ;
; Report Parameter Settings ; On ; On ;
; Report Source Assignments ; On ; On ;
; Report Connectivity Checks ; On ; On ;
; Ignore Maximum Fan-Out Assignments ; Off ; Off ;
; Synchronization Register Chain Length ; 3 ; 3 ;
; PowerPlay Power Optimization During Synthesis ; Normal compilation ; Normal compilation ;
; HDL message level ; Level2 ; Level2 ;
; Suppress Register Optimization Related Messages ; Off ; Off ;
; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ;
; Number of Swept Nodes Reported in Synthesis Report ; 5000 ; 5000 ;
; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ;
; Clock MUX Protection ; On ; On ;
; Auto Gated Clock Conversion ; Off ; Off ;
; Block Design Naming ; Auto ; Auto ;
; SDC constraint protection ; Off ; Off ;
; Synthesis Effort ; Auto ; Auto ;
; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ;
; Pre-Mapping Resynthesis Optimization ; Off ; Off ;
; Analysis & Synthesis Message Level ; Medium ; Medium ;
; Disable Register Merging Across Hierarchies ; Auto ; Auto ;
; Resource Aware Inference For Block RAM ; On ; On ;
; Synthesis Seed ; 1 ; 1 ;
; Automatic Parallel Synthesis ; On ; On ;
; Partial Reconfiguration Bitstream ID ; Off ; Off ;
+---------------------------------------------------------------------------------+--------------------+--------------------+
+------------------------------------------+
; Parallel Compilation ;
+----------------------------+-------------+
; Processors ; Number ;
+----------------------------+-------------+
; Number detected on machine ; 8 ;
; Maximum allowed ; 4 ;
; ; ;
; Average used ; 1.00 ;
; Maximum used ; 1 ;
; ; ;
; Usage by Processor ; % Time Used ;
; Processor 1 ; 100.0% ;
+----------------------------+-------------+
+---------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+----------------------------------+-----------------+------------------------+-----------------------------------+---------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ;
+----------------------------------+-----------------+------------------------+-----------------------------------+---------+
; ../mylib/hex_2_7seg.v ; yes ; User Verilog HDL File ; C:/VERI/part_1/mylib/hex_2_7seg.v ; ;
; ex4_top.v ; yes ; User Verilog HDL File ; C:/VERI/part_1/ex4/ex4_top.v ; ;
+----------------------------------+-----------------+------------------------+-----------------------------------+---------+
+------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+---------------------------------------------+--------+
; Resource ; Usage ;
+---------------------------------------------+--------+
; Estimate of Logic utilization (ALMs needed) ; 29 ;
; ; ;
; Combinational ALUT usage for logic ; 43 ;
; -- 7 input functions ; 0 ;
; -- 6 input functions ; 14 ;
; -- 5 input functions ; 7 ;
; -- 4 input functions ; 18 ;
; -- <=3 input functions ; 4 ;
; ; ;
; Dedicated logic registers ; 0 ;
; ; ;
; I/O pins ; 38 ;
; ; ;
; Total DSP Blocks ; 0 ;
; ; ;
; Maximum fan-out node ; BCD0~7 ;
; Maximum fan-out ; 8 ;
; Total fan-out ; 266 ;
; Average fan-out ; 2.24 ;
+---------------------------------------------+--------+
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+----------------------------+-------------------+--------------+-------------------+------------+------+--------------+---------------------------+-------------+--------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Block Memory Bits ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name ; Entity Name ; Library Name ;
+----------------------------+-------------------+--------------+-------------------+------------+------+--------------+---------------------------+-------------+--------------+
; |ex4_top ; 43 (22) ; 0 (0) ; 0 ; 0 ; 38 ; 0 ; |ex4_top ; ex4_top ; work ;
; |hex_to_7seg:SEG0| ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex4_top|hex_to_7seg:SEG0 ; hex_to_7seg ; work ;
; |hex_to_7seg:SEG1| ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex4_top|hex_to_7seg:SEG1 ; hex_to_7seg ; work ;
; |hex_to_7seg:SEG2| ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex4_top|hex_to_7seg:SEG2 ; hex_to_7seg ; work ;
+----------------------------+-------------------+--------------+-------------------+------------+------+--------------+---------------------------+-------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 0 ;
; Number of registers using Synchronous Clear ; 0 ;
; Number of registers using Synchronous Load ; 0 ;
; Number of registers using Asynchronous Clear ; 0 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 0 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+----------------------------------------------+
; Port Connectivity Checks: "hex_to_7seg:SEG3" ;
+----------+-------+----------+----------------+
; Port ; Type ; Severity ; Details ;
+----------+-------+----------+----------------+
; in[3..1] ; Input ; Info ; Stuck at GND ;
+----------+-------+----------+----------------+
+-----------------------------------------------------+
; Post-Synthesis Netlist Statistics for Top Partition ;
+-----------------------+-----------------------------+
; Type ; Count ;
+-----------------------+-----------------------------+
; arriav_lcell_comb ; 50 ;
; normal ; 50 ;
; 0 data inputs ; 2 ;
; 1 data inputs ; 5 ;
; 3 data inputs ; 4 ;
; 4 data inputs ; 18 ;
; 5 data inputs ; 7 ;
; 6 data inputs ; 14 ;
; boundary_port ; 38 ;
; ; ;
; Max LUT depth ; 5.00 ;
; Average LUT depth ; 4.12 ;
+-----------------------+-----------------------------+
+-------------------------------+
; Elapsed Time Per Partition ;
+----------------+--------------+
; Partition Name ; Elapsed Time ;
+----------------+--------------+
; Top ; 00:00:01 ;
+----------------+--------------+
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus Prime Analysis & Synthesis
Info: Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
Info: Processing started: Thu Nov 17 11:14:00 2016
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off ex4 -c ex4_top
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
Info (12021): Found 1 design units, including 1 entities, in source file /veri/part_1/mylib/hex_2_7seg.v
Info (12023): Found entity 1: hex_to_7seg File: C:/VERI/part_1/mylib/hex_2_7seg.v Line: 1
Info (12021): Found 1 design units, including 1 entities, in source file ex4_top.v
Info (12023): Found entity 1: ex4_top File: C:/VERI/part_1/ex4/ex4_top.v Line: 1
Info (12127): Elaborating entity "ex4_top" for the top level hierarchy
Warning (10230): Verilog HDL assignment warning at ex4_top.v(32): truncated value with size 32 to match size of target (4) File: C:/VERI/part_1/ex4/ex4_top.v Line: 32
Warning (10230): Verilog HDL assignment warning at ex4_top.v(30): truncated value with size 32 to match size of target (4) File: C:/VERI/part_1/ex4/ex4_top.v Line: 30
Warning (10230): Verilog HDL assignment warning at ex4_top.v(28): truncated value with size 32 to match size of target (4) File: C:/VERI/part_1/ex4/ex4_top.v Line: 28
Info (12128): Elaborating entity "hex_to_7seg" for hierarchy "hex_to_7seg:SEG3" File: C:/VERI/part_1/ex4/ex4_top.v Line: 50
Warning (13024): Output pins are stuck at VCC or GND
Warning (13410): Pin "HEX3[1]" is stuck at GND File: C:/VERI/part_1/ex4/ex4_top.v Line: 7
Warning (13410): Pin "HEX3[2]" is stuck at GND File: C:/VERI/part_1/ex4/ex4_top.v Line: 7
Warning (13410): Pin "HEX3[6]" is stuck at VCC File: C:/VERI/part_1/ex4/ex4_top.v Line: 7
Info (286030): Timing-Driven Synthesis is running
Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL
Info (21057): Implemented 81 device resources after synthesis - the final resource count might be different
Info (21058): Implemented 10 input pins
Info (21059): Implemented 28 output pins
Info (21061): Implemented 43 logic cells
Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 8 warnings
Info: Peak virtual memory: 887 megabytes
Info: Processing ended: Thu Nov 17 11:14:11 2016
Info: Elapsed time: 00:00:11
Info: Total CPU time (on all processors): 00:00:22
|
