summaryrefslogtreecommitdiff
path: root/part_2/ex5/simulation/modelsim/ex5_top_run_msim_rtl_verilog.do
blob: 98180fe124fc4649b0317d1526560da2116cc797 (plain)
1
2
3
4
5
6
7
8
9
transcript on
if {[file exists rtl_work]} {
	vdel -lib rtl_work -all
}
vlib rtl_work
vmap work rtl_work

vlog -vlog01compat -work work +incdir+C:/VERI/part_2/ex5 {C:/VERI/part_2/ex5/counter_8.v}