part_3/ex10/ex10_top.v


1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29

module ex10_top (
	SW,
	CLOCK_50,
	DAC_SDI,
	DAC_CS,
	DAC_LD,
	DAC_SCK
);
	input CLOCK_50;
	input [9:0] SW;
	output DAC_SDI,DAC_CS,DAC_SCK,DAC_LD;

	wire CLOCK_DIVIDED;
	
	divider_5000 COUNT0 (CLOCK_50, CLOCK_DIVIDED);
	
	spi2dac SPI0 (
		.sysclk(CLOCK_50), 
		.data_in(SW[9:0]), 
		.load(CLOCK_DIVIDED), 
		.dac_sdi(DAC_SDI), 
		.dac_cs(DAC_CS), 
		.dac_sck(DAC_SCK), 
		.dac_ld(DAC_LD)
		);
	
endmodule