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Info: Start Nativelink Simulation process
Info: NativeLink has detected Verilog design -- Verilog simulation models will be used
========= EDA Simulation Settings =====================
Sim Mode : RTL
Family : cyclonev
Quartus root : c:/altera/16.0/quartus/bin64/
Quartus sim root : c:/altera/16.0/quartus/eda/sim_lib
Simulation Tool : modelsim-altera
Simulation Language : verilog
Simulation Mode : GUI
Sim Output File :
Sim SDF file :
Sim dir : simulation\modelsim
=======================================================
Info: Starting NativeLink simulation with ModelSim-Altera software
Sourced NativeLink script c:/altera/16.0/quartus/common/tcl/internal/nativelink/modelsim.tcl
Warning: File ex10_top_run_msim_rtl_verilog.do already exists - backing up current file as ex10_top_run_msim_rtl_verilog.do.bak2
Info: Spawning ModelSim-Altera Simulation software
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