1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
|
module ex11_top (
SW,
CLOCK_50,
DAC_SDI,
DAC_CS,
DAC_LD,
DAC_SCK,
PWM_OUT
);
input CLOCK_50;
input [9:0] SW;
output DAC_SDI,DAC_CS,DAC_SCK,DAC_LD,PWM_OUT;
wire CLOCK_DIVIDED;
divider_5000 COUNT0 (CLOCK_50, CLOCK_DIVIDED);
spi2dac SPI0 (
.sysclk(CLOCK_50),
.data_in(SW[9:0]),
.load(CLOCK_DIVIDED),
.dac_sdi(DAC_SDI),
.dac_cs(DAC_CS),
.dac_sck(DAC_SCK),
.dac_ld(DAC_LD)
);
pwm PWM0 (
.clk(CLOCK_50),
.data_in(SW[9:0]),
.load(CLOCK_DIVIDED),
.pwm_out(PWM_OUT)
);
endmodule
|
