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|
TimeQuest Timing Analyzer report for ex13_top
Mon Dec 05 11:21:15 2016
Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. TimeQuest Timing Analyzer Summary
3. Parallel Compilation
4. Clocks
5. Slow 1100mV 85C Model Fmax Summary
6. Timing Closure Recommendations
7. Slow 1100mV 85C Model Setup Summary
8. Slow 1100mV 85C Model Hold Summary
9. Slow 1100mV 85C Model Recovery Summary
10. Slow 1100mV 85C Model Removal Summary
11. Slow 1100mV 85C Model Minimum Pulse Width Summary
12. Slow 1100mV 85C Model Metastability Summary
13. Slow 1100mV 0C Model Fmax Summary
14. Slow 1100mV 0C Model Setup Summary
15. Slow 1100mV 0C Model Hold Summary
16. Slow 1100mV 0C Model Recovery Summary
17. Slow 1100mV 0C Model Removal Summary
18. Slow 1100mV 0C Model Minimum Pulse Width Summary
19. Slow 1100mV 0C Model Metastability Summary
20. Fast 1100mV 85C Model Setup Summary
21. Fast 1100mV 85C Model Hold Summary
22. Fast 1100mV 85C Model Recovery Summary
23. Fast 1100mV 85C Model Removal Summary
24. Fast 1100mV 85C Model Minimum Pulse Width Summary
25. Fast 1100mV 85C Model Metastability Summary
26. Fast 1100mV 0C Model Setup Summary
27. Fast 1100mV 0C Model Hold Summary
28. Fast 1100mV 0C Model Recovery Summary
29. Fast 1100mV 0C Model Removal Summary
30. Fast 1100mV 0C Model Minimum Pulse Width Summary
31. Fast 1100mV 0C Model Metastability Summary
32. Multicorner Timing Analysis Summary
33. Board Trace Model Assignments
34. Input Transition Times
35. Signal Integrity Metrics (Slow 1100mv 0c Model)
36. Signal Integrity Metrics (Slow 1100mv 85c Model)
37. Signal Integrity Metrics (Fast 1100mv 0c Model)
38. Signal Integrity Metrics (Fast 1100mv 85c Model)
39. Setup Transfers
40. Hold Transfers
41. Report TCCS
42. Report RSKM
43. Unconstrained Paths Summary
44. Clock Status Summary
45. Unconstrained Output Ports
46. Unconstrained Output Ports
47. TimeQuest Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, the Altera Quartus Prime License Agreement,
the Altera MegaCore Function License Agreement, or other
applicable license agreement, including, without limitation,
that your use is for the sole purpose of programming logic
devices manufactured by Altera and sold by Altera or its
authorized distributors. Please refer to the applicable
agreement for further details.
+---------------------------------------------------------------------------------+
; TimeQuest Timing Analyzer Summary ;
+-----------------------+---------------------------------------------------------+
; Quartus Prime Version ; Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition ;
; Timing Analyzer ; TimeQuest ;
; Revision Name ; ex13_top ;
; Device Family ; Cyclone V ;
; Device Name ; 5CSEMA5F31C6 ;
; Timing Models ; Final ;
; Delay Model ; Combined ;
; Rise/Fall Delays ; Enabled ;
+-----------------------+---------------------------------------------------------+
+------------------------------------------+
; Parallel Compilation ;
+----------------------------+-------------+
; Processors ; Number ;
+----------------------------+-------------+
; Number detected on machine ; 8 ;
; Maximum allowed ; 4 ;
; ; ;
; Average used ; 1.09 ;
; Maximum used ; 4 ;
; ; ;
; Usage by Processor ; % Time Used ;
; Processor 1 ; 100.0% ;
; Processor 2 ; 3.2% ;
; Processor 3 ; 3.2% ;
; Processor 4 ; 3.1% ;
+----------------------------+-------------+
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clocks ;
+-----------------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+---------------------------+
; Clock Name ; Type ; Period ; Frequency ; Rise ; Fall ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets ;
+-----------------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+---------------------------+
; CLOCK_50 ; Base ; 1.000 ; 1000.0 MHz ; 0.000 ; 0.500 ; ; ; ; ; ; ; ; ; ; ; { CLOCK_50 } ;
; divider_5000:DIV0|out ; Base ; 1.000 ; 1000.0 MHz ; 0.000 ; 0.500 ; ; ; ; ; ; ; ; ; ; ; { divider_5000:DIV0|out } ;
; spi2dac:SPI0|clk_1MHz ; Base ; 1.000 ; 1000.0 MHz ; 0.000 ; 0.500 ; ; ; ; ; ; ; ; ; ; ; { spi2dac:SPI0|clk_1MHz } ;
+-----------------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+---------------------------+
+-------------------------------------------------------------------------------------------------------+
; Slow 1100mV 85C Model Fmax Summary ;
+------------+-----------------+-----------------------+------------------------------------------------+
; Fmax ; Restricted Fmax ; Clock Name ; Note ;
+------------+-----------------+-----------------------+------------------------------------------------+
; 214.18 MHz ; 214.18 MHz ; CLOCK_50 ; ;
; 283.37 MHz ; 283.37 MHz ; spi2dac:SPI0|clk_1MHz ; ;
; 431.97 MHz ; 315.06 MHz ; divider_5000:DIV0|out ; limit due to minimum period restriction (tmin) ;
+------------+-----------------+-----------------------+------------------------------------------------+
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
----------------------------------
; Timing Closure Recommendations ;
----------------------------------
HTML report is unavailable in plain text report export.
+------------------------------------------------+
; Slow 1100mV 85C Model Setup Summary ;
+-----------------------+--------+---------------+
; Clock ; Slack ; End Point TNS ;
+-----------------------+--------+---------------+
; CLOCK_50 ; -3.786 ; -127.682 ;
; spi2dac:SPI0|clk_1MHz ; -3.430 ; -59.331 ;
; divider_5000:DIV0|out ; -3.088 ; -40.814 ;
+-----------------------+--------+---------------+
+------------------------------------------------+
; Slow 1100mV 85C Model Hold Summary ;
+-----------------------+--------+---------------+
; Clock ; Slack ; End Point TNS ;
+-----------------------+--------+---------------+
; CLOCK_50 ; -2.415 ; -2.415 ;
; spi2dac:SPI0|clk_1MHz ; 0.064 ; 0.000 ;
; divider_5000:DIV0|out ; 0.721 ; 0.000 ;
+-----------------------+--------+---------------+
------------------------------------------
; Slow 1100mV 85C Model Recovery Summary ;
------------------------------------------
No paths to report.
-----------------------------------------
; Slow 1100mV 85C Model Removal Summary ;
-----------------------------------------
No paths to report.
+---------------------------------------------------+
; Slow 1100mV 85C Model Minimum Pulse Width Summary ;
+-----------------------+--------+------------------+
; Clock ; Slack ; End Point TNS ;
+-----------------------+--------+------------------+
; divider_5000:DIV0|out ; -2.174 ; -68.032 ;
; CLOCK_50 ; -0.649 ; -44.630 ;
; spi2dac:SPI0|clk_1MHz ; -0.394 ; -13.046 ;
+-----------------------+--------+------------------+
-----------------------------------------------
; Slow 1100mV 85C Model Metastability Summary ;
-----------------------------------------------
No synchronizer chains to report.
+-------------------------------------------------------------------------------------------------------+
; Slow 1100mV 0C Model Fmax Summary ;
+------------+-----------------+-----------------------+------------------------------------------------+
; Fmax ; Restricted Fmax ; Clock Name ; Note ;
+------------+-----------------+-----------------------+------------------------------------------------+
; 207.94 MHz ; 207.94 MHz ; CLOCK_50 ; ;
; 286.45 MHz ; 286.45 MHz ; spi2dac:SPI0|clk_1MHz ; ;
; 426.08 MHz ; 315.06 MHz ; divider_5000:DIV0|out ; limit due to minimum period restriction (tmin) ;
+------------+-----------------+-----------------------+------------------------------------------------+
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
+------------------------------------------------+
; Slow 1100mV 0C Model Setup Summary ;
+-----------------------+--------+---------------+
; Clock ; Slack ; End Point TNS ;
+-----------------------+--------+---------------+
; CLOCK_50 ; -3.809 ; -121.513 ;
; spi2dac:SPI0|clk_1MHz ; -3.501 ; -60.759 ;
; divider_5000:DIV0|out ; -3.137 ; -41.684 ;
+-----------------------+--------+---------------+
+------------------------------------------------+
; Slow 1100mV 0C Model Hold Summary ;
+-----------------------+--------+---------------+
; Clock ; Slack ; End Point TNS ;
+-----------------------+--------+---------------+
; CLOCK_50 ; -2.594 ; -4.145 ;
; spi2dac:SPI0|clk_1MHz ; 0.139 ; 0.000 ;
; divider_5000:DIV0|out ; 0.751 ; 0.000 ;
+-----------------------+--------+---------------+
-----------------------------------------
; Slow 1100mV 0C Model Recovery Summary ;
-----------------------------------------
No paths to report.
----------------------------------------
; Slow 1100mV 0C Model Removal Summary ;
----------------------------------------
No paths to report.
+--------------------------------------------------+
; Slow 1100mV 0C Model Minimum Pulse Width Summary ;
+-----------------------+--------+-----------------+
; Clock ; Slack ; End Point TNS ;
+-----------------------+--------+-----------------+
; divider_5000:DIV0|out ; -2.174 ; -67.833 ;
; CLOCK_50 ; -0.709 ; -41.115 ;
; spi2dac:SPI0|clk_1MHz ; -0.394 ; -13.016 ;
+-----------------------+--------+-----------------+
----------------------------------------------
; Slow 1100mV 0C Model Metastability Summary ;
----------------------------------------------
No synchronizer chains to report.
+------------------------------------------------+
; Fast 1100mV 85C Model Setup Summary ;
+-----------------------+--------+---------------+
; Clock ; Slack ; End Point TNS ;
+-----------------------+--------+---------------+
; CLOCK_50 ; -3.145 ; -78.814 ;
; spi2dac:SPI0|clk_1MHz ; -1.511 ; -25.776 ;
; divider_5000:DIV0|out ; -1.290 ; -15.605 ;
+-----------------------+--------+---------------+
+------------------------------------------------+
; Fast 1100mV 85C Model Hold Summary ;
+-----------------------+--------+---------------+
; Clock ; Slack ; End Point TNS ;
+-----------------------+--------+---------------+
; CLOCK_50 ; -1.431 ; -1.431 ;
; spi2dac:SPI0|clk_1MHz ; -0.076 ; -0.391 ;
; divider_5000:DIV0|out ; 0.435 ; 0.000 ;
+-----------------------+--------+---------------+
------------------------------------------
; Fast 1100mV 85C Model Recovery Summary ;
------------------------------------------
No paths to report.
-----------------------------------------
; Fast 1100mV 85C Model Removal Summary ;
-----------------------------------------
No paths to report.
+---------------------------------------------------+
; Fast 1100mV 85C Model Minimum Pulse Width Summary ;
+-----------------------+--------+------------------+
; Clock ; Slack ; End Point TNS ;
+-----------------------+--------+------------------+
; divider_5000:DIV0|out ; -2.174 ; -68.036 ;
; CLOCK_50 ; -0.781 ; -30.977 ;
; spi2dac:SPI0|clk_1MHz ; 0.015 ; 0.000 ;
+-----------------------+--------+------------------+
-----------------------------------------------
; Fast 1100mV 85C Model Metastability Summary ;
-----------------------------------------------
No synchronizer chains to report.
+------------------------------------------------+
; Fast 1100mV 0C Model Setup Summary ;
+-----------------------+--------+---------------+
; Clock ; Slack ; End Point TNS ;
+-----------------------+--------+---------------+
; CLOCK_50 ; -2.671 ; -64.193 ;
; spi2dac:SPI0|clk_1MHz ; -1.454 ; -24.377 ;
; divider_5000:DIV0|out ; -1.230 ; -14.966 ;
+-----------------------+--------+---------------+
+------------------------------------------------+
; Fast 1100mV 0C Model Hold Summary ;
+-----------------------+--------+---------------+
; Clock ; Slack ; End Point TNS ;
+-----------------------+--------+---------------+
; CLOCK_50 ; -1.476 ; -1.476 ;
; spi2dac:SPI0|clk_1MHz ; -0.064 ; -0.263 ;
; divider_5000:DIV0|out ; 0.429 ; 0.000 ;
+-----------------------+--------+---------------+
-----------------------------------------
; Fast 1100mV 0C Model Recovery Summary ;
-----------------------------------------
No paths to report.
----------------------------------------
; Fast 1100mV 0C Model Removal Summary ;
----------------------------------------
No paths to report.
+--------------------------------------------------+
; Fast 1100mV 0C Model Minimum Pulse Width Summary ;
+-----------------------+--------+-----------------+
; Clock ; Slack ; End Point TNS ;
+-----------------------+--------+-----------------+
; divider_5000:DIV0|out ; -2.174 ; -67.914 ;
; CLOCK_50 ; -0.827 ; -36.470 ;
; spi2dac:SPI0|clk_1MHz ; 0.044 ; 0.000 ;
+-----------------------+--------+-----------------+
----------------------------------------------
; Fast 1100mV 0C Model Metastability Summary ;
----------------------------------------------
No synchronizer chains to report.
+---------------------------------------------------------------------------------------+
; Multicorner Timing Analysis Summary ;
+------------------------+----------+--------+----------+---------+---------------------+
; Clock ; Setup ; Hold ; Recovery ; Removal ; Minimum Pulse Width ;
+------------------------+----------+--------+----------+---------+---------------------+
; Worst-case Slack ; -3.809 ; -2.594 ; N/A ; N/A ; -2.174 ;
; CLOCK_50 ; -3.809 ; -2.594 ; N/A ; N/A ; -0.827 ;
; divider_5000:DIV0|out ; -3.137 ; 0.429 ; N/A ; N/A ; -2.174 ;
; spi2dac:SPI0|clk_1MHz ; -3.501 ; -0.076 ; N/A ; N/A ; -0.394 ;
; Design-wide TNS ; -227.827 ; -4.145 ; 0.0 ; 0.0 ; -125.708 ;
; CLOCK_50 ; -127.682 ; -4.145 ; N/A ; N/A ; -44.630 ;
; divider_5000:DIV0|out ; -41.684 ; 0.000 ; N/A ; N/A ; -68.036 ;
; spi2dac:SPI0|clk_1MHz ; -60.759 ; -0.391 ; N/A ; N/A ; -13.046 ;
+------------------------+----------+--------+----------+---------+---------------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Board Trace Model Assignments ;
+---------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
; Pin ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ;
+---------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
; DAC_SDI ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
; DAC_CS ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
; DAC_LD ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
; DAC_SCK ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
; PWM_OUT ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+---------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
+-------------------------------------------------------------+
; Input Transition Times ;
+----------+--------------+-----------------+-----------------+
; Pin ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;
+----------+--------------+-----------------+-----------------+
; CLOCK_50 ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
+----------+--------------+-----------------+-----------------+
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Signal Integrity Metrics (Slow 1100mv 0c Model) ;
+---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; DAC_SDI ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
; DAC_CS ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ;
; DAC_LD ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
; DAC_SCK ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ;
; PWM_OUT ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
+---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Signal Integrity Metrics (Slow 1100mv 85c Model) ;
+---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; DAC_SDI ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ;
; DAC_CS ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ;
; DAC_LD ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ;
; DAC_SCK ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ;
; PWM_OUT ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ;
+---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Signal Integrity Metrics (Fast 1100mv 0c Model) ;
+---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; DAC_SDI ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
; DAC_CS ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ;
; DAC_LD ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
; DAC_SCK ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ;
; PWM_OUT ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
+---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Signal Integrity Metrics (Fast 1100mv 85c Model) ;
+---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; DAC_SDI ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
; DAC_CS ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ;
; DAC_LD ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
; DAC_SCK ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ;
; PWM_OUT ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
+---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+-------------------------------------------------------------------------------------------+
; Setup Transfers ;
+-----------------------+-----------------------+----------+----------+----------+----------+
; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+-----------------------+-----------------------+----------+----------+----------+----------+
; CLOCK_50 ; CLOCK_50 ; 683 ; 0 ; 0 ; 0 ;
; divider_5000:DIV0|out ; CLOCK_50 ; 32 ; 22 ; 0 ; 0 ;
; spi2dac:SPI0|clk_1MHz ; CLOCK_50 ; 16 ; 1 ; 0 ; 0 ;
; CLOCK_50 ; divider_5000:DIV0|out ; 10 ; 0 ; 0 ; 0 ;
; divider_5000:DIV0|out ; divider_5000:DIV0|out ; 10 ; 0 ; 0 ; 0 ;
; CLOCK_50 ; spi2dac:SPI0|clk_1MHz ; 15 ; 0 ; 0 ; 0 ;
; divider_5000:DIV0|out ; spi2dac:SPI0|clk_1MHz ; 10 ; 0 ; 0 ; 0 ;
; spi2dac:SPI0|clk_1MHz ; spi2dac:SPI0|clk_1MHz ; 118 ; 0 ; 0 ; 0 ;
+-----------------------+-----------------------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
+-------------------------------------------------------------------------------------------+
; Hold Transfers ;
+-----------------------+-----------------------+----------+----------+----------+----------+
; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+-----------------------+-----------------------+----------+----------+----------+----------+
; CLOCK_50 ; CLOCK_50 ; 683 ; 0 ; 0 ; 0 ;
; divider_5000:DIV0|out ; CLOCK_50 ; 32 ; 22 ; 0 ; 0 ;
; spi2dac:SPI0|clk_1MHz ; CLOCK_50 ; 16 ; 1 ; 0 ; 0 ;
; CLOCK_50 ; divider_5000:DIV0|out ; 10 ; 0 ; 0 ; 0 ;
; divider_5000:DIV0|out ; divider_5000:DIV0|out ; 10 ; 0 ; 0 ; 0 ;
; CLOCK_50 ; spi2dac:SPI0|clk_1MHz ; 15 ; 0 ; 0 ; 0 ;
; divider_5000:DIV0|out ; spi2dac:SPI0|clk_1MHz ; 10 ; 0 ; 0 ; 0 ;
; spi2dac:SPI0|clk_1MHz ; spi2dac:SPI0|clk_1MHz ; 118 ; 0 ; 0 ; 0 ;
+-----------------------+-----------------------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
---------------
; Report TCCS ;
---------------
No dedicated SERDES Transmitter circuitry present in device or used in design
---------------
; Report RSKM ;
---------------
No non-DPA dedicated SERDES Receiver circuitry present in device or used in design
+------------------------------------------------+
; Unconstrained Paths Summary ;
+---------------------------------+-------+------+
; Property ; Setup ; Hold ;
+---------------------------------+-------+------+
; Illegal Clocks ; 0 ; 0 ;
; Unconstrained Clocks ; 0 ; 0 ;
; Unconstrained Input Ports ; 0 ; 0 ;
; Unconstrained Input Port Paths ; 0 ; 0 ;
; Unconstrained Output Ports ; 5 ; 5 ;
; Unconstrained Output Port Paths ; 18 ; 18 ;
+---------------------------------+-------+------+
+--------------------------------------------------------------------+
; Clock Status Summary ;
+-----------------------+-----------------------+------+-------------+
; Target ; Clock ; Type ; Status ;
+-----------------------+-----------------------+------+-------------+
; CLOCK_50 ; CLOCK_50 ; Base ; Constrained ;
; divider_5000:DIV0|out ; divider_5000:DIV0|out ; Base ; Constrained ;
; spi2dac:SPI0|clk_1MHz ; spi2dac:SPI0|clk_1MHz ; Base ; Constrained ;
+-----------------------+-----------------------+------+-------------+
+-----------------------------------------------------------------------------------------------------+
; Unconstrained Output Ports ;
+-------------+---------------------------------------------------------------------------------------+
; Output Port ; Comment ;
+-------------+---------------------------------------------------------------------------------------+
; DAC_CS ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; DAC_LD ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; DAC_SCK ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; DAC_SDI ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; PWM_OUT ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+-------------+---------------------------------------------------------------------------------------+
+-----------------------------------------------------------------------------------------------------+
; Unconstrained Output Ports ;
+-------------+---------------------------------------------------------------------------------------+
; Output Port ; Comment ;
+-------------+---------------------------------------------------------------------------------------+
; DAC_CS ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; DAC_LD ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; DAC_SCK ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; DAC_SDI ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; PWM_OUT ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+-------------+---------------------------------------------------------------------------------------+
+------------------------------------+
; TimeQuest Timing Analyzer Messages ;
+------------------------------------+
Info: *******************************************************************
Info: Running Quartus Prime TimeQuest Timing Analyzer
Info: Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
Info: Processing started: Mon Dec 05 11:21:09 2016
Info: Command: quartus_sta ex13 -c ex13_top
Info: qsta_default_script.tcl version: #1
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
Info (21077): Low junction temperature is 0 degrees C
Info (21077): High junction temperature is 85 degrees C
Critical Warning (332012): Synopsys Design Constraints File file not found: 'ex13_top.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
Info (332105): Deriving Clocks
Info (332105): create_clock -period 1.000 -name CLOCK_50 CLOCK_50
Info (332105): create_clock -period 1.000 -name divider_5000:DIV0|out divider_5000:DIV0|out
Info (332105): create_clock -period 1.000 -name spi2dac:SPI0|clk_1MHz spi2dac:SPI0|clk_1MHz
Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
Info: Analyzing Slow 1100mV 85C Model
Critical Warning (332148): Timing requirements not met
Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
Info (332146): Worst-case setup slack is -3.786
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): -3.786 -127.682 CLOCK_50
Info (332119): -3.430 -59.331 spi2dac:SPI0|clk_1MHz
Info (332119): -3.088 -40.814 divider_5000:DIV0|out
Info (332146): Worst-case hold slack is -2.415
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): -2.415 -2.415 CLOCK_50
Info (332119): 0.064 0.000 spi2dac:SPI0|clk_1MHz
Info (332119): 0.721 0.000 divider_5000:DIV0|out
Info (332140): No Recovery paths to report
Info (332140): No Removal paths to report
Info (332146): Worst-case minimum pulse width slack is -2.174
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): -2.174 -68.032 divider_5000:DIV0|out
Info (332119): -0.649 -44.630 CLOCK_50
Info (332119): -0.394 -13.046 spi2dac:SPI0|clk_1MHz
Info: Analyzing Slow 1100mV 0C Model
Info (334003): Started post-fitting delay annotation
Info (334004): Delay annotation completed successfully
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
Critical Warning (332148): Timing requirements not met
Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
Info (332146): Worst-case setup slack is -3.809
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): -3.809 -121.513 CLOCK_50
Info (332119): -3.501 -60.759 spi2dac:SPI0|clk_1MHz
Info (332119): -3.137 -41.684 divider_5000:DIV0|out
Info (332146): Worst-case hold slack is -2.594
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): -2.594 -4.145 CLOCK_50
Info (332119): 0.139 0.000 spi2dac:SPI0|clk_1MHz
Info (332119): 0.751 0.000 divider_5000:DIV0|out
Info (332140): No Recovery paths to report
Info (332140): No Removal paths to report
Info (332146): Worst-case minimum pulse width slack is -2.174
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): -2.174 -67.833 divider_5000:DIV0|out
Info (332119): -0.709 -41.115 CLOCK_50
Info (332119): -0.394 -13.016 spi2dac:SPI0|clk_1MHz
Info: Analyzing Fast 1100mV 85C Model
Info (334003): Started post-fitting delay annotation
Info (334004): Delay annotation completed successfully
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
Critical Warning (332148): Timing requirements not met
Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
Info (332146): Worst-case setup slack is -3.145
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): -3.145 -78.814 CLOCK_50
Info (332119): -1.511 -25.776 spi2dac:SPI0|clk_1MHz
Info (332119): -1.290 -15.605 divider_5000:DIV0|out
Info (332146): Worst-case hold slack is -1.431
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): -1.431 -1.431 CLOCK_50
Info (332119): -0.076 -0.391 spi2dac:SPI0|clk_1MHz
Info (332119): 0.435 0.000 divider_5000:DIV0|out
Info (332140): No Recovery paths to report
Info (332140): No Removal paths to report
Info (332146): Worst-case minimum pulse width slack is -2.174
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): -2.174 -68.036 divider_5000:DIV0|out
Info (332119): -0.781 -30.977 CLOCK_50
Info (332119): 0.015 0.000 spi2dac:SPI0|clk_1MHz
Info: Analyzing Fast 1100mV 0C Model
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
Critical Warning (332148): Timing requirements not met
Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
Info (332146): Worst-case setup slack is -2.671
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): -2.671 -64.193 CLOCK_50
Info (332119): -1.454 -24.377 spi2dac:SPI0|clk_1MHz
Info (332119): -1.230 -14.966 divider_5000:DIV0|out
Info (332146): Worst-case hold slack is -1.476
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): -1.476 -1.476 CLOCK_50
Info (332119): -0.064 -0.263 spi2dac:SPI0|clk_1MHz
Info (332119): 0.429 0.000 divider_5000:DIV0|out
Info (332140): No Recovery paths to report
Info (332140): No Removal paths to report
Info (332146): Worst-case minimum pulse width slack is -2.174
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): -2.174 -67.914 divider_5000:DIV0|out
Info (332119): -0.827 -36.470 CLOCK_50
Info (332119): 0.044 0.000 spi2dac:SPI0|clk_1MHz
Info (332102): Design is not fully constrained for setup requirements
Info (332102): Design is not fully constrained for hold requirements
Info: Quartus Prime TimeQuest Timing Analyzer was successful. 0 errors, 6 warnings
Info: Peak virtual memory: 1231 megabytes
Info: Processing ended: Mon Dec 05 11:21:15 2016
Info: Elapsed time: 00:00:06
Info: Total CPU time (on all processors): 00:00:05
|
