path: root/part_3/ex14/MULT.v

// megafunction wizard: %ALTMEMMULT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altmemmult 

// ============================================================
// File Name: MULT.v
// Megafunction Name(s):
// 			altmemmult
//
// Simulation Library Files(s):
// 			altera_mf;cyclonev
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 16.0.0 Build 211 04/27/2016 SJ Standard Edition
// ************************************************************


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//Your use of Altera Corporation's design tools, logic functions 
//and other software and tools, and its AMPP partner logic 
//functions, and any output files from any of the foregoing 
//(including device programming or simulation files), and any 
//associated documentation or information are expressly subject 
//to the terms and conditions of the Altera Program License 
//Subscription Agreement, the Altera Quartus Prime License Agreement,
//the Altera MegaCore Function License Agreement, or other 
//applicable license agreement, including, without limitation, 
//that your use is for the sole purpose of programming logic 
//devices manufactured by Altera and sold by Altera or its 
//authorized distributors.  Please refer to the applicable 
//agreement for further details.


//altmemmult CBX_AUTO_BLACKBOX="ALL" COEFF_REPRESENTATION="UNSIGNED" COEFFICIENT0="10000" DATA_REPRESENTATION="UNSIGNED" DEVICE_FAMILY="Cyclone V" MAX_CLOCK_CYCLES_PER_RESULT=4 RAM_BLOCK_TYPE="AUTO" TOTAL_LATENCY=7 WIDTH_C=16 WIDTH_D=16 WIDTH_R=32 clock data_in result result_valid sload_data
//VERSION_BEGIN 16.0 cbx_altaccumulate 2016:04:27:18:05:34:SJ cbx_altera_syncram_nd_impl 2016:04:27:18:05:34:SJ cbx_altmemmult 2016:04:27:18:05:34:SJ cbx_altsyncram 2016:04:27:18:05:34:SJ cbx_cycloneii 2016:04:27:18:05:34:SJ cbx_lpm_add_sub 2016:04:27:18:05:34:SJ cbx_lpm_compare 2016:04:27:18:05:34:SJ cbx_lpm_counter 2016:04:27:18:05:34:SJ cbx_lpm_decode 2016:04:27:18:05:34:SJ cbx_lpm_mux 2016:04:27:18:05:34:SJ cbx_mgl 2016:04:27:18:06:48:SJ cbx_nadder 2016:04:27:18:05:34:SJ cbx_stratix 2016:04:27:18:05:34:SJ cbx_stratixii 2016:04:27:18:05:34:SJ cbx_stratixiii 2016:04:27:18:05:34:SJ cbx_stratixv 2016:04:27:18:05:34:SJ cbx_util_mgl 2016:04:27:18:05:34:SJ  VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463



//altaccumulate CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Cyclone V" LPM_REPRESENTATION="SIGNED" RIGHT_SHIFT_DISTANCE=4 WIDTH_IN=20 WIDTH_OUT=21 clock data result sload
//VERSION_BEGIN 16.0 cbx_altaccumulate 2016:04:27:18:05:34:SJ cbx_cycloneii 2016:04:27:18:05:34:SJ cbx_lpm_add_sub 2016:04:27:18:05:34:SJ cbx_mgl 2016:04:27:18:06:48:SJ cbx_nadder 2016:04:27:18:05:34:SJ cbx_stratix 2016:04:27:18:05:34:SJ cbx_stratixii 2016:04:27:18:05:34:SJ  VERSION_END

//synthesis_resources = lut 21 reg 21 
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module  MULT_accum_u5f
	( 
	clock,
	data,
	result,
	sload) ;
	input   clock;
	input   [19:0]  data;
	output   [20:0]  result;
	input   sload;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
	tri0   sload;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif

	reg	[20:0]	acc_ffa;
	wire  [0:0]   wire_acc_cella_0cout;
	wire  [0:0]   wire_acc_cella_1cout;
	wire  [0:0]   wire_acc_cella_2cout;
	wire  [0:0]   wire_acc_cella_3cout;
	wire  [0:0]   wire_acc_cella_4cout;
	wire  [0:0]   wire_acc_cella_5cout;
	wire  [0:0]   wire_acc_cella_6cout;
	wire  [0:0]   wire_acc_cella_7cout;
	wire  [0:0]   wire_acc_cella_8cout;
	wire  [0:0]   wire_acc_cella_9cout;
	wire  [0:0]   wire_acc_cella_10cout;
	wire  [0:0]   wire_acc_cella_11cout;
	wire  [0:0]   wire_acc_cella_12cout;
	wire  [0:0]   wire_acc_cella_13cout;
	wire  [0:0]   wire_acc_cella_14cout;
	wire  [0:0]   wire_acc_cella_15cout;
	wire  [0:0]   wire_acc_cella_16cout;
	wire  [0:0]   wire_acc_cella_17cout;
	wire  [0:0]   wire_acc_cella_18cout;
	wire  [0:0]   wire_acc_cella_19cout;
	wire  [20:0]   wire_acc_cella_datab;
	wire  [20:0]   wire_acc_cella_sumout;

	// synopsys translate_off
	initial
		acc_ffa = 21'b000000000000000000000;
	// synopsys translate_on
	always @ ( posedge clock)
		
			if (sload == 1'b1) acc_ffa <= {data[19], data};
			else  acc_ffa <= wire_acc_cella_sumout;
	cyclonev_lcell_comb   acc_cella_0
	( 
	.cin(1'b0),
	.combout(),
	.cout(wire_acc_cella_0cout[0:0]),
	.dataa(acc_ffa[4:4]),
	.datab(wire_acc_cella_datab[0:0]),
	.shareout(),
	.sumout(wire_acc_cella_sumout[0:0]),
	.datac(1'b0),
	.datad(1'b0),
	.datae(1'b0),
	.dataf(1'b0),
	.datag(1'b0),
	.sharein(1'b0)
	);
	defparam
		acc_cella_0.lut_mask = 64'h000033330000AAAA,
		acc_cella_0.lpm_type = "cyclonev_lcell_comb";
	cyclonev_lcell_comb   acc_cella_1
	( 
	.cin(wire_acc_cella_0cout[0:0]),
	.combout(),
	.cout(wire_acc_cella_1cout[0:0]),
	.dataa(acc_ffa[5:5]),
	.datab(wire_acc_cella_datab[1:1]),
	.shareout(),
	.sumout(wire_acc_cella_sumout[1:1]),
	.datac(1'b0),
	.datad(1'b0),
	.datae(1'b0),
	.dataf(1'b0),
	.datag(1'b0),
	.sharein(1'b0)
	);
	defparam
		acc_cella_1.lut_mask = 64'h000033330000AAAA,
		acc_cella_1.lpm_type = "cyclonev_lcell_comb";
	cyclonev_lcell_comb   acc_cella_2
	( 
	.cin(wire_acc_cella_1cout[0:0]),
	.combout(),
	.cout(wire_acc_cella_2cout[0:0]),
	.dataa(acc_ffa[6:6]),
	.datab(wire_acc_cella_datab[2:2]),
	.shareout(),
	.sumout(wire_acc_cella_sumout[2:2]),
	.datac(1'b0),
	.datad(1'b0),
	.datae(1'b0),
	.dataf(1'b0),
	.datag(1'b0),
	.sharein(1'b0)
	);
	defparam
		acc_cella_2.lut_mask = 64'h000033330000AAAA,
		acc_cella_2.lpm_type = "cyclonev_lcell_comb";
	cyclonev_lcell_comb   acc_cella_3
	( 
	.cin(wire_acc_cella_2cout[0:0]),
	.combout(),
	.cout(wire_acc_cella_3cout[0:0]),
	.dataa(acc_ffa[7:7]),
	.datab(wire_acc_cella_datab[3:3]),
	.shareout(),
	.sumout(wire_acc_cella_sumout[3:3]),
	.datac(1'b0),
	.datad(1'b0),
	.datae(1'b0),
	.dataf(1'b0),
	.datag(1'b0),
	.sharein(1'b0)
	);
	defparam
		acc_cella_3.lut_mask = 64'h000033330000AAAA,
		acc_cella_3.lpm_type = "cyclonev_lcell_comb";
	cyclonev_lcell_comb   acc_cella_4
	( 
	.cin(wire_acc_cella_3cout[0:0]),
	.combout(),
	.cout(wire_acc_cella_4cout[0:0]),
	.dataa(acc_ffa[8:8]),
	.datab(wire_acc_cella_datab[4:4]),
	.shareout(),
	.sumout(wire_acc_cella_sumout[4:4]),
	.datac(1'b0),
	.datad(1'b0),
	.datae(1'b0),
	.dataf(1'b0),
	.datag(1'b0),
	.sharein(1'b0)
	);
	defparam
		acc_cella_4.lut_mask = 64'h000033330000AAAA,
		acc_cella_4.lpm_type = "cyclonev_lcell_comb";
	cyclonev_lcell_comb   acc_cella_5
	( 
	.cin(wire_acc_cella_4cout[0:0]),
	.combout(),
	.cout(wire_acc_cella_5cout[0:0]),
	.dataa(acc_ffa[9:9]),
	.datab(wire_acc_cella_datab[5:5]),
	.shareout(),
	.sumout(wire_acc_cella_sumout[5:5]),
	.datac(1'b0),
	.datad(1'b0),
	.datae(1'b0),
	.dataf(1'b0),
	.datag(1'b0),
	.sharein(1'b0)
	);
	defparam
		acc_cella_5.lut_mask = 64'h000033330000AAAA,
		acc_cella_5.lpm_type = "cyclonev_lcell_comb";
	cyclonev_lcell_comb   acc_cella_6
	( 
	.cin(wire_acc_cella_5cout[0:0]),
	.combout(),
	.cout(wire_acc_cella_6cout[0:0]),
	.dataa(acc_ffa[10:10]),
	.datab(wire_acc_cella_datab[6:6]),
	.shareout(),
	.sumout(wire_acc_cella_sumout[6:6]),
	.datac(1'b0),
	.datad(1'b0),
	.datae(1'b0),
	.dataf(1'b0),
	.datag(1'b0),
	.sharein(1'b0)
	);
	defparam
		acc_cella_6.lut_mask = 64'h000033330000AAAA,
		acc_cella_6.lpm_type = "cyclonev_lcell_comb";
	cyclonev_lcell_comb   acc_cella_7
	( 
	.cin(wire_acc_cella_6cout[0:0]),
	.combout(),
	.cout(wire_acc_cella_7cout[0:0]),
	.dataa(acc_ffa[11:11]),
	.datab(wire_acc_cella_datab[7:7]),
	.shareout(),
	.sumout(wire_acc_cella_sumout[7:7]),
	.datac(1'b0),
	.datad(1'b0),
	.datae(1'b0),
	.dataf(1'b0),
	.datag(1'b0),
	.sharein(1'b0)
	);
	defparam
		acc_cella_7.lut_mask = 64'h000033330000AAAA,
		acc_cella_7.lpm_type = "cyclonev_lcell_comb";
	cyclonev_lcell_comb   acc_cella_8
	( 
	.cin(wire_acc_cella_7cout[0:0]),
	.combout(),
	.cout(wire_acc_cella_8cout[0:0]),
	.dataa(acc_ffa[12:12]),
	.datab(wire_acc_cella_datab[8:8]),
	.shareout(),
	.sumout(wire_acc_cella_sumout[8:8]),
	.datac(1'b0),
	.datad(1'b0),
	.datae(1'b0),
	.dataf(1'b0),
	.datag(1'b0),
	.sharein(1'b0)
	);
	defparam
		acc_cella_8.lut_mask = 64'h000033330000AAAA,
		acc_cella_8.lpm_type = "cyclonev_lcell_comb";
	cyclonev_lcell_comb   acc_cella_9
	( 
	.cin(wire_acc_cella_8cout[0:0]),
	.combout(),
	.cout(wire_acc_cella_9cout[0:0]),
	.dataa(acc_ffa[13:13]),
	.datab(wire_acc_cella_datab[9:9]),
	.shareout(),
	.sumout(wire_acc_cella_sumout[9:9]),
	.datac(1'b0),
	.datad(1'b0),
	.datae(1'b0),
	.dataf(1'b0),
	.datag(1'b0),
	.sharein(1'b0)
	);
	defparam
		acc_cella_9.lut_mask = 64'h000033330000AAAA,
		acc_cella_9.lpm_type = "cyclonev_lcell_comb";
	cyclonev_lcell_comb   acc_cella_10
	( 
	.cin(wire_acc_cella_9cout[0:0]),
	.combout(),
	.cout(wire_acc_cella_10cout[0:0]),
	.dataa(acc_ffa[14:14]),
	.datab(wire_acc_cella_datab[10:10]),
	.shareout(),
	.sumout(wire_acc_cella_sumout[10:10]),
	.datac(1'b0),
	.datad(1'b0),
	.datae(1'b0),
	.dataf(1'b0),
	.datag(1'b0),
	.sharein(1'b0)
	);
	defparam
		acc_cella_10.lut_mask = 64'h000033330000AAAA,
		acc_cella_10.lpm_type = "cyclonev_lcell_comb";
	cyclonev_lcell_comb   acc_cella_11
	( 
	.cin(wire_acc_cella_10cout[0:0]),
	.combout(),
	.cout(wire_acc_cella_11cout[0:0]),
	.dataa(acc_ffa[15:15]),
	.datab(wire_acc_cella_datab[11:11]),
	.shareout(),
	.sumout(wire_acc_cella_sumout[11:11]),
	.datac(1'b0),
	.datad(1'b0),
	.datae(1'b0),
	.dataf(1'b0),
	.datag(1'b0),
	.sharein(1'b0)
	);
	defparam
		acc_cella_11.lut_mask = 64'h000033330000AAAA,
		acc_cella_11.lpm_type = "cyclonev_lcell_comb";
	cyclonev_lcell_comb   acc_cella_12
	( 
	.cin(wire_acc_cella_11cout[0:0]),
	.combout(),
	.cout(wire_acc_cella_12cout[0:0]),
	.dataa(acc_ffa[16:16]),
	.datab(wire_acc_cella_datab[12:12]),
	.shareout(),
	.sumout(wire_acc_cella_sumout[12:12]),
	.datac(1'b0),
	.datad(1'b0),
	.datae(1'b0),
	.dataf(1'b0),
	.datag(1'b0),
	.sharein(1'b0)
	);
	defparam
		acc_cella_12.lut_mask = 64'h000033330000AAAA,
		acc_cella_12.lpm_type = "cyclonev_lcell_comb";
	cyclonev_lcell_comb   acc_cella_13
	( 
	.cin(wire_acc_cella_12cout[0:0]),
	.combout(),
	.cout(wire_acc_cella_13cout[0:0]),
	.dataa(acc_ffa[17:17]),
	.datab(wire_acc_cella_datab[13:13]),
	.shareout(),
	.sumout(wire_acc_cella_sumout[13:13]),
	.datac(1'b0),
	.datad(1'b0),
	.datae(1'b0),
	.dataf(1'b0),
	.datag(1'b0),
	.sharein(1'b0)
	);
	defparam
		acc_cella_13.lut_mask = 64'h000033330000AAAA,
		acc_cella_13.lpm_type = "cyclonev_lcell_comb";
	cyclonev_lcell_comb   acc_cella_14
	( 
	.cin(wire_acc_cella_13cout[0:0]),
	.combout(),
	.cout(wire_acc_cella_14cout[0:0]),
	.dataa(acc_ffa[18:18]),
	.datab(wire_acc_cella_datab[14:14]),
	.shareout(),
	.sumout(wire_acc_cella_sumout[14:14]),
	.datac(1'b0),
	.datad(1'b0),
	.datae(1'b0),
	.dataf(1'b0),
	.datag(1'b0),
	.sharein(1'b0)
	);
	defparam
		acc_cella_14.lut_mask = 64'h000033330000AAAA,
		acc_cella_14.lpm_type = "cyclonev_lcell_comb";
	cyclonev_lcell_comb   acc_cella_15
	( 
	.cin(wire_acc_cella_14cout[0:0]),
	.combout(),
	.cout(wire_acc_cella_15cout[0:0]),
	.dataa(acc_ffa[19:19]),
	.datab(wire_acc_cella_datab[15:15]),
	.shareout(),
	.sumout(wire_acc_cella_sumout[15:15]),
	.datac(1'b0),
	.datad(1'b0),
	.datae(1'b0),
	.dataf(1'b0),
	.datag(1'b0),
	.sharein(1'b0)
	);
	defparam
		acc_cella_15.lut_mask = 64'h000033330000AAAA,
		acc_cella_15.lpm_type = "cyclonev_lcell_comb";
	cyclonev_lcell_comb   acc_cella_16
	( 
	.cin(wire_acc_cella_15cout[0:0]),
	.combout(),
	.cout(wire_acc_cella_16cout[0:0]),
	.dataa(acc_ffa[20:20]),
	.datab(wire_acc_cella_datab[16:16]),
	.shareout(),
	.sumout(wire_acc_cella_sumout[16:16]),
	.datac(1'b0),
	.datad(1'b0),
	.datae(1'b0),
	.dataf(1'b0),
	.datag(1'b0),
	.sharein(1'b0)
	);
	defparam
		acc_cella_16.lut_mask = 64'h000033330000AAAA,
		acc_cella_16.lpm_type = "cyclonev_lcell_comb";
	cyclonev_lcell_comb   acc_cella_17
	( 
	.cin(wire_acc_cella_16cout[0:0]),
	.combout(),
	.cout(wire_acc_cella_17cout[0:0]),
	.dataa(acc_ffa[20:20]),
	.datab(wire_acc_cella_datab[17:17]),
	.shareout(),
	.sumout(wire_acc_cella_sumout[17:17]),
	.datac(1'b0),
	.datad(1'b0),
	.datae(1'b0),
	.dataf(1'b0),
	.datag(1'b0),
	.sharein(1'b0)
	);
	defparam
		acc_cella_17.lut_mask = 64'h000033330000AAAA,
		acc_cella_17.lpm_type = "cyclonev_lcell_comb";
	cyclonev_lcell_comb   acc_cella_18
	( 
	.cin(wire_acc_cella_17cout[0:0]),
	.combout(),
	.cout(wire_acc_cella_18cout[0:0]),
	.dataa(acc_ffa[20:20]),
	.datab(wire_acc_cella_datab[18:18]),
	.shareout(),
	.sumout(wire_acc_cella_sumout[18:18]),
	.datac(1'b0),
	.datad(1'b0),
	.datae(1'b0),
	.dataf(1'b0),
	.datag(1'b0),
	.sharein(1'b0)
	);
	defparam
		acc_cella_18.lut_mask = 64'h000033330000AAAA,
		acc_cella_18.lpm_type = "cyclonev_lcell_comb";
	cyclonev_lcell_comb   acc_cella_19
	( 
	.cin(wire_acc_cella_18cout[0:0]),
	.combout(),
	.cout(wire_acc_cella_19cout[0:0]),
	.dataa(acc_ffa[20:20]),
	.datab(wire_acc_cella_datab[19:19]),
	.shareout(),
	.sumout(wire_acc_cella_sumout[19:19]),
	.datac(1'b0),
	.datad(1'b0),
	.datae(1'b0),
	.dataf(1'b0),
	.datag(1'b0),
	.sharein(1'b0)
	);
	defparam
		acc_cella_19.lut_mask = 64'h000033330000AAAA,
		acc_cella_19.lpm_type = "cyclonev_lcell_comb";
	cyclonev_lcell_comb   acc_cella_20
	( 
	.cin(wire_acc_cella_19cout[0:0]),
	.combout(),
	.cout(),
	.dataa(acc_ffa[20:20]),
	.datab(wire_acc_cella_datab[20:20]),
	.shareout(),
	.sumout(wire_acc_cella_sumout[20:20]),
	.datac(1'b0),
	.datad(1'b0),
	.datae(1'b0),
	.dataf(1'b0),
	.datag(1'b0),
	.sharein(1'b0)
	);
	defparam
		acc_cella_20.lut_mask = 64'h000033330000AAAA,
		acc_cella_20.lpm_type = "cyclonev_lcell_comb";
	assign
		wire_acc_cella_datab = {data[19], data};
	assign
		result = acc_ffa;
endmodule //MULT_accum_u5f


//altshiftreg CBX_AUTO_BLACKBOX="ALL" LPM_DIRECTION="RIGHT" LPM_WIDTH=12 SHIFT_DISTANCE=4 clock data load shiftout
//VERSION_BEGIN 16.0 cbx_altaccumulate 2016:04:27:18:05:34:SJ cbx_altera_syncram_nd_impl 2016:04:27:18:05:34:SJ cbx_altmemmult 2016:04:27:18:05:34:SJ cbx_altsyncram 2016:04:27:18:05:34:SJ cbx_cycloneii 2016:04:27:18:05:34:SJ cbx_lpm_add_sub 2016:04:27:18:05:34:SJ cbx_lpm_compare 2016:04:27:18:05:34:SJ cbx_lpm_counter 2016:04:27:18:05:34:SJ cbx_lpm_decode 2016:04:27:18:05:34:SJ cbx_lpm_mux 2016:04:27:18:05:34:SJ cbx_mgl 2016:04:27:18:06:48:SJ cbx_nadder 2016:04:27:18:05:34:SJ cbx_stratix 2016:04:27:18:05:34:SJ cbx_stratixii 2016:04:27:18:05:34:SJ cbx_stratixiii 2016:04:27:18:05:34:SJ cbx_stratixv 2016:04:27:18:05:34:SJ cbx_util_mgl 2016:04:27:18:05:34:SJ  VERSION_END

//synthesis_resources = reg 12 
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module  MULT_altshiftreg_mda
	( 
	clock,
	data,
	load,
	q,
	shiftout) ;
	input   clock;
	input   [11:0]  data;
	input   load;
	output   [11:0]  q;
	output   [3:0]  shiftout;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
	tri0   [11:0]  data;
	tri0   load;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif

	reg	[11:0]	dffe7a;
	wire sclr;
	wire  [11:0]  shift_node;
	wire  [3:0]  shiftin_wire;
	wire sset;

	// synopsys translate_off
	initial
		dffe7a = 0;
	// synopsys translate_on
	always @ ( posedge clock)
		  dffe7a <= ({12{(~ sclr)}} & ({12{sset}} | (({12{(~ load)}} & shift_node) | ({12{load}} & data))));
	assign
		q = dffe7a,
		sclr = 1'b0,
		shift_node = {shiftin_wire, dffe7a[11:4]},
		shiftin_wire = {4{1'b0}},
		shiftout = dffe7a[3:0],
		sset = 1'b0;
endmodule //MULT_altshiftreg_mda


//altshiftreg CBX_AUTO_BLACKBOX="ALL" LPM_DIRECTION="RIGHT" LPM_WIDTH=12 SHIFT_DISTANCE=4 clock q shiftin
//VERSION_BEGIN 16.0 cbx_altaccumulate 2016:04:27:18:05:34:SJ cbx_altera_syncram_nd_impl 2016:04:27:18:05:34:SJ cbx_altmemmult 2016:04:27:18:05:34:SJ cbx_altsyncram 2016:04:27:18:05:34:SJ cbx_cycloneii 2016:04:27:18:05:34:SJ cbx_lpm_add_sub 2016:04:27:18:05:34:SJ cbx_lpm_compare 2016:04:27:18:05:34:SJ cbx_lpm_counter 2016:04:27:18:05:34:SJ cbx_lpm_decode 2016:04:27:18:05:34:SJ cbx_lpm_mux 2016:04:27:18:05:34:SJ cbx_mgl 2016:04:27:18:06:48:SJ cbx_nadder 2016:04:27:18:05:34:SJ cbx_stratix 2016:04:27:18:05:34:SJ cbx_stratixii 2016:04:27:18:05:34:SJ cbx_stratixiii 2016:04:27:18:05:34:SJ cbx_stratixv 2016:04:27:18:05:34:SJ cbx_util_mgl 2016:04:27:18:05:34:SJ  VERSION_END

//synthesis_resources = reg 12 
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module  MULT_altshiftreg_ci9
	( 
	clock,
	q,
	shiftin,
	shiftout) ;
	input   clock;
	output   [11:0]  q;
	input   [3:0]  shiftin;
	output   [3:0]  shiftout;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
	tri1   [3:0]  shiftin;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif

	reg	[11:0]	dffe8a;
	wire [11:0]  data;
	wire load;
	wire sclr;
	wire  [11:0]  shift_node;
	wire  [3:0]  shiftin_wire;
	wire sset;

	// synopsys translate_off
	initial
		dffe8a = 0;
	// synopsys translate_on
	always @ ( posedge clock)
		  dffe8a <= ({12{(~ sclr)}} & ({12{sset}} | (({12{(~ load)}} & shift_node) | ({12{load}} & data))));
	assign
		data = {12{1'b0}},
		load = 1'b0,
		q = dffe8a,
		sclr = 1'b0,
		shift_node = {shiftin_wire, dffe8a[11:4]},
		shiftin_wire = shiftin,
		shiftout = dffe8a[3:0],
		sset = 1'b0;
endmodule //MULT_altshiftreg_ci9

//synthesis_resources = altsyncram 1 lut 21 reg 56 
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module  MULT_altmemmult_ipq
	( 
	clock,
	data_in,
	result,
	result_valid,
	sload_data) ;
	input   clock;
	input   [15:0]  data_in;
	output   [31:0]  result;
	output   result_valid;
	input   sload_data;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
	tri0   sload_data;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif

	wire  [20:0]   wire_accum5_result;
	wire  [11:0]   wire_altshiftreg1_q;
	wire  [3:0]   wire_altshiftreg1_shiftout;
	wire  [11:0]   wire_altshiftreg6_q;
	wire  [3:0]   wire_altshiftreg6_shiftout;
	wire  [19:0]   wire_altsyncram4_q_a;
	reg	[0:0]	dffe2a0;
	reg	[0:0]	dffe2a1;
	reg	[0:0]	dffe2a2;
	reg	[0:0]	dffe2a3;
	reg	[0:0]	dffe2a4;
	reg	[0:0]	dffe2a5;
	reg	[0:0]	dffe2a6;
	reg	[3:0]	dffe3a;
	wire  [31:0]  result_wire;
	wire sclr;

	MULT_accum_u5f   accum5
	( 
	.clock(clock),
	.data({wire_altsyncram4_q_a[19:0]}),
	.result(wire_accum5_result),
	.sload(dffe2a2[0:0]));
	MULT_altshiftreg_mda   altshiftreg1
	( 
	.clock(clock),
	.data({data_in[15:4]}),
	.load(sload_data),
	.q(wire_altshiftreg1_q),
	.shiftout(wire_altshiftreg1_shiftout));
	MULT_altshiftreg_ci9   altshiftreg6
	( 
	.clock(clock),
	.q(wire_altshiftreg6_q),
	.shiftin(wire_accum5_result[3:0]),
	.shiftout(wire_altshiftreg6_shiftout));
	altsyncram   altsyncram4
	( 
	.address_a(dffe3a[3:0]),
	.clock0(clock),
	.eccstatus(),
	.q_a(wire_altsyncram4_q_a),
	.q_b()
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_off
	`endif
	,
	.aclr0(1'b0),
	.aclr1(1'b0),
	.address_b({1{1'b1}}),
	.addressstall_a(1'b0),
	.addressstall_b(1'b0),
	.byteena_a({1{1'b1}}),
	.byteena_b({1{1'b1}}),
	.clock1(1'b1),
	.clocken0(1'b1),
	.clocken1(1'b1),
	.clocken2(1'b1),
	.clocken3(1'b1),
	.data_a({20{1'b1}}),
	.data_b({1{1'b1}}),
	.rden_a(1'b1),
	.rden_b(1'b1),
	.wren_a(1'b0),
	.wren_b(1'b0)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_on
	`endif
	);
	defparam
		altsyncram4.init_file = "MULT.hex",
		altsyncram4.operation_mode = "ROM",
		altsyncram4.outdata_reg_a = "CLOCK0",
		altsyncram4.ram_block_type = "AUTO",
		altsyncram4.width_a = 20,
		altsyncram4.widthad_a = 4,
		altsyncram4.intended_device_family = "Cyclone V",
		altsyncram4.lpm_type = "altsyncram";
	// synopsys translate_off
	initial
		dffe2a0 = 0;
	// synopsys translate_on
	always @ ( posedge clock)
		  dffe2a0 <= (sload_data & (~ sclr));
	// synopsys translate_off
	initial
		dffe2a1 = 0;
	// synopsys translate_on
	always @ ( posedge clock)
		  dffe2a1 <= (dffe2a0[0:0] & (~ sclr));
	// synopsys translate_off
	initial
		dffe2a2 = 0;
	// synopsys translate_on
	always @ ( posedge clock)
		  dffe2a2 <= (dffe2a1[0:0] & (~ sclr));
	// synopsys translate_off
	initial
		dffe2a3 = 0;
	// synopsys translate_on
	always @ ( posedge clock)
		  dffe2a3 <= (dffe2a2[0:0] & (~ sclr));
	// synopsys translate_off
	initial
		dffe2a4 = 0;
	// synopsys translate_on
	always @ ( posedge clock)
		  dffe2a4 <= ((dffe2a3[0:0] & (~ dffe2a2[0:0])) & (~ sclr));
	// synopsys translate_off
	initial
		dffe2a5 = 0;
	// synopsys translate_on
	always @ ( posedge clock)
		  dffe2a5 <= ((dffe2a4[0:0] & (~ dffe2a2[0:0])) & (~ sclr));
	// synopsys translate_off
	initial
		dffe2a6 = 0;
	// synopsys translate_on
	always @ ( posedge clock)
		  dffe2a6 <= ((dffe2a5[0:0] & (~ dffe2a2[0:0])) & (~ sclr));
	// synopsys translate_off
	initial
		dffe3a = 0;
	// synopsys translate_on
	always @ ( posedge clock)
		  dffe3a <= ((data_in[3:0] & {4{sload_data}}) | (wire_altshiftreg1_shiftout & {4{(~ sload_data)}}));
	assign
		result = {result_wire[31:0]},
		result_valid = dffe2a6[0:0],
		result_wire = {wire_accum5_result[19:0], wire_altshiftreg6_q[11:0]},
		sclr = 1'b0;
endmodule //MULT_altmemmult_ipq
//VALID FILE


// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module MULT (
	clock,
	data_in,
	sload_data,
	result,
	result_valid);

	input	  clock;
	input	[15:0]  data_in;
	input	  sload_data;
	output	[31:0]  result;
	output	  result_valid;

	wire [31:0] sub_wire0;
	wire  sub_wire1;
	wire [31:0] result = sub_wire0[31:0];
	wire  result_valid = sub_wire1;

	MULT_altmemmult_ipq	MULT_altmemmult_ipq_component (
				.clock (clock),
				.data_in (data_in),
				.sload_data (sload_data),
				.result (sub_wire0),
				.result_valid (sub_wire1));

endmodule

// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: COEFFICIENT0 STRING "10000"
// Retrieval info: PRIVATE: COEFF_REPRESENTATION_COMBO STRING "UNSIGNED"
// Retrieval info: PRIVATE: COUNT_C_COMBO STRING "16"
// Retrieval info: PRIVATE: COUNT_D_COMBO STRING "16"
// Retrieval info: PRIVATE: DATA_REPRESENTATION_COMBO STRING "UNSIGNED"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: LOADABLE_COEFF STRING "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SCLR_CHECK STRING "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: CONSTANT: COEFFICIENT0 STRING "10000"
// Retrieval info: CONSTANT: COEFF_REPRESENTATION STRING "UNSIGNED"
// Retrieval info: CONSTANT: DATA_REPRESENTATION STRING "UNSIGNED"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: MAX_CLOCK_CYCLES_PER_RESULT NUMERIC "4"
// Retrieval info: CONSTANT: RAM_BLOCK_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: TOTAL_LATENCY NUMERIC "7"
// Retrieval info: CONSTANT: WIDTH_C NUMERIC "16"
// Retrieval info: CONSTANT: WIDTH_D NUMERIC "16"
// Retrieval info: CONSTANT: WIDTH_R NUMERIC "32"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: data_in 0 0 16 0 INPUT NODEFVAL "data_in[15..0]"
// Retrieval info: USED_PORT: result 0 0 32 0 OUTPUT NODEFVAL "result[31..0]"
// Retrieval info: USED_PORT: result_valid 0 0 0 0 OUTPUT NODEFVAL "result_valid"
// Retrieval info: USED_PORT: sload_data 0 0 0 0 INPUT NODEFVAL "sload_data"
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data_in 0 0 16 0 data_in 0 0 16 0
// Retrieval info: CONNECT: @sload_data 0 0 0 0 sload_data 0 0 0 0
// Retrieval info: CONNECT: result 0 0 32 0 @result 0 0 32 0
// Retrieval info: CONNECT: result_valid 0 0 0 0 @result_valid 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL MULT.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL MULT.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL MULT.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL MULT.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL MULT_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL MULT_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
// Retrieval info: LIB_FILE: cyclonev