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|
Analysis & Synthesis report for ex17_top
Sat Dec 10 18:44:45 2016
Quartus Prime Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Analysis & Synthesis Summary
3. Analysis & Synthesis Settings
4. Parallel Compilation
5. Analysis & Synthesis Source Files Read
6. Analysis & Synthesis Resource Usage Summary
7. Analysis & Synthesis Resource Utilization by Entity
8. Analysis & Synthesis RAM Summary
9. Analysis & Synthesis IP Cores Summary
10. State Machine - |ex17_top|processor:ALLPASS|pulse_gen:PULSE0|state
11. State Machine - |ex17_top|spi2adc:SPI_ADC|sr_state
12. State Machine - |ex17_top|spi2dac:SPI_DAC|sr_state
13. Registers Removed During Synthesis
14. Removed Registers Triggering Further Register Optimizations
15. General Register Statistics
16. Inverted Register Statistics
17. Multiplexer Restructuring Statistics (Restructuring Performed)
18. Source assignments for processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|altsyncram_44t1:FIFOram
19. Parameter Settings for User Entity Instance: clktick_16:GEN_10K
20. Parameter Settings for User Entity Instance: spi2dac:SPI_DAC
21. Parameter Settings for User Entity Instance: spi2adc:SPI_ADC
22. Parameter Settings for User Entity Instance: processor:ALLPASS
23. Parameter Settings for User Entity Instance: processor:ALLPASS|pulse_gen:PULSE0
24. Parameter Settings for User Entity Instance: processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component
25. scfifo Parameter Settings by Entity Instance
26. Port Connectivity Checks: "hex_to_7seg:SEG2"
27. Port Connectivity Checks: "processor:ALLPASS|FIFO:DELAY1024"
28. Port Connectivity Checks: "spi2adc:SPI_ADC"
29. Port Connectivity Checks: "clktick_16:GEN_10K"
30. Post-Synthesis Netlist Statistics for Top Partition
31. Elapsed Time Per Partition
32. Analysis & Synthesis Messages
33. Analysis & Synthesis Suppressed Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 2016 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel MegaCore Function License Agreement, or other
applicable license agreement, including, without limitation,
that your use is for the sole purpose of programming logic
devices manufactured by Intel and sold by Intel or its
authorized distributors. Please refer to the applicable
agreement for further details.
+-------------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+---------------------------------+---------------------------------------------+
; Analysis & Synthesis Status ; Successful - Sat Dec 10 18:44:44 2016 ;
; Quartus Prime Version ; 16.1.0 Build 196 10/24/2016 SJ Lite Edition ;
; Revision Name ; ex17_top ;
; Top-level Entity Name ; ex17_top ;
; Family ; Cyclone V ;
; Logic utilization (in ALMs) ; N/A ;
; Total registers ; 153 ;
; Total pins ; 41 ;
; Total virtual pins ; 0 ;
; Total block memory bits ; 73,728 ;
; Total DSP Blocks ; 0 ;
; Total HSSI RX PCSs ; 0 ;
; Total HSSI PMA RX Deserializers ; 0 ;
; Total HSSI TX PCSs ; 0 ;
; Total HSSI PMA TX Serializers ; 0 ;
; Total PLLs ; 0 ;
; Total DLLs ; 0 ;
+---------------------------------+---------------------------------------------+
+---------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings ;
+---------------------------------------------------------------------------------+--------------------+--------------------+
; Option ; Setting ; Default Value ;
+---------------------------------------------------------------------------------+--------------------+--------------------+
; Device ; 5CSEMA5F31C6 ; ;
; Top-level entity name ; ex17_top ; ex17_top ;
; Family name ; Cyclone V ; Cyclone V ;
; Use smart compilation ; Off ; Off ;
; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ;
; Enable compact report table ; Off ; Off ;
; Restructure Multiplexers ; Auto ; Auto ;
; MLAB Add Timing Constraints For Mixed-Port Feed-Through Mode Setting Don't Care ; Off ; Off ;
; Create Debugging Nodes for IP Cores ; Off ; Off ;
; Preserve fewer node names ; On ; On ;
; OpenCore Plus hardware evaluation ; Enable ; Enable ;
; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
; VHDL Version ; VHDL_1993 ; VHDL_1993 ;
; State Machine Processing ; Auto ; Auto ;
; Safe State Machine ; Off ; Off ;
; Extract Verilog State Machines ; On ; On ;
; Extract VHDL State Machines ; On ; On ;
; Ignore Verilog initial constructs ; Off ; Off ;
; Iteration limit for constant Verilog loops ; 5000 ; 5000 ;
; Iteration limit for non-constant Verilog loops ; 250 ; 250 ;
; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
; Infer RAMs from Raw Logic ; On ; On ;
; Parallel Synthesis ; On ; On ;
; DSP Block Balancing ; Auto ; Auto ;
; NOT Gate Push-Back ; On ; On ;
; Power-Up Don't Care ; On ; On ;
; Remove Redundant Logic Cells ; Off ; Off ;
; Remove Duplicate Registers ; On ; On ;
; Ignore CARRY Buffers ; Off ; Off ;
; Ignore CASCADE Buffers ; Off ; Off ;
; Ignore GLOBAL Buffers ; Off ; Off ;
; Ignore ROW GLOBAL Buffers ; Off ; Off ;
; Ignore LCELL Buffers ; Off ; Off ;
; Ignore SOFT Buffers ; On ; On ;
; Limit AHDL Integers to 32 Bits ; Off ; Off ;
; Optimization Technique ; Balanced ; Balanced ;
; Carry Chain Length ; 70 ; 70 ;
; Auto Carry Chains ; On ; On ;
; Auto Open-Drain Pins ; On ; On ;
; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ;
; Auto ROM Replacement ; On ; On ;
; Auto RAM Replacement ; On ; On ;
; Auto DSP Block Replacement ; On ; On ;
; Auto Shift Register Replacement ; Auto ; Auto ;
; Allow Shift Register Merging across Hierarchies ; Auto ; Auto ;
; Auto Clock Enable Replacement ; On ; On ;
; Strict RAM Replacement ; Off ; Off ;
; Allow Synchronous Control Signals ; On ; On ;
; Force Use of Synchronous Clear Signals ; Off ; Off ;
; Auto Resource Sharing ; Off ; Off ;
; Allow Any RAM Size For Recognition ; Off ; Off ;
; Allow Any ROM Size For Recognition ; Off ; Off ;
; Allow Any Shift Register Size For Recognition ; Off ; Off ;
; Use LogicLock Constraints during Resource Balancing ; On ; On ;
; Ignore translate_off and synthesis_off directives ; Off ; Off ;
; Timing-Driven Synthesis ; On ; On ;
; Report Parameter Settings ; On ; On ;
; Report Source Assignments ; On ; On ;
; Report Connectivity Checks ; On ; On ;
; Ignore Maximum Fan-Out Assignments ; Off ; Off ;
; Synchronization Register Chain Length ; 3 ; 3 ;
; PowerPlay Power Optimization During Synthesis ; Normal compilation ; Normal compilation ;
; HDL message level ; Level2 ; Level2 ;
; Suppress Register Optimization Related Messages ; Off ; Off ;
; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ;
; Number of Swept Nodes Reported in Synthesis Report ; 5000 ; 5000 ;
; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ;
; Clock MUX Protection ; On ; On ;
; Auto Gated Clock Conversion ; Off ; Off ;
; Block Design Naming ; Auto ; Auto ;
; SDC constraint protection ; Off ; Off ;
; Synthesis Effort ; Auto ; Auto ;
; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ;
; Pre-Mapping Resynthesis Optimization ; Off ; Off ;
; Analysis & Synthesis Message Level ; Medium ; Medium ;
; Disable Register Merging Across Hierarchies ; Auto ; Auto ;
; Resource Aware Inference For Block RAM ; On ; On ;
; Automatic Parallel Synthesis ; On ; On ;
; Partial Reconfiguration Bitstream ID ; Off ; Off ;
+---------------------------------------------------------------------------------+--------------------+--------------------+
+------------------------------------------+
; Parallel Compilation ;
+----------------------------+-------------+
; Processors ; Number ;
+----------------------------+-------------+
; Number detected on machine ; 2 ;
; Maximum allowed ; 2 ;
; ; ;
; Average used ; 1.00 ;
; Maximum used ; 2 ;
; ; ;
; Usage by Processor ; % Time Used ;
; Processor 1 ; 100.0% ;
; Processor 2 ; 0.0% ;
+----------------------------+-------------+
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+----------------------------------+-----------------+------------------------------+-----------------------------------------------------------------------+---------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ;
+----------------------------------+-----------------+------------------------------+-----------------------------------------------------------------------+---------+
; single_echo.v ; yes ; User Verilog HDL File ; H:/Year 2/VERI/part_4/ex17/single_echo.v ; ;
; ex17_top.v ; yes ; User Verilog HDL File ; H:/Year 2/VERI/part_4/ex17/ex17_top.v ; ;
; ../mylib/spi2dac.v ; yes ; User Verilog HDL File ; H:/Year 2/VERI/part_4/mylib/spi2dac.v ; ;
; ../mylib/spi2adc.v ; yes ; User Verilog HDL File ; H:/Year 2/VERI/part_4/mylib/spi2adc.v ; ;
; ../mylib/pwm.v ; yes ; User Verilog HDL File ; H:/Year 2/VERI/part_4/mylib/pwm.v ; ;
; ../mylib/pulse_gen.v ; yes ; User Verilog HDL File ; H:/Year 2/VERI/part_4/mylib/pulse_gen.v ; ;
; ../mylib/hex_to_7seg.v ; yes ; User Verilog HDL File ; H:/Year 2/VERI/part_4/mylib/hex_to_7seg.v ; ;
; ../mylib/clktick_16.v ; yes ; User Verilog HDL File ; H:/Year 2/VERI/part_4/mylib/clktick_16.v ; ;
; FIFO.v ; yes ; User Wizard-Generated File ; H:/Year 2/VERI/part_4/ex17/FIFO.v ; ;
; scfifo.tdf ; yes ; Megafunction ; c:/intelfpga_lite/16.1/quartus/libraries/megafunctions/scfifo.tdf ; ;
; a_regfifo.inc ; yes ; Megafunction ; c:/intelfpga_lite/16.1/quartus/libraries/megafunctions/a_regfifo.inc ; ;
; a_dpfifo.inc ; yes ; Megafunction ; c:/intelfpga_lite/16.1/quartus/libraries/megafunctions/a_dpfifo.inc ; ;
; a_i2fifo.inc ; yes ; Megafunction ; c:/intelfpga_lite/16.1/quartus/libraries/megafunctions/a_i2fifo.inc ; ;
; a_fffifo.inc ; yes ; Megafunction ; c:/intelfpga_lite/16.1/quartus/libraries/megafunctions/a_fffifo.inc ; ;
; a_f2fifo.inc ; yes ; Megafunction ; c:/intelfpga_lite/16.1/quartus/libraries/megafunctions/a_f2fifo.inc ; ;
; aglobal161.inc ; yes ; Megafunction ; c:/intelfpga_lite/16.1/quartus/libraries/megafunctions/aglobal161.inc ; ;
; db/scfifo_j791.tdf ; yes ; Auto-Generated Megafunction ; H:/Year 2/VERI/part_4/ex17/db/scfifo_j791.tdf ; ;
; db/a_dpfifo_qd91.tdf ; yes ; Auto-Generated Megafunction ; H:/Year 2/VERI/part_4/ex17/db/a_dpfifo_qd91.tdf ; ;
; db/a_fefifo_4be.tdf ; yes ; Auto-Generated Megafunction ; H:/Year 2/VERI/part_4/ex17/db/a_fefifo_4be.tdf ; ;
; db/cntr_di7.tdf ; yes ; Auto-Generated Megafunction ; H:/Year 2/VERI/part_4/ex17/db/cntr_di7.tdf ; ;
; db/altsyncram_44t1.tdf ; yes ; Auto-Generated Megafunction ; H:/Year 2/VERI/part_4/ex17/db/altsyncram_44t1.tdf ; ;
; db/cntr_1ib.tdf ; yes ; Auto-Generated Megafunction ; H:/Year 2/VERI/part_4/ex17/db/cntr_1ib.tdf ; ;
+----------------------------------+-----------------+------------------------------+-----------------------------------------------------------------------+---------+
+--------------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+---------------------------------------------+----------------+
; Resource ; Usage ;
+---------------------------------------------+----------------+
; Estimate of Logic utilization (ALMs needed) ; 96 ;
; ; ;
; Combinational ALUT usage for logic ; 165 ;
; -- 7 input functions ; 0 ;
; -- 6 input functions ; 10 ;
; -- 5 input functions ; 23 ;
; -- 4 input functions ; 31 ;
; -- <=3 input functions ; 101 ;
; ; ;
; Dedicated logic registers ; 153 ;
; ; ;
; I/O pins ; 41 ;
; Total MLAB memory bits ; 0 ;
; Total block memory bits ; 73728 ;
; ; ;
; Total DSP Blocks ; 0 ;
; ; ;
; Maximum fan-out node ; CLOCK_50~input ;
; Maximum fan-out ; 162 ;
; Total fan-out ; 1285 ;
; Average fan-out ; 3.14 ;
+---------------------------------------------+----------------+
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+---------------------------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------+--------------+
; Compilation Hierarchy Node ; Combinational ALUTs ; Dedicated Logic Registers ; Block Memory Bits ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name ; Entity Name ; Library Name ;
+---------------------------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------+--------------+
; |ex17_top ; 165 (0) ; 153 (0) ; 73728 ; 0 ; 41 ; 0 ; |ex17_top ; ex17_top ; work ;
; |clktick_16:GEN_10K| ; 20 (20) ; 17 (17) ; 0 ; 0 ; 0 ; 0 ; |ex17_top|clktick_16:GEN_10K ; clktick_16 ; work ;
; |hex_to_7seg:SEG0| ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex17_top|hex_to_7seg:SEG0 ; hex_to_7seg ; work ;
; |hex_to_7seg:SEG1| ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex17_top|hex_to_7seg:SEG1 ; hex_to_7seg ; work ;
; |hex_to_7seg:SEG2| ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex17_top|hex_to_7seg:SEG2 ; hex_to_7seg ; work ;
; |processor:ALLPASS| ; 69 (22) ; 53 (11) ; 73728 ; 0 ; 0 ; 0 ; |ex17_top|processor:ALLPASS ; processor ; work ;
; |FIFO:DELAY1024| ; 45 (0) ; 40 (0) ; 73728 ; 0 ; 0 ; 0 ; |ex17_top|processor:ALLPASS|FIFO:DELAY1024 ; FIFO ; work ;
; |scfifo:scfifo_component| ; 45 (0) ; 40 (0) ; 73728 ; 0 ; 0 ; 0 ; |ex17_top|processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component ; scfifo ; work ;
; |scfifo_j791:auto_generated| ; 45 (0) ; 40 (0) ; 73728 ; 0 ; 0 ; 0 ; |ex17_top|processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated ; scfifo_j791 ; work ;
; |a_dpfifo_qd91:dpfifo| ; 45 (1) ; 40 (0) ; 73728 ; 0 ; 0 ; 0 ; |ex17_top|processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo ; a_dpfifo_qd91 ; work ;
; |a_fefifo_4be:fifo_state| ; 18 (5) ; 14 (1) ; 0 ; 0 ; 0 ; 0 ; |ex17_top|processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|a_fefifo_4be:fifo_state ; a_fefifo_4be ; work ;
; |cntr_di7:count_usedw| ; 13 (13) ; 13 (13) ; 0 ; 0 ; 0 ; 0 ; |ex17_top|processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|a_fefifo_4be:fifo_state|cntr_di7:count_usedw ; cntr_di7 ; work ;
; |altsyncram_44t1:FIFOram| ; 0 (0) ; 0 (0) ; 73728 ; 0 ; 0 ; 0 ; |ex17_top|processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|altsyncram_44t1:FIFOram ; altsyncram_44t1 ; work ;
; |cntr_1ib:rd_ptr_count| ; 13 (13) ; 13 (13) ; 0 ; 0 ; 0 ; 0 ; |ex17_top|processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|cntr_1ib:rd_ptr_count ; cntr_1ib ; work ;
; |cntr_1ib:wr_ptr| ; 13 (13) ; 13 (13) ; 0 ; 0 ; 0 ; 0 ; |ex17_top|processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|cntr_1ib:wr_ptr ; cntr_1ib ; work ;
; |pulse_gen:PULSE0| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; |ex17_top|processor:ALLPASS|pulse_gen:PULSE0 ; pulse_gen ; work ;
; |pwm:PWM_DC| ; 19 (19) ; 21 (21) ; 0 ; 0 ; 0 ; 0 ; |ex17_top|pwm:PWM_DC ; pwm ; work ;
; |spi2adc:SPI_ADC| ; 23 (23) ; 40 (40) ; 0 ; 0 ; 0 ; 0 ; |ex17_top|spi2adc:SPI_ADC ; spi2adc ; work ;
; |spi2dac:SPI_DAC| ; 17 (17) ; 22 (22) ; 0 ; 0 ; 0 ; 0 ; |ex17_top|spi2dac:SPI_DAC ; spi2dac ; work ;
+---------------------------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis RAM Summary ;
+---------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+-------+------+
; Name ; Type ; Mode ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size ; MIF ;
+---------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+-------+------+
; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|altsyncram_44t1:FIFOram|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 8192 ; 10 ; 8192 ; 10 ; 81920 ; None ;
+---------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+-------+------+
+------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis IP Cores Summary ;
+--------+--------------+---------+--------------+--------------+--------------------------------------------+-----------------+
; Vendor ; IP Core Name ; Version ; Release Date ; License Type ; Entity Instance ; IP Include File ;
+--------+--------------+---------+--------------+--------------+--------------------------------------------+-----------------+
; Altera ; FIFO ; 16.1 ; N/A ; N/A ; |ex17_top|processor:ALLPASS|FIFO:DELAY1024 ; FIFO.v ;
+--------+--------------+---------+--------------+--------------+--------------------------------------------+-----------------+
Encoding Type: One-Hot
+--------------------------------------------------------------------+
; State Machine - |ex17_top|processor:ALLPASS|pulse_gen:PULSE0|state ;
+----------------+------------+----------------+---------------------+
; Name ; state.IDLE ; state.WAIT_LOW ; state.IN_HIGH ;
+----------------+------------+----------------+---------------------+
; state.IDLE ; 0 ; 0 ; 0 ;
; state.IN_HIGH ; 1 ; 0 ; 1 ;
; state.WAIT_LOW ; 1 ; 1 ; 0 ;
+----------------+------------+----------------+---------------------+
Encoding Type: One-Hot
+------------------------------------------------------------------------------------------+
; State Machine - |ex17_top|spi2adc:SPI_ADC|sr_state ;
+------------------------+---------------+------------------------+------------------------+
; Name ; sr_state.IDLE ; sr_state.WAIT_CSB_HIGH ; sr_state.WAIT_CSB_FALL ;
+------------------------+---------------+------------------------+------------------------+
; sr_state.IDLE ; 0 ; 0 ; 0 ;
; sr_state.WAIT_CSB_FALL ; 1 ; 0 ; 1 ;
; sr_state.WAIT_CSB_HIGH ; 1 ; 1 ; 0 ;
+------------------------+---------------+------------------------+------------------------+
Encoding Type: One-Hot
+------------------------------------------------------------------------------------------+
; State Machine - |ex17_top|spi2dac:SPI_DAC|sr_state ;
+------------------------+---------------+------------------------+------------------------+
; Name ; sr_state.IDLE ; sr_state.WAIT_CSB_HIGH ; sr_state.WAIT_CSB_FALL ;
+------------------------+---------------+------------------------+------------------------+
; sr_state.IDLE ; 0 ; 0 ; 0 ;
; sr_state.WAIT_CSB_FALL ; 1 ; 0 ; 1 ;
; sr_state.WAIT_CSB_HIGH ; 1 ; 1 ; 0 ;
+------------------------+---------------+------------------------+------------------------+
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Registers Removed During Synthesis ;
+----------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------+
; Register name ; Reason for Removal ;
+----------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------+
; spi2dac:SPI_DAC|clk_1MHz ; Merged with spi2adc:SPI_ADC|clk_1MHz ;
; spi2dac:SPI_DAC|tick ; Merged with spi2adc:SPI_ADC|tick ;
; spi2dac:SPI_DAC|ctr[4] ; Merged with spi2adc:SPI_ADC|ctr[4] ;
; spi2dac:SPI_DAC|ctr[3] ; Merged with spi2adc:SPI_ADC|ctr[3] ;
; spi2dac:SPI_DAC|ctr[2] ; Merged with spi2adc:SPI_ADC|ctr[2] ;
; spi2dac:SPI_DAC|ctr[1] ; Merged with spi2adc:SPI_ADC|ctr[1] ;
; spi2dac:SPI_DAC|ctr[0] ; Merged with spi2adc:SPI_ADC|ctr[0] ;
; spi2dac:SPI_DAC|shift_reg[0,1] ; Stuck at GND due to stuck port data_in ;
; processor:ALLPASS|pulse_gen:PULSE0|state.IN_HIGH ; Lost fanout ;
; processor:ALLPASS|pulse_gen:PULSE0|state.WAIT_LOW ; Lost fanout ;
; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|a_fefifo_4be:fifo_state|b_non_empty ; Stuck at VCC due to stuck port data_in ;
; Total Number of Removed Registers = 12 ; ;
+----------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------+
+---------------------------------------------------------------------------------------------------+
; Removed Registers Triggering Further Register Optimizations ;
+------------------------------+---------------------------+----------------------------------------+
; Register name ; Reason for Removal ; Registers Removed due to This Register ;
+------------------------------+---------------------------+----------------------------------------+
; spi2dac:SPI_DAC|shift_reg[0] ; Stuck at GND ; spi2dac:SPI_DAC|shift_reg[1] ;
; ; due to stuck port data_in ; ;
+------------------------------+---------------------------+----------------------------------------+
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 153 ;
; Number of registers using Synchronous Clear ; 9 ;
; Number of registers using Synchronous Load ; 9 ;
; Number of registers using Asynchronous Clear ; 0 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 93 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+--------------------------------------------------+
; Inverted Register Statistics ;
+----------------------------------------+---------+
; Inverted Register ; Fan out ;
+----------------------------------------+---------+
; spi2adc:SPI_ADC|adc_cs ; 9 ;
; Total number of inverted registers = 1 ; ;
+----------------------------------------+---------+
+-------------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed) ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------------------+
; 3:1 ; 3 bits ; 6 LEs ; 3 LEs ; 3 LEs ; Yes ; |ex17_top|spi2dac:SPI_DAC|shift_reg[13] ;
; 3:1 ; 9 bits ; 18 LEs ; 0 LEs ; 18 LEs ; Yes ; |ex17_top|spi2dac:SPI_DAC|shift_reg[11] ;
; 6:1 ; 3 bits ; 12 LEs ; 6 LEs ; 6 LEs ; No ; |ex17_top|spi2dac:SPI_DAC|Selector2 ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------------------+
+---------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|altsyncram_44t1:FIFOram ;
+---------------------------------+--------------------+------+-------------------------------------------------------------------------------------------+
; Assignment ; Value ; From ; To ;
+---------------------------------+--------------------+------+-------------------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ;
+---------------------------------+--------------------+------+-------------------------------------------------------------------------------------------+
+-----------------------------------------------------------------+
; Parameter Settings for User Entity Instance: clktick_16:GEN_10K ;
+----------------+-------+----------------------------------------+
; Parameter Name ; Value ; Type ;
+----------------+-------+----------------------------------------+
; N_BIT ; 16 ; Signed Integer ;
+----------------+-------+----------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+--------------------------------------------------------------+
; Parameter Settings for User Entity Instance: spi2dac:SPI_DAC ;
+----------------+-------+-------------------------------------+
; Parameter Name ; Value ; Type ;
+----------------+-------+-------------------------------------+
; BUF ; 1 ; Unsigned Binary ;
; GA_N ; 1 ; Unsigned Binary ;
; SHDN_N ; 1 ; Unsigned Binary ;
; TC ; 11000 ; Unsigned Binary ;
; IDLE ; 00 ; Unsigned Binary ;
; WAIT_CSB_FALL ; 01 ; Unsigned Binary ;
; WAIT_CSB_HIGH ; 10 ; Unsigned Binary ;
+----------------+-------+-------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+--------------------------------------------------------------+
; Parameter Settings for User Entity Instance: spi2adc:SPI_ADC ;
+----------------+-------+-------------------------------------+
; Parameter Name ; Value ; Type ;
+----------------+-------+-------------------------------------+
; SGL ; 1 ; Unsigned Binary ;
; MSBF ; 1 ; Unsigned Binary ;
; TIME_CONSTANT ; 11000 ; Unsigned Binary ;
; IDLE ; 00 ; Unsigned Binary ;
; WAIT_CSB_FALL ; 01 ; Unsigned Binary ;
; WAIT_CSB_HIGH ; 10 ; Unsigned Binary ;
+----------------+-------+-------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+----------------------------------------------------------------+
; Parameter Settings for User Entity Instance: processor:ALLPASS ;
+----------------+------------+----------------------------------+
; Parameter Name ; Value ; Type ;
+----------------+------------+----------------------------------+
; ADC_OFFSET ; 0110000001 ; Unsigned Binary ;
; DAC_OFFSET ; 1000000000 ; Unsigned Binary ;
+----------------+------------+----------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+---------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: processor:ALLPASS|pulse_gen:PULSE0 ;
+----------------+-------+--------------------------------------------------------+
; Parameter Name ; Value ; Type ;
+----------------+-------+--------------------------------------------------------+
; IDLE ; 00 ; Unsigned Binary ;
; IN_HIGH ; 01 ; Unsigned Binary ;
; WAIT_LOW ; 10 ; Unsigned Binary ;
+----------------+-------+--------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+-------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component ;
+-------------------------+-------------+---------------------------------------------------------------+
; Parameter Name ; Value ; Type ;
+-------------------------+-------------+---------------------------------------------------------------+
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
; lpm_width ; 10 ; Signed Integer ;
; LPM_NUMWORDS ; 8192 ; Signed Integer ;
; LPM_WIDTHU ; 13 ; Signed Integer ;
; LPM_SHOWAHEAD ; OFF ; Untyped ;
; UNDERFLOW_CHECKING ; ON ; Untyped ;
; OVERFLOW_CHECKING ; ON ; Untyped ;
; ALLOW_RWCYCLE_WHEN_FULL ; OFF ; Untyped ;
; ADD_RAM_OUTPUT_REGISTER ; OFF ; Untyped ;
; ALMOST_FULL_VALUE ; 0 ; Untyped ;
; ALMOST_EMPTY_VALUE ; 0 ; Untyped ;
; ENABLE_ECC ; FALSE ; Untyped ;
; USE_EAB ; ON ; Untyped ;
; MAXIMIZE_SPEED ; 5 ; Untyped ;
; DEVICE_FAMILY ; Cyclone V ; Untyped ;
; OPTIMIZE_FOR_SPEED ; 5 ; Untyped ;
; CBXI_PARAMETER ; scfifo_j791 ; Untyped ;
+-------------------------+-------------+---------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+---------------------------------------------------------------------------------------+
; scfifo Parameter Settings by Entity Instance ;
+----------------------------+----------------------------------------------------------+
; Name ; Value ;
+----------------------------+----------------------------------------------------------+
; Number of entity instances ; 1 ;
; Entity Instance ; processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component ;
; -- FIFO Type ; Single Clock ;
; -- lpm_width ; 10 ;
; -- LPM_NUMWORDS ; 8192 ;
; -- LPM_SHOWAHEAD ; OFF ;
; -- USE_EAB ; ON ;
+----------------------------+----------------------------------------------------------+
+----------------------------------------------+
; Port Connectivity Checks: "hex_to_7seg:SEG2" ;
+----------+-------+----------+----------------+
; Port ; Type ; Severity ; Details ;
+----------+-------+----------+----------------+
; in[3..2] ; Input ; Info ; Stuck at GND ;
+----------+-------+----------+----------------+
+-----------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "processor:ALLPASS|FIFO:DELAY1024" ;
+-------+--------+----------+-------------------------------------------------------------------------------------+
; Port ; Type ; Severity ; Details ;
+-------+--------+----------+-------------------------------------------------------------------------------------+
; empty ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; q[0] ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+-------+--------+----------+-------------------------------------------------------------------------------------+
+---------------------------------------------+
; Port Connectivity Checks: "spi2adc:SPI_ADC" ;
+---------+-------+----------+----------------+
; Port ; Type ; Severity ; Details ;
+---------+-------+----------+----------------+
; channel ; Input ; Info ; Stuck at VCC ;
+---------+-------+----------+----------------+
+------------------------------------------------+
; Port Connectivity Checks: "clktick_16:GEN_10K" ;
+-----------+-------+----------+-----------------+
; Port ; Type ; Severity ; Details ;
+-----------+-------+----------+-----------------+
; enable ; Input ; Info ; Stuck at VCC ;
; N[9..7] ; Input ; Info ; Stuck at VCC ;
; N[2..0] ; Input ; Info ; Stuck at VCC ;
; N[15..13] ; Input ; Info ; Stuck at GND ;
; N[11..10] ; Input ; Info ; Stuck at GND ;
; N[6..3] ; Input ; Info ; Stuck at GND ;
; N[12] ; Input ; Info ; Stuck at VCC ;
+-----------+-------+----------+-----------------+
+-----------------------------------------------------+
; Post-Synthesis Netlist Statistics for Top Partition ;
+-----------------------+-----------------------------+
; Type ; Count ;
+-----------------------+-----------------------------+
; arriav_ff ; 153 ;
; ENA ; 84 ;
; ENA SLD ; 9 ;
; SCLR ; 9 ;
; plain ; 51 ;
; arriav_lcell_comb ; 173 ;
; arith ; 84 ;
; 1 data inputs ; 61 ;
; 2 data inputs ; 23 ;
; normal ; 89 ;
; 0 data inputs ; 1 ;
; 1 data inputs ; 10 ;
; 2 data inputs ; 8 ;
; 3 data inputs ; 6 ;
; 4 data inputs ; 31 ;
; 5 data inputs ; 23 ;
; 6 data inputs ; 10 ;
; boundary_port ; 41 ;
; stratixv_ram_block ; 9 ;
; ; ;
; Max LUT depth ; 3.90 ;
; Average LUT depth ; 1.90 ;
+-----------------------+-----------------------------+
+-------------------------------+
; Elapsed Time Per Partition ;
+----------------+--------------+
; Partition Name ; Elapsed Time ;
+----------------+--------------+
; Top ; 00:00:03 ;
+----------------+--------------+
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus Prime Analysis & Synthesis
Info: Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition
Info: Processing started: Sat Dec 10 18:43:39 2016
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off ex17 -c ex17_top
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected
Info (12021): Found 1 design units, including 1 entities, in source file single_echo.v
Info (12023): Found entity 1: processor File: H:/Year 2/VERI/part_4/ex17/single_echo.v Line: 1
Info (12021): Found 1 design units, including 1 entities, in source file ex17_top.v
Info (12023): Found entity 1: ex17_top File: H:/Year 2/VERI/part_4/ex17/ex17_top.v Line: 1
Info (12021): Found 1 design units, including 1 entities, in source file /year 2/veri/part_4/mylib/spi2dac.v
Info (12023): Found entity 1: spi2dac File: H:/Year 2/VERI/part_4/mylib/spi2dac.v Line: 9
Info (12021): Found 1 design units, including 1 entities, in source file /year 2/veri/part_4/mylib/spi2adc.v
Info (12023): Found entity 1: spi2adc File: H:/Year 2/VERI/part_4/mylib/spi2adc.v Line: 9
Info (12021): Found 1 design units, including 1 entities, in source file /year 2/veri/part_4/mylib/pwm.v
Info (12023): Found entity 1: pwm File: H:/Year 2/VERI/part_4/mylib/pwm.v Line: 1
Info (12021): Found 1 design units, including 1 entities, in source file /year 2/veri/part_4/mylib/pulse_gen.v
Info (12023): Found entity 1: pulse_gen File: H:/Year 2/VERI/part_4/mylib/pulse_gen.v Line: 9
Info (12021): Found 1 design units, including 1 entities, in source file /year 2/veri/part_4/mylib/multiply_k.v
Info (12023): Found entity 1: multiply_k File: H:/Year 2/VERI/part_4/mylib/multiply_k.v Line: 39
Info (12021): Found 1 design units, including 1 entities, in source file /year 2/veri/part_4/mylib/multiply_4.v
Info (12023): Found entity 1: multiply_4 File: H:/Year 2/VERI/part_4/mylib/multiply_4.v Line: 39
Info (12021): Found 1 design units, including 1 entities, in source file /year 2/veri/part_4/mylib/hex_to_7seg.v
Info (12023): Found entity 1: hex_to_7seg File: H:/Year 2/VERI/part_4/mylib/hex_to_7seg.v Line: 10
Info (12021): Found 1 design units, including 1 entities, in source file /year 2/veri/part_4/mylib/counter_13.v
Info (12023): Found entity 1: counter_13 File: H:/Year 2/VERI/part_4/mylib/counter_13.v Line: 3
Info (12021): Found 1 design units, including 1 entities, in source file /year 2/veri/part_4/mylib/clktick_16.v
Info (12023): Found entity 1: clktick_16 File: H:/Year 2/VERI/part_4/mylib/clktick_16.v Line: 6
Info (12021): Found 1 design units, including 1 entities, in source file /year 2/veri/part_4/mylib/bin2bcd_16.v
Info (12023): Found entity 1: bin2bcd_16 File: H:/Year 2/VERI/part_4/mylib/bin2bcd_16.v Line: 12
Info (12021): Found 1 design units, including 1 entities, in source file /year 2/veri/part_4/mylib/add3_ge5.v
Info (12023): Found entity 1: add3_ge5 File: H:/Year 2/VERI/part_4/mylib/add3_ge5.v Line: 9
Info (12021): Found 1 design units, including 1 entities, in source file fifo.v
Info (12023): Found entity 1: FIFO File: H:/Year 2/VERI/part_4/ex17/FIFO.v Line: 40
Info (12127): Elaborating entity "ex17_top" for the top level hierarchy
Info (12128): Elaborating entity "clktick_16" for hierarchy "clktick_16:GEN_10K" File: H:/Year 2/VERI/part_4/ex17/ex17_top.v Line: 24
Info (12128): Elaborating entity "spi2dac" for hierarchy "spi2dac:SPI_DAC" File: H:/Year 2/VERI/part_4/ex17/ex17_top.v Line: 26
Info (12128): Elaborating entity "pwm" for hierarchy "pwm:PWM_DC" File: H:/Year 2/VERI/part_4/ex17/ex17_top.v Line: 27
Info (12128): Elaborating entity "spi2adc" for hierarchy "spi2adc:SPI_ADC" File: H:/Year 2/VERI/part_4/ex17/ex17_top.v Line: 38
Info (12128): Elaborating entity "processor" for hierarchy "processor:ALLPASS" File: H:/Year 2/VERI/part_4/ex17/ex17_top.v Line: 40
Info (12128): Elaborating entity "pulse_gen" for hierarchy "processor:ALLPASS|pulse_gen:PULSE0" File: H:/Year 2/VERI/part_4/ex17/single_echo.v Line: 23
Info (12128): Elaborating entity "FIFO" for hierarchy "processor:ALLPASS|FIFO:DELAY1024" File: H:/Year 2/VERI/part_4/ex17/single_echo.v Line: 33
Info (12128): Elaborating entity "scfifo" for hierarchy "processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component" File: H:/Year 2/VERI/part_4/ex17/FIFO.v Line: 77
Info (12130): Elaborated megafunction instantiation "processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component" File: H:/Year 2/VERI/part_4/ex17/FIFO.v Line: 77
Info (12133): Instantiated megafunction "processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component" with the following parameter: File: H:/Year 2/VERI/part_4/ex17/FIFO.v Line: 77
Info (12134): Parameter "add_ram_output_register" = "OFF"
Info (12134): Parameter "intended_device_family" = "Cyclone V"
Info (12134): Parameter "lpm_numwords" = "8192"
Info (12134): Parameter "lpm_showahead" = "OFF"
Info (12134): Parameter "lpm_type" = "scfifo"
Info (12134): Parameter "lpm_width" = "10"
Info (12134): Parameter "lpm_widthu" = "13"
Info (12134): Parameter "overflow_checking" = "ON"
Info (12134): Parameter "underflow_checking" = "ON"
Info (12134): Parameter "use_eab" = "ON"
Info (12021): Found 1 design units, including 1 entities, in source file db/scfifo_j791.tdf
Info (12023): Found entity 1: scfifo_j791 File: H:/Year 2/VERI/part_4/ex17/db/scfifo_j791.tdf Line: 25
Info (12128): Elaborating entity "scfifo_j791" for hierarchy "processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated" File: c:/intelfpga_lite/16.1/quartus/libraries/megafunctions/scfifo.tdf Line: 300
Info (12021): Found 1 design units, including 1 entities, in source file db/a_dpfifo_qd91.tdf
Info (12023): Found entity 1: a_dpfifo_qd91 File: H:/Year 2/VERI/part_4/ex17/db/a_dpfifo_qd91.tdf Line: 29
Info (12128): Elaborating entity "a_dpfifo_qd91" for hierarchy "processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo" File: H:/Year 2/VERI/part_4/ex17/db/scfifo_j791.tdf Line: 36
Info (12021): Found 1 design units, including 1 entities, in source file db/a_fefifo_4be.tdf
Info (12023): Found entity 1: a_fefifo_4be File: H:/Year 2/VERI/part_4/ex17/db/a_fefifo_4be.tdf Line: 25
Info (12128): Elaborating entity "a_fefifo_4be" for hierarchy "processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|a_fefifo_4be:fifo_state" File: H:/Year 2/VERI/part_4/ex17/db/a_dpfifo_qd91.tdf Line: 41
Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_di7.tdf
Info (12023): Found entity 1: cntr_di7 File: H:/Year 2/VERI/part_4/ex17/db/cntr_di7.tdf Line: 26
Info (12128): Elaborating entity "cntr_di7" for hierarchy "processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|a_fefifo_4be:fifo_state|cntr_di7:count_usedw" File: H:/Year 2/VERI/part_4/ex17/db/a_fefifo_4be.tdf Line: 38
Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_44t1.tdf
Info (12023): Found entity 1: altsyncram_44t1 File: H:/Year 2/VERI/part_4/ex17/db/altsyncram_44t1.tdf Line: 28
Info (12128): Elaborating entity "altsyncram_44t1" for hierarchy "processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|altsyncram_44t1:FIFOram" File: H:/Year 2/VERI/part_4/ex17/db/a_dpfifo_qd91.tdf Line: 42
Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_1ib.tdf
Info (12023): Found entity 1: cntr_1ib File: H:/Year 2/VERI/part_4/ex17/db/cntr_1ib.tdf Line: 26
Info (12128): Elaborating entity "cntr_1ib" for hierarchy "processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|cntr_1ib:rd_ptr_count" File: H:/Year 2/VERI/part_4/ex17/db/a_dpfifo_qd91.tdf Line: 43
Info (12128): Elaborating entity "hex_to_7seg" for hierarchy "hex_to_7seg:SEG0" File: H:/Year 2/VERI/part_4/ex17/ex17_top.v Line: 42
Warning (14284): Synthesized away the following node(s):
Warning (14285): Synthesized away the following RAM node(s):
Warning (14320): Synthesized away node "processor:ALLPASS|FIFO:DELAY1024|scfifo:scfifo_component|scfifo_j791:auto_generated|a_dpfifo_qd91:dpfifo|altsyncram_44t1:FIFOram|q_b[0]" File: H:/Year 2/VERI/part_4/ex17/db/altsyncram_44t1.tdf Line: 40
Warning (13024): Output pins are stuck at VCC or GND
Warning (13410): Pin "HEX2[1]" is stuck at GND File: H:/Year 2/VERI/part_4/ex17/ex17_top.v Line: 7
Info (286030): Timing-Driven Synthesis is running
Info (17049): 2 registers lost all their fanouts during netlist optimizations.
Info (144001): Generated suppressed messages file H:/Year 2/VERI/part_4/ex17/output_files/ex17_top.map.smsg
Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL
Warning (21074): Design contains 10 input pin(s) that do not drive logic
Warning (15610): No output dependent on input pin "SW[0]" File: H:/Year 2/VERI/part_4/ex17/ex17_top.v Line: 6
Warning (15610): No output dependent on input pin "SW[1]" File: H:/Year 2/VERI/part_4/ex17/ex17_top.v Line: 6
Warning (15610): No output dependent on input pin "SW[2]" File: H:/Year 2/VERI/part_4/ex17/ex17_top.v Line: 6
Warning (15610): No output dependent on input pin "SW[3]" File: H:/Year 2/VERI/part_4/ex17/ex17_top.v Line: 6
Warning (15610): No output dependent on input pin "SW[4]" File: H:/Year 2/VERI/part_4/ex17/ex17_top.v Line: 6
Warning (15610): No output dependent on input pin "SW[5]" File: H:/Year 2/VERI/part_4/ex17/ex17_top.v Line: 6
Warning (15610): No output dependent on input pin "SW[6]" File: H:/Year 2/VERI/part_4/ex17/ex17_top.v Line: 6
Warning (15610): No output dependent on input pin "SW[7]" File: H:/Year 2/VERI/part_4/ex17/ex17_top.v Line: 6
Warning (15610): No output dependent on input pin "SW[8]" File: H:/Year 2/VERI/part_4/ex17/ex17_top.v Line: 6
Warning (15610): No output dependent on input pin "SW[9]" File: H:/Year 2/VERI/part_4/ex17/ex17_top.v Line: 6
Info (21057): Implemented 256 device resources after synthesis - the final resource count might be different
Info (21058): Implemented 12 input pins
Info (21059): Implemented 29 output pins
Info (21061): Implemented 206 logic cells
Info (21064): Implemented 9 RAM segments
Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 17 warnings
Info: Peak virtual memory: 710 megabytes
Info: Processing ended: Sat Dec 10 18:44:47 2016
Info: Elapsed time: 00:01:08
Info: Total CPU time (on all processors): 00:00:40
+------------------------------------------+
; Analysis & Synthesis Suppressed Messages ;
+------------------------------------------+
The suppressed messages can be found in H:/Year 2/VERI/part_4/ex17/output_files/ex17_top.map.smsg.
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