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module processor (sysclk, data_in, data_out, data_valid);
input sysclk; // system clock
input data_valid;
input [9:0] data_in; // 10-bit input data
output [9:0] data_out; // 10-bit output data
wire sysclk;
wire [9:0] data_in;
reg [9:0] data_out;
wire [9:0] x,y,FIFO_out;
wire pulse;
wire FIFO_full, FIFO_empty;
reg full_reg;
parameter ADC_OFFSET = 10'h181;
parameter DAC_OFFSET = 10'h200;
assign x = data_in[9:0] - ADC_OFFSET; // x is input in 2's complement
assign y = x + {FIFO_out[9],FIFO_out[9:1]};
pulse_gen PULSE0 (pulse, data_valid, sysclk);
FIFO DELAY1024 (
.clock(sysclk),
.data(x),
.full(FIFO_full),
.empty(FIFO_empty),
.wrreq(pulse),
.rdreq(pulse && full_reg),
.q(FIFO_out)
);
// Now clock y output with system clock
always @ (posedge sysclk)
begin
full_reg <= FIFO_full;
data_out <= y + DAC_OFFSET;
end
endmodule
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