part_4/mylib/counter_13.v


1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

`timescale 1ns / 100ps

module counter_13 (
		clock,
		enable,
		count,
		reset
		);
		
		parameter BIT_SZ = 13;
		input clock;
		input enable;
		input reset;
		output reg [BIT_SZ-1:0] count;
		
		
		initial count = 0;
		
		always @ (posedge clock)
			if (reset == 1'b0)
				count <= 0;
			else if (enable == 1'b0)
				count <= count + 1'b1;				
endmodule