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| author | Vasil Zlatanov <v@skozl.com> | 2016-12-12 21:51:10 +0000 |
|---|---|---|
| committer | Vasil Zlatanov <v@skozl.com> | 2016-12-12 21:51:10 +0000 |
| commit | 4b6e0102d20d9ab060ce930e4b846c8be446bb06 (patch) | |
| tree | e475eab3716738f2928f0b2063956e9b155f94ab /part_2/ex9/divider_2500.v | |
| download | e2-verilab-4b6e0102d20d9ab060ce930e4b846c8be446bb06.tar.gz e2-verilab-4b6e0102d20d9ab060ce930e4b846c8be446bb06.tar.bz2 e2-verilab-4b6e0102d20d9ab060ce930e4b846c8be446bb06.zip | |
public push
Diffstat (limited to 'part_2/ex9/divider_2500.v')
| -rw-r--r-- | part_2/ex9/divider_2500.v | 36 |
1 files changed, 36 insertions, 0 deletions
diff --git a/part_2/ex9/divider_2500.v b/part_2/ex9/divider_2500.v new file mode 100644 index 0000000..305b2b6 --- /dev/null +++ b/part_2/ex9/divider_2500.v @@ -0,0 +1,36 @@ +`timescale 1ns / 100ps
+
+
+module divider_2500 (
+ clock,
+ clock_ms,
+ out
+ );
+
+ parameter BIT_SZ = 12;
+ input clock;
+ input clock_ms;
+ reg [BIT_SZ-1:0] count;
+
+ initial count = 0;
+
+ output reg out;
+
+
+ always @ (posedge clock)
+ begin
+ if (clock_ms)
+ begin
+ if (count < 12'd499)
+ begin
+ count <= count + 1'b1;
+ out <= 1'b0;
+ end
+ else
+ begin
+ out <= 1'b1;
+ count <= 1'b0;
+ end
+ end
+ end
+endmodule
|