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|
`timescale 1ns / 100ps
module divider_2500 (
clock,
clock_ms,
out
);
parameter BIT_SZ = 12;
input clock;
input clock_ms;
reg [BIT_SZ-1:0] count;
initial count = 0;
output reg out;
always @ (posedge clock)
begin
if (clock_ms)
begin
if (count < 12'd499)
begin
count <= count + 1'b1;
out <= 1'b0;
end
else
begin
out <= 1'b1;
count <= 1'b0;
end
end
end
endmodule
|
