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| author | Vasil Zlatanov <v@skozl.com> | 2016-12-12 21:51:10 +0000 |
|---|---|---|
| committer | Vasil Zlatanov <v@skozl.com> | 2016-12-12 21:51:10 +0000 |
| commit | 4b6e0102d20d9ab060ce930e4b846c8be446bb06 (patch) | |
| tree | e475eab3716738f2928f0b2063956e9b155f94ab /part_3/mylib/add3_ge5.v | |
| download | e2-verilab-4b6e0102d20d9ab060ce930e4b846c8be446bb06.tar.gz e2-verilab-4b6e0102d20d9ab060ce930e4b846c8be446bb06.tar.bz2 e2-verilab-4b6e0102d20d9ab060ce930e4b846c8be446bb06.zip | |
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Diffstat (limited to 'part_3/mylib/add3_ge5.v')
| -rw-r--r-- | part_3/mylib/add3_ge5.v | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/part_3/mylib/add3_ge5.v b/part_3/mylib/add3_ge5.v new file mode 100644 index 0000000..282dcac --- /dev/null +++ b/part_3/mylib/add3_ge5.v @@ -0,0 +1,11 @@ +module add3_ge5 (in,out);
+
+ input [3:0] in;
+ output reg [3:0] out;
+
+ always @ (in)
+ if (in >= 4'd5)
+ out <= in + 4'd3;
+ else
+ out <= in;
+endmodule
\ No newline at end of file |