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| author | Vasil Zlatanov <v@skozl.com> | 2016-12-12 21:51:10 +0000 |
|---|---|---|
| committer | Vasil Zlatanov <v@skozl.com> | 2016-12-12 21:51:10 +0000 |
| commit | 4b6e0102d20d9ab060ce930e4b846c8be446bb06 (patch) | |
| tree | e475eab3716738f2928f0b2063956e9b155f94ab /part_3/mylib/counter_16.v | |
| download | e2-verilab-4b6e0102d20d9ab060ce930e4b846c8be446bb06.tar.gz e2-verilab-4b6e0102d20d9ab060ce930e4b846c8be446bb06.tar.bz2 e2-verilab-4b6e0102d20d9ab060ce930e4b846c8be446bb06.zip | |
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Diffstat (limited to 'part_3/mylib/counter_16.v')
| -rw-r--r-- | part_3/mylib/counter_16.v | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/part_3/mylib/counter_16.v b/part_3/mylib/counter_16.v new file mode 100644 index 0000000..a52dc38 --- /dev/null +++ b/part_3/mylib/counter_16.v @@ -0,0 +1,24 @@ +`timescale 1ns / 100ps
+
+module counter_16 (
+ clock,
+ enable,
+ count,
+ reset
+ );
+
+ parameter BIT_SZ = 16;
+ input clock;
+ input enable;
+ input reset;
+ output reg [BIT_SZ-1:0] count;
+
+
+ initial count = 0;
+
+ always @ (posedge clock)
+ if (reset == 1'b0)
+ count <= 0;
+ else if (enable == 1'b0)
+ count <= count + 1'b1;
+endmodule
|