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| author | Vasil Zlatanov <v@skozl.com> | 2016-12-12 21:51:10 +0000 |
|---|---|---|
| committer | Vasil Zlatanov <v@skozl.com> | 2016-12-12 21:51:10 +0000 |
| commit | 4b6e0102d20d9ab060ce930e4b846c8be446bb06 (patch) | |
| tree | e475eab3716738f2928f0b2063956e9b155f94ab /part_3/mylib/pwm.v | |
| download | e2-verilab-4b6e0102d20d9ab060ce930e4b846c8be446bb06.tar.gz e2-verilab-4b6e0102d20d9ab060ce930e4b846c8be446bb06.tar.bz2 e2-verilab-4b6e0102d20d9ab060ce930e4b846c8be446bb06.zip | |
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Diffstat (limited to 'part_3/mylib/pwm.v')
| -rw-r--r-- | part_3/mylib/pwm.v | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/part_3/mylib/pwm.v b/part_3/mylib/pwm.v new file mode 100644 index 0000000..6dce0a5 --- /dev/null +++ b/part_3/mylib/pwm.v @@ -0,0 +1,28 @@ +module pwm (clk, data_in, load, pwm_out);
+
+ input clk;
+ input [9:0] data_in;
+ input load;
+ output pwm_out;
+
+ reg [9:0] d;
+ reg [9:0] count;
+ reg pwm_out;
+
+ always @ (posedge clk)
+ if (load == 1'b1) d <= data_in;
+
+ initial count = 10'b0;
+
+ always @ (posedge clk) begin
+ count <= count + 1'b1;
+ if (count > d)
+ pwm_out <= 1'b0;
+ else
+ pwm_out <= 1'b1;
+
+ end
+
+
+
+endmodule
\ No newline at end of file |