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| author | Vasil Zlatanov <v@skozl.com> | 2016-12-12 21:51:10 +0000 |
|---|---|---|
| committer | Vasil Zlatanov <v@skozl.com> | 2016-12-12 21:51:10 +0000 |
| commit | 4b6e0102d20d9ab060ce930e4b846c8be446bb06 (patch) | |
| tree | e475eab3716738f2928f0b2063956e9b155f94ab /part_4/ex16/mult4.v | |
| download | e2-verilab-4b6e0102d20d9ab060ce930e4b846c8be446bb06.tar.gz e2-verilab-4b6e0102d20d9ab060ce930e4b846c8be446bb06.tar.bz2 e2-verilab-4b6e0102d20d9ab060ce930e4b846c8be446bb06.zip | |
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Diffstat (limited to 'part_4/ex16/mult4.v')
| -rw-r--r-- | part_4/ex16/mult4.v | 35 |
1 files changed, 35 insertions, 0 deletions
diff --git a/part_4/ex16/mult4.v b/part_4/ex16/mult4.v new file mode 100644 index 0000000..30a1798 --- /dev/null +++ b/part_4/ex16/mult4.v @@ -0,0 +1,35 @@ +//------------------------------
+// Module name: allpass processor
+// Function: Simply to pass input to output
+// Creator: Peter Cheung
+// Version: 1.1
+// Date: 24 Jan 2014
+//------------------------------
+
+module processor (sysclk, data_in, data_out);
+
+ input sysclk; // system clock
+ input [9:0] data_in; // 10-bit input data
+ output [9:0] data_out; // 10-bit output data
+
+ wire sysclk;
+ wire [9:0] data_in;
+ reg [9:0] data_out;
+ wire [9:0] x,y,z;
+
+ parameter ADC_OFFSET = 10'h181;
+ parameter DAC_OFFSET = 10'h200;
+
+ assign x = data_in[9:0] - ADC_OFFSET; // x is input in 2's complement
+
+ // This part should include your own processing hardware
+ // ... that takes x to produce y
+ // ... In this case, it is ALL PASS.
+ multiply_4 MULT4 (x,y);
+
+ // Now clock y output with system clock
+ always @(posedge sysclk)
+ data_out <= y + DAC_OFFSET;
+
+endmodule
+
\ No newline at end of file |