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| author | Vasil Zlatanov <v@skozl.com> | 2016-12-12 21:51:10 +0000 |
|---|---|---|
| committer | Vasil Zlatanov <v@skozl.com> | 2016-12-12 21:51:10 +0000 |
| commit | 4b6e0102d20d9ab060ce930e4b846c8be446bb06 (patch) | |
| tree | e475eab3716738f2928f0b2063956e9b155f94ab /part_4/ex16/pulse_gen.v | |
| download | e2-verilab-4b6e0102d20d9ab060ce930e4b846c8be446bb06.tar.gz e2-verilab-4b6e0102d20d9ab060ce930e4b846c8be446bb06.tar.bz2 e2-verilab-4b6e0102d20d9ab060ce930e4b846c8be446bb06.zip | |
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Diffstat (limited to 'part_4/ex16/pulse_gen.v')
| -rw-r--r-- | part_4/ex16/pulse_gen.v | 43 |
1 files changed, 43 insertions, 0 deletions
diff --git a/part_4/ex16/pulse_gen.v b/part_4/ex16/pulse_gen.v new file mode 100644 index 0000000..d82fe49 --- /dev/null +++ b/part_4/ex16/pulse_gen.v @@ -0,0 +1,43 @@ +//------------------------------
+// Module name: pulse_gen (Moore)
+// Function: Generate one clock pulse on +ve edge of input
+// Creator: Peter Cheung
+// Version: 1.0
+// Date: 29 Jan 2014
+//------------------------------
+
+module pulse_gen(pulse, in, clk);
+
+ output pulse; // output pulse lasting one clk cycle
+ input in; // input, +ve edge to be detected
+ input clk; // clock signal
+
+ reg [1:0] state;
+ reg pulse;
+
+ parameter IDLE = 2'b0; // state coding for IDLE state
+ parameter IN_HIGH = 2'b01;
+ parameter WAIT_LOW = 2'b10;
+
+ initial state = IDLE;
+
+ always @ (posedge clk)
+ begin
+ pulse <= 0; // default output
+ case (state)
+ IDLE: if (in == 1'b1) begin
+ state <= IN_HIGH; pulse <= 1'b1; end
+ else
+ state <= IDLE;
+ IN_HIGH: if (in == 1'b1)
+ state <= WAIT_LOW;
+ else
+ state <= IDLE;
+ WAIT_LOW: if (in == 1'b1)
+ state <= WAIT_LOW;
+ else
+ state <= IDLE;
+ default: ;
+ endcase
+ end //... always
+endmodule
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